MB90V370_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13729-1E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90370

/375 Series

MB90372/F372/F377/V370

■ DESCRIPTION

The MB90370/375 series is a line of general-purpose, 16-bit microcontrollers designed for those applications

which require high-speed real-time processing. The instruction set is designed to be optimized for controller

applications which inheriting the AT architecture of F²MC-16LX series and allow a wide range of control tasks to

be processed efficiently at high speed.

A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices

in computer system. Moreover, SMbus compliant I²C*², comparator for battery control and A/D converter imple-

ments the smart battery control. With these features, the MB90370/375 series matches itself as keyboard con-

troller with smart battery control.

(Continued)

■ PACKAGE

144-pin plastic LQFP

(FPT-144P-M12)

MB90370/375 Series

(Continued)

While inheriting the AT architecture of the F²MC*¹family, the instruction set for the F²MC-16LX CPU core of the

MB90370/375seriesincorporatesadditionalinstructionsforhigh-levellanguages, supportsextendedaddressing

modes, and contains enhanced multiplication and division instructions as well as a substantial collection of

improved bit manipulation instructions. In addition, the MB90370 has an on-chip 32-bit accumulator which

enables processing of long-word data.

*1 : F²MC stands for FUJITSU Flexible Microcontroller and a registered trademark of FUJITSU LIMITED.

*2 : Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined

by Philips.

■ FEATURES

• Clock

• Embedded PLL clock multiplication circuit

• Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation

(at oscillation of 4 MHz to 16 MHz) .

• Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at

V^CCof 3.3 V)

• CPU addressing space of 16M bytes

• Internal 24-bit addressing

• Instruction set optimized for controller applications

• Rich data types (bit, byte, word, long word)

• Rich addressing mode (23 types)

• High code efficiency

• Enhanced precision calculation realized by the 32-bit accumulator

• Instruction set designed for high level language (C) and multi-task operations

• Adoption of system stack pointer

• Enhanced pointer indirect instructions

• Barrel shift instructions

• Program patch function (2 address pointer)

• Improved execution speed

• 4-byte instruction queue

• Powerful interrupt function

• Priority level programmable : 8 levels

• 32 factors of stronger interrupt function

• Automatic data transmission function independent of CPU operation

• Extended intelligent I/O service function (EI²OS)

• Maximum 16 channels

• Low-power consumption (standby) mode

• Sleep mode (mode in which CPU operating clock is stopped)

• Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped)

• Stop mode (mode in which all oscillations are stopped)

• CPU intermittent operation mode

• Watch mode

• Package

• LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)

• Process

• CMOS technology

2

MB90370/375 Series

■ PRODUCT LINEUP

Part number

Parameter

MB90V370

MB90F372

MB90F377

MB90372

Classification

ROM size

—

Flash type ROM

Mask ROM

64K Bytes

6K Bytes

RAM size

15.7K Bytes

Number of instruction : 351

Minimum execution time : 62.5 ns / 4 MHz (PLL × 4)

Addressing mode : 23

CPU function

Data bit length : 1, 8, 16 bits

Maximum memory space : 16M Bytes

I/O port (N-channel) : 16

I/O port (CMOS) : 72

I/O port (CMOS with pull-up control) : 32

Total : 120

I/O port

Reload timer : 4 channels

Reload mode, single-shot mode or event count mode selectable

16-bit reload timer

PPG timer : 3 channels

PWM mode or single-shot mode selectable

16-bit PPG timer

Bit decoder

Bit decoder : 1 channel

Parity generator : 1 channel

Selectable odd/even parity

Parity generator

PS/2 interface : 3 channels

4 selectable sampling clocks

PS/2 interface

LPC interface

LPC bus interface : 1 channel

Universal peripheral Interface : 4 channels

GA20 output control : for UPI channel 0 only

Data buffer array : 48 bytes

LPC Standby (able to work

in Stop/TBT/Watch mode)

Yes

No

Yes

No

Serial IRQ request : 6 channels

LPC clock monitor / control

Serial IRQ controller

With full-duplex double buffer (variable data length)

UART

Clock asynchronized or clock synchronized transmission (with start and stop bits)

can be selectively used

I²C (SMbus compliant) : 1 channel

Support I²C bus of Philips and the SMbus proposed by Intel

Selectable packet error check

I²C

Timeout detection function

PC Arbitration under

a paticular condition*²

No

Yes

No

(Continued)

3

MB90370/375 Series

(Continued)

Part number

MB90V370

MB90F372

MB90F377

MB90372

Parameter

Multi-address I²C (SMbus compliant) : 1 channel

Support I²C bus of Philips and the SMbus proposed by Intel

Selectable packet error check

Multi-address I²C

Timeout detection function

6 addresses support

ALERT function

Bridge circuit

Comparator

Three bus connection routes can be switched by I²C / multi-address I²C

A comparator that can change the hysteresis width is contained

Battery voltage, mounting/dismounting and instantaneous interruption can be de-

tected

Parallel and serial charging/discharging

External

interrupt

6 independent channels

Selectable causes : Rise/fall edge, fall edge, “L” level or “H” level

Key-on wake-up

interrupt

8 independent channels

Causes : “L” level

8/10-bit A/D

converter

8/10-bit resolution : 12 channels

Conversion time : Less than 6.13 µs (16 MHz internal clock)

8-bit D/A

converter

8-bit resolution : 2 channels

Up to 9 SEG × 4 COM

Selectable LCD output or CMOS I/O port controller/driver

Without LCD

Same as

MB90F372

LCD controller/driver*³

Low-power

consumption

Stop mode / Sleep mode / CPU intermittent operation mode / Watch mode

Process

Package

CMOS

PGA256

LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)

3.0 V to 3.6 V @ 16 MHz *¹

Operating voltage

*1 : Varies with conditions such as the operating frequency (see Section “■ ELECTRICAL CHARACTERISTICS”) ,

Assurance for the MB90V370 is given only for operation with a tool at power supply voltage of 3.0 V to 3.6 V,

an operating temperature of 0 °C to +25 °C, and an operating frequency of 1 MHz to 16 MHz.

*2 : I²C can detect the arbitration lost when another I²C starts another communication at the same time.

*3 : After reset, PF5 to PF7 serve as general purpose I/O pins in MB90F377; however, these pins serve as V1, V2

and V3 function in other products.

4

MB90370/375 Series

■ PACKAGE AND CORRESPONDING PRODUCTS

Package

MB90V370

MB90F372

MB90F377

MB90372

PGA256

X

FPT-144P-M12

X

: Available

X : Not available

Note : For more information about each package, see Section “■ PACKAGE DIMENSIONS”.

■ DIFFERENCES AMONG PRODUCTS

Memory size

In evaluation with an evaluation product, note the difference between the evaluation product and the product

actually used. The following items must be taken into consideration.

• The MB90V370 does not have an internal ROM, however, operations equivalent to chips with an internal ROM

can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the

development tool.

• In the MB90V370, images from FF4000^Hto FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are

mapped to bank FF only. (This setting can be changed by the development tool configuration.)

• In the MB90372/F372, images from FF4000^Hto FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH

are mapped to bank FF only.

5

MB90370/375 Series

■ PIN ASSIGNMENT

• MB90372/F372

(TOP VIEW)

P40/PSCK0

P41/PSDA0

P42/PSCK1

P43/PSDA1

P44/PSCK2

P45/PSDA2

P46/CLKRUN

P47/SERIRQ

P50/GA20

P51/LFRAME

P52/LRESET

P53/LCK

P54/LAD0

P55/LAD1

P56/LAD2

P57/LAD3

RST

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

P77/PPG1

P76/UI3

P75/UO3

P74/UCK3

P73/UI2

P72/UO2

P71/UCK2

P70/UI1

P67/UO1

P66/UCK1

P65/INT5

P64/INT4

P63/INT3

P62/INT2

P61/INT1

P60/INT0

PD7/PPG3

Vss

Vcc

PF7/V3*

PF6/V2*

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

LQFP-144

Vcc

Vss

X0A

X1A

PA0/ALR1

PA1/ALR2

PA2/ALR3

PA3/ACO

PA4/OFB1

PA5/OFB2

PA6/OFB3

CVcc

PF5/V1*

PF4/COM3*

PF3/COM2*

PF2/COM1*

PF1/COM0*

PF0/SEG8*

PE7/TO4/SEG7

PE6/TIN4/SEG6

PE5/TO3/SEG5

PE4/TIN3/SEG4

PE3/TO2/SEG3

PE2/TIN2/SEG2

PE1/TO1/SEG1

PE0/TIN1/SEG0

P82/ALERT

CVRH1

CVRH2

CVRL

CVss

PB0/DCIN

PB1/DCIN2

PB2/VOL1

74

73

(FPT-144P-M12)

* : High current pins

6

MB90370/375 Series

• MB90F377

(TOP VIEW)

P40/PSCK0

P41/PSDA0

P42/PSCK1

P43/PSDA1

P44/PSCK2

P45/PSDA2

P46/CLKRUN

P47/SERIRQ

P50/GA20

P51/LFRAME

P52/LRESET

P53/LCK

P54/LAD0

P55/LAD1

P56/LAD2

P57/LAD3

RST

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

P77/PPG1

P76/UI3

P75/UO3

P74/UCK3

P73/UI2

P72/UO2

P71/UCK2

P70/UI1

P67/UO1

P66/UCK1

P65/INT5

P64/INT4

P63/INT3

P62/INT2

P61/INT1

P60/INT0

PD7/PPG3

Vss

Vcc

PF7*

PF6*

PF5*

PF4*

PF3*

PF2*

PF1*

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

LQFP-144

Vcc

Vss

X0A

X1A

PA0/ALR1

PA1/ALR2

PA2/ALR3

PA3/ACO

PA4/OFB1

PA5/OFB2

PA6/OFB3

CVcc

PF0*

PE7/TO4

PE6/TIN4

PE5/TO3

PE4/TIN3

PE3/TO2

PE2/TIN2

PE1/TO1

PE0/TIN1

P82/ALERT

CVRH1

CVRH2

CVRL

CVss

PB0/DCIN

PB1/DCIN2

PB2/VOL1

74

73

(FPT-144P-M12)

* : High current pins

7

MB90370/375 Series

■ PIN DESCRIPTION

Pin no.

I/O

Pin status

Pin name

Function

circuit during reset

LQFP-144

128, 129

20, 21

X0, X1

X0A, X1A

RST

A

B

Oscillating Main oscillation pins.

Oscillating Sub-clock oscillation pins.

Reset input External reset input pin.

17

MD0 to

MD2

Input pin for operation mode specification. Connect this pin

directly to Vcc or Vss.

58, 57, 56

109 to 116

C

Mode input

P00 to P07

General-purpose I/O ports.

Can be used as key-on wake-up interrupt input channel 0 to

channel 7. Input is enabled when 1 is set in EICR : EN0 to EN7

in standby mode.

D

KSI0 to

KSI7

117 to 124 P10 to P17

E

General-purpose I/O ports.

125,

P20 to P27

130 to 136

General-purpose I/O ports.

137 to 143 P30 to P36

General-purpose I/O ports.

P37

144

General-purpose I/O ports.

E

ADTG

External trigger input pin (ADTG) for the A/D converter.

General-purpose N-ch open-drain I/O port.

P40

1

F

Serial clock I/O pin for PS/2 interface channel 0. This function

is selected when PS/2 interface channel 0 is enabled.

PSCK0

P41

General-purpose N-ch open-drain I/O port.

2

F

Serial data I/O pin for PS/2 interface channel 0. This function

is selected when PS/2 interface channel 0 is enabled.

PSDA0

Port input

P42

General-purpose N-ch open-drain I/O port.

3

Serial clock I/O pin for PS/2 interface channel 1. This function

is selected when PS/2 interface channel 1 is enabled.

PSCK1

P43

General-purpose N-ch open-drain I/O port.

4

Serial data I/O pin for PS/2 interface channel 1. This function

is selected when PS/2 interface channel 1 is enabled.

PSDA1

P44

General-purpose N-ch open-drain I/O port.

5

Serial clock I/O pin for PS/2 interface channel 2. This function

is selected when PS/2 interface channel 2 is enabled.

PSCK2

P45

General-purpose N-ch open-drain I/O port.

6

Serial data I/O pin for PS/2 interface channel 2. This function

is selected when PS/2 interface channel 2 is enabled.

PSDA2

P46

General-purpose N-ch open-drain I/O port.

LPC clock status / restart request I/O pin for serial IRQ control-

ler. This function is selected when serial IRQ and LPC clock

restart request is enabled.

7

G

CLKRUN

(Continued)

8

MB90370/375 Series

Pin no.

I/O

Pin status

Pin name

Function

circuit during reset

LQFP-144

P47

SERIRQ

P50

General-purpose I/O port.

8

9

H

Serial IRQ data I/O pin for serial IRQ controller. This function

is selected when serial IRQ is enabled.

General-purpose I/O port.

H

GA20 output for LPC interface. This function is selected when

GA20 function is enabled.

GA20

P51

General-purpose I/O port.

10

LFRAME input for LPC interface. This function is selected

when LPC interface is enabled.

LFRAME

P52

General-purpose I/O port.

11

Reset input for LPC interface. This function is selected when

LPC interface is enabled.

LRESET

P53

General-purpose I/O port.

12

Clock input for LPC interface. This function is selected when

LPC interface is enabled.

LCK

P54 to P57

General-purpose I/O ports.

13 to 16

H

LAD0 to

LAD3

Address/Data I/O for LPC interface. This function is selected

when LPC interface is enabled.

Port input

P60 to P65

General-purpose I/O ports.

Can be used as DTP/external interrupt request input channel

0 to 5. Input is enabled when 1 is set in ENIR : EN0 to EN5 in

standby mode.

93 to 98

I

INT0 to

INT5

P66

UCK1

P67

General-purpose I/O port.

99

I

Serial clock I/O pin for UART channel 1. This function is

enabled when UART channel 1 enables clock output.

General-purpose I/O port.

100

Serial data output pin for UART channel 1. This function is

enabled when UART channel 1 enables data output.

UO1

P70

General-purpose I/O port.

Serial data input pin for UART channel 1. While UART

channel 1 is operating for input, the input of this pin is used as

required and must not be used for any other input.

101

102

I

UI1

P71

General-purpose I/O port.

Serial clock I/O pin for UART channel 2. This function is

enabled when UART channel 2 enables clock output.

UCK2

(Continued)

9

MB90370/375 Series

Pin no.

I/O

Pin status

Pin name

Function

circuit during reset

LQFP-144

P72

UO2

P73

General-purpose I/O port.

103

I

Serial data output pin for UART channel 2. This function is

enabled when UART channel 2 enables data output.

General-purpose I/O port.

Serial data input pin for UART channel 2. While UART

channel 2 is operating for input, the input of this pin is used as

required and must not be used for any other input.

104

UI2

P74

UCK3

P75

General-purpose I/O port.

105

106

I

Serial clock I/O pin for UART channel 3. This function is

enabled when UART channel 3 enables clock output.

General-purpose I/O port.

Serial data output pin for UART channel 3. This function is

enabled when UART channel 3 enables data output.

UO3

P76

General-purpose I/O port.

Serial data input pin for UART channel 3. While UART

channel 3 is operating for input, the input of this pin is used as

required and must not be used for any other input.

107

108

I

UI3

P77

General-purpose I/O port.

Port input

I

Output pin for PPG channel 1. This function is enabled when

PPG channel 1 output is enabled.

PPG1

P80

SCL1

P81

General-purpose N-ch open-drain I/O port.

Serial clock I/O pin for multi-address I²C.

General-purpose N-ch open-drain I/O port.

Serial data I/O pin for multi-address I²C.

General-purpose N-ch open-drain I/O port.

ALERT output pin for multi-address I²C.

General-purpose N-ch open-drain I/O port.

Serial clock I/O pin for bridge circuit.

71

72

73

65

66

67

68

T

J

SDA1

P82

ALERT

P90

T

SCL2

P91

General-purpose N-ch open-drain I/O port.

Serial data I/O pin for bridge circuit.

SDA2

P92

General-purpose N-ch open-drain I/O port.

Serial clock I/O pin for bridge circuit.

SCL3

P93

General-purpose N-ch open-drain I/O port.

SDA3

Serial data I/O pin for bridge circuit.

(Continued)

10

MB90370/375 Series

Pin no.

I/O

Pin status

Pin name

Function

circuit during reset

LQFP-144

P94

SCL4

General-purpose N-ch open-drain I/O port.

69

70

T

Serial clock I/O pin for bridge circuit.

General-purpose N-ch open-drain I/O port.

Serial data I/O pin for bridge circuit.

General-purpose I/O ports.

P95

T

SDA4

PA0 to PA2

22 to 24

25

H

ALR1 to

ALR3

Alarm signal output when battery 1 to 3 run down in

comparator circuit.

Port input

PA3

ACO

General-purpose I/O port.

H

AC power set signal output in comparator circuit.

General-purpose I/O ports.

PA4 to PA6

26 to 28

OFB1 to

OFB3

Battery 1 to 3 discharge control signal output in comparator

circuit.

PB0 to PB1

General-purpose I/O ports.

34, 35

K

DCIN to

DCIN2

AC power monitoring input in comparator circuit.

General-purpose I/O ports.

PB2

36

37

38

39

40

41

Battery 1 power instantaneous interruption monitoring input in

comparator circuit.

VOL1

PB3

VSI1

PB4

General-purpose I/O ports.

K

Battery 1 indicator monitoring input in comparator circuit.

General-purpose I/O ports.

Comparator

K

input

Battery 2 power instantaneous interruption monitoring input in

comparator circuit.

VOL2

PB5

VSI2

PB6

General-purpose I/O ports.

Battery 2 indicator monitoring input in comparator circuit.

General-purpose I/O ports.

Battery 3 power instantaneous interruption monitoring input in

comparator circuit.

VOL3

PB7

General-purpose I/O ports.

VSI3

Battery 3 indicator monitoring input in comparator circuit.

PC0 to

PC2

General-purpose I/O ports.

Comparator

input

SW1 to

SW3

Battery 1 to 3 mount / dismount detection input in comparator

circuit.

45 to 47

L

or

A/D input

AN0 to

AN2

A/D converter analog input pin 0 to 2. This function is enabled

when the analog input specification is enabled (ADER1) .

(Continued)

11

MB90370/375 Series

Pin no.

I/O

circuit

Pin status

during reset

Pin name

Function

General-purpose I/O ports.

LQFP-144

PC3 to PC7

A/D converter analog input pin 3 to 7. This function is

enabled when the analog input specification is enabled

(ADER1) .

48 to 52

M

AN3 to AN7

PD0 to PD3

A/D input

General-purpose I/O ports.

53,

59 to 61

A/D converter analog input pin 8 to 11. This function is

enabled when the analog input specification is enabled

(ADER2) .

AN8 to

AN11

PD4 to PD5

DA1 to DA2

PD6 to PD7

General-purpose I/O ports.

62 to 63

64, 92

N

H

D/A converter analog output 1 to 2. This function is

selected when D/A converter is enabled.

General-purpose I/O port.

PPG2 to

PPG3

Output pin for PPG channel 2 to 3. This function is

selected when PPG channel 2 to 3 output is enabled.

PE0

General-purpose I/O port.

O1

(O2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

74

75

76

77

78

79

SEG0*¹

TIN1

PE1

External clock input pin for reload timer 1.

General-purpose I/O port.

O1

(O2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

SEG1*¹

TO1

PE2

Event output pin for reload timer 1.

General-purpose I/O port.

Port input

O1

(O2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

SEG2*¹

TIN2

PE3

External clock input pin for reload timer 2.

General-purpose I/O port.

O1

(O2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

SEG3*¹

TO2

PE4

Event output pin for reload timer 2.

General-purpose I/O port.

O1

(O2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

SEG4*¹

TIN3

PE5

External clock input pin for reload timer 3.

General-purpose I/O port.

O1

(O2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

SEG5*¹

TO3

Event output pin for reload timer 3.

(Continued)

12

MB90370/375 Series

(Continued)

Pin no.

I/O

circuit

Pin status

during reset

Pin name

Function

LQFP-144

PE6

General-purpose I/O port.

O1

(O2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

80

SEG6*¹

TIN4

PE7

External clock input pin for reload timer 4.

General-purpose I/O port.

O1

(O2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

81

SEG7*¹

Port input

TO4

PF0

Event output pin for reload timer 4.

General-purpose I/O port.

P1

82

(P2 for

MB90F377)

Segment output pin for LCD controller/driver. This function

is selected when LCD segment output is enabled.

SEG8*¹

PF1 to PF4

General-purpose I/O port.

P1

83 to 86

87 to 89

(P2 for

MB90F377)

COM0 to

COM3*²

COM output pin for LCD controller/driver. This function is

selected when LCD COM output is enabled.

PF5 to PF7

V1 to V3*²

AVCC

General-purpose I/O port.

Q1

(Q2 for

MB90F377)

Power input

Power input pin for LCD controller/driver. This function is

selected when external voltage divider is enabled.

42

43

R

S

Vcc power input pin for analog circuits.

Power input Vref+ input pin for the A/D converter. This voltage must not

exceed Vcc. Vref- is fixed to AVSS.

AVR

44

29

30

31

32

33

AV^SS

CV^CC

R

Vss power input pin for analog circuits.

Vcc power input pin for analog circuits.

CVRH1

CVRH2

CVRL

CVSS

Power input

Standard power input pin of the comparator.

Vss power input pin for analog circuits.

19, 55, 91,

127

Vss

Vcc

–

Power (0 V) input pin.

Power input

18, 54, 90,

126

Power (3.3 V) input pin.

*1 : It doesn’t exist in MB90F377.

*2 : They don’t exist in MB90F377.

13

MB90370/375 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

X1/X1A

X0/X0A

Main/Sub clock (main/sub clock crystal

oscillator)

Xout

N-ch P-ch

• High-rate oscillation feedback

resistor of approximately 1 MΩ

• Low-rate oscillation feedback

resistor of approximately 10 MΩ

P-ch

N-ch

A

Standby mode control

• Hysteresis input

• Pull-up resistor approximately

50 kΩ

R

B

C

• Hysteresis input

• CMOS output

• Hysteresis input

• Selectable pull-up resistor

approximately 50 kΩ

• I^OL= 4 mA

R

P-ch

Pull-up control

P-ch

Pout

Nout

D

N-ch

Hysteresis input

Standby mode control

• CMOS output

• CMOS input

R

P-ch

• Selectable pull-up resistor

approximately 50 kΩ

• I^OL= 4 mA

Pull-up control

P-ch

Pout

Nout

E

N-ch

CMOS input

Standby mode control

• N-ch open-drain output

• Hysteresis input

• I^OL= 4 mA

N-ch

• 5 V tolerant

Nout

F

Hysteresis input

Standby mode control

(Continued)

14

MB90370/375 Series

Type

Circuit

Remarks

• N-ch open-drain output

• CMOS input

• I^OL= 4 mA

P-ch

N-ch

Nout

G

CMOS input

Standby mode control

• CMOS output

• CMOS input

• IOL = 4 mA

P-ch

N-ch

Pout

Nout

H

CMOS input

Standby mode control

• CMOS output

• Hysteresis input

• IOL = 4 mA

P-ch

N-ch

Pout

Nout

I

Hysteresis input

Standby mode control

• N-ch open-drain output

• CMOS input

• I^OL= 4 mA

N-ch

• 5 V tolerant

Nout

J

CMOS input

Standby mode control

• CMOS output

• CMOS input

• Comparator input

• IOL = 4 mA

P-ch

N-ch

Pout

Nout

K

CMOS input

Standby mode control

+

−

Comparator input

(Continued)

15

MB90370/375 Series

Type

Circuit

Remarks

• CMOS output

• CMOS input

P-ch

N-ch

Pout

Nout

• Comparator input

• A/D analog input

• I^OL= 4 mA

L

CMOS input

Standby mode control

+

−

Comparator input

Analog input

• CMOS output

• CMOS input

• A/D analog input

• I^OL= 4 mA

P-ch

Pout

Nout

N-ch

M

CMOS input

Standby mode control

Analog input

• CMOS output

• CMOS input

• D/A analog output

• I^OL= 4 mA

P-ch

N-ch

Pout

Nout

N

CMOS input

Standby mode control

Analog input

• CMOS output

• CMOS input

• Segment output

• I^OL= 4 mA

P-ch

N-ch

Pout

Nout

O1

CMOS input

Standby mode control

Segment output

(Continued)

16

MB90370/375 Series

Type

Circuit

Remarks

• CMOS output

• CMOS input

• I^OL= 4 mA

P-ch

N-ch

Pout

Nout

O2

CMOS input

Standby mode control

• CMOS output

• CMOS input

• Segment output

• I^OL= 12 mA

P-ch

Pout

Nout

N-ch

P1

P2

Q1

Q2

CMOS input

Standby mode control

Segment output

• CMOS output

• CMOS input

• I^OL= 12 mA

P-ch

N-ch

Pout

Nout

CMOS input

Standby mode control

• CMOS output

• CMOS input

• LCD driving power supply

• I^OL= 12 mA

P-ch

N-ch

Pout

Nout

CMOS input

Standby mode control

LCD driving power supply

• CMOS output

• CMOS input

• I^OL= 12 mA

P-ch

N-ch

Pout

Nout

CMOS input

Standby mode control

(Continued)

17

MB90370/375 Series

(Continued)

Type

Circuit

Remarks

• Power supply input protection circuit

P-ch

N-ch

IN

R

• A/D converter reference voltage

(AVR) input pin with protection circuit

Analog input enable

P-ch

IN

S

N-ch

Analog input enable

• N-ch open-drain output

• CMOS input

N-ch

• I^OL= 4 mA

• 5 V tolerant

Nout

N-ch

T

CMOS input

Standby mode control

18

MB90370/375 Series

■ HANDLING DEVICES

• Be sure that the maximum rated voltage is not exceeded (latch-up prevention) .

A latch-up may occur on a CMOS IC if a voltage higher than V^CCor lower than VSS is applied to an input or

output pin other than medium-to-high voltage pins. A latch-up may also occur if a voltage higher than the

rating is applied between VCC and VSS. A latch-up causes a rapid increase in the power supply current, which

can result in thermal damage to an element. Take utmost care that the maximum rated voltage is not exceeded.

When turning the power on or off to analog circuits, be sure that the analog supply voltages (AV^CC, CVCC, AVR,

CVRH1, CVRH2 and CVRL) and analog input voltage do not exceed the digital supply voltage (VCC) .

• Stabilize the supply voltages

Even within the operation guarantee range of the V^CCsupply voltage, a malfunction can be caused if the supply

voltage undergoes a rapid change. For voltage stabilization guidelines, the VCC ripple fluctuations (P-P value)

at commercial frequencies (50 Hz to 60 Hz) should be suppressed to 10% or less of the reference V^CCvalue.

During a momentary change such as when switching a supply voltage, voltage fluctuations should also be

suppressed so that the transient fluctuation rate is 0.1 V/ms or less.

• Power-on

To prevent a malfunction in the built-in voltage drop circuit, secure 50 µs (between 0.2 V and 1.8 V) or more

for the voltage rise time during power-on.

• Treatment of unused input pins

An unused input pin may cause a malfunction if it is left open. Every unused input pin should be pulled up or

down.

• Treatment of A/D converter, D/A converter and comparator power pin

When the A/D converter, D/A converter and comparator is not used, connect the pins as follows : AV^CC= CVCC

= VCC, AVSS = AVR = CVSS = CVRL = CVRH1 = CVRH2 = VSS.

• Notes on external clock

When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at

cancellation of sub-clock mode or stop mode. As shown in diagram below, when an external clock is used,

connect only the X0 pin and leave the X1 pin open.

X0

MB90370/375 series

X1

Open

• Power supply pins

When a device has two or more V^CCor VSS pins, the pins that should have equal potential are connected within

the device in order to prevent a latch-up or other malfunction. To reduce extraneous emission, to prevent a

malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current

rating, connect all these power supply pins to an external power supply and ground them.

The current source should be connected to the V^CCand VSS pins of the device with minimum impedance. It

is recommended that a bypass capacitor of about 0.1 µF be connected near the terminals between VCC and VSS.

19

MB90370/375 Series

• Analog power-on sequence of A/D converter, D/A converter and comparator

The power to the A/D converter, D/A converter and comparator (AV^CC, CVCC, AVR, CVRH1, CVRH2 and CVRL)

and analog inputs (AN0 to AN11, VOL1 to VOL3, VSI1 to VSI3, SW1 to SW3, DCIN and DCIN2) must be

turned on after the power to the digital circuits (V^CC) is turned on. When turning off the power, turn off the

power to the digital circuits (VCC) after turning off the power to the A/D converter, D/A converter, comparator

and analog inputs. When the power is turned on or off, AVR should not exceed AV^CC. And CVRH1, CVRH2

and CVRL should not exceed CVCC. Also, when a pin that is used for A/D analog input is used as an input port,

the input voltage should not exceed AVCC. And when comparator analog input is also used as an input port,

the input voltage should not exceed CV^CC. (The power to the analog circuits and the power to the digital circuits

can be simultaneously turned on or off.)

• Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

20

MB90370/375 Series

■ BLOCK DIAGRAM

• MB90372/F372/V370

Other pins

CPU

X0, X0A

Vss x 4, Vcc x 4, MD0-2, AVcc, AVss, CVcc, CVss

Clock control

circuit

F²MC-16LX series core

X1, X1A

Delayed interrupt generator

Reset circuit

RST

(Watchdog timer)

Interrupt controller

Timebase timer

N-ch open-drain I/O port 8, 9

P80/SCL1

P81/SDA1

P82/ALERT

I²C bus

(Multi-address)

P90/SCL2

P91/SDA2

P92/SCL3

P93/SDA3

P94/SCL4

P95/SDA4

8

P00/KSI0 to

P07/KSI7

I²C bus

CMOS I/O port 0, 1, 2, 3*

8

P10 to P17

8

P20 to P27

Key-on wake-up

interrupt

P30 to P36

P37/ADTG

6

Bridge circuit

P40/PSCK0

P41/PSDA0

P42/PSCK1

P43/PSDA1

P44/PSCK2

P45/PSDA2

P46/CLKRUN

P47/SERIRQ

N-ch open-drain I/O port 4

(P47 is CMOS I/O port)

PA0/ALR1 to

PA2/ALR3

PA3/ACO

CMOS I/O port A, B

Comparator

6

3CH PS/2 interface

PA4/OFB1 to

PA6/OFB3

PB0/DCIN

PB1/DCIN2

PB2/VOL1

PB3/VSI1

PB4/VOL2

PB5/VSI2

PB6/VOL3

PB7/VSI3

2

Serial IRQ (6 channels)

7

Battery select circuit

LPC Interface

P50/GA20

P51/LFRAME

P52/LRESET

P53/LCK

GateA20 control

8

3

Voltage comparator

7

P54/LAD0

UPI

P55/LAD1

(Ch0, 1, 2, 3)

P56/LAD2

CVRH1, CVRH2, CVRL

AVR

P57/LAD3

12

2

PC0/AN0/SW1

PC1/AN1/SW2

PC2/AN2/SW3

PC3/AN3 to

PC7/AN7

PD0/AN8 to

PD3/AN11

PD4/DA1

A/D converter

(8/10 bit)

CMOS I/O port 5

6

P60/INT0 to

P65/INT5

P66/UCK1

P67/UO1

P70/UI1

P71/UCK2

P72/UO2

P73/UI2

6

DTP/External interrupt

D/A converter

UART

(Ch1, 2, 3)

16-bit PPG

(Ch2, 3)

PD5/DA2

PD6/PPG2

PD7/PPG3

P74/UCK3

P75/UO3

P76/UI3

16-bit PPG (Ch1)

CMOS I/O port C, D

CMOS I/O port E, F

P77/PPG1

CMOS I/O port 6, 7

PE0/TIN1

PE1/TO1

PE2/TIN2

PE3/TO2

PE4/TIN3

PE5/TO3

PE6/TIN4

PE7/TO4

RAM

ROM

16-bit reload timer

(Ch1, 2, 3, 4)

ROM correction

ROM mirroring

PF0

PF1 to

PF4

PF5 to

PF7

* : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With registers that can be used as input pull-up resistors

Note: PF0 to PF7 : High current pins

21

MB90370/375 Series

• MB90F377

Other pins

CPU

X0, X0A

Vss x 4, Vcc x 4, MD0-2, AVcc, AVss, CVcc, CVss

Clock control

F²MC-16LX series core

circuit

X1, X1A

Delayed interrupt generator

Reset circuit

RST

(Watchdog timer)

Interrupt controller

Timebase timer

N-ch open-drain I/O port 8, 9

P80/SCL1

P81/SDA1

P82/ALERT

I²C bus

(Multi-address)

P90/SCL2

P91/SDA2

P92/SCL3

P93/SDA3

P94/SCL4

P95/SDA4

8

P00/KSI0 to

P07/KSI7

I²C bus

CMOS I/O port 0, 1, 2, 3*

8

P10 to P17

8

P20 to P27

Key-on wake-up

interrupt

P30 to P36

P37/ADTG

6

Bridge circuit

P40/PSCK0

P41/PSDA0

P42/PSCK1

P43/PSDA1

P44/PSCK2

P45/PSDA2

P46/CLKRUN

P47/SERIRQ

N-ch open-drain I/O port 4

(P47 is CMOS I/O port)

PA0/ALR1 to

PA2/ALR3

PA3/ACO

CMOS I/O port A, B

Comparator

6

3CH PS/2 interface

PA4/OFB1 to

PA6/OFB3

PB0/DCIN

PB1/DCIN2

PB2/VOL1

PB3/VSI1

PB4/VOL2

PB5/VSI2

PB6/VOL3

PB7/VSI3

2

Serial IRQ (6 channels)

7

Battery select circuit

LPC Interface

P50/GA20

P51/LFRAME

P52/LRESET

P53/LCK

GateA20 control

8

3

Voltage comparator

7

P54/LAD0

UPI

P55/LAD1

(Ch0, 1, 2, 3)

P56/LAD2

CVRH1, CVRH2, CVRL

AVR

P57/LAD3

12

2

PC0/AN0/SW1

PC1/AN1/SW2

PC2/AN2/SW3

PC3/AN3 to

PC7/AN7

PD0/AN8 to

PD3/AN11

PD4/DA1

A/D converter

(8/10 bit)

CMOS I/O port 5

6

P60/INT0 to

P65/INT5

P66/UCK1

P67/UO1

P70/UI1

P71/UCK2

P72/UO2

P73/UI2

6

DTP/External interrupt

D/A converter

UART

(Ch1, 2, 3)

16-bit PPG

(Ch2, 3)

PD5/DA2

PD6/PPG2

PD7/PPG3

P74/UCK3

P75/UO3

P76/UI3

16-bit PPG (Ch1)

CMOS I/O port C, D

CMOS I/O port E, F

P77/PPG1

CMOS I/O port 6, 7

PE0/TIN1

PE1/TO1

PE2/TIN2

PE3/TO2

PE4/TIN3

PE5/TO3

PE6/TIN4

PE7/TO4

RAM

ROM

16-bit reload timer

(Ch1, 2, 3, 4)

ROM correction

ROM mirroring

PF0

PF1 to

PF4

PF5 to

PF7

* : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With registers that can be used as input pull-up resistors

Note: PF0 to PF7 : High current pins

22

MB90370/375 Series

■ MEMORY MAP

Single-chip mode

(with ROM mirroring function)

FFFFFFH

ROM area

Address #1

FC0000H

010000H

ROM area

(FF bank image)

Address #2

004000H

Peripheral area

RAM

003FC0H

Address #3

Register

area

000100H

0000F8H

000000H

: Internal access memory

: Access not allowed

Peripheral area

Address #1

FF0000H

FF0000H*

Address #2

Address #3

001900H

003FC0H

Model

MB90372

MB90F372/F377

MB90V370

004000H

004000H*

* : The MB90V370 does not contain ROM. Assume that the development tool uses these area for its ROM decode

areas.

Note : ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C

compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the table in ROM can

be referenced without the “far” specification. For example, when 00C000H is accessed, the contents of

ROM at FFC000H are actually accessed. The ROM area in the FF bank exceeds 48 kilobytes, and all

areas cannot be seen as images in the 00 bank. Because ROM data from FF4000H to FFFFFFH is seen

as an image at 004000H to 00FFFFH, the ROM data table should be stored in the area from FF4000H to

FFFFFFH.

23

MB90370/375 Series

■ F²MC-16LX CPU PROGRAMMING MODEL

• Dedicated registers

AH

AL

Accumulator (A)

USP

SSP

PS

User Stack Pointer (USP)

System Stack Pointer (SSP)

Processor Status (PS)

PC

Program Counter (PC)

DPR

Direct Page Register (DPR)

PCB

DTB

USB

SSB

ADB

Program Bank Register (PCB)

Data Bank Register (DTB)

User Stack Bank Register (USB)

System Stack Bank Register (SSB)

Additional Data Bank Register (ADB)

8 bits

16 bits

32 bits

24

MB90370/375 Series

• General-purpose registers

CPU

Dedicated register

RAM

General-purpose

register

Accumulator

User stack pointer

System stack pointer

Processor status

Program counter

Direct page register

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

• Processor status (PS)

15

1312

8 7

0

ILM

000

RP

CCR

PS

Default value

00000

-01XXXXX

7

6

I

5

4

T

3

2

Z

1

0

S

N

V

X

C

X

: CCR

0

1

X

Default value

B4 B3 B2 B1 B0

: RP

Default value

0

: ILM

ILM2

ILM1

0

ILM0

0

- : Not used

X : Undefined

0

25

MB90370/375 Series

■ I/O MAP

Abbrevia-

Byte

access access

Word

Resource

name

Address

Register

Initial value

tion

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

00000AH

00000BH

00000CH

00000DH

00000EH

00000FH

000010H

000011H

000012H

000013H

000014H

000015H

000016H

000017H

000018H

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

PDRB

PDRC

PDRD

PDRE

PDRF

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

PGDR

Port 0 data register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

Port D

Port E

Port F

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

XXXXXXXXB

X1111111B

XXXXXXXXB

-----111B

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

--111111B

Port A data register

Port B data register

Port C data register

Port D data register

Port E data register

Port F data register

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Parity generator data register

-XXXXXXXB

XXXXXXXXB

00000000B

0-------B

00000000B

XXXXXXXXB

Parity generator

Parity generator control status

register

000019H

PGCSR

R/W

X------0B

00001AH

00001BH

00001CH

00001DH

00001EH

00001FH

DDRA

DDRB

DDRC

DDRD

DDRE

DDRF

Port A direction register

Port B direction register

Port C direction register

Port D direction register

Port E direction register

Port F direction register

R/W

Port A

Port B

Port C

Port D

Port E

Port F

-0000000B

00000000B

(Continued)

26

MB90370/375 Series

Abbrevia-

tion

Byte

access access

Word

Resource

name

Address

Register

Initial value

000020^H

000021H

SMR1

SCR1

Serial mode register 1

Serial control register 1

Input data register 1 /

R/W

00000-00B

00000100B

SIDR1/

000022H

R/W

UART1

XXXXXXXXB

SODR1 Output data register 1

000023H

000024H

SSR1 Serial status register 1

R/W

00001000B

----1000B

M2CR1 Mode 2 control register 1

Communication

prescaler 1

000025H

CDCR1 Clock division control register 1

R/W

0---0000B

000026H

000027H

000028H

000029H

00002AH

00002BH

00002CH

00002DH

00002EH

00002FH

000030H

000031H

000032H

000033H

ENIR

EIRR

Interrupt / DTP enable register

Interrupt / DTP cause register

R/W

R

R/W

R

--000000B

--XXXXXXB

00000000^B

----0000B

DTP/external

interrupt

ELVR

Request level setting register

ADER1 Analog input enable register 1

ADER2 Analog input enable register 2

Port C, A/D

Port D, A/D

Bridge circuit

11111111B

----1111B

BRSR

ADC0

Bridge circuit selection register

A/D control register

--000000B

00000000^B

XXXXXXXXB

00000-XXB

00--------B

ADCR0

ADCR1

ADCS0

ADCS1

SICRL

SICRH

A/D data register

8/10-bit A/D

converter

R/W

A/D control status register

00000000B

Serial interrupt request register

Serial interrupt control register

Serial interrupt frame number

register 1

000034H

000035H

000036H

000037H

SIFR1

SIFR2

SIFR3

SIFR4

R/W

--000000B

Serial interrupt frame number

register 2

Serial IRQ

Serial interrupt frame number

register 3

Serial interrupt frame number

register 4

--000000B

(Continued)

27

MB90370/375 Series

Abbrevia-

Byte

access access

Word

Resource

name

Address

Register

Initial value

tion

000038^H

000039H

00003AH

00003BH

00003CH

00003DH

00003EH

00003FH

000040H

000041H

000042H

000043H

000044H

000045H

000046H

000047H

000048H

000049H

00004AH

00004BH

00004CH

00004DH

00004EH

00004FH

000050H

000051H

000052H

000053H

000054H

000055H

000056H

000057H

000058H

000059H

PDCRL1

PDCRH1

PCSRL1

PCSRH1

PDUTL1

PDUTH1

PCNTL1

PCNTH1

PDCRL2

PDCRH2

PCSRL2

PCSRH2

PDUTL2

PDUTH2

PCNTL2

PCNTH2

PDCRL3

PDCRH3

PCSRL3

PCSRH3

PDUTL3

PDUTH3

PCNTL3

PCNTH3

R

11111111^B

11111111B

XXXXXXXXB

--000000B

PPG1 down counter register

PPG1 period setting register

PPG1 duty setting register

PPG1 control status register

PPG2 down counter register

PPG2 period setting register

PPG2 duty setting register

PPG2 control status register

PPG3 down counter register

PPG3 period setting register

PPG3 duty setting register

PPG3 control status register

W

16-bit

PPG timer

(CH1)

R/W

R

00000000B

11111111B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

--000000B

R

W

16-bit

PPG timer

(CH2)

W

R/W

R

00000000B

11111111^B

11111111B

XXXXXXXXB

--000000B

R

W

16-bit

PPG timer

(CH3)

W

R/W

00000000B

0--00000B

PSCR0 PS/2 interface control register 0

PSSR0 PS/2 interface status register 0

PSCR1 PS/2 interface control register 1

PSSR1 PS/2 interface status register 1

PSCR2 PS/2 interface control register 2

PSSR2 PS/2 interface status register 2

PSDR0 PS/2 interface data register 0

PSDR1 PS/2 interface data register 1

PSDR2 PS/2 interface data register 2

00000000B

0--00000B

00000000B

0--00000B

3-channel PS/2

interface

00000000B

PSMR

PS/2 interface mode register

----0000B

(Continued)

28

MB90370/375 Series

Abbrevia-

tion

Byte

access access

Word

Resource

name

Address

Register

Initial value

00005A^H

00005BH

00005CH

00005DH

00005EH

00005FH

000060H

000061H

000062H

000063H

000064H

000065H

DAT0

DAT1

D/A converter data register 0

D/A converter data register 1

R/W

XXXXXXXXB

-------0B

D/A converter

DACR0 D/A control register 0

DACR1 D/A control register 1

-------0B

UPAL1

UPI1 address register (lower)

XXXXXXXXB

00000000B

-000-000B

UPAH1 UPI1 address register (upper)

UPAL2

UPAH2 UPI2 address register (upper)

UPAL3 UPI3 address register (lower)

UPAH3 UPI3 address register (upper)

UPI2 address register (lower)

UPCL

UPCH

UPDI0/

UPI control register (lower)

UPI control register (upper)

UPI0 data input register / data

000066H

000067H

000068H

000069H

00006AH

00006BH

00006CH

R/W

XXXXXXXXB

00000000B

UPDO0 output register

LPC interface

UPS0

UPI0 status register

UPI1 data input register / data

UPDI1/

UPDO1 output register

XXXXXXXXB

00000000B

UPS1

UPI1 status register

UPI2 data input register / data

UPDI2/

UPDO2 output register

XXXXXXXXB

00000000B

UPS2

UPI2 status register

UPDI3/

UPDO3 output register

UPI3 data input register / data

XXXXXXXXB

00006DH

00006EH

UPS3

LCR

UPI3 status register

R/W

00000000B

-----000B

LPC control register

ROM mirroring function selection

register

ROM mirroring

function

00006FH

ROMM

W

------01^B

Timer control status register CH1

(lower)

000070H TMCSRL1

000071H TMCSRH1

R/W

00000000B

Timer control status register CH1

(upper)

16-bit reload

timer (CH1)

----0000B

000072H

000073H

R/W

XXXXXXXX^B

TMR1/

TMRD1

16-bit timer/reload register CH1

XXXXXXXXB

(Continued)

29

MB90370/375 Series

Abbrevia-

Byte

access access

Word

Resource

name

Address

Register

Initial value

00000000B

----0000B

tion

Timer control status register CH2

(lower)

000074^HTMCSRL2

000075H TMCSRH2

R/W

Timer control status register CH2

(upper)

16-bit reload

timer (CH2)

000076H

000077H

R/W

XXXXXXXX^B

XXXXXXXXB

TMR2/

TMRD2

16-bit timer/reload register CH2

Timer control status register CH3

(lower)

000078H TMCSRL3

000079H TMCSRH3

R/W

00000000B

----0000B

Timer control status register CH3

(upper)

16-bit reload

timer (CH3)

00007AH

00007BH

R/W

XXXXXXXX^B

XXXXXXXXB

TMR3/

TMRD3

16-bit timer/reload register CH3

Timer control status register CH4

(lower)

00007CH TMCSRL4

00007DH TMCSRH4

R/W

00000000^B

----0000B

Timer control status register CH4

(upper)

16-bit reload

timer (CH4)

00007EH

00007FH

000080H

000081H

000082H

000083H

000084H

000085H

000086H

000087H

000088H

000089H

00008AH

00008BH

R/W

R

XXXXXXXX^B

XXXXXXXXB

----0000^B

TMR4/

TMRD4

16-bit timer/reload register CH4

IBCRL

IBCRH

IBSRL

IBSRH

IDAR

IADR

ICCR

ITCR

I²C bus control register (lower)

I²C bus control register (upper)

I²C bus status register (lower)

I²C bus status register (upper)

I²C data register

R/W

R

00000000B

--000000B

R/W

XXXXXXXXB

-XXXXXXXB

0-000000B

-0-00000B

I²C address register

I²C

I²C clock control register

I²C timeout control register

I²C timeout clock register

I²C timeout data register

I²C slave timeout register

I²C master timeout register

ITOC

ITOD

ISTO

00000000B

IMTO

Port 0 pull-up resistor setting

register

00008CH

00008DH

00008EH

00008FH

RDR0

RDR1

RDR2

RDR3

R/W

Port 0

Port 1

Port 2

Port 3

00000000B

Port 1 pull-up resistor setting

register

Port 2 pull-up resistor setting

register

Port 3 pull-up resistor setting

register

00000000B

(Continued)

30

MB90370/375 Series

Abbrevia-

tion

Byte

access access

Word

Resource

name

Address

Register

Initial value

000090^H

to 9DH

Prohibited area

Program address detect control

status register

00009EH

00009FH

PACSR

DIRR

R/W

ROM correction

----0000B

-------0B

Delayed interrupt cause / clear

register

Delayed

interrupt

Low-power consumption mode

register

Low-power

consumption

control register

0000A0H

0000A1H

LPMCR

R/W

00011000^B

11111100B

CKSCR Clock selection register

0000A2H

to A7H

Prohibited area

R/W

0000A8^H

0000A9H

0000AAH

0000ABH

0000AC^H

0000ADH

WDTC

TBTC

WTC

Watchdog control register

R/W

Watchdog timer X-XXX111B

Timebase timer 1--00100B

Timebase timer control register

Watch timer control register

R/W

Watch timer

10001000B

Prohibited area

EICR

EIFR

Wake-up interrupt control register

R/W

00000000B

-------0B

Wake-up

interrupt

Wake-up interrupt flag register

Flash memory control status

register

Flash memory

interface circuit

0000AEH

FMCS

R/W

00010000B

0000AFH

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

Prohibited area

R/W

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

R/W

00000111B

R/W

Interrupt

controller

R/W

00000111B

(Continued)

31

MB90370/375 Series

Abbrevia-

Byte

access access

Word

Resource

name

Address

Register

Initial value

tion

0000BB^H

0000BCH

0000BDH

0000BEH

0000BFH

0000C0H

0000C1H

0000C2H

0000C3H

0000C4H

0000C5H

0000C6H

0000C7H

0000C8H

0000C9H

0000CAH

0000CBH

0000CCH

0000CDH

0000CEH

0000CFH

0000D0H

0000D1H

0000D2H

0000D3H

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

R/W

R

R/W

R

00000111B

----0000^B

Interrupt

controller

MBCRL MI²C bus control register (lower)

MBCRH MI²C bus control register (upper)

MBSRL MI²C bus status register (lower)

MBSRH MI²C bus status register (upper)

00000000B

--000000B

R/W

MDAR

MI²C data register

MI²C alert register

XXXXXXXXB

----0000B

MALR

MADR1 MI²C address register 1

MADR2 MI²C address register 2

MADR3 MI²C address register 3

MADR4 MI²C address register 4

MADR5 MI²C address register 5

MADR6 MI²C address register 6

-XXXXXXXB

0-000000B

-0-00000B

MI²C

MCCR

MTCR

MTOC

MTOD

MSTO

MMTO

SMR2

SCR2

MI²C clock control register

MI²C timeout control register

MI²C timeout clock register

MI²C timeout data register

MI²C slave timeout register

MI²C master timeout register

Serial mode register 2

00000000B

00000-00^B

00000100B

Serial control register 2

SIDR2/

Input data register 2 /

0000D4H

R/W

UART2

XXXXXXXXB

SODR2 output data register 2

0000D5H

0000D6H

SSR2 Status register 2

R/W

00001000B

----1000B

M2CR2 Mode 2 control register 2

Communication

prescaler 2

0000D7H

CDCR2 Clock division control register 2

R/W

0---0000B

(Continued)

32

MB90370/375 Series

Abbrevia-

tion

Byte

access access

Word

Resource

name

Address

0000D8^H

0000D9H

0000DAH

0000DBH

0000DCH

0000DDH

0000DEH

0000DFH

Register

Initial value

--000000B

Comparator control register

(lower)

COCRL

COCRH

COSRL1

COSRH1

CICRL

R/W

R

R/W

R

Comparator control register

(upper)

00011111B

00000000B

--000000B

Comparator status register 1

(lower)

Comparator status register 1

(upper)

Voltage

comparator

Comparator interrupt control

register (lower)

00000000B

--000000B

Comparator interrupt control

register (upper)

CICRH

Comparator status register 2

(lower)

COSRL2

COSRH2

XXXXXXXXB

--XXXXXXB

Comparator status register 2

(upper)

R

0000E0H

0000E1H

0000E2H

0000E3H

0000E4H

0000E5H

CIER

BDR

Comparator input enable register

Bit data register

R/W

R

R/W

R

---11111B

----XXXXB

BRRL

BRRH

SMR3

SCR3

SIDR3/

Bit result register (lower)

Bit result register (upper)

Serial mode register 3

Serial control register 3

Input data register 3 /

Bit decoder

UART3

XXXXXXXXB

00000-00B

00000100B

R

R/W

0000E6H

R/W

XXXXXXXXB

SODR3 output data register 3

0000E7H

0000E8H

SSR3 Status register 3

R/W

00001000B

----1000B

M2CR3 Mode 2 control register 3

Communication

prescaler 3

0000E9H

CDCR3 Clock division control register 3

R/W

0---0000B

0000EAH

PDL3

Port 3 data latch register

R/W Port 3 data latch 00000000B

0000EBH

to EDH

Prohibited area

0000EE^H

0000EFH

LCRL*¹LCD control register 0*²

LCRH*¹LCD control register 1*²

R/W

00010000B

LCD controller / 00000000B

driver

0000F0H

to F4H

VRAM*¹LCD display RAM*²

R/W

Prohibited area

External area

XXXXXXXXB

0000F5H

to F7H

0000F8^H

to FFH

(Continued)

33

MB90370/375 Series

Abbrevia-

Byte

access access

Word

Resource

name

Address

001FF0^H

001FF1H

001FF2H

001FF3H

001FF4H

001FF5H

Register

Initial value

XXXXXXXXB

tion

Program address detection

register 0

R/W

Program address detection

register 1

PADR0

Program address detection

register 2

ROM correction

Program address detection

register 3

Program address detection

register 4

PADR1

Program address detection

register 5

003FC0H

003FC1H

003FC2H

003FC3H

003FC4H

003FC5H

003FC6H

003FC7H

003FC8H

003FC9H

003FCAH

003FCBH

003FCCH

003FCDH

003FCEH

003FCFH

003FD0H

003FD1H

003FD2H

003FD3H

UDRL0 UP data register 0 (lower)

UDRH0 UP data register 0 (upper)

UDRL1 UP data register 1 (lower)

UDRH1 UP data register 1 (upper)

UDRL2 UP data register 2 (lower)

UDRH2 UP data register 2 (upper)

UDRL3 UP data register 3 (lower)

UDRH3 UP data register 3 (upper)

UDRL4 UP data register 4 (lower)

UDRH4 UP data register 4 (upper)

UDRL5 UP data register 5 (lower)

UDRH5 UP data register 5 (upper)

UDRL6 UP data register 6 (lower)

UDRH6 UP data register 6 (upper)

UDRL7 UP data register 7 (lower)

UDRH7 UP data register 7 (upper)

UDRL8 UP data register 8 (lower)

UDRH8 UP data register 8 (upper)

UDRL9 UP data register 9 (lower)

UDRH9 UP data register 9 (upper)

R/W

XXXXXXXX^B

XXXXXXXXB

(Continued)

LPC data buffer

array

34

MB90370/375 Series

(Continued)

Abbrevia-

tion

Byte

access access

Word

Resource

name

Address

Register

Initial value

003FD4^H

003FD5H

003FD6H

003FD7H

003FD8H

003FD9H

003FDAH

003FDBH

003FDCH

003FDDH

003FDEH

003FDFH

003FE0H

003FE1H

003FE2H

003FE3H

003FE4H

003FE5H

003FE6H

003FE7H

003FE8H

003FE9H

003FEAH

003FEBH

003FECH

003FEDH

003FEEH

003FEFH

UDRLA UP data register A (lower)

UDRHA UP data register A (upper)

UDRLB UP data register B (lower)

UDRHB UP data register B (upper)

UDRLC UP data register C (lower)

UDRHC UP data register C (upper)

UDRLD UP data register D (lower)

UDRHD UP data register D (upper)

UDRLE UP data register E (lower)

UDRHE UP data register E (upper)

UDRLF UP data register F (lower)

UDRHF UP data register F (upper)

DNDL0 DOWN data register 0 (lower)

DNDH0 DOWN data register 0 (upper)

DNDL1 DOWN data register 1 (lower)

DNDH1 DOWN data register 1 (upper)

DNDL2 DOWN data register 2 (lower)

DNDH2 DOWN data register 2 (upper)

DNDL3 DOWN data register 3 (lower)

DNDH3 DOWN data register 3 (upper)

DNDL4 DOWN data register 4 (lower)

DNDH4 DOWN data register 4 (upper)

DNDL5 DOWN data register 5 (lower)

DNDH5 DOWN data register 5 (upper)

DNDL6 DOWN data register 6 (lower)

DNDH6 DOWN data register 6 (upper)

DNDL7 DOWN data register 7 (lower)

DNDH7 DOWN data register 7 (upper)

R/W

R

R/W

R

XXXXXXXXB

R

LPC data buffer

array

R

Data buffer array address register

003FF0H

003FF1H

DBAAL

(lower)

R/W

XXXXXXXXB

Data buffer array address register

DBAAH

(upper)

003FF2H

to

Prohibited area

003FFFH

35

MB90370/375 Series

• Meaning of abbreviations used for reading and writing

R/W : Read and write enabled

R :

Read-only

Write-only

W :

• Explanation of initial values

0 :

1 :

X :

- :

The bit is initialized to 0.

The bit is initialized to 1.

The initial value of the bit is undefined.

The bit is not used. Its initial value is undefined.

• Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FC0^Hto 003FFF^H.

*1 : It doesn’t exist in MB90F377.

*2 : Prohibited area in MB90F377.

36

MB90370/375 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control

EI²OS

support

Interrupt vector

register

Interrupt cause

Priority*2

Number Address ICR

#08 08^HFFFFDCH

#09 09^HFFFFD8H

#10 0A^HFFFFD4H

#11 0B^HFFFFD0H

Address

Reset

X

High

INT9 instruction

Exception processing

A/D converter conversion termination

Timebase timer

*1

*2

*1

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H

ICR04 0000B4H

ICR05 0000B5H

ICR06 0000B6H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

#12 0CH FFFFCCH

#13 0DH FFFFC8H

#14 0EH FFFFC4H

#15 0FH FFFFC0H

#16 10H FFFFBCH

#17 11H FFFFB8H

#18 12H FFFFB4H

#19 13H FFFFB0H

#20 14H FFFFACH

#21 15H FFFFA8H

#22 16H FFFFA4H

#23 17H FFFFA0H

#24 18H FFFF9CH

#25 19H FFFF98H

#26 1AH FFFF94H

#27 1BH FFFF90H

#28 1CH FFFF8CH

#29 1DH FFFF88H

#30 1EH FFFF84H

#31 1FH FFFF80H

#32 20H FFFF7CH

#33 21H FFFF78H

#34 22H FFFF74H

#35 23H FFFF70H

#36 24H FFFF6CH

#37 25H FFFF68H

#38 26H FFFF64H

#39 27H FFFF60H

#40 28H FFFF5CH

#41 29H FFFF58H

#42 2AH FFFF54H

UPI0 IBF / LPC reset

UPI1 IBF

UPI2 IBF

UPI3 IBF

DTP/ext. interrupt channels 0/1 detection

DTP/ext. interrupt channels 2/3 detection

DTP/ext. interrupt channels 4/5 detection

Wake-up interrupt detection

UPI0/1/2/3 OBE

16-bit PPG timer 1

PS/2 interface 0/1

PS/2 interface 2

Watch timer

I²C transfer complete / bus error

16-bit PPG timer 2/3

Voltage comparator 1

MI²C transfer complete / bus error

Voltage comparator 2

I²C timeout / standby wake-up

16-bit reload timer 1/2 underflow

MI²C timeout / standby wake-up

16-bit reload timer 3/4 underflow

UART1 receive

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

ICR13 0000BDH

ICR14 0000BEH

*1

UART1 send

UART2 receive

UART2 send

UART3 receive

UART3 send

Flash memory status

Delayed interrupt generator module

*1

Low

ICR15 0000BFH

37

MB90370/375 Series

: Can be used and interrupt request flag is cleared by EI²OS interrupt clear signal.

× : Cannot be used.

: Can be used and support the EI²OS stop request.

: Can be used.

*1 : • For peripheral functions that share the ICR register, the interrupt level will be the same.

• If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with

anotherperipheralfunction, theservicecanbestartedbyeitherofthefunction. AndifEI²OSclearissupported,

both interrupt request flags for the two interrupt causes are cleared by EI²OS interrupt clear signal. It is

recommended to mask either of the interrupt request during the use of EI²OS.

• EI²OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt is

masked during EI²OS operation. It is recommended to mask either of the interrupt requests during the use

of EI²OS.

*2 : This priority is applied when interrupts of the same level occur simultaneously.

38

MB90370/375 Series

■ PERIPHERAL RESOURCES

1. Low-power Consumption Control Circuit

The MB90370/375 series has the following CPU operating mode selected by the configuration of an operating

clock and clock operation control.

• Clock Mode

• PLL clock mode

In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and

peripheral functions.

• Main clock mode

In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate

the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.

• Sub-clock mode

In this mode, the sub-clock, with the sub-clock (SCLK) frequency divided by 4 is used to operate the CPU

and peripheral functions. In the sub-clock mode, the main clock and PLL multiplier circuit are inactive.

• CPU Intermittent Operating Mode

In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral func-

tions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to the CPU

while it is accessing a register, internal memory, or peripheral function.

• Standby Mode

In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode) or

the CPU and peripheral functions (timebase timer mode) or stops the oscillation clock itself (stop mode) , thereby

reducing power consumption.

• PLL sleep mode

The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components

excluding the CPU operate on the PLL clock.

• Main sleep mode

The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components

excluding the CPU operate on the main clock.

• Sub-sleep mode

The sub-sleep mode is activated to stop the CPU operating clock in the sub-clock mode. Components

excluding the CPU operate on the divided-by-four sub-clock.

• Timebase timer mode

The timebase timer mode causes the operation of functions, excluding the oscillation clock, timebase timer,

and watch timer, to stop. All functions other than the timebase timer and watch timer are inactivated.

• Watch mode and main watch mode

The watch mode and main watch mode operates the watch timer only. The sub-clock operates but the

main clock and PLL multiplier circuit stop.

• Stop mode

The stop mode causes the oscillation to stop. All functions are inactivated.

Note : Because the stop mode turns the oscillation clock off, data can be retained by the lowest power consumption.

39

MB90370/375 Series

(1) Register configuration

Clock Selection Register

Bit number

CKSCR

15

14

13

12

11

10

9

8

Address :0000A1^H

SCM

MCM

WS1

WS0

SCS

MCS

CS1

CS0

R

1

R

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

0

R/W

0

Read/write

Initial value

Lower Power Consumption Mode Control Register

Bit number

LPMCR

7

6

5

4

3

2

1

0

Address :0000A0^H

STP

SLP

SPL

RST

TMD

CG1

CG0 Reserved

W

0

W

0

R/W

0

W

1

W

1

R/W

0

R/W

0

R/W

0

Read/write

Initial value

(2) Block diagram

Low power consumption mode control register (LPMCR)

STP SLP SPL RST TMD CG1 CG0 RESV

Pin high-

Pin Hi-Z control

Internal reset

impedance

control circuit

Internal reset

generation

circuit

RST

CPU intermittent

operation selector

Intermittent cycle

selection

CPU clock

control circuit

CPU clock pulse

2

Standby

control circuit

Stop and sleep signals

Interrupt clearing

Stop signal

Peripheral

clock control

circuit

Machine clock

Peripheral clock

Oscillation stabiliza-

tion wait clearing

Clock genera-

tion part

Oscillation

stabilization

wait time

selector

Clock selector

2

Divide-

by-4

Subclock

2

PLL multiplier

circuit

Subclock

SCM MCM WS1 WS0 SCS MCS CS1 CS0

Clock selection register (CKSCR)

generation

circuit

System clock

generation

circuit

X0A

X1A

Divide-

by-4

Divide-

by-4

Divide-

by-8

Divide-

by-16

Divide-

by-128

Divide-

by-2

X0

Main clock

Timebase timer

X1 Pin

40

MB90370/375 Series

2. I/O Ports

(1) Outline of I/O ports

Each I/O port outputs data from the CPU to the I/O pins or inputs signals from the I/O pins to the CPU as directed

by the port data register (PDR) . Each CMOS I/O port can also designate the direction of a data flow (input or

output) at the I/O pins in bit units using the port data direction register (DDR) . Or N-channel open-drain port

can designate the direction of a data flow (input or output) at the I/O pins in bit units using the port data register

(PDR) . The function of each port and the resources using it are described below :

• Port 0

• Port 1

• Port 2

• Port 3

• Port 4

• Port 5

• Port 6

• Port 7

• Port 8

• Port 9

• Port A

• Port B

• Port C

• Port D

• Port E

• Port F

: General-purpose I/O port/resource (Key-on wake-up interrupt)

: General-purpose I/O port

: General-purpose I/O port/resource (A/D converter external trigger)

: General-purpose I/O port/resource (PS/2 interface / serial IRQ controller)

: General-purpose I/O port/resource (LPC interface)

: General-purpose I/O port/resource (DTP / UART1)

: General-purpose I/O port/resource (UART1 / UART2 / UART3 / PPG1)

: General-purpose I/O port/resource (Multi-address I²C)

: General-purpose I/O port/resource (I²C / Multi-address I²C)

: General-purpose I/O port/resource (Comparator)

: General-purpose I/O port/resource (Comparator / A/D converter)

: General-purpose I/O port/resource (A/D converter / D/A converter / PPG2 / PPG3)

: General-purpose I/O port/resource (Reload timer1 to 4 / LCD controller*)

: General-purpose I/O port/resource (LCD controller*)

* : LCD controller doesn’t exist in MB90F377, and so Port E and F of MB90F377 are not used for this purpose.

(2) Register configuration

Register

Port 0 data register (PDR0)

Read/Write

R/W

Address

000000^H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

00000AH

00000BH

00000CH

00000DH

00000EH

Initial value

XXXXXXXXB

X1111111B

XXXXXXXXB

-----111B

Port 1 data register (PDR1)

Port 2 data register (PDR2)

Port 3 data register (PDR3)

Port 4 data register (PDR4)

Port 5 data register (PDR5)

Port 6 data register (PDR6)

Port 7 data register (PDR7)

Port 8 data register (PDR8)

Port 9 data register (PDR9)

Port A data register (PDRA)

Port B data register (PDRB)

Port C data register (PDRC)

Port D data register (PDRD)

Port E data register (PDRE)

R/W

--111111B

R/W

-XXXXXXXB

XXXXXXXXB

R/W

XXXXXXXXB

(Continued)

41

MB90370/375 Series

(Continued)

Register

Read/Write

R/W

Address

00000F^H

000010H

000011H

000012H

000013H

000014H

000015H

000016H

000017H

00001AH

00001BH

00001CH

00001DH

00001EH

00001FH

00002AH

00002BH

0000E0H

0000EFH

00008CH

00008DH

00008EH

00008FH

0000EAH

Initial value

XXXXXXXXB

00000000B

0-------B

Port F data register (PDRF)

Port 0 data direction register (DDR0)

Port 1 data direction register (DDR1)

Port 2 data direction register (DDR2)

Port 3 data direction register (DDR3)

Port 4 data direction register (DDR4)

Port 5 data direction register (DDR5)

Port 6 data direction register (DDR6)

Port 7 data direction register (DDR7)

Port A data direction register (DDRA)

Port B data direction register (DDRB)

Port C data direction register (DDRC)

Port D data direction register (DDRD)

Port E data direction register (DDRE)

Port F data direction register (DDRF)

Analog data input enable register (ADER1)

Analog data input enable register (ADER2)

Comparator input enable register (CIER)

LCD control register 1 (LCRH)

00000000B

-0000000B

00000000B

11111111B

----1111B

---11111B

00000000B

Port 0 pull-up resistor setting register (RDR0)

Port 1 pull-up resistor setting register (RDR1)

Port 2 pull-up resistor setting register (RDR2)

Port 3 pull-up resistor setting register (RDR3)

Port 3 data latch register (PDL3)

R/W : Read/write enabled

X

-

: Undefined

: Not used

42

MB90370/375 Series

(3) Block diagram of I/O ports

• Block diagram of port 0 pins

RDR

Resource input

Port data register (PDR)

Pull-up resistor

About 50 kΩ

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

• Block diagram of port 1 pins

RDR

Port data register (PDR)

Pull-up resistor

About 50 kΩ

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

43

MB90370/375 Series

• Block diagram of port 2 pins

RDR

Port data register (PDR)

Pull-up resistor

About 50 kΩ

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

• Block diagram of port 3 pins

RDR

Resource input

Port data register (PDR)

Pull-up resistor

About 50 kΩ

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

Port data latch register (PDL)

Input latch

R

44

MB90370/375 Series

• Block diagram of port 47 pin

Resource output

Resource input

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

• Block diagram of port 46 pin

Resource output

Resource input

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Read-Modify-Write instruction

Standby control (SPL = 1)

45

MB90370/375 Series

• Block diagram of port 45 to 40 pins

Resource output

Resource input

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Read-Modify-Write instruction

Standby control (SPL = 1)

• Block diagram of port 5 pins

Resource output

Resource input

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

46

MB90370/375 Series

• Block diagram of port 6 pins

Resource output

Resource input

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

• Block diagram of port 7 pins

Resource output

Resource input

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

47

MB90370/375 Series

• Block diagram of port 8 pins

Port data register (PDR)

Resource output

Resource input

Resource output enable

PDR read

Output latch

PDR write

Read-Modify-Write instruction

Standby control (SPL = 1)

• Block diagram of port 9 pins

Resource output

Resource input

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Read-Modify-Write instruction

Standby control (SPL = 1)

48

MB90370/375 Series

• Block diagram of port A pins

Resource output

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

• Block diagram of port B pins

CIER

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

Comparator

operation

enable

Standby control (SPL = 1)

Comparator input

DDR read

49

MB90370/375 Series

• Block diagram of port C7 to C3 pins

ADER

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

A/D converter

channel

selection bit

Standby control (SPL = 1)

DDR read

to A/D converter analog input

• Block diagram of port C2 to C0 pins

CIER

Comparator operation

enable bit

Comparator

(COCRH)

ADER

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

A/D converter

channel

selection bit

Standby control (SPL = 1)

DDR read

to A/D converter analog input

50

MB90370/375 Series

• Block diagram of port D7 and D6 pins

Resource output

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

• Block diagram of port D5 and D4 pins

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

Analog output

D/A output enable

51

MB90370/375 Series

• Block diagram of port D3 to D0 pins

ADER

A/D input

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

• Block diagram of port E pins (not for MB90F377)

Resource output

Resource input

Resource output enable

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

LCD output

LCD output enable

52

MB90370/375 Series

• Block diagram of port F7 to F5 pins (not for MB90F377)

LCRH

VS

LCD input (V1 to V3)

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

Standby control (SPL = 1)

DDR read

• Block diagram of port F4 to F0 pins (not for MB90F377)

Port data register (PDR)

PDR read

Output latch

PDR write

Port data direction register (DDR)

Direction latch

DDR write

DDR read

Standby control (SPL = 1)

LCD output

LCD output enable

53

MB90370/375 Series

3. Timebase timer

The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with

the internal count clock (one-half of the source oscillation) .

Features of timebase timer :

• Interrupt generated when counter overflow

• EI²OS supported

• Interval timer function :

An interrupt generated at four different time intervals

• Clock supply function :

Four different clocks can be selected as watchdog timer’s count clock.

Supply clock for oscillation stabilization

(1) Register configuration

Timebase Timer Control Register

Bit number

TBTC

15

14

13

12

11

10

9

8

Address :0000A9^H

Reserved

TBIE

TBOF

TBR

TBC1

TBC0

R/W

1

R/W

0

R/W

0

R/W

1

R/W

0

R/W

0

Read/write

Initial value

(2) Block diagram of timebase timer

Timebase

To watchdog timer

timer counter

Divide-by

-two HCLK

×2¹×2²×2³

×2⁷× 2⁸×2⁹×2¹⁰×2¹¹×2¹²×2¹³×2¹⁴×2¹⁵×2¹⁶×2¹⁷×2¹⁸

OF OF OF OF

To the oscillation

stabilization wait

time selector in the

clock control

section

Power-on reset

Stop mode start

Counter

clear circuit

Interval

timer selector

CKSCR : MCS = 1 → 0 (*1)

SCS = 1 → 0 (*2)

TBOF set

Timebase timer

interrupt signal

#12 (0CH)

RESV

TBIE TBOF TBR TBC1 TBC0

Timebase timer interrupt register (TBTC)

: Unused

OF : Overflow

HCLK : Oscillation clock

*1 : Switching of the machine clock from the oscillation clock to the PLL clock

*2 : Switching from main clock to sub-clock

54

MB90370/375 Series

4. Watchdog timer

The watchdog timer is a 2-bit counter that uses the timebase timer’s supply clock as the count clock. After

activation, if the watchdog timer is not cleared within a given period, the CPU will be reset.

• Features of watchdog timer :

Reset CPU at four different time intervals

Status bits to indicate the reset causes

(1) Register configuration of watchdog timer

Watchdog Timer Control Register

Bit number

WDTC

7

6

5

4

3

2

1

0

Address :0000A8^H

PONR

WRST ERST

SRST

WTE

WT1

WT0

R

X

R

X

R

X

R

X

W

1

W

1

W

1

Read/write

Initial value

(2) Block diagram of watchdog timer

Watchdog timer control register (WDTC)

WDCS (from watch timer

control register, WTC)

PONR

WRST ERST SRST WTE WT1 WT0

2

Watchdog timer

Activation with CLR

Count

CLR

To the

Start of watch mode

Start of sleep mode

Start of stop mode

reset generation

Counter

clear control

circuit

Watchdog

Overflow

2-bit

internal

reset

clock

reset

generator

counter

selector

generator

CLK

4

(Timebase timer counter)

×2¹×2²×2⁸×2⁹×2¹⁰×2¹¹×2¹²×2¹³×2¹⁴×2¹⁵×2¹⁶×2¹⁷×2¹⁸

One-half of HCLK

×2¹×2²

×2¹⁰×2¹¹×2¹²×2¹³×2¹⁴×2¹⁵

Sub-clock divide by 4

Watch timer counter

HCLK : Oscillation clock

55

MB90370/375 Series

5. Watch timer

The watch timer is a 15-bit timer that uses sub-clocks and can generate an interval interrupt. It can also be used

as the watchdog timer clock source and sub-clock oscillation wait time.

Features of the watch timer :

• Provides the watchdog timer clock source

• Sub-clock oscillation stabilization wait timer function

• Interval timer function that generates interrupts in a given cycle

(1) Register configuration of watch timer

Watch Timer Control Register

Bit number

WTC

7

6

5

4

3

2

1

0

Address : 0000AA^H

WDCS

SCE

WTIE

WTOF

WTR

WTC2 WTC1 WTC0

R/W

1

R

0

R/W

0

R/W

0

W

1

R/W

0

R/W

0

R/W

0

Read/write

Initial value

(2) Block diagram of watch timer

Watch timer control register (WTC)

SCE WTIE WTOF WTR WTC2 WTC1 WTC0

WDCS

2⁸

2⁹

Clear

2¹⁰

2¹¹

2¹²

2¹³

2¹⁴

2¹⁵

Interrupt

generator

Watch counter

Interval selector

Watch

timer

interrupt

The subclock

divided by 4

2¹⁰

2¹³

2¹⁴

2¹⁵

To the

watchdog

timer

56

MB90370/375 Series

6. 16-bit PPG timer (× 3)

The 16-bit PPG (Programmable Pulse Generator) timer consists of a 16-bit down counter, prescaler, 16-bit

period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin.

Features of 16-bit PPG timer :

• 8typesofcounteroperationclock(φ,φ/2,φ/4,φ/8,φ/16,φ/32,φ/64,φ/128)canbeselected(φ isthemachineclock)

• An interrupt is generated when there is a trigger or a counter borrow or when PPG rising (normal polarity) /

PPG falling (inverted polarity) .

• PPG output operation

The 16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be used as

D/A converter in conjunction with an external circuit.

(1) Register configuration of PPG timer

PPG Down Counter Register (Upper)

Address : ch1 000039^H

ch2 000041H

Bit number

PDCRH1 to

PDCRH3

15

14

13

12

11

10

9

1

9

1

8

0

8

0

ch3 000049H

DC15

DC14

DC13

DC12

DC11

DC10

DC09

DC08

Read/write

Initial value

R

1

R

1

R

1

R

1

R

1

R

1

R

1

R

1

PPG Down Counter Register (Lower)

Address : ch1 000038^H

ch2 000040H

Bit number

PDCRL1 to

PDCRL3

7

6

5

4

3

2

ch3 000048H

DC07

DC06

DC05

DC04

DC03

DC02

DC01

DC00

Read/write

Initial value

R

1

R

1

R

1

R

1

R

1

R

1

R

1

R

1

PPG Period Setting Buffer Register (Upper)

Address : ch1 00003B^H

ch2 000043H

Bit number

PCSRH1 to

PCSRH3

15

14

13

12

11

10

ch3 00004BH

CS15

CS14

CS13

CS12

CS11

CS10

CS09

CS08

Read/write

Initial value

W

X

W

X

W

X

W

X

W

X

W

X

W

X

W

X

PPG Period Setting Buffer Register (Lower)

Address : ch1 00003A^H

ch2 000042H

Bit number

PCSRL1 to

PCSRL3

7

6

5

4

3

2

ch3 00004AH

CS07

CS06

CS05

CS04

CS03

CS02

CS01

CS00

Read/write

Initial value

W

X

W

X

W

X

W

X

W

X

W

X

W

X

W

X

(Continued)

57

MB90370/375 Series

(Continued)

PPG Duty Setting Buffer Register (Upper)

Address : ch1 00003D^H

ch2 000045H

Bit number

PDUTH1 to

PDUTH3

15

14

13

12

11

10

9

1

9

8

0

8

0

ch3 00004DH

DU15

DU14

DU13

DU12

DU11

DU10

DU09

DU08

Read/write

Initial value

W

X

W

X

W

X

W

X

W

X

W

X

W

X

W

X

PPG Duty Setting Buffer Register (Lower)

Address : ch1 00003C^H

ch2 000044H

Bit number

PDUTL1 to

PDUTL3

7

6

5

4

3

2

ch3 00004CH

DU07

DU06

DU05

DU04

DU03

DU02

DU01

DU00

Read/write

Initial value

W

X

W

X

W

X

W

X

W

X

W

X

W

X

W

X

PPG Control Status Register (Upper)

Address : ch1 00003F^H

ch2 000047H

Bit number

PCNTH1 to

PCNTH3

15

14

13

12

11

10

ch3 00004FH

CNTE

STGR MDSE RTRG

CKS2

CKS1

CKS0 PGMS

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

PPG Control Status Register (Lower)

Address : ch1 00003E^H

ch2 000046H

Bit number

PCNTL1 to

PCNTL3

7

6

5

4

3

2

1

ch3 00004EH

IREN

IRQF

IRS1

IRS0

POEN

OSEL

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Note : Registers PDCR1 to PDCR3, PCSR1 to PCSR3 and PDUT1 to PDUT3 are word access only.

58

MB90370/375 Series

(2) Block diagram of PPG timer

Period setting buffer

Duty setting buffer

register 1/2/3

Prescaler

Period setting

register 1/2/3

Duty setting

register 1/2/3

CKS2 CKS1 CKS0

1/1

1/2

1/4

1/8

CLK

LOAD

1/16

1/32

1/64

1/128

P77/PPG1

16-bit down counter

STOP

MDSE PGMS OSEL POEN

or

PD6/PPG2

or

PD7/PPG3

START BORROW

Machine clock φ

S

R

Q

Interrupt

selection

Interrupt

#22 (for PPG1)

or

#27 (for PPG2/3)

IRS1 IRS0 IRQF IREN

STGR CNTE RTRG

59

MB90370/375 Series

7. 16-bit reload timer (× 4)

The 16-bit reload timer provides two operating modes, internal clock mode and event count mode. In each

operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot

mode) .

Output pins TO1 to TO4 are able to output different waveform according to the counter operating mode. TO1 to

TO4 toggles when counter underflow if counter is operated as reload mode. TO1 to TO4 output specified level

(“H” or “L”) when counter is counting if the counter is in one-shot mode.

Features of the 16-bit reload timer :

• Interrupt generated when timer underflow

• EI²OS supported

• Internal clock operating mode :

Three internal count clocks can be selected.

Counter can be activated by software or external trigger (signal at TIN1 to TIN4 pin) .

Counter can be reloaded or stopped when underflow after activated.

• Event count operating mode :

Counter counts down by one when specified edge at TIN1 to TIN4 pin.

Counter can be reloaded or stopped when underflow.

(1) Register configuration of reload timer

Timer Control Status Register (Upper)

Address : ch1 000071H

ch2 000075H

Bit number

TMCSRH1 to

TMCSRH4

15

14

13

12

11

10

9

8

ch3 000079H

ch4 00007DH

Read/write

CSL1

CSL0

MOD2 MOD1

R/W

0

R/W

0

R/W

0

R/W

0

Initial value

Timer Control Status Register (Lower)

Address : ch1 000070^H

ch2 000074H

ch3 000078H

ch4 00007CH

Read/write

Initial value

Bit number

TMCSRL1 to

TMCSRL4

7

6

5

4

3

2

1

0

MOD0 OUTE OUTL

RELD

INTE

UF

CNTE

TRG

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

16-bit Timer Register / 16-bit Reload Register (Upper)

Address : ch1 000073^H

ch2 000077H

Bit number

TMR1 to TMR4/

TMRD1 to

TMRD4

15

14

13

12

11

10

9

8

ch3 00007BH

ch4 00007FH

Read/write

D15

D14

D13

D12

D11

D10

D09

D08

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Initial value

16-bit Timer Register / 16-bit Reload Register (Lower)

Address : ch1 000072^H

ch2 000076H

Bit number

TMR1 to TMR4/

TMRD1 to

TMRD4

7

6

5

4

3

2

1

0

ch3 00007AH

ch4 00007EH

Read/write

D07

D06

D05

D04

D03

D02

D01

D00

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Initial value

60

MB90370/375 Series

(2) Block diagram of reload timer

F²MC-16LX Bus

TMRD1*¹

<TMRD2, 3, 4>

16-bit reload register

Reload

control

circuit

Reload signal

TMR1*¹

<TMR2, 3, 4>

16-bit timer register

CLK

Count clock generation

circuit

Gate

input

Valid

3

Machine

clock

Wait signal

clock

Prescaler

judgment

circuit

To UART1*¹

<UART2, UART3,

A/D converter>

CLK

Clear

PE0/TIN1/SEG0

PE2/TIN2/SEG2

PE4/TIN3/SEG4

PE6/TIN4/SEG6

Output control circuit

Internal

clock

Output signal

generation

Input

control

circuit

Clock

selector

Invert

circuit

External clock

PE1/TO1/SEG1

PE3/TO2/SEG3

PE5/TO3/SEG5

PE7/TO4/SEG7

EN

3

2

Select

signal

Operation

control

circuit

Function selection

CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register TMCSR1*¹

<TMCSR2,3,4>

Interrupt request signal

2

#32 (20H)*^1,

<#34 (22H)>

*

*1 : This register includes channel 1, 2, 3 and 4. The register enclosed in “<” and “>” indicates the

channel 2, 3 and 4 register.

*2 : Interrupt numbers : channel 1 and 2 share one interrupt number, channel 3 and 4 share another.

61

MB90370/375 Series

8. I²C

The I²C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line

(SDA)andaserialclockline(SCL). Amongthedevicesconnectedwiththesetwowires, informationistransmitted

to one another. By recognizing the unique address of each device, it can operate as a transmitting or receiving

device in accordance with the function of each device. Among these devices, the master/slave relation is estab-

lished.

The I²C interface can connect two or more devices to the bus provided the upper limit of the bus capacitance

does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and communication

adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data

transfer simultaneously.

The communication adjustment procedure permits only one master to control the bus when two or more masters

attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multi-

master means that multiple masters attempt to control the bus simultaneously without losing messages.

This I²C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that performs automatic

Packet Error Code (PEC) generation and verification.

(1) Register configuration of I²C

I²C Bus Control Register (Lower)

Bit number

IBCRL

7

6

5

4

3

2

1

0

Address : 000080^H

RES

PECE

LBT

WUE

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

I²C Bus Control Register (Upper)

Bit number

IBCRH

15

14

13

12

11

10

9

8

Address : 000081^H

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

I²C Bus Status Register (Lower)

Bit number

IBSRL

7

6

5

4

3

2

1

0

Address : 000082^H

BB

RSC

AL

LRB

TRX

AAS

GCA

FBT

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Read/write

Initial value

I²C Bus Status Register (Upper)

Bit number

IBSRH

15

14

13

12

11

10

9

8

Address : 000083^H

PMATCH WUF

TDR

TCR

MTR

STR

R

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

I²C Data Register

Bit number

IDAR

7

6

5

4

3

2

1

0

Address : 000084^H

D7

D6

D5

D4

D3

D2

D1

D0

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

(Continued)

62

MB90370/375 Series

(Continued)

I²C Address Register

Bit number

IADR

15

14

A6

13

A5

12

A4

11

A3

10

A2

9

8

Address : 000085^H

A1

A0

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

I²C Clock Control Register

Bit number

ICCR

7

6

5

4

3

2

1

0

Address : 000086^H

DMBP

EN

CS4

CS3

CS2

CS1

CS0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

I²C Timeout Control Register

Bit number

ITCR

15

14

13

12

11

10

9

8

Address : 000087^H

AAC

TOE

EXT

TS2

TS1

TS0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

I²C Timeout Clock Register

Bit number

ITOC

7

6

5

4

3

2

1

0

Address : 000088^H

C7

C6

C5

C4

C3

C2

C1

C0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

I²C Timeout Data Register

Bit number

ITOD

15

14

13

12

11

10

9

8

Address : 000089^H

D7

D6

D5

D4

D3

D2

D1

D0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

I²C Slave Timeout Register

Bit number

ISTO

7

6

5

4

3

2

1

0

Address : 00008A^H

S6

S5

S4

S3

S2

S1

S0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

I²C Master Timeout Register

Bit number

IMTO

15

14

13

12

11

10

9

8

Address : 00008B^H

M7

M6

M5

M4

M3

M2

M1

M0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

63

MB90370/375 Series

(2) Block diagram of I²C

I²C enable

ICCR

Peripheral clock

Clock frequency divider 1

8

DMBP

EN

5

6

7

Clock selector 1

CS4

CS3

Clock frequency divider 2

CS2

CS1

CS0

Sync

4

8

16 32

64 128

256 512

Shift clock

generator

Clock selector 2

IBSRL

Shift clock edge

BB

RSC

LRB

TRX

FBT

Bus busy

Repeat start

Start/stop condition

detector

Last bit

Transmission/

reception

Error

First byte

AL

Arbitration lost detector

IBCRH

BER

BEIE

INTE

INT

Interrupt #26

End

Start

SCC

MSS

ACK

Master

Start/stop condition

generator

Enables ACK

Enables GC-ACK

GCAA

CRC-8 calculator

IDAR register

IBCRL

LBT

IBSRL

Slave

AAS

GCA

Slave address comparator

General call

IADR register

ITCR

TDR

Timeout detector

SCL line

IBSRH

SDA line

TCR

MTR

STR

ITOD

ITOC

ISTO

IMTO

IBCRL

Interrupt #31

WUE

WUF

IBSRH

64

MB90370/375 Series

9. MI²C

The Multi-address I²C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a

serial data line (SDA) and a serial clock line (SCL) . Among the devices connected with these two wires,

information is transmitted to one another. By recognizing the unique address of each device, it can operate as

a transmitting or receiving device in accordance with the function of each device. Among these devices, the

master/slave relation is established.

The Multi-address I²C interface can connect two or more devices to the bus provided the upper limit of the bus

capacitance does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and

communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt

to start data transfer simultaneously. This macro provides 6 addresses to implement the multi-address function.

The communication adjustment procedure permits only one master to control the bus when two or more masters

attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multi-

master means that multiple masters attempt to control the bus simultaneously without losing messages.

This Multi-address I²C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that

performs automatic Packet Error Code (PEC) generation and verification.

(1) Register configuration of MI²C

Multi-address I²C Bus Control Register (Lower)

Bit number

MBCRL

7

6

5

4

3

2

1

0

Address : 0000C0^H

RES

PECE

LBT

WUE

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Multi-address I²C Bus Control Register (Upper)

Bit number

MBCRH

15

14

13

12

11

10

9

8

Address : 0000C1^H

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Multi-address I²C Bus Status Register (Lower)

Bit number

MBSRL

7

6

5

4

3

2

1

0

Address : 0000C2^H

BB

RSC

AL

LRB

TRX

AAS

GCA

FBT

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Read/write

Initial value

Multi-address I²C Bus Status Register (Upper)

Bit number

MBSRH

15

14

13

12

11

10

9

8

Address : 0000C3^H

PMATCH WUF

TDR

TCR

MTR

STR

R

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Multi-address I²C Data Register

Bit number

MDAR

7

6

5

4

3

2

1

0

Address : 0000C4^H

D7

D6

D5

D4

D3

D2

D1

D0

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

(Continued)

65

MB90370/375 Series

Multi-address I²C Alert Register

Bit number

MALR

15

14

13

12

11

10

9

8

Address : 0000C5^H

ARAE

ARO

ARF

AEN

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Multi-address I²C Address Register 1/3/5

Address ch1 : 0000C6^H

Address ch3 : 0000C8H

Address ch5 :0000CAH

Bit number

MADR1/3/5

7

6

5

4

3

2

1

0

A6

A5

A4

A3

A2

A1

A0

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Multi-address I²C Address Register 2/4/6

Address ch2 : 0000C7^H

Address ch4 : 0000C9H

Address ch6 :0000CBH

Bit number

MADR2/4/6

15

14

13

12

11

10

9

8

A6

A5

A4

A3

A2

A1

A0

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Multi-address I²C Clock Control Register

Bit number

MCCR

7

6

5

4

3

2

1

0

Address :0000CC^H

DMBP

EN

CS4

CS3

CS2

CS1

CS0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Multi-address I²C Timeout Control Register

Bit number

MTCR

15

14

13

12

11

10

9

8

Address :0000CD^H

AAC

TOE

EXT

TS2

TS1

TS0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Multi-address I²C Timeout Clock Register

Bit number

MTOC

7

6

5

4

3

2

1

0

Address :0000CE^H

C7

C6

C5

C4

C3

C2

C1

C0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Multi-address I²C Timeout Data Register

Bit number

MTOD

15

14

13

12

11

10

9

8

Address : 0000CF^H

D7

D6

D5

D4

D3

D2

D1

D0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

(Continued)

66

MB90370/375 Series

(Continued)

Multi-address I²C Slave Timeout Register

Bit number

MSTO

7

6

5

4

3

2

1

0

Address : 0000D0^H

S6

S5

S4

S3

S2

S1

S0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Multi-address I²C Master Timeout Register

Bit number

MMTO

15

14

13

12

11

10

9

8

Address : 0000D1^H

M7

M6

M5

M4

M3

M2

M1

M0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

67

MB90370/375 Series

(2) Block diagram of MI²C

Multi-address I²C enable

MCCR

Peripheral clock

Clock frequency divider 1

8

DMBP

EN

5

6

7

Clock selector 1

CS4

CS3

Clock frequency divider 2

CS2

CS1

CS0

Sync

4

8

16 32

64

128 256 512

Shift clock

generator

Clock selector 2

MBSRL

Shift clock edge

BB

RSC

LRB

TRX

FBT

Bus busy

Repeat start

Start/stop condition

detector

Last bit

Transmission/

reception

Error

First byte

AL

Arbitration lost detector

MBCRH

BER

BEIE

INTE

INT

Interrupt #29

End

Start

SCC

MSS

ACK

Master

Start/stop condition

generator

Enables ACK

Enables GC-ACK

GCAA

CRC-8 calculator

MDAR register

MBCRL

LBT

MBSRL

Slave

Slave address comparator

AAS

GCA

General call

MADR1~6 registers

Timeout detector

MTCR

SCL line

MBSRH

TDR TCR MTR STR

MTOD

MMTO

MTOC

MSTO

SDA line

MALR

ARAE

ARO

ARF

MBCRL

Interrupt #33

ALERT line

WUE

WUF

AEN

MBSRH

68

MB90370/375 Series

10. Bridge circuit

The bridge circuit can switch the I/O path of each port to I²C or Multi-address I²C.

(1) Register configuration of bridge circuit

Bridge Circuit Selection Register

Bit number

BRSR

7

6

5

4

3

2

1

0

Address : 00002C^H

BM4

BI4

BM3

BI3

BM2

BI2

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

(2) Block diagram of bridge circuit

I²C I/O

P81/SDA1

P80/SCL1

Multi-address I²C

BRSR

P91/SDA2

P90/SCL2

BM2

P93/SDA3

P92/SCL3

BM3

BM4

P95/SDA4

P94/SCL4

I²C

BI2

BI3

BI4

69

MB90370/375 Series

11. Comparator

This comparator circuit monitors voltage of up to three batteries and automatically controls electric discharge.

Either parallel discharge or sequential discharge can be selected.

• Parallel discharge control

In parallel discharge control, all batteries are allowed to discharge when power is not being supplied from the

AC adapter.

• If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is controlled

by software.

• Sequential discharge control

In sequential discharge control, the comparator controls discharge in a specified order, while monitoring

intermittent interruption of power, voltage level, and mount/dismount of batteries, when power is not being

supplied from the AC adapter.

• If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is controlled

by software.

• Up to three batteries can be controlled, and the order of discharge can be selected.

• The affect of intermittent interruption of power is automatically filtered.

• Mount/dismount of batteries is automatically detected and discharge is controlled.

• Battery voltage is monitored, and if battery voltage is below the specified voltage, a change over to the next

battery is automatically done.

70

MB90370/375 Series

(1) Register configuration of comparator

Comparator Control Register (Lower)

Bit number

COCRL

7

6

5

4

3

2

1

0

Address : 0000D8^H

BOF3

BOF2

BOF1

SPM2

SPM1

SPM0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Comparator Control Register (Upper)

Bit number

COCRH

15

14

13

12

B3

11

B2

10

B1

9

8

Address : 0000D9^H

SPL3

SPL2

SPL1

DC2

DC1

R/W

0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Read/write

Initial value

Comparator Status Register 1 (Lower)

Bit number

COSRL1

7

6

5

4

3

2

1

0

Address :0000DA^H

COR8 COR7 COR6 COR5 COR4 COR3 COR2 COR1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Comparator Status Register 1 (Upper)

Bit number

COSRH1

15

14

13

12

11

10

9

8

Address :0000DB^H

SWR3 SWR2 SWR1 VAR3

VAR2

VAR1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Comparator Interrupt Control Register (Lower)

Bit number

CICRL

7

6

5

4

3

2

1

0

Address :0000DC^H

CEN8

CEN7

CEN6

CEN5

CEN4

CEN3

CEN2

CEN1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

(Continued)

71

MB90370/375 Series

(Continued)

Comparator Interrupt Control Register (Upper)

Bit number

CICRH

15

14

13

12

11

10

9

8

Address :0000DD^H

SEN3

SEN2

SEN1

VEN3

VEN2

VEN1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Comparator Status Register 2 (Lower)

Bit number

COSRL2

7

6

5

4

3

2

1

0

Address :0000DE^H

COS8

COS7 COS6

COS5

COS4

COS3

COS2

COS1

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

Read/write

Initial value

Comparator Status Register 2 (Upper)

Bit number

COSRH2

15

14

13

12

11

10

9

8

Address : 0000DF^H

SWS3 SWS2 SWS1

VAL3

VAL2

VAL1

R

X

R

X

R

X

R

X

R

X

R

X

Read/write

Initial value

Comparator Input Enable Register

Bit number

CIER

7

6

5

4

3

2

1

0

Address : 0000E0^H

BIE3

BIE2

BIE1

DIE2

DIE1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Read/write

Initial value

72

MB90370/375 Series

(2) Block diagram of comparator

Battery selection circuit

PB0/DCIN

CVRH2

SW

+

PA3/ACO

−

Comparator 1

OUT

CVRL

IN

RH

PB1/DCIN2

RL (Voltage

comparator 2)

CVRH1

SPL

VOL

VSI

SW

IN

RH

OUT

(Voltage

PB4/VOL2

VALID

SW

RL comparator 5)

Battery

PA4/OFB1

O12

IN

RH

OUT

(Voltage

supervisory

circuit 2

PB5/VSI2

RL comparator 6)

ALARM

−

+

PA1/ALR2

OFB

PC1/AN1/SW2

Comparator 2

IN

RH

RL

OUT

(Voltage

comparator 7)

VOL

VSI

SW

SPL

PB6/VOL3

VALID

Battery

IN

RH

RL

OUT

(Voltage

comparator 8)

O13

supervisory

circuit 3

PB7/VSI3

ALARM

−

+

SW

PA2/ALR3

OFB

PC2/AN2/SW3

Comparator 3

SPL

IN

RH

RL

OUT

(Voltage

comparator 3)

VOL

VSI

SW

VALID

PB2/VOL1

SW

Battery

O21

O23

PA5/OFB2

supervisory

circuit 1

IN

RH

RL

OUT

(Voltage

comparator 4)

PB3/VSI1

ALARM

−

+

PA0/ALR1

OFB

PC0/AN0/SW1

Comparator 4

Watch

prescaler

XOA

SW

O31

O32

X1A

PA6/OFB3

Power-on

reset

VCC

RST

8

3

SPL3 SPL2 SPL1 B3

B2

B1 DC2 DC1

COS8 COS7 COS6 COS5 COS4 COS3 COS2 COS1

(COSRL2) Comparator status register 2 (lower)

(COCRH) Comparator control register (upper)

3

6

COR8 COR7 COR6 COR5 COR4 COR3 COR2 COR1

SWR3 SWR2 SWR1 VAR3 VAR2 VAR1

(COSRL1) Comparator status register 1 (lower)

(COSRH1) Comparator status register 1 (upper)

(CICRL) Comparator interrupt control register (lower)

interrupt request

#28

(CICRH) Comparator interrupt control register (upper)

interrupt request

#30

CEN8 CEN7 CEN6 CEN5 CEN4 CEN3 CEN2 CEN1

SEN3 SEN2SEN1 VEN3VEN2VEN1

Decoder

SWS3 SWS2 SWS1 VAL3 VAL2 VAL1

(COSRH2) Comparator status register 2 (upper)

BOF3 BOF2BOF1 SPM2 SPM1 SPM0

(COCRL) Comparator control register (lower)

Internal data bus

73

MB90370/375 Series

12. UART (× 3)

The UART (Universal Asychronous Receiver Transmitter) is a serial I/O port for asynchronous (start-stop) com-

munication or clock-synchronous communication.

The UART has the following features :

• Full-duplex double buffering

• Capable of asynchronous (start-stop bit) and CLK-synchronous communications

• Support for the multiprocessor mode

• Various method of baud rate generation :

- External clock input possible

- Internal clock (a clock supplied from 16-bit reload timer can be used)

- Embedded dedicated baud rate generator

Operation

Asynchronous

CLK synchronous

Baud rate

76923 / 38461 / 19230 / 9615 / 500K / 250K bps

16M / 8M / 4M / 2M / 1M / 500K bps

• Error detection functions (parity, framing, overrun)

• NRZ (Non Return to Zero) signal format

• Interrupt request :

- Receive interrupt (receive complete, receive error detection)

- Transmit interrupt (transmission complete)

- Transmit / receive conforms to extended intelligent I/O service (EI²OS)

74

MB90370/375 Series

(1) Register configuration of UART

Serial Mode Register

Address : ch1 000020^H

ch2 0000D2H

Bit number

SMR1/2/3

7

6

5

4

3

2

1

9

1

9

1

0

8

0

8

0

ch3 0000E4H

MD1

MD0

CS2

CS1

CS0

SCKE

SOE

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Serial Control Register

Address : ch1 000021^H

ch2 0000D3H

Bit number

SCR1/2/3

15

14

13

12

11

10

ch3 0000E5H

PEN

P

SBL

CL

A/D

REC

RXE

TXE

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

W

1

R/W

0

R/W

0

UART Input Data Register / Output Data Register

Address : ch1 000022^H

ch2 0000D4H

Bit number

SIDR1/2/3

SODR1/2/3

7

6

5

4

3

2

ch3 0000E6H

D7

D6

D5

D4

D3

D2

D1

D0

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

UART Status Register

Address : ch1 000023^H

ch2 0000D5H

Bit number

SSR1/2/3

15

7

14

6

13

5

12

4

11

3

10

2

ch3 0000E7H

PE

ORE

FRE

RDRF

TFRE

BDS

RIE

TIE

Read/write

Initial value

R

0

R

0

R

0

R

0

R

1

R/W

0

R/W

0

R/W

0

Clock Division Control Register

Address : ch1 000025^H

ch2 0000D7H

Bit number

CDCR1/2/3

ch3 0000E9H

MD

DIV3

DIV2

DIV1

DIV0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Mode 2 Control Register

Address : ch1 000024^H

ch2 0000D6H

Bit number

M2CR1/2/3

ch3 0000E8H

SCKL

M2L2

M2L1

M2L0

Read/write

Initial value

R/W

1

R/W

0

R/W

0

R/W

0

75

MB90370/375 Series

(2) Block diagram of UART

From

Reception interrupt

#35 (23H)*

communication

prescaler

<#37 (25H)*>

<#39 (27H)*>

Baud rate

generator

Transmission

interrupt

Transmission clock

#36 (24H)*

Clock

selection

circuit

Reception clock

<#38 (26H)*>

<#40 (28H)*>

16-bit reload timer 1/2/3

Reception control

Transmission control

P66/UCK1

circuit

External clock

Start bit detection

circuit

Transmission

start circuit

P70/UI1

Reception bit

counter

Transmission bit

counter

Reception parity

counter

Transmission parity

counter

P67/UO1

Reception status

judgement circuit

Reception shifter

SIDR1/2/3

Transmission shifter

SODR1/2/3

EI²OS reception error

signal (to CPU)

F²MC-16LX bus

MD1

MD0

CS2

CS1

CS0

PEN

P

PE

SCKL

M2L2

M2L1

M2L0

ORE

FRE

RDRF

TDRE

BDS

RIE

SBL

CL

SMR1/2/3

registers

SCR1/2/3

registers

SSR1/2/3

registers

M2CR1/2/3

registers

A/D

REC

RXE

TXE

SCKE

SOE

TIE

Control signal

* : Interrupt number

76

MB90370/375 Series

13. LCD controller/driver (not for MB90F377)

The LCD (Liquid Crystal Display) controller/driver function displays the contents of a display data memory directly

to the LCD panel by segment and common outputs.

• Up to nine segment outputs (SEG0 to SEG8) and four common outputs (COM0 to COM3) may be used.

• Built-in display RAM.

• Three selectable duty ratios (1/2, 1/3, and 1/4) . However, not all duty ratios are available with all bias settings.

• Either the main or sub-clock can be selected as the drive clock.

• LCD can be driven directly.

Table below shows the duty ratios available with each bias setting.

Part number

Bias

1/2 duty ratio

1/3 duty ratio

1/4 duty ratio

1/2 bias

1/3 bias

X

MB90370 series

X

: Recommended mode

X : Do not use

(1) Register configuration of LCD

LCDC Control Register (Upper)

Bit number

LCRH

15

14

13

12

11

10

9

8

Address : 0000EF^H

SS4

VS

CS1

CS0

SS3

SS2

SS1

SS0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

LCDC Control Register (Lower)

Bit number

LCRL

7

6

5

4

3

2

1

0

Address : 0000EE^H

CSS

LCEN

VSEL

BK

MS1

MS0

FP1

FP0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

R/W

0

77

MB90370/375 Series

(2) Block diagram of LCD

LCDC supply voltage (V1 to V3)

LCDC control register

(LCR)

HCLK / 2⁸

4

COM0

COM1

COM2

COM3

Timing

controller

Prescaler

4

Sub-clock

(32 kHz)

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

9

Display RAM

9 x 4 bit

Controller

Driver

78

MB90370/375 Series

14. A/D converter

The A/D (Analog to Digital) converter converts the analog voltage input to an analog input pin (input voltage) to

a digital value.

The converter has the following features :

• The minimum conversion time is 6.13 µs (for a machine clock of 16 MHz; includes the sampling time) .

• The minimum sampling time is 3.75 µs (for a machine clock of 16 MHz) .

• The converter uses the RC-type successive approximation conversion method with a sample and hold circuit.

• A resolution of 10 bits or 8 bits can be selected.

• Up to twelve channels for analog input pins can be selected by a program.

• Various conversion modes :

- Single conversion mode : Selectively convert one channel.

- Scan conversion mode : Continuously convert multiple channels. Maximum of 12 selectable channels.

- Continuous conversion mode : Repeatedly convert specified channels.

- Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of

the conversion start timing.)

• At the end of A/D conversion, an interrupt request can be generated and EI²OS can be activated.

• In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being

lost through continuous conversion.

• The conversion can be activated by software, 16-bit reload timer 4 (rise edge) and ADTG.

(1) Register configuration of A/D converter

Analog Input Enable Register 2

Bit number

ADER2

15

14

13

12

11

10

9

8

Address : 00002B^H

ADE11 ADE10 ADE9

ADE8

Read/write

Initial value

R/W

1

R/W

1

R/W

1

R/W

1

Analog Input Enable Register 1

Bit number

ADER1

7

6

5

4

3

2

1

0

Address : 00002A^H

ADE7

ADE6

ADE5

ADE4

ADE3

ADE2

ADE1

ADE0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

Read/write

Initial value

A/D Control Status Register 1

Bit number

ADCS1

15

14

13

12

11

10

9

8

Address : 000031^H

BUSY

INT

INTE

PAUS

STS1

STS0

STRT

RESV

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

W

0

R/W

0

A/D Control Status Register 0

Bit number

ADCS0

7

6

5

4

3

2

1

0

Address : 000030^H

MD1

MD0

R/W

0

R/W

0

Read/write

Initial value

(Continued)

79

MB90370/375 Series

(Continued)

A/D Control Register

Bit number

ADC0

15

14

13

12

11

10

9

8

Address : 00002D^H

ANS3

ANS2

ANS1

ANS0

ANE3

ANE2

ANE1

ANE0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

A/D Data Register (Upper)

Bit number

ADCR1

15

14

13

12

11

10

9

8

Address : 00002F^H

S10

ST1

ST0

CT1

CT0

D9

D8

R/W

0

W

0

W

0

W

0

W

0

R

X

R

X

Read/write

Initial value

A/D Data Register (Lower)

Bit number

ADCR0

7

6

5

4

3

2

1

0

Address : 00002E^H

D7

D6

D5

D4

D3

D2

D1

D0

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

Read/write

Initial value

(2) Block diagram of A/D converter

AVCC AVR AVSS

MP

D/A converter

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

Sequential

comparison register

Comparator

Sample and holding circuit

Data register

ADCR0/1

A/D control register

A/D control status register 0

A/D control status register 1

ADCS0/1

16-bit reload timer 4

P37/ADTG

Operation clock

φ

Prescalar

φ : Machine clock

80

MB90370/375 Series

15. D/A converter

The D/A (Digital to Analog) converter is used to generate an analog output from an 8-bit digital input. By setting

the enable bit in the D/A control register (DACR) to 1, it will enable the corresponding D/A output channel. Hence,

setting this bit to 0 will disable that channel.

If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is

turned off. In the D/A converter, the bit is cleared to 0 and the direct-current path is shut off. The above is also

true in the stop mode.

The output voltage of the D/A converter ranges from 0 V to 255/256 x AV^CC.

The D/A converter output does not have the internal buffer amplifier. The analog switch ( = 100 Ω) is inserted

to the output in series. To apply load to the output externally, estimate a sufficient stabilization time.

Table below lists the theoretical values of output voltage of the D/A converter.

Value written to DA07 to DA00 and DA17 to DA10

Theoretical value of output voltage

0/256 × AVCC ( = 0 V)

1/256 × AVCC

00^H

01^H

02H

:

2/256 × AVCC

:

FD^H

FEH

FFH

253/256 × AVCC

254/256 × AVCC

255/256 × AVCC

81

MB90370/375 Series

(1) Register configuration of D/A converter

D/A converter register 1

Bit number

DAT1

15

14

13

12

11

10

9

8

Address : 00005B^H

DA17

DA16

DA15

DA14

DA13

DA12

DA11

DA10

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

D/A converter register 0

Bit number

DAT0

7

6

5

4

3

2

1

0

Address : 00005A^H

DA07

DA06

DA05

DA04

DA03

DA02

DA01

DA00

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

D/A control register 1

Bit number

DACR1

15

14

13

12

11

10

9

1

8

Address : 00005D^H

DAE1

R/W

0

Read/write

Initial value

D/A control register 0

Bit number

DACR0

7

6

5

4

3

2

0

Address : 00005C^H

DAE0

R/W

0

Read/write

Initial value

82

MB90370/375 Series

(2) Block diagram of D/A converter

F²MC-16LX BUS

DA DA DA DA DA DA DA DA

17 16 15 14 13 12 11 10

DA DA DA DA DA DA DA DA

07 06 05 04 03 02 01 00

AVCC

DA17

DA07

2R

R

2R

R

DA16

DA06

2R

R

2R

R

DA15

DA11

DA05

DA01

2R

R

2R

R

DA10

DA00

2R

DAE1

DAE0

Standby control

DA output ch.1

DA output ch.0

83

MB90370/375 Series

16. LPC interface

The LPC (Low Pin Count) interface consists of an LPC bus interface, universal parallel interface (UPI ×

4 channels) , gate address A20 function and LPC data buffer array. By using the LPC bus interface and UPI,

data can be exchanged with an external host CPU synchronously via an external LPC bus.

• LPC bus interface

The LPC bus interface provides direct access of host CPU to UPI.

• It supports I/O read and I/O write cycle only. Other cycle types will be ignored.

• It supports LPC clock running at 33 MHz.

• Universal parallel interface, UPI × 4 channels

The UPI is used to exchange parallel data to serial data in LPC bus with host CPU.

• An 8-bit data will be transmitted or received.

• A buffer function is available for independent input and output.

• The I/O buffer status can be output externally through LPC bus interface.

• Gate address A20 function for UPI channel 0

The GA20 (Gate Address A20) is intended to implement the memory management in a PC architecture. This

allows the access to the extended memory needed by the operating system. On-chip logic is provided to speed

up the generation of GA20.

• Data buffer array

The data buffer array is consisted of 32 bytes UP data register and 16 bytes DOWN data register to speed up

the data transfer between MCU and external host through LPC bus.

(1) Register configuration of LPC bus interface register

LPC Control Register

Bit number

LCR

7

6

5

4

3

2

1

0

Address : 00006E^H

LRF

LRIE

LPE

Read/write

Initial value

R/W

0

R/W

0

R/W

0

84

MB90370/375 Series

(2) Register configuration of UPI registers

UPI Address Register (Upper)

Address : ch1 00005F^H

ch2 000061H

Bit number

UPAH1 to

UPAH3

15

14

13

12

11

10

9

8

ch3 000063H

UPA15 UPA14 UPA13 UPA12 UPA11 UPA10 UPA09 UPA08

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

UPI Address Register (Lower)

Address : ch1 00005E^H

ch2 000060H

Bit number

UPAL1 to

UPAL3

7

6

5

4

3

2

1

0

ch3 000062H

UPA07 UPA06 UPA05 UPA04 UPA03 UPA02 UPA01 UPA00

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

UPI Control Register (Upper)

Bit number

UPCH

15

14

13

12

11

10

9

8

Address : 000065^H

UPE3

IBFE3 OBEE3

UPE2

IBFE2 OBEE2

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

UPI Control Register (Lower)

Bit number

UPCL

7

6

5

4

3

2

1

0

Address : 000064^H

DBAE

UPE1

IBFE1 OBEE1 GA20E UPE0

IBFE0 OBEE0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

UPI Status Register

Address : ch0 000067^H

ch1 000069H

ch2 00006BH

ch3 00006DH

Read/write

15

14

13

12

11

10

9

8

Bit number

UPS0 to

UPS3

UF4

UF3

UF2

UF1

A2

UF0

IBF

OBF

R/W

0

R/W

0

R/W

0

R/W

0

R

0

R/W

0

R

0

R

0

Initial value

UPI Data Input Register / Data Output Register

Address : ch0 000066^H

7

6

5

4

3

2

1

0

Bit number

UPDI0 to

UPDI3/

UPDO0 to

UPDO3

ch1 000068H

ch2 00006AH

ch3 00006CH

Read/write

UPD7

UPD6

UPD5

UPD4

UPD3

UPD2

UPD1

UPD0

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Initial value

85

MB90370/375 Series

(3) Register configuration of LPC data buffer registers

Data Buffer Array Address Register (Upper)

Bit number

DBAAH

15

14

13

12

11

10

9

8

Address : 003FF1^H

DA15

DA14

DA13

DA12

DA11

DA10

DA09

DA08

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

Data Buffer Array Address Register (Lower)

Bit number

DBAAL

7

6

5

4

3

2

1

0

Address : 003FF0^H

DA07

DA06

DA05

DA04

DA03

DA02

DA01

DA00

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

UP Data Register (upper)

Address : ch0 003FC1^H

ch1 003FC3H

to

15

14

13

12

11

10

9

8

Bit number

UDRH0 to

UDRHF

UP15

UP14

UP13

UP12

UP11

UP10

UP09

UP08

chF003FDF^H

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

UP Data Register (lower)

Address : ch0 003FC0^H

ch1 003FC2H

to

7

15

7

6

14

6

5

13

5

4

12

4

3

11

3

2

10

2

1

9

1

0

8

0

Bit number

UDRL0 to

UDRLF

UP07

UP06

UP05

UP04

UP03

UP02

UP01

UP00

chF003FDEH

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

DOWN Data Register (upper)

Address : ch0 003FE1^H

ch1 003FE3H

Bit number

DNDH0 to

DNDH7

to

DN15

DN14

DN13

DN12

DN11

DN10

DN09

DN08

ch7 003FEFH

Read/write

Initial value

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

DOWN Data Register (lower)

Address : ch0 003FE0^H

ch1 003FE2H

Bit number

DNDL0 to

DNDL7

to

DN07

DN06

DN05

DN04

DN03

DN02

DN01

DN00

ch7003FEEH

Read/write

Initial value

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

(Continued)

86

MB90370/375 Series

(Continued)

Index Register

Bit number

IXR

7

6

5

4

3

2

1

0

Address :

IX05

IX04

IX03

IX02

IX01

IX00

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Data Port Register

Bit number

DPR

7

6

5

4

3

2

1

0

Address :

Read/write

DP07

DP06

DP05

DP04

DP03

DP02

DP01

DP00

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Initial value

(4) Block diagram of LPC interface

Address

comparator

UPI address register, UPAH1 to UPAH3, UPAL1 to UPAL3

Data buffer array address register, DBAA

R/W

comp

match

UPE

LPC/RW

DBAE

Interrupt

request #16

Interrupt

UPI0 to UPI3

request #15

Interrupt

UPE IBFE OBEE

request #14

Interrupt

request #13

UPC

Interrupt

request #21

OBF0 to OBF3

UPS

UF4 UF3 UF2

UF1

A2

UF0

IBF

OBF

LCR

LRF LRIE LPE

UPDI

LA3 LA2 LA1 LA0

UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0

EN

R/W

UPDO

LFRAME

UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0

State

machine

LRESET

LCLK

4

LAD3 to

LAD0

for UPI0 only

UPC

GA20E

EN

GA20 output

generator

LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0

LPC bus interface

GA20

UPC

Data buffer array

IXR

DBAE

Index register

UP data register (32 bytes)

DOWN data register (16 bytes)

Data port register

DPR

87

MB90370/375 Series

17. Serial IRQ controller

The serial IRQ controller consists of a 6-channel serial IRQ control circuit and an LPC clock monitor / control

circuit. By using this serial IRQ controller, host interrupt requests can be transferred serially through a single

signal wire (SERIRQ) , synchronized with the LPC clock.

6-channel serial IRQ control circuit

• The 6-channel serial IRQ control circuit consists of a serial interrupt control register (SICR) , 4 serial interrupt

frame number registers (SIFR1 to SIFR4) , a protocol state machine and a serial interrupt data latch and output

control.

• For channel 0A, 0B and 1 to 3, if SICR : OBE bit (OBF controlled enable bit) = 0, then serial IRQ can be

controlled by software setting of SICR : IRR bit. If SICR : OBE bit = 1, then software control is disabled and

serial IRQ is controlled by OBF flag (Output buffer full flag) from LPC UPI0 to UPI3.

• For channel 4, serial IRQ can be controlled by software setting of SICR : IRR bit.

• For channel 0A and 0B, additional enable bit (SICR : EN0A/0B bit) can be used to latch and keep the OBF0

or IRR0A/0B bit status.

• The serial interrupt data latch transfers serial IRQs serially according to their frame number. The frame number

for channel 0A is fixed to “IRQ1”, for channel 0B is fixed to “IRQ12”, and the frame number for channel 1 to

channel 4 are software programmable (IRQ1 to IRQ15, and IRQ21 to IRQ31) by setting the SIFR1 to SIFR4.

• By monitoring the SERIRQ and the LPC clock pin, the protocol state machine can detect the START frame

condition. Then it starts counting the DATA frame and transfers its serial IRQs through SERIRQ. Finally it can

switch to continuous/quiet mode operation by determine the STOP frame condition.

• The serial interrupt output control support both continuous and quiet mode operation. In continuous mode

operation, only the host can initiate the serial IRQs transfer; In quiet mode operation, both the host and slave

(e.g. the serial IRQ controller) can initiate the serial IRQs transfer.

LPC clock monitor / control circuit

• The LPC clock monitor / control circuit consists of a clock-run monitor / control circuit. By monitoring the clock-

run pin (CLKRUN) , the clock monitor / control circuit can determine whether the host has stopped LPC clock

in quiet mode operation or not. If LPC clock is stopped and the controller wants to initiate the serial IRQs

transfer, then it can request the host to restart the LPC clock by controlling the CLKRUN pin.

88

MB90370/375 Series

(1) Register configuration of serial IRQ controller

Serial Interrupt Control Register (Lower)

Bit number

SICRL

7

6

5

4

3

2

1

0

Address : 000032^H

EN0B

EN0A

IRR4

IRR3

IRR2

IRR1

IRR0B IRR0A

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Serial Interrupt Control Register (Upper)

Bit number

SICRH

15

14

13

12

11

10

9

8

Address : 000033^H

IRQEN RSEN BUSY

OBE3

OBE2

OBE1 OBE0B OBE0A

R/W

0

R/W

0

R

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Serial Interrupt Frame Number Register 1

Bit number

SIFR1

7

6

5

4

3

2

1

0

Address : 000034^H

LV1

FR14

FR13

FR12

FR11

FR10

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Serial Interrupt Frame Number Register 2

Bit number

SIFR2

15

14

13

12

11

10

9

8

Address : 000035^H

LV2

FR24

FR23

FR22

FR21

FR20

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Serial Interrupt Frame Number Register 3

Bit number

SIFR3

7

6

5

4

3

2

1

0

Address : 000036^H

LV3

FR34

FR33

FR32

FR31

FR30

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Serial Interrupt Frame Number Register 4

Bit number

SIFR4

15

14

13

12

11

10

9

8

Address : 000037^H

LV4

FR44

FR43

FR42

FR41

FR40

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

89

MB90370/375 Series

(2) Block diagram of the serial IRQ controller

Serial IRQ controller

OBF0

OBF1

OBF2

OBF3

from UPI0 to UPI3

in LPC

interface

OBF1

OBF2

OBF3

6-channel serial

IRQ control circuit

SIRQ

Pin SERIRQ

LCLK

Pin LCK

LCLK stop

status

LRESET

Pin LRESET

LCLK restart

request

LCLK

LPC clock

monitor / control

circuit

LRESET

CRUN

Pin CLKRUN

90

MB90370/375 Series

(3) Block diagram of the 6-channel serial IRQ control circuit

IRQEN

SIRQ enable

Serial interrupt

control register

(upper)

SERIRQ

busy

OBF0

OBF1

OBF2

OBF3

Register

write

disable

IRR0A, IRR0B, IRR1 to IRR3

Serial interrupt

control register

(lower)

Software

control

Hardware

control

Serial IRQ control

selector for channel

0A, 0B, 1 to 3

IRR4

EN0A,

Latches for

channel 0A, 0B

EN0B

Serial interrupt

data latch and

output control

SIRQO

LCK

Serial IRQs

Serial interrupt

frame number

register

frame no. for

channel 1 to channel 4

LRESET

Serial IRQ

Frame

sample cycle cycle count

Initiate serial

IRQ transfer

request

Protocol

state

machine

SIRQI

LCK stop

status

LCK

restart

request

91

MB90370/375 Series

(4) Block diagram of the LPC clock monitor / control circuit

RSEN

IRQEN

CRUNO enable

LCK stop

status

LCK

restart

request

LCK

restart

request

CRUNO

Clock-run

monitor /

control

CRUNI

LCK

LRESET

92

MB90370/375 Series

18. 3-channel PS/2 interface

The 3-channel PS/2 interface consists of 3 individual channels of PS/2 interface that can be operated concur-

rently. PS/2 interface is a two wires, bidirectional serial bus providing economical way for data exchange between

host (keyboard controller) and device (keyboard / mouse, etc) .

(1) Register configuration of 3-channel PS/2 interface

PS/2 Interface Mode Register

Bit number

PSMR

15

14

13

12

11

10

9

8

Address : 000059^H

NFS1

NFS0

DIV1

DIV0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

PS/2 Interface Data Register (Ch 1)

Bit number

PSDR1

15

14

13

12

11

10

9

8

Address : 000057^H

D7

D6

D5

D4

D3

D2

D1

D0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

PS/2 Interface Data Register (Ch 0, Ch 2)

Bit number

PSDR0/2

7

6

5

4

3

2

1

0

Address : ch1 000056^H

ch2 000058H

D7

D6

D5

D4

D3

D2

D1

D0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

PS/2 Interface Status Register

Address : ch0 000051^H

ch1 000053H

Bit number

PSSR0/1/2

15

14

13

12

11

10

9

8

ch2 000055H

PE

FED FRE/NAK RAF

TS

TBC

BNR

TC

Read/write

Initial value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R/W

0

PS/2 Interface Control Register

Address : ch0 000050^H

ch1 000052H

Bit number

PSCR0/1/2

7

6

5

4

3

2

1

0

ch2 000054H

PS2E

FEDE

IE

BREQ

TE

RE

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

93

MB90370/375 Series

(2) Block diagram of 3-channel PS/2 interface

F²MC-16LX bus

PSCKI0

Noise filter

PSCKO0

PSDAO0

Channel 0

transmission/

reception

circuit

NFS1 NFS0 DIV1 DIV0

PSDAI0

2

PSMR

Interrupt

request 0

PSCKI1

PSDAI1

Noise filter

PSCKO1

PSDAO1

Channel 1

transmission/

reception

circuit

Interrupt

request 1

PSCKI2

PSDAI2

Noise filter

PSCKO2

PSDAO2

Channel 2

transmission/

reception

circuit

1/4

Prescaler

circuit

1/8

Interrupt

request 2

φ

1/16

1/32

Sampling clock

94

MB90370/375 Series

(3) Block diagram of PS/2 interface transmission/reception circuit (1 channel)

F²MC-16LX bus

Sampling

clock

PSDR

D7 D6 D5 D4 D3 D2 D1 D0

SYNDA

SYNCK

PSDAI

PSCKI

Synchronous

circuit

PSDAO

Start of

reception

Start of

transmission

Reception control

circuit

Transmission control

circuit

Reception

completion detector

Acknowledge

reception generator

Parity checker

Parity generator

Reception start bit

detection circuit

Reception

enable

Transmission

enable

Transmission

completion detector

Reception status

judgment circuit

PE & FRE Reception Reception

active complete

Acknowledge Transmission

result

complete

Transfer

break

request

Transfer complete

processing circuit

PSCKO

Transfer

status flags

clear

Error flags

Falling edge

detection

PS/2 interface

interrupt

#23 (17H)* ch0/1

#24 (18H)* ch2

FRE/

PS2E

FEDE IE BREQ TE RE

PE FED

PSSR

RAF TS TBC BNR TC

NAK

PSCR

F²MC-16LX bus

* : Interrupt number

95

MB90370/375 Series

19. Parity generator

The parity generator is a simple circuit that generates odd / even parity based on the input data. It consists of a

parity generator data register (PGDR) , an odd / even parity generation logic and a parity generator control status

register (PGCSR) .

An 8-bit data can be loaded into PGDR, then the parity generator will generate odd / even parity based on the

input data. Either odd or even parity can be generated by setting the PGCSR.

For odd parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will

be set to “1”, otherwise the parity bit will be set to “0”.

For even parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will

be set to “0”, otherwise the parity bit will be set to “1”.

Table shows some examples of odd / even parity generation.

Input data

Parity bit (odd parity)

Parity bit (even parity)

0000 0000^B

0101 0101B

1000 0000B

1010 1011B

1

0

1

(1) Register configuration of parity generator

Parity Generator Data Register

Bit number

7

6

5

4

3

2

1

0

Address : 000018^H

PGDR

D7

D6

D5

D4

D3

D2

D1

D0

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

Parity Generator Control Status Register

Bit number

PGCSR

15

14

13

12

11

10

9

8

Address : 000019^H

PRTY

PSEL

R

X

R/W

0

Read/write

Initial value

96

MB90370/375 Series

(2) Block diagram of parity generator

8

Parity generator data register

8

Parity generation logic

odd /

even

result

2

Parity generator

control status register

97

MB90370/375 Series

20. Bit decoder

The bit decoder is a simple one-hot decoder that can be used together with the keyscan inputs. It consists of a

bit data register (BDR) , a decoder logic and a bit result register (BRR) . A 4-bit encoded data can be loaded

into BDR, then the decoder logic will decode the data and store the 16-bit resulted data into BRR. A table below

shows the decoder’s logic.

4-bit encoded data

16-bit resulted data

0^H

1H

2H

3H

4H

5H

6H

7H

8H

9H

AH

BH

CH

DH

EH

FH

0000 0000 0000 0001B

0000 0000 0000 0010B

0000 0000 0000 0100B

0000 0000 0000 1000B

0000 0000 0001 0000B

0000 0000 0010 0000B

0000 0000 0100 0000B

0000 0000 1000 0000B

0000 0001 0000 0000B

0000 0010 0000 0000B

0000 0100 0000 0000B

0000 1000 0000 0000B

0001 0000 0000 0000B

0010 0000 0000 0000B

0100 0000 0000 0000B

1000 0000 0000 0000B

(1) Register configuration of bit decoder

Bit Data Register

Bit number

BDR

15

14

13

12

11

10

9

8

Address : 0000E1^H

D3

D2

D1

D0

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

Bit Result Register (Upper)

Bit number

BRRH

15

14

13

12

11

10

9

8

Address : 0000E3^H

R15

R14

R13

R12

R11

R10

R9

R8

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

Read/write

Initial value

Bit Result Register (Lower)

Bit number

BRRL

7

6

5

4

3

2

1

0

Address : 0000E2^H

R7

R6

R5

R4

R3

R2

R1

R0

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

Read/write

Initial value

98

MB90370/375 Series

(2) Block diagram of bit decoder

4

Bit data register

4

Decoder logic

16

Bit result register

99

MB90370/375 Series

21. Wake-up interrupt

The wake-up interrupt circuit detects the signals of the “L” levels input to the external interrupt pins and to

generate interrupt request to the CPU. These interrupts can wake up the CPU from standby mode.

Wake-up interrupt pins :

8 pins (P00/KSI0 to P07/KSI7) .

Wake-up interrupt sources : “L” level signal input to a wake-up interrupt pin.

Enables or disables to input wake-up interrupt controlled by wake-up interrupt control

register (EICR) .

Interrupt control :

IRQ flag bit of wake-up interrupt flag register (EIFR) . Flag set

when there is an IRQ.

Interrupt flag :

Interrupt request :

Interrupt request #20 is generated if any enabled external interrupt pin goes LOW.

(1) Register configuration of wake-up interrupt

Wake-up Interrupt Flag Register

Bit number

EIFR

15

14

13

12

11

10

9

8

Address :0000AD^H

WIF

R/W

0

Read/write

Initial value

Wake-up Interrupt Control Register

Bit number

EICR

7

6

5

4

3

2

1

0

Address :0000AC^H

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

(2) Block diagram of wake-up interrupt

7

EICR

6

5

3

2

1

0

4

P07/KSI7

P06/KSI6

P05/KSI5

P04/KSI4

P03/KSI3

EIFR

P02/KSI2

P01/KSI1

P00/KSI0

Interrupt Request Generator

100

MB90370/375 Series

22. DTP/External interrupts

The DTP (Data Transfer Peripheral) /external interrupt circuit is activated by the signal supplied to a DTP/external

interrupt pin. The CPU accepts the signal using the same as procedure used for normal hardware interrupts

and generates external interrupts or activates the extended intelligent I/O service (EI²OS) .

Features of DTP/External interrupt :

• Total 6 external interrupt channels

• Two request levels (“H” and “L”) are provided for the intelligent I/O service.

• Four request levels (rise/fall edge, fall edge, “H” level and “L” level) are provided for external interrupt requests .

(1) Register configuration

DTP/Interrupt Source Register

Bit number

15

14

13

12

11

10

9

8

Address : 000027^H

EIRR

ER5

ER4

ER3

ER2

ER1

ER0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

DTP/Interrupt Enable Register

Bit number

ENIR

7

6

5

4

3

2

1

0

Address : 000026^H

EN5

EN4

EN3

EN2

EN1

EN0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Request Level Setting Register (Upper)

Bit number

ELVRH

15

14

13

12

11

10

9

8

Address : 000029^H

LB5

LA5

LB4

LA4

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

Request Level Setting Register (Lower)

Bit number

ELVRL

7

6

5

4

3

2

1

0

Address : 000028^H

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

Read/write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

101

MB90370/375 Series

(2) Block diagram of DTP/External interrupts

Request level setting register (ELVR)

LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

2

Selector

P60/INT0

Selector

P61/INT1

Selector

P65/INT5

P62/INT2

Selector

P64/INT4

P63/INT3

DTP/interrupt cause register

(EIRR)

ER5

ER4

ER3

ER2

ER1

ER0

Interrupt request number

#17(11H)

#18(12H)

#19(13H)

DTP/interrupt enable register

(ENIR)

EN5

EN4

EN3

EN2

EN1

EN0

102

MB90370/375 Series

23. Delayed interrupt generation module

The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the

F²MC-16LX CPU can be generated and cleared by software using this module.

(1) Register configuration

Delayed Interrupt Generator Module Register

Bit number

DIRR

15

14

13

12

11

10

9

8

Address : 00009F^H

R0

Read/write

Initial value

R/W

0

(2) Block diagram

Delayed interrupt cause issuance / cancellation decoder

Interrupt cause latch

103

MB90370/375 Series

24. ROM correction function

When an address matches the value set in the address detection register, the instruction code to be loaded into

the CPU is forced to be replaced with the INT9 instruction code (01H) . When executing a set instruction, the

CPU executes the INT9 instruction. The ROM correction function is implemented by processing using the INT9

interrupt routine.

The device contains two address detection registers, each provided with a compare enable bit. When the value

set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code

to be loaded into the CPU is forced to be replaced with the INT9 instruction code.

(1) Register configuration

Program Address Detection Control / Status Register

Bit number

PACSR

7

6

5

4

3

2

1

0

Address : 00009E^H

AD1E

AD1D

AD0E

AD0D

R/W

0

R/W

0

R/W

0

R/W

0

Read/write

Initial value

Program Address Detection Register 0 (Upper Byte)

Bit number

PADRH0

7

6

5

4

3

2

1

0

Address : 001FF2^H

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

Program Address Detection Register 0 (Middle Byte)

Bit number

PADRM0

15

14

13

12

11

10

9

8

Address : 001FF1^H

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Program Address Detection Register 0 (Lower Byte)

Bit number

PADRL0

7

6

5

4

3

2

1

0

Address : 001FF0^H

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Read/write

Initial value

(Continued)

104

MB90370/375 Series

(Continued)

Program Address Detection Register 1 (Upper Byte)

Bit number

15

14

13

12

11

10

9

8

Address : 001FF5^H

PADRH1

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Program Address Detection Register 1 (Middle Byte)

Bit number

PADRM1

7

6

5

4

3

2

1

0

Address : 001FF4^H

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Program Address Detection Register 1 (Lower Byte)

Bit number

PADRL1

15

14

13

12

11

10

9

8

Address : 001FF3^H

Read/write

Initial value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

(2) Block diagram

Address latch

INT9

Comparator

command

Address detection register 0/1

F²MC-16LX

CPU

PACSR

AD0E/AD1E AD0D/AD1D

105

MB90370/375 Series

25. ROM mirroring function selection module

The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the

00 bank according to register settings.

(1) Register configuration

ROM Mirror Function Selection Register

Bit number

ROMM

15

14

13

12

11

10

9

8

Address : 0006F^H

M1

Read/write

Initial value

W

1

(2) Block diagram

ROM mirroring register

Address area

FF bank

00 bank

ROM

106

MB90370/375 Series

26. 512K bit flash memory

The 512K bit flash memory is allocated in the FFH banks on the CPU memory map. Like masked ROM, flash

memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The

flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit.

The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated

CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as

“enable sector protect” cannot be used.

Features of 512K bit flash memory :

• 64 Kwords × 8 bits / 32 Kwords × 16 bits (16 K + 8 K + 8 K + 32 K) sector configuration

• Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA)

• Installation of the deletion temporary stop/delete restart function

• Write/delete completion detected by the data polling or toggle bit

• Write/delete completion detected by the CPU interrupt

• Compatibility with the JEDEC standard-type command

• Each sector deletion can be executed (Sectors can be freely combined) .

• Number of write/delete operations 10,000 times guaranteed

* : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.

(1) Register configuration

Flash Memory Control Status Register

Bit number

FMCS

7

6

5

4

3

2

1

0

Address : 0000AE^H

INTE RDYINT

WE

RDY Reserved LPM1 Reserved LPM0

R/W

0

R/W

0

R/W

0

R

1

W

0

R/W

0

W

0

R/W

0

Read/write

Initial value

107

MB90370/375 Series

(2) Sector configuration of 512K bits flash memory

The 512K bits flash memory has the sector configuration illustrated below. The addresses in the illustration are

the upper and lower addresses of each sector.

When accessed from the CPU, SA0 and SA1 to SA3 are allocated in the FF bank registers, respectively.

CPU address

FFFFFFH

Flash memory

*Writer address

7FFFFH

SA3 (16 Kbytes)

FFC000H

FFBFFFH

7C000H

7BFFFH

SA2 (8 Kbytes)

SA1 (8 Kbytes)

FFA000H

FF9FFFH

7A000H

79FFFH

FF8000H

FF7FFFH

FF0000H

78000H

77FFFH

SA0 (32 Kbytes)

70000H

* : Writer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel writer.

Writer addresses are used to program/erase data using a general-purpose writer.

108

MB90370/375 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = CVSS = 0.0 V)

Rating

Symbol

Unit

Remarks

Parameter

Min

Max

V^CC

VSS − 0.3 VSS + 4.0

V

Power supply voltage

CV^CC

AVCC

VCC ≥ CVCC *¹

VCC ≥ AVCC *¹

A/D converter reference

input voltage

AVR

VSS − 0.3 VSS + 4.0

V

AVCC ≥ AVR, AVR ≥ AVSS

CVRH1

CVRH2

CVRL

CVCC ≥ CVRH1, CVRH1 ≥ CVSS

CVCC ≥ CVRH2, CVRH2 ≥ CVSS

CVCC ≥ CVRL, CVRL ≥ CVSS

Comparator reference

input voltage

VSS − 0.3 VSS + 4.0

V

V1 to V3 must not exceed VCC

Not for MB90F377

LCD power supply voltage

Input voltage

V1 to V3

V^I1

VSS − 0.3 VSS + 4.0

V

All pins except P40 to P45, P80 to

P82, P90 to P95 *²

VI2

V^O

VSS − 0.3 VSS + 6.0

VSS − 0.3 VSS + 4.0

V

P40 to P45, P80 to P82, P90 to P95

Output voltage

*2

*4

Maximum clamp current

ICLAMP

−2.0

+2.0

mA

Total maximum clamp cur-

rent

Σ|I^CLAMP|

20

mA

*4

IOL1

IOL2

10

20

mA

All pins except PF0 to PF7*³

PF0 to PF7*³

“L” level maximum output

current

All pins except PF0 to PF7

I^OLAV1

4

mA

Average output current = operating

current × operating efficiency

“L” level average output

current

PF0 to PF7

Average output current = operating

current × operating efficiency

I^OLAV2

12

“L” level total maximum

output current

ΣI^OL

ΣI^OLAV

IOH

100

50

mA

“L” level total average

output current

Average output current = operating

current × operating efficiency

“H” level maximum output

current

−10

−3

*3

“H” level average output

current

Average output current = operating

current × operating efficiency

I^OHAV

ΣI^OH

“H” level total maximum

output current

−100

−50

“H” level total average

output current

Average output current = operating

current × operating efficiency

ΣI^OHAV

(Continued)

109

MB90370/375 Series

(Continued)

(VSS = AVSS = CVSS = 0.0 V)

Rting

Symbol

Unit

Remarks

Parameter

Min

Max

200

Power consumption

Operating temperature

Storage temperature

P^D

T^A

mW

°C

−40

−55

+85

Tstg

+150

°C

*1 : Set AV^CC, CVCC and VCC at the same voltage. Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed

VCC + 0.3 V when the power is turned on.

*2 : VI and VO shall never exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum

current to/from an input is limited by some means with external components, the ICLAMP rating supersedes

the VI rating.

*3 : The maximum output current is a peak value for a corresponding pin.

*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P47, P50 to P57, P60 to P67,

P70 to P77, PA0 to PA6, PC3 to PC7, PD0 to PD3, PD6, PD7

Use within recommended operating conditions.

Use at DC voltage (current) .

The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

The value of the limiting resistance should be set so that when the +B signal is applied the input current to the

microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

Notethatwhenthemicrocontrollerdrivecurrentislow, suchasinthepowersavingmodes, the+Binputpotential

may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other

devices.

Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V) , the power supply

is provided from the pins, so that incomplete operation may result.

Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting

supply voltage may not be sufficient to operate the power-on reset.

Care must be taken not to leave the +B input pin open.

Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins,

etc.) cannot accept +B signal input.

Sample recommended circuits :

Input/Output Equivalent circuits

Protective diode

Vcc

P-ch

Limiting

resistance

+B input (0V to 16V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

110

MB90370/375 Series

2. Recommended Operating Conditions

Value

(VSS = AVSS = CVSS = 0.0 V)

Parameter

Symbol

Unit

Remarks

Min

3.0

3.3

1.8

Max

3.6

VCC

CVCC

V^CC

V

Normal operation assurance range

Retains the RAM state in stop mode

Power supply

voltage *¹

A/D converter

reference input

voltage *²

AVR

0

AVCC

V

Normal operation assurance range

V1 to V3 pins

LCD power supply

voltage

(TheoptimumvalueisdependentontheLCD

element in use.)

Not for MB90F377

V1 to V3

T^A

V^SS

VCC

V

Operating

temperature

−40

+85

°C

*1 : Set AV^CC, CVCC and VCC at the same voltage.

*2 : Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed VCC + 0.3 V when power is turned on.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

111

MB90370/375 Series

3. DC Characteristics

(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Typ

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Max

P10 to P17

P20 to P27

P30 to P37

P46, P47

P50 to P57

PA0 to PA6

PB0 to PB7

PC0 to PC7

PD0 to PD7

PF0 to PF7

CMOS

V

V^IH

0.7 V^CC

VCC + 0.3

input pins

P00 to P07

P60 to P67

P70 to P77

PE0 to PE7

RST

CMOS

hysteresis

input pins

V^IHS

0.8 VCC

VCC + 0.3

V

“H” level input

voltage

5 V tolerant

CMOS

hysteresis

input pins

V^IHS5

P40 to P45

P82

0.8 VCC

0.7 VCC

VSS + 5.5

V

5 V tolerant

CMOS

V^IH5

input pin

P80, P81

P90 to P95

SMbus

input pins

V^IHSM

2.1

VSS + 5.5

VCC + 0.3

V

VIHM

MD0 to MD2

VCC − 0.3

Mode pins

P10 to P17

P20 to P27

P30 to P37

P46, P47

P50 to P57

P82

CMOS

input pins

V^IL

V^SS− 0.3

0.3 VCC

V

PA0 to PA6

PB0 to PB7

PC0 to PC7

PD0 to PD7

PF0 to PF7

“L” level input

voltage

P00 to P07

P40 to P45

P60 to P67

P70 to P77

PE0 to PE7

RST

CMOS

hysteresis

input pins

V^ILS

VSS − 0.3

0.2 VCC

V

(Continued)

112

MB90370/375 Series

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

P80, P81

Condition

Unit Remarks

Min

Typ

Max

0.8

SMbus

V

V^ILSM

V^ILM

VSS − 0.3

“L” level input

voltage

P90 to P95

input pins

MD0 to MD2

VSS + 0.3

V

Mode pins

P40 to P45

P80 to P82

P90 to P95

Open-drain

output pin

application

voltage

VD5

VD

VSS − 0.3

VSS + 5.5

VCC + 0.3

P46

All port pins

except

P40 to P46

P80 to P82

P90 to P95

PF0 to PF7

V^CC= 3.0 V

IOH1 = −4.0 mA

V^OH1

VCC − 0.5

V

“H” level output

voltage

VCC = 3.0 V

IOH2 = −8.0 mA

V^OH2

PF0 to PF7

All port pins

except

PF0 to PF7

V^OL1

V^OL2

IOL1 = 4.0 mA

IOL2 = 12.0 mA

0.4

V

“L” level output

voltage

PF0 to PF7

Input leakage

current (High-Z

output leakage

current)

VCC = 3.3 V,

VSS < VI < VCC

IIL

All input pins

−5

+5

µA

Open-drain

output leakage

current

P40 to P46

P80 to P82

P90 to P95

I^LEAK

5

µA

MB90F372 /

F377

VCC = 3.3 V,

Internal operation

at 16 MHz

37

30

45

35

mA

I^CC

mA MB90372

VCC = 3.3 V,

Internal operation

at 16 MHz,

In sleep mode

I^CCS

15

20

mA

Power supply

current*

VCC

VCC = 3.3 V,

External 32 kHz,

Internal operation

at 8 kHz,

I^CCL

23

80

µA

In sub-clock mode,

T^A= +25 °C

(Continued)

113

MB90370/375 Series

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Typ

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Max

VCC = 3.3 V,

External 32 kHz,

Internal operation

at 8 kHz,

I^CCLS

10

50

µA

In sub-clock sleep

mode,

TA = +25 °C

VCC = 3.3 V,

External 32 kHz,

Internal operation

at 8 kHz,

In watch mode,

TA = +25 °C

I^CCWAT

1.5

30

µA

Power supply

current*

VCC

VCC = 3.3 V,

Internal operation

at 16 MHz,

In timebase timer

mode

ICCT

1.3

1

2

mA

VCC = 3.3 V,

In stop mode,

TA = +25 °C

I^CCH

20

µA

All input pins

except VCC,

AVCC, CVCC,

Input

capacitance

C^IN

5

15

pF

VSS, AVSS, CVSS

Between V^CCand V3

at VCC = 3.3 V

100

50

200

400

LCD divided

resistance

Not for

kΩ

Between V3 and V2

Between V2 and V1

Between V1 and VSS

at VCC = 3.3 V

R^LCD

MB90F377

100

200

COM0 to

COM3 output

impedance

R^VCOMCOM0 to COM3

5

kΩ

Not for

MB90F377

V1 to V3 = 3.3 V

SEG0 to SEG8

output

R^VSEG

SEG0 to SEG8

kΩ

impedance

V1 to V3

COM0 to COM3

SEG0 to SEG8

LCD leakage

current

Not for

µA

L^LCDL

±1

MB90F377

(Continued)

114

MB90370/375 Series

(Continued)

(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Typ

Max

P00 to P07

P10 to P17

P20 to P27

P30 to P37

RST

Pull-up

resistance

R^UP

25

50

100

kΩ

MB90V370,

kΩ MB90372

only

Pull-down

resistance

R^DOWNMD2

25

50

100

* : The power supply current is measured with an external clock.

115

MB90370/375 Series

4. AC Characteristics

(1) Clock Timings

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Typ

Parameter

Clock frequency

Clock cycle time

Symbol Pin name Condition

Unit

Remarks

Min

3

Max

16

F^CH

X0, X1

MHz Crystal oscillator*

3

32

MHz External clock*

F^CL

X0A, X1A

X0, X1

32.768

30.5

kHz

ns

t^HCYL

t^LCYL

31.25

5

333

X0A, X1A

µs

P^WH

PWL

Recommend duty

ns

X0

X0A

X0

ratio of 30% to 70%

Input clock pulse width

Input clock rise/fall time

P^WHL

PWLL

Recommend duty

µs

15.2

ratio of 30% to 70%

t^CR

tCF

External clock

operation

5

ns

Internaloperatingclock

frequency

f^CP

f^LCP

t^CP

1.5

16

MHz Main clock operation

kHz Sub-clock operation

ns Main clock operation

µs Sub-clock operation

8.192

122.1

62.5

666

Internaloperatingclock

cycle time

t^LCP

* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned

in “Relationship between oscillating frequency and internal operating clock frequency” of “• PLL operation

guarantee range”.

X0, X1 clock timing

tHCYL

0.8 VCC

X0

0.2 VCC

PWH

PWL

tCF

tCR

X0A, X1A clock timing

tLCYL

0.8 VCC

0.2 VCC

X0A

PWHL

PWLL

tCF

tCR

116

MB90370/375 Series

• PLL operation guarantee range

Relationship between internal operating clock frequency and power supply voltage

3.6

Operation guarantee

range of PLL

3.0

Normal operation guarantee range

1.5

4

8

16

Internal operating clock fCP (MHz)

Relationship between oscillating frequency and internal operating clock frequency

Multiplied- Multiplied-

by-4 by-3

Multiplied-

by-2

Multiplied-

by-1

16

12

9

8

Not multiplied

4

3

4

8

16

Oscillation clock FC (MHz)

117

MB90370/375 Series

The AC ratings are measured for the following measurement reference voltages :

• Input signal waveform

Hysteresis input pin

• Output signal waveform

Output pin

0.8 VCC

0.2 VCC

2.4 V

0.8 V

CMOS input pin

0.7 VCC

0.3 VCC

SMbus input pin

2.1 V

0.8 V

118

MB90370/375 Series

(2) Reset Input Timing

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name Condition

Unit

Remarks

Normal

Min

Max

16 t^CP

ns

operation

Reset input time

t^RSTL

RST

In stop mode

ms and sub-clock

mode

Oscillation time of

oscillator* + 16 t^CP

* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal

oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time

is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.

• In stop mode and sub-clock mode

t

RSTL

RST

0.2 Vcc

90% of the oscillation amplitude

X0

Internal

operation

clock

Oscillation time of

oscillator

16 tCP

Oscillator stabilization time

Instruction

execution

Internal reset

119

MB90370/375 Series

(3) Power-on Reset

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name Condition

Unit

Remarks

Min

Max

Power supply rise time

t^R

VCC*

50

ms

Due to repeated

operations

Power supply cut-off time

t^OFF

1

* : V^CCmust be kept lower than 0.2 V before power-on.

Notes : • The above values are used for causing a power-on reset.

Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn

on the power supply using the above values.

• Make sure that power supply rises within the selected oscillation stabilization time. If the power supply

voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

t

R

tOFF

2.2 V

0.2 V

VCC

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommneded

to raise the voltage smoothly to suppress fluctuations as shown below. In this case,

change the supply voltage with the PLL clock not used. If the voltage drop is 1 V

or fewer per second, however, you can use the PLL clock.

VCC

It is recommended to keep

the rising speed of the supply

voltage at 50 mV/ms or slower.

1.8 V

VSS

RAM data hold

120

MB90370/375 Series

(4) UART1 to UART3

Parameter

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol

Pin name

Condition

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

UCK1 to UCK3

8 t^CP

ns

UCK1 to UCK3

UO1 to UO3

UCK ↓ → UO delay time

−80

100

tCP

+80

C^L= 80 pF + 1 TTL

for an output pin of

internal shift clock

mode

UCK1 to UCK3

UI1 to UI3

Valid UI → UCK ↑

t^IVSH

ns

UCK1 to UCK3

UI1 to UI3

UCK ↑ → valid UI hold time

tSHIX

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

UCK1 to UCK3

4 t^CP

ns

tSLSH

4 tCP

UCK1 to UCK3 C^L= 80 pF + 1 TTL

UCK ↓ → UO delay time

Valid UI → UCK ↑

t^SLOV

t^IVSH

t^SHIX

150

ns

UO1 to UO3

for an output pin of

external shift clock

mode

UCK1 to UCK3

UI1 to UI3

60

UCK1 to UCK3

UI1 to UI3

UCK ↑ → valid UI hold time

Notes : • These are AC ratings in the CLK synchronous mode.

• C^Lis the load capacitance value connected to pins while testing.

• t^CPis the internal operating clock cycle time.

121

MB90370/375 Series

• Internal shift clock mode

tSCYC

UCK

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

UO

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

UI

• External shift clock mode

tSLSH

tSHSL

0.8 VCC

UCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

UO

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

UI

122

MB90370/375 Series

(5) Resources Input Timing

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Max

t^TIWH

tTIWL

Timer input pulse width

TIN1 to TIN4

4 tCP

ns

0.8 VCC

TIN1 to TIN4

0.2 VCC

tTIWH

tTIWL

(6) Trigger Input Timing

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min

Max

ADTG

INT0 to INT5

KSI0 to KSI7

5 tCP

ns Normal operation

t^TRGH

tTRGL

Input pulse width

1

µs Stop mode

0.8 VCC

INT0 to INT5

KSI0 to KSI7

0.2 VCC

tTRGH

tTRGL

0.7 VCC

0.3 VCC

ADTG

0.3 VCC

tTRGH

tTRGL

123

MB90370/375 Series

(7) I²C / MI²C Timing

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name

Unit Remarks

Min

Max

SCL

SDA

Master

mode

Start condition output

Stop condition output

Start condition detect

Stop condition detect

Restart condition output

Restart condition detect

SCL output “L” width

t^STA

tCP (m × n/2 − 1) - 20 tCP (m × n/2 − 1) + 20 ns

tCP (m × n/2 + 3) - 20 tCP (m × n/2 + 3) + 20 ns

SCL

SDA

Master

mode

t^STO

SCL

SDA

t^STA

tCP + 40

ns

SCL

SDA

tSTO

SCL

t^STASU

Master

mode

tCP (m × n/2 + 3) - 20 tCP (m × n/2 + 3) + 20 ns

SDA

SCL

t^STASU

tCP + 40

ns

SDA

Master

mode

t^LOW

SCL

tCP × m x n/2 - 20

tCP × m × n/2 + 20

Master

mode

SCL output “H” width

SDA output delay

tHIGH

SCL

SDA

tCP (m × n/2 + 2) - 20 tCP (m × n/2 + 2) + 20 ns

t^DO

tCP × 3 − 20

t^CP× m × n/2 − 20

t^CP× 4 − 20

tCP × 3 + 40

tCP + 40

tCP × 3 + 20

ns

ns *1

ns *2

ns

SDA output setup time

after interrupt

t^DOSU*³

SDA

SCL input “L” pulse

SCL input “H” pulse

SDA output setup time

SDA hold time

t^LOW

t^HIGH

t^SU

SCL

SDA

ns

40

ns

t^HO

0

ns

*1 : At the stop condition or transferring of next byte.

*2 : After setting register bit IBCRH : SCC/MBCRH : SCC at restart.

*3 : t^DOSUis longer than the “L” width of SCL.

Notes : • tCP is the internal operating clock cycle time.

• m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4 to CS3) ” and “MCCR register

(CS4 to CS3) ”. Please refer to the MB90370/375 series H/W manual for details.

• n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 to CS0) ” and “MCCR register

(CS2 to CS0) ”. Please refer to the MB90370/375 series H/W manual for details.

• SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”.

124

MB90370/375 Series

• Data transmit (master / slave)

tDO

tSU

tHO

tDOSU

ACK

9

SDA

tSTASU

tSTA

tLOW

tHO

1

SCL

• Data receive (master / slave)

tDOSU

tSU

tHO

tDO

ACK

SDA

tHIGH

tLOW

tSTO

6

7

8

9

SCL

125

MB90370/375 Series

(8) PS/2 Interface Timing

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Typ

Parameter

PSCK clock

Symbol

Pin name

Condition

Unit Remarks

Min

Max

PSCK0 to PSCK2

PSDA0 to PSDA2

t^PCYC

tPLOV

tPIVSH

t^PHIX

4 tCP

ns

cycle time

PSCK0 to PSCCK2 Transmission

PSDA0 to PSDA2 Mode

PSCK ↓ → PSDA

2 tCP

1 tCP

2 tCP

Valid PSDA →

PSCK ↓

PSCK0 to PSCK2

PSDA0 to PSDA2

Reception

Mode

PSCK0 to PSCK2

PSDA0 to PSDA2

PSCK ↓ → valid

PSDA hold time

PSCK clock “H”

pulse width

PSCK0 to PSCK2

PSDA0 to PSDA2

tPHSL

t^PLSH

PSCK0 to PSCK2

PSDA0 to PSDA2

PSCK clock “L”

pulse width

Note : t^CPis the internal operating clock cycle time.

tPCYC

0.8 VCC

PSCK0

PSCK1

PSCK2

0.2 VCC

tPLOV

• Transmission Mode

2.4 V

0.8 V

PSDA0

PSDA1

PSDA2

tPIVSH

tPHIX

• Reception Mode

0.8 VCC

0.2 VCC

PSDA0

PSDA1

PSDA2

126

MB90370/375 Series

(9) LPC Timing

Parameter

(V^CC= AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Symbol Pin name Condition

Unit

Remarks

Min

30

Typ

Max

LCLK cycle time

LCLK high time

LCLK low time

t^CYCLE

tHIGH

t^LOW

ns

12

LCLK AC timing

tCYCLE

tHIGH

0.7 VCC

0.3 VCC

LCLK

tLOW

127

MB90370/375 Series

LAD, LFRAME, GA20 AC timing

0.4 VCC

LCLK

tVAL

OUTPUT

Delay

tON

Tri-state

OUTPUT

tOFF

0.4 VCC

LCLK

tH

tS

INPUT

128

MB90370/375 Series

5. A/D Converter Electrical Characteristics

(2.7 V ≤ AVR − AVSS, VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Unit

Remarks

name

Min

Typ

Max

10

Resolution

bit

Total error

±3.0

±2.5

LSB

Non-linear error

Differential linearity

error

±1.9

LSB

mV

AV^SS+

5.5 LSB

For MB90V370

Zero transition

voltage

AN0 to

AN11

AVSS −

1.5 LSB

AVSS +

0.5 LSB

V^OT

AVSS +

2.5 LSB

For MB90F372/F377/372

Full-scaletransition

voltage

AN0 to

AN11

AVR −

3.5 LSB

AVR −

1.5 LSB

AVR +

0.5 LSB

V^FST

Actual value is specified as

a sum of values specified in

ADCR0 : CT1, CT0 and

ADCR0 : ST1, ST0. Be sure

that the setting value is

Conversion time

Sampling period

3.1

2

µs

greater than the Min value.

Actual value is specified in

ADCR0 : ST1, ST0 bits. Be

sure that the setting value is

greater than the Min value.

Analog port input

current

AN0 to

AN11

I^AIN

0.1

10

µA

Analog input

voltage

AN0 to

AN11

V^AIN

AVSS

AVR

V

Reference voltage

AVR

AV^SS+ 2.7

AVCC

6.4

5

V

IA

IAH

I^R

1.4

94

mA

µA

Power supply

current

AVCC

*

300

5

Reference voltage

supply current

AVR

I^RH

Offset between

channels

AN0 to

AN11

—

4

LSB

* : The current when the A/D converter is not operating or the CPU is in stop mode (for V^CC= AVCC = AVR = 3.0 V) .

129

MB90370/375 Series

6. A/D Converter Glossary

Resolution :

Analog changes that are identifiable with the A/D converter.

Linearity error :

The deviation of the straight line connecting the zero transition point (“00 0000 0000”

↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111

1111”) from actual conversion characteristics.

Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value.

Total error :

The total error is defined as a difference between the actual value and the theoretical

value, which includes zero-transition error/full-scale transition error and linearity error.

Total error

3FF

3FE

3FD

Actual conversion

value

0.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

004

VNT

(Measured value)

Actual conversion

value

003

002

001

Theoretical

characteristics

0.5 LSB

AVRL

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

Total error for digital output N =

1 LSB = (Theoretical value)

[LSB]

1 LSB

AVR − AVss

1024

[V]

VOT (Theoretical value) = AVss + 0.5 LSB [V]

VFST (Theoretical value) = AVR − 1.5 LSB [V]

VNT : Voltage at a transition of digital output from (N - 1) to N

(Continued)

130

MB90370/375 Series

(Continued)

Linearity error

Differential linearity error

Theoretical

characteristics

Actual conversion

3FF

value

Actual conversion

value

3FE

3FD

N + 1

{1 LSB × (N − 1)

+ VOT }

VFST

(Measured

value)

N

V (N + 1) T

(Measured

value)

N − 1

VNT

004

003

(Measured value)

VNT

Actual conversion

value

(Measured value)

002

001

N − 2

Actual conversion

value

Theoretical

characteristics

VOT (Measured value)

AVRL

AVRH

AVRL

AVRH

Analog input

Linearity error of

digital output N

V^NT− {1 LSB × (N − 1) + VOT}

=

[LSB]

1 LSB

Differential linearity error

of digital output N

V ^{(N + 1) T}− VNT

− 1 [LSB]

1 LSB

V^FST− VOT

[V]

1 LSB =

1022

V^OT: Voltage at transition of digital output from “000H” to “001H”

VFST : Voltage at transition of digital output from “3FEH” to “3FFH”

131

MB90370/375 Series

7. Notes on Using A/D Converter

Select the output impedance value for the external circuit of analog input according to the following conditions.

Output impedance values of the external circuit of 4 kΩ or lower are recommended.

When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor

value is recommended to minimized the effect of voltage distribution between the external capacitor and internal

capacitor.

When the output impedance of the external circuit is too high, the sampling period for analog voltages may not

be sufficient.

• Equipment of analog input circuit model

Sampling and hold circuit

Analog input

Comparator

R

C

R : about 1.9 kΩ

C : about 32.3 pF

Note : Listed values must be considered as standards.

• Error

The smaller the | AVR - AV^SS| is, the greater the error would become relatively.

8. D/A Electrical Characteristics

(VCC = AVCC = CVCC = 3.0 V to 3.6V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Resolution

Symbol Pin name Condition

Unit Remarks

Min

Typ

Max

8

bit

Differential linearity error

Non-linearity error

Conversion time

Analog output impedance

Power supply

±0.9

±1.5

LSB

0.6

2.9

µs

kΩ

µA

*

2.0

3.8

I^DVR

AVCC

460

Current

IDVRS

0.1

µA D/A stops

* : With load capacitance is 20 pF.

132

MB90370/375 Series

9. Comparator Electrical Characteristics

(VCC = AVCC = CVCC = 3.3 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

1.1

Typ

Max

2.9

CVRH2

CVRH1

CVRL

V

Reference voltage

CVRL

1.1

2.9

V

*

CVRH1

CVRH2

CVRH1

CVRL

Reference voltage

supply current

I^CR

±1

µA

50

10

µA active

Comparator

supply current

I^CV

CVCC

µA inactive

DCIN

DCIN2

VOL1 to VOL3

VSI1 to VSI3

Analog input voltage

V^IH

CV^SS

CVCC

V

*: Please use the reference voltage of CVRH2, CVRH1 and CVRL to 0.5V^CCfor MB90F377.

10. Serial IRQ Electrical Characteristics

(VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C)

Value

Parameter

Symbol Pin name Condition

Unit Remarks

Min

0.7VCC

VSS

Typ

Max

VCC

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

V^IH

VIL

V

0.3VCC

V^OH

VOL

VCC − 0.5

0.4

11. Flash Memory Program/Erase Characteristics

Value

Parameter

Condition

Unit

Remarks

Min

Typ

Max

Excludes 00^Hprogramming prior

to erasure

Sector erase time

Chip erase time

1

15

s

T^A= +25 °C

VCC = 3.0 V

Excludes 00^Hprogramming prior

to erasure

4

Word (16 bit width)

programing time

Except for the over head time of

the system

16

3,600

µs

Program/Erase cycle

10,000

cycle

133

MB90370/375 Series

■ EXAMPLE CHARACTERISTICS

• MB90F372

VCC vs. ICCS

VCC vs. ICC

18.0

16.0

14.0

12.0

10.0

8.0

50.0

Ta

25 °C

Ta

25 °C

FCH = 16.0 MHz

FCH = 12.0 MHz

40.0

30.0

20.0

10.0

0.0

FCH = 12.0 MHz

FCH = 10.0 MHz

FCH = 8.0 MHz

6.0

FCH = 4.0 MHz

FCH = 2.0 MHz

FCH = 4.0 MHz

FCH = 2.0 MHz

4.0

2.0

0.0

2.0

2.5

3.0

VCC (V)

3.5

4.0

4.5

2.0

2.5

3.0

3.5

4.0

4.5

VCC (V)

VCC vs. ICCL

30.0

25.0

20.0

15.0

10.0

5.0

Ta

25 °C

FCL = 32.0 kHz

0.0

2.0

2.5

3.0

VCC (V)

3.5

4.0

4.5

(Continued)

134

MB90370/375 Series

(Continued)

IOH2 vs. VCC - VOH2

IOH1 vs. VCC - VOH1

2.0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Ta

25 °C

Ta

25 °C

1.5

1.0

0.5

0.0

Vcc = 2.5 V

Vcc = 3.0 V

Vcc = 2.5 V

Vcc = 3.0 V

Vcc = 3.5 V

-10

0

-2

-4

-6

-8

0

-2

-4

-6

-8

-10

IOH1 (mA)

IOH2 (mA)

IOL2 vs. VOL2

IOL1 vs. VOL1

0.8

0.3

Ta

25 °C

Ta

25 °C

Vcc = 2.5 V

Vcc = 3.0 V

0.6

0.4

0.2

0.0

Vcc = 2.5 V

Vcc = 3.0 V

0.2

0.1

0.0

Vcc = 3.5 V

0

2

4

6

8

10

0

2

4

6

8

10

IOL1 (mA)

IOL2 (mA)

135

MB90370/375 Series

• MB90372t

VCC vs. ICCS

VCC vs. ICC

18.0

16.0

14.0

12.0

10.0

8.0

40.0

Ta

25 °C

FCH = 16.0 MHz

Ta

25 °C

FCH = 16.0 MHz

FCH = 12.0 MHz

30.0

20.0

10.0

0.0

FCH = 12.0 MHz

FCH = 10.0 MHz

FCH = 8.0 MHz

6.0

FCH = 4.0 MHz

FCH = 2.0 MHz

4.0

FCH = 4.0 MHz

FCH = 2.0 MHz

2.0

0.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

1.5

2.0

2.5

3.0

3.5

4.0

4.5

VCC (V)

VCC vs. ICCL

30.0

Ta

25 °C

25.0

20.0

15.0

10.0

5.0

FCL = 32.0 kHz

0.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

VCC (V)

(Continued)

136

MB90370/375 Series

(Continued)

IOH1 vs. VCC - VOH1

IOH2 vs. VCC - VOH2

1.0

0.4

0.3

0.2

0.1

0.0

Ta

25 °C

Ta

25 °C

Vcc = 2.5 V

0.8

0.6

0.4

0.2

0.0

Vcc = 2.5 V

Vcc = 3.0 V

Vcc = 3.5 V

-10

0

-2

-4

-6

-8

-10

0

-2

-4

-6

-8

IOH1 (mA)

IOH2 (mA)

IOL1 vs. VOL1

IOL2 vs. VOL2

0.25

0.20

0.15

0.10

0.05

0.0

0.8

Vcc = 2.5 V

Vcc = 3.0 V

Vcc = 3.5 V

Ta

25 °C

Ta

25 °C

Vcc = 2.5 V

Vcc = 3.0 V

0.6

0.4

0.2

0.0

Vcc = 3.5 V

10

0

2

4

6

8

0

2

4

6

8

IOL2 (mA)

IOL1 (mA)

137

MB90370/375 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F372PFF-G

MB90F377PFF-G

MB90372PFF-G-XXX

144-pin Plastic LQFP

(FPT-144P-M12)

XXX is the ROM release number.

138

MB90370/375 Series

■ PACKAGE DIMENSION

Note 1) * : These dimensions include resin protrusion.

Resin protrusion is +0.25(.010)Max(each side).

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

144-pin plastic LQFP

(FPT-144P-M12)

18.00±0.20(.709±.008)SQ

+0.40

16.00^–^0.10.630 ⁺–^.^.⁰⁰⁰¹⁴⁶SQ

*

73

108

72

109

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.210⁰

.059 –⁺.^.0⁰⁰04⁸

(Mounting height)

INDEX

0~8˚

37

144

"A"

0.10±0.05

(.004±.002)

(Stand off)

0.60±0.15

(.024±.006)

1

LEAD No.

36

0.25(.010)

0.145 ⁺–0⁰.^.0⁰3⁵

.006 ⁺^–.^.⁰⁰⁰⁰¹²

0.40(.016)

0.18±0.035

.007±.001

M

0.07(.003)

C

2003 FUJITSU LIMITED F144024S-c-3-3

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

139

MB90370/375 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0402

FUJITSU LIMITED Printed in Japan


型号：	MB90V370
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总140页 (文件大小：1283K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90V370 [FUJITSU]

相关型号：

MB90V378

MB90V390H

MB90V390HA

MB90V390HACR

MB90V390HB

MB90V390HBCR

MB90V390HCR

MB90V420G

MB90V440G

MB90V440GCR

MB90V460

MB90V480