MB90V390HCR_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13723-3E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90390 Series

MB90F394H/V390H

■ DESCRIPTION

The MB90390-series with up to five FULL-CAN* interfaces and FLASH ROM is especially designed for automotive

and industrial applications. Its main feature are up to five on board CAN Interfaces, which conform to V2.0 Part

A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a

normal full CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM

program memory up to 512K bytes. An internal voltage booster removes the necessity for a second programming

voltage.

An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms

of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external

4 MHz clock.

The unit features 6 Stepper Motor Controllers with slew rate controlled high current outputs.

Furthermore it features an 8 channel Output Compare Unit and a 6 channel Input Capture Unit with two separate

16-bit free running timers. Up to 4 UARTs constitute additional functionality for communication purposes.

* : Controller Area Network (CAN) - License of Robert Bosch GmbH

■ PACKAGE

120-pin Plastic LQFP

(FPT-120P-M21)

MB90390 Series

■ FEATURES

• 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instruction execution time)

• New 0.35 µm CMOS Process Technology

• Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures

• Up to five FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, flexible message buffering

(mailbox and FIFO buffering can be mixed)

• Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)

• EI²OS - Automatic transfer function indep.of CPU; 16 ch. of intelligent I/O Services

• 18-bit Time-base counter

• Watchdog Timer

• Up to 3 full duplex UARTs; support 10.4 KBand (USA standard )

• 1 full duplex UART (SCI)

• Serial I/O : 1ch for synchronous data transfer

• Optional I²C with 400 Kbps

• A/D Converter : 8 ch to 15 ch. analog inputs (Resolution 10 bits or 8 bits)

• 16-bit reload timer × 2 ch

• ICU (Input capture) 16-bit × 6 ch (2 input pins are shared with OCU outputs)

• OCU (Output capture) 16-bit × 8 ch (2 output pins are shared with ICU input pins)

• 16-bit free running timer × 2 ch (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5, OCU 4/5/6/7)

• 8/16-bit Programmable Pulse Generator 6ch × 16-bit / 12ch × 8-bit

• Stepping Motor Controller 6ch with slew rate controlled high current outputs

• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different

addressing modes; barrel shift; variety of pointers)

• 4-byte instruction execution queue

• signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available

• Program Patch Function

• Fast Interrupt processing

• Low Power Consumption mode

Sleep mode

Timebase timer mode

Stop mode

CPU intermittent mode

• Sound Generator

• Real Time Watch Timer

• Programmable input levels (Automotive Hysteresis / CMOS Hysteresis, initial level is Automotive Hysteresis)

• Package : 120-pin plastic LQFP

2

MB90390 Series

■ PRODUCT LINEUP

Part Number

Parameter

MB90F394H

MB90V390H

CPU

F²MC-16LX CPU

On-chip PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)

System clock

Boot-block

ROM

RAM

Flash memory 384K bytes

Hard-wired reset vector

External

10K bytes

16K bytes

Yes

Emulator-specific

power supply*¹

0.35 µm CMOS with on-chip voltage

regulator for internal power supply + Flash

memory with

On-chip charge pump for programming

voltage

0.35 µm CMOS with on-chip voltage

regulator for internal power supply

Technology

Operating

voltage range

3.5 V to 5.5 V

(4.5 V to 5.5 V if A/D Converter is used)

5 V ± 10%

Temperature range

Package

−40 °C to +85 °C

LQFP-120

PGA-299

2 channels

3 channels

Full duplex double buffer

UART

Supports asynchronous/synchronous (with start/stop bit) transfer

Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous)

500 K/1 M/2 Mbps (synchronous) at System clock = 24 MHz

UART

(SCI)

1 channel

I²C (400 Kbps)

Transfer can be started from MSB or LSB

Supports internal clock synchronized transfer and external clock synchronized transfer

Supports positive-edge and negative-edge clock synchronization

Serial I/O

Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 24 MHz

8 input channels

10-bit or 8-bit resolution

Conversion time : Min 4.9 µs include sample time (per one channel)

15 input channels

A/D

Converter

16-bit Reload Timer Operation clock frequency : fsys/2¹, fsys/2³, fsys/2⁵(fsys = System clock frequency)

(2 channels)

Supports External Event Count function

Directly operates with the oscillation clock

Facility to correct oscillation deviation

Read/Write accessible Second/Minute/Hour registers

Signals interrupts

Watch Timer

(Continued)

3

MB90390 Series

Part Number

Parameter

MB90F394H

Signals an interrupt when overflowing

MB90V390H

16-bit

I/O Timer

(2 channels)

Supports Timer Clear when a match with Output Compare (Channel 0)

Operation clock freq. : fsys/2², fsys/2⁴, fsys/2⁶, fsys/2⁸(fsys = System clock freq.)

I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3

I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5, OCU 4/5/6/7

Signals an interrupt when a match with 16-bit I/O Timer

Eight 16-bit compare registers.

A pair of compare registers can be used to generate an output signal.

OCU 6/7 outputs are shared with ICU 3/5 inputs

16-bit

Output Compare

(8 channels)

Rising edge, falling edge or rising & falling edge sensitive

Six 16-bit Capture registers

Signals an interrupt upon external event

ICU 3/5 inputs are shared with OCU 6/7 outputs

16-bit

Input Capture

(6 channels)

Supports 8-bit and 16-bit operation modes

Twelve 8-bit reload counters

8/16-bit

Twelve 8-bit reload registers for L pulse width

ProgrammablePulse Twelve 8-bit reload registers for H pulse width

Generator

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

(6 channels)

8-bit prescaler plus 8-bit reload counter

Operation clock freq. : fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴or 102.4 µs @fosc = 5 MHz

(fsys = System clock frequency, fosc = Oscillation clock frequency)

2 channels

5 channels

Conforms to CAN Specification Version 2.0 Part A and B

Automatic re-transmission in case of error

Automatic transmission responding to Remote Frame

Prioritized 16 message buffers for data and ID’s

Supports multiple messages

CAN Interface

(up to 5

channels)

Flexible configuration of acceptance filtering :

Full bit compare/Full bit mask/Two partial bit masks

Supports up to 1 Mbps

Stepping Motor

Controller

(6 channels)

Four high current outputs with controlled slew rate for each channel

Synchronized two 8-bit PWM’s for each channel

External Interrupt

(8 channels)

Can be programmed edge sensitive or level sensitive

8-bit PWM signal is mixed with tone frequency from 8-bit reload counter

PWM frequency : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz at System clock = 16 MHz

Tone frequency : PWM frequency/2/ (reload value + 1)

Sound Generator

Virtually all external pins can be used as general purpose I/O

All push-pull outputs

Bit-wise programmable as input/output or peripheral signal

Port-wise programmable as CMOS Hysteresis or automotive Hysteresis inputs (default)

I/O Ports

(Continued)

4

MB90390 Series

(Continued)

Part Number

Parameter

MB90F394H

MB90V390H

Supports automatic programming,

Embedded Algorithm^TM*²

Write/Erase/Erase-Suspend/Resume

commands

A flag indicating completion of the algorithm

Number of erase cycles : 10,000 times

Data retention time : 20 years

Hard-wired reset vector available in order to

point to a fixed boot sector in Flash Memory

Boot block configuration

Flash

Memory

Erase can be performed on each block

Block protection with external programming

voltage

*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.

Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply

Switching) about details.

*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

5

MB90390 Series

■ PIN ASSIGNMENTS

• MB90V390H

(TOP VIEW)

1

2

3

4

5

6

7

8

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

P30/RX0

P31/TX0

RST

MD0

P32/TIN1

P33/TOT1

P34/SOT0

P35/SCK0

P36/SIN0

P37/SIN1

P40/SCK1

P41/SOT1

P42/SDA

P43/SCL

MD1

MD2

DVSS

DVCC

PA7/PWM2M5

PA6/PWM2P5

PA5/PWM1M5

PA4/PWM1P5

PA3/PWM2M4

PA2/PWM2P4

PA1/PWM1M4

PA0/PWM1P4

DVSS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P44

P45/ADTG

VCC

VSS

C

DVCC

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

DVSS

P46/INT0

P47/INT1

P50/PPG10

P51/PPG11

P52/PPG12

P53/PPG13

P54/PPG14

P55/PPG15

P56/PPG00/RX2

P57/PPG01/TX2

P90/SIN2

P91/SCK2

P92/SOT2

DVCC

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

(FPT-120P-M21)

As seen with QFP120 probe cable

6

MB90390 Series

• MB90F394H

(TOP VIEW)

1

2

3

4

5

6

7

8

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

P30/RX0

RST

P31/TX0

P32/TIN1

P33/TOT1

P34/SOT0

P35/SCK0

P36/SIN0

P37/SIN1

P40/SCK1

P41/SOT1

P42

MD0

MD1

MD2

DVSS

DVCC

PA7/PWM2M5

PA6/PWM2P5

PA5/PWM1M5

PA4/PWM1P5

PA3/PWM2M4

PA2/PWM2P4

PA1/PWM1M4

PA0/PWM1P4

DVSS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P43

P44

P45/ADTG

VCC

VSS

C

DVCC

P87/PWM2M3

P86/PWM2P3

P85/PWM1M3

P84/PWM1P3

P83/PWM2M2

P82/PWM2P2

P81/PWM1M2

P80/PWM1P2

DVSS

P46/INT0

P47/INT1

P50/PPG10

P51/PPG11

P52/PPG12

P53/PPG13

P54/PPG14

P55/PPG15

P56/PPG00

P57/PPG01

P90

DVCC

P77/PWM2M1

P76/PWM2P1

P75/PWM1M1

P74/PWM1P1

P91

P92

(FPT-120P-M21)

7

MB90390 Series

■ PIN DESCRIPTION

Pin no.

107

Pin name

X1

Circuit type

Function

Oscillation output

Oscillation input

Reset input

A

B

D

108

X0

90

RST

P00 to P02

IN0 to IN2

P03

General purpose I/O

93 to 95

Inputs for the Input Captures 0-2

General purpose I/O

96

IN3

D

Input for the Input Capture 3

Output for the Output Compare 6

General purpose I/O

OUT6

P04

97

IN4

Input for the Input Capture 4

General purpose I/O

P05

98

IN5

Input for the Input Capture 5

Output for the Output Compare 7

OUT7

P06, P07,

P10 to P13

General purpose I/O

99 to 104

D

OUT0 to OUT5

P14

Outputs for the Output Compares

General purpose I/O

109

110

D

TIN0

TIN0 input for the 16-bit Reload Timer 0

General purpose I/O

P15

TOT0

P16

TOT0 output for the 16-bit Reload Timer 0

General purpose I/O

111

SGO

SGO output for the Sound Generator

General purpose I/O

P17

112

SGA

SGA output for the Sound Generator

General purpose I/O

P20

113

TX1

TX output for CAN Interface 1

General purpose I/O

P21

114

RX1

RX input for CAN Interface 1

General purpose I/O

P22 to P27

INT2 to INT7

P30

115 to 120

1

External interrupt inputs for INT2 to INT7

General purpose I/O

RX0

RX input for CAN Interface 0

General purpose I/O

P31

2

TX0

TX output for CAN Interface 0

(Continued)

8

MB90390 Series

Pin no.

Pin name

P32

Circuit type

Function

General purpose I/O

3

D

TIN1

TIN1 input for the 16-bit Reload Timer 1

General purpose I/O

P33

4

5

D

TOT1

P34

TOT1 output for the 16-bit Reload Timer 1

General purpose I/O

SOT0

P35

SOT output for UART 0

General purpose I/O

6

SCK0

P36

SCK input/output for UART 0

General purpose I/O

7

SIN0

SIN input for UART 0

P37

General purpose I/O

8

SIN1

SIN input for UART 1

P40

General purpose I/O

9

SCK1

P41

SCK input/output for UART 1

General purpose I/O

10

11

SOT1

P42

SOT output for UART 1

General purpose I/O

SDA

Serial data for I²C interface

P43

General purpose I/O

12

13

14

D

SCL

Serial clock for I²C interface

General purpose I/O

P44

P45

General purpose I/O

ADTG

P46, P47

INT0, INT1

P50 to P55

PPG10 to PPG15

P56

External trigger input of the A/D Converter

General purpose I/O

18, 19

D

External interrupt inputs for INT0 to INT1

General purpose I/O

20 to 25

Outputs for the Programmable Pulse Generators

General purpose I/O

26

PPG00

RX2

D

Output for the Programmable Pulse Generator 0

RX input for CAN Interface 2

General purpose I/O

P57

27

28

PPG01

TX2

D

Output for the Programmable Pulse Generator 1

TX output for CAN Interface 2

General purpose I/O

P90

SIN2

SIN input for UART 2

(Continued)

9

MB90390 Series

Pin no.

Pin name

P91

Circuit type

Function

General purpose I/O

29

D

SCK2

P92

SCK input/output for UART 2

General purpose I/O

30

31

D

E

SOT2

P93

SOT output for UART 2

General purpose I/O

SIN3

SIN input for UART 3 (SCI)

General purpose I/O

P94

32

SCK3

P95

SCK input/output for UART 3 (SCI)

General purpose I/O

33

SOT3

P96

SOT output for UART 3 (SCI)

General purpose I/O

34

WOT

P60 to P67

AN0 to AN7

PB0

WOT output for the Watch Timer

General purpose I/O

39 to 46

Inputs for the A/D Converter

General purpose I/O

PPG02

TX3

Output for the Programmable Pulse Generator 2

TX output for CAN Interface 3

Input for the A/D Converter

General purpose I/O

48

49

50

E

AN8

PB1

PPG03

RX3

Output for the Programmable Pulse Generator 3

RX input for CAN Interface 3

Input for the A/D Converter

General purpose I/O

AN9

PB2

PPG04

TX4

Output for the Programmable Pulse Generator 4

TX output for CAN Interface 4

Input for the A/D Converter

General purpose I/O

AN10

PB3

PPG05

RX4

Output for the Programmable Pulse Generator 5

RX input for CAN Interface 4

Input for the A/D Converter

General purpose I/O

51

52

E

AN11

PB4

SIN4

SIN input for the Serial I/O

Input for the A/D Converter

AN12

(Continued)

10

MB90390 Series

Pin no.

Pin name

PB5

Circuit type

Function

General purpose I/O

53

SCK4

E

SCK input/output for the Serial I/O

Input for the A/D Converter

General purpose I/O

AN13

PB6

54

SOT4

E

F

SOT output for the Serial I/O

Input for the A/D Converter

General purpose I/O

AN14

P70 to P73

PWM1P0

PWM1M0

PWM2P0

PWM2M0

57 to 60

Output for Stepping Motor Controller channel 0

P74 to P77

General purpose I/O

PWM1P1

PWM1M1

PWM2P1

PWM2M1

61 to 64

67 to 70

71 to 74

77 to 80

F

Output for Stepping Motor Controller channel 1

P80 to P83

General purpose I/O

PWM1P2

PWM1M2

PWM2P2

PWM2M2

Output for Stepping Motor Controller channel 2

P84 to P87

General purpose I/O

PWM1P3

PWM1M3

PWM2P3

PWM2M3

Output for Stepping Motor Controller channel 3

PA0 to PA3

General purpose I/O

PWM1P4

PWM1M4

PWM2P4

PWM2M4

Output for Stepping Motor Controller channel 4

PA4 to PA7

General purpose I/O

PWM1P5

PWM1M5

PWM2P5

PWM2M5

81 to 84

F

Output for Stepping Motor Controller channel 5

PB7

General purpose I/O

91

FRCK0

HCLK

D

FRCK0 input for the 16-bit I/O Timer 0

Oscillation Clock output

(Continued)

11

MB90390 Series

(Continued)

Pin no.

Pin name

P97

Circuit type

Function

General purpose I/O

92

FRCK1

HCLKX

D

FRCK1 input for the 16-bit I/O Timer 1

Inverted Oscillation Clock output

55

65

75

85

Dedicated power supply pins for the high current output buffers

(Pin No. 57 to 84)

DVcc

DVss

56

66

76

86

Dedicated ground pins for the high current output buffers

(Pin No. 57 to 84)

35

36

37

38

AVCC

AVRH

AVRL

AVss

Dedicated power supply pin (5 V) for the A/D converter

Dedicated pos. reference voltage pin for the A/D converter

Dedicated neg. reference voltage pin for the A/D converter

Dedicated power supply pin (0 V) for the A/D converter

These are input pins used to designate the operating mode. They

should be connected directly to V^CCor VSS.

88, 89

87

MD1, MD0

MD2

C

G

This is an input pin used to designate the operating mode. It

should be connected directly to V^CCor VSS.

15

105

Vcc

These are power supply (5 V) input pins

16

47

106

Vss

C

These are power supply (0 V) input pins

This is the power supply stabilization capacitor pin. It should be

connected to higher than or equal to 0.1 µF ceramic capacitor.

17

12

MB90390 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Oscillation feedback resistor :

1 MΩ approx.

X1

Clock input

P-ch

N-ch

X0

A

Standby control signal

• CMOS Hysteresis input with pull-up

Resistor :

50 kΩ approx.

VCC

R (pull-up)

R

B

C

CMOS HYS

• EVA device :

R

CMOS Hysteresis input

• Flash device :

CMOS input.

• CMOS output

• CMOS Hysteresis input

• Automotive Hysteresis input

VCC

P-ch

N-ch

D

CMOS HYS

R

Automotive

HYS

(Continued)

13

MB90390 Series

(Continued)

Type

Circuit

Remarks

• CMOS output

VCC

• CMOS Hysteresis input

• Automotive Hysteresis input

• Analog input

P-ch

N-ch

P-ch

E

Analog input

CMOS HYS

N-ch

R

Automotive

HYS

• CMOS high current output

• CMOS Hysteresis input

• Automotive Hysteresis input

Vcc

P-ch

High current

N-ch

F

R

CMOS HYS

Automotive

HYS

• EVA device :

CMOS HYS

CMOS Hysteresis input with pull-

down Resistor : 50 kΩ approx.

• Flash device :

R

G

R (pull-down)

CMOS input without pull-down.

14

MB90390 Series

■ HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Stabilization of supply voltage

• Treatment of unused pins

• Using external clock

• Power supply pins (V^CC/VSS)

• Pull-up/down resistors

• Crystal Oscillator Circuit

• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

• Connection of Unused Pins of A/D Converter if A/D Converter is unused.

• Notes on Energization

• Initialization

• Caution on Operations during PLL Clock Mode

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between V^CCand VSS.

• The AV^CCpower supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

For the same reason, also be careful not to let the analog power-supply voltage (AV^CC, AVRH) exceed the digital

power-supply voltage.

2. Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply

voltage operating range. Therefore, the VCC supply voltage should be stabilized.

For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at

commercial frequencies (50 Hz to 60 Hz) fall below 10 of the standard VCC supply voltage and the coefficient of

fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

3. Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the

device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should

be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

4. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90390 Series

X0

X1

15

MB90390 Series

5. Power supply pins (V^CC/V^SS)

• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential

are connected the inside of the device to prevent such malfunctioning as latch up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and observe the standard for total output current, be sure to connect the V^CCand VSS pins to the power supply

and ground externally.

• Connect V^CCand VSS to the device from the current supply source at a low impedance.

• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between

V^CCand VSS in the vicinity of VCC and VSS pins of the device.

VCC

VSS

VCC

VSS

VCC

MB90390

Series

VCC

VSS

VCC

VSS

6. Pull-up/down resistors

The MB90390 Series does not support internal pull-up/down resistors. Use external components where needed.

7. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground

area for stabilizing the operation.

8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14)

after turning-on the digital power supply (VCC) .

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure

that the voltage not exceed AVRH or AV^CC(turning on/off the analog and digital power supplies simultaneously

is acceptable) .

9. Connection of Unused Pins of A/D Converter if A/D Converter is unused

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.

10. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50

or more µs (0.2 V to 2.7 V) .

16

MB90390 Series

11. Initialization

In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers,

turn on the power again.

12. Notes on During Operation of PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

17

MB90390 Series

■ BLOCK DIAGRAMS

MB90V390

X0, X1

Clock

16LX

CPU

Controller

RST

I/O Timer 0

FRCK0

RAM 16 K

Input

Capture

6 ch

IN5 to IN0

Output

Compare

8 ch

OUT7 to OUT0

FRCK1

Prescaler x4

I/O Timer 1

SOT3 to SOT0

SCK3 to SCK0

SIN3 to SIN0

UART 4 ch

(1 ch SCI)

8/16-bit

PPG

6 ch

PPG05 to PPG00

PPG15 to PPG10

Prescaler

Serial I/O

RX4 to RX0

TX4 to TX0

CAN

5 ch

SOT4

SCK4

SIN4

PWM1M5 to PWM1M0

PWM1P5 to PWM1P0

PWM2M5 to PWM2M0

PWM2P5 to PWM2P0

DVcc3 to DVcc0

AVcc

SMC

6 ch

AVss

AN14 to AN0

AVRH

10-bit ADC

15 ch

DVss3 to DVss0

AVRL

ADTG

External

Interrupt

INT7 to INT0

TIN1, TIN0

16-bit Reload

Timer 2 ch

TOT1, TOT0

Sound

Generator

SGO

SGA

Watch

Timer

WOT

I²C

Interface

SDA

SCL

18

MB90390 Series

MB90F394H

X0, X1

RST

16LX

CPU

Clock

Controller

I/O Timer 0

FRCK0

RAM 10 K

Input

Capture

6 ch

IN5 to IN0

ROM/Flash

384 K

Output

Compare

8 ch

OUT7 to OUT0

FRCK1

Prescaler x 3

I/O Timer 1

SOT3, SOT1, SOT0

SCK3, SCK1, SCK0

SIN3, SIN1, SIN0

UART 3 ch

(1 ch SCI)

PPG05 to PPG00

PPG15 to PPG10

8/16-bit

PPG

6 ch

Prescaler

Serial I/O

RX1, RX0

TX1, TX0

CAN

2 ch

SOT4

SCK4

SIN4

PWM1M5 to PWM1M0

PWM1P5 to PWM1P0

PWM2M5 to PWM2M0

PWM2P5 to PWM2P0

DVcc3 to DVcc0

AVcc

SMC

6 ch

AVss

AN7 to AN0

AVRH

AVRL

10-bit ADC

8 ch

DVss3 to DVss0

ADTG

External

Interrupt

INT7 to INT0

TIN1, TIN0

16-bit Reload

Timer 2 ch

TOT1, TOT0

SGO

SGA

Sound

Generator

Watch

Timer

WOT

19

MB90390 Series

■ MEMORY MAP

MB90V390H

FFFFFFH

ROM (FF bank)

FF0000H

FEFFFFH

ROM (FE bank)

FE0000H

MB90F394H

FFFFFFH

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

FF0000H

FEFFFFH

FE0000H

FDFFFFH

ROM (FD bank)

FD0000H

FCFFFFH

FD0000H

FCFFFFH

ROM (FC bank)

FC0000H

FBFFFFH

ROM (FB bank)

FB0000H

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

FB0000H

FAFFFFH

ROM (FA bank)

FA0000H

F9FFFFH

ROM (F9 bank)

F90000H

FA0000H

F9FFFFH

F90000H

00FFFFH

ROM (Image of

FF bank)

0 0 8 0 0 0 H

0 0 4 0 0 0 H

or

0 0 8 0 0 0 H

0050FFH

0 0 4 1 0 0 H

RAM 4 K

003FFFH

Peripheral

0 0 3 5 0 0 H

0030FFH

0 0 3 5 0 0 H

0028FFH

RAM 12 K

Peripheral

RAM 10 K

Peripheral

0 0 0 1 0 0 H

0000BFH

0 0 0 0 0 0 H

0000BFH

0 0 0 0 0 0 H

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without

using the far specification in the pointer declaration.

For example, an attempt to access 00C000^Haccesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 32/48K bytes, and its entire image cannot be shown in bank 00.

The image between FF4000^H/FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H

and FF3FFFH/FF7FFFH is visible only in bank FF.

In MB90V390H, the image for only ROM data between FF8000H to FFFFFFH is visible in bank 00.

As for MB90F394H, it is possible to set the FF bank area which looks the 00 bank image in the ROM mirror

function select register (ROMM) .

20

MB90390 Series

■ I/O MAP

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

00^H

01H

Port 0 Data Register

Port 1 Data Register

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

PDRB

ADER0

ADER1

ILSR

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port 6, A/D

Port B, A/D

Ports

XXXXXXXX

11111111

01111111

00000000

02^H

Port 2 Data Register

03^H

Port 3 Data Register

04H

Port 4 Data Register

05^H

Port 5 Data Register

06^H

Port 6 Data Register

07H

Port 7 Data Register

08^H

Port 8 Data Register

09H

Port 9 Data Register

0A^H

0BH

0CH

0D^H

0EH

0FH

10^H

Port A Data Register

Port B Data Register

Analog Input Enable 0

Analog Input Enable 1/ ADC Select

Input Level Select Register

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

Port 3 Direction Register

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

Port 7 Direction Register

Port 8 Direction Register

Port 9 Direction Register

Port A Direction Register

Port B Direction Register

ILSR

Ports

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

DDRA

DDRB

Reserved

UMC0

USR0

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

11H

12^H

13H

14H

15^H

16H

17H

18H

19^H

1AH

1BH

1C^Hto 1FH

20H

Serial Mode Control 0

Status 0

R/W

00000100

00010000

21H

UART0

UIDR0/

UODR0

22^H

23H

Input/Output Data 0

Rate and Data 0

R/W

XXXXXXXX

URD0

0000000X

(Continued)

21

MB90390 Series

Abbrevia-

tion

Address

Register

Serial Mode Control 1

Access

Resource name

Initial value

24^H

25H

UMC1

USR1

R/W

00000100

00010000

Status 1

UART1

UIDR1/

UODR1

26^H

Input/Output Data 1

R/W

XXXXXXXX

27^H

28H

29^H

Rate and Data 1

Serial Mode Control 2

Status 2

URD1

UMC2

USR2

R/W

0000000X

00000100

00010000

UART2

UIDR2/

UODR2

2A^H

Input/Output Data 2

R/W

XXXXXXXX

2BH

2CH

2DH

2E^H

2FH

30H

31^H

32H

33^H

34H

35^H

36^H

37H

38H

39^H

3A^H

Rate and Data 2

URD2

SMCS4

SDR4

R/W

R

0000000X

XXXX0000

00000010

XXXXXXXX

0 X 0 X 0000

00000000

XXXXXXXX

00000000

XXXXXXXX

000010XX

0X000XX1

0X000001

000000XX

Serial Mode Control 4

Serial I/O

Serial Data 4

Serial I/O Prescaler/Edge Selector 4

External Interrupt Enable

External Interrupt Request

External Interrupt Level

A/D Control Status 0

CDCR4

ENIR

EIRR

External Interrupt

A/D Converter

ELVR

ADCS0

ADCS1

ADCR0

ADCR1

PPGC0

PPGC1

PPG01

A/D Control Status 1

A/D Data 0

A/D Data 1

R/W

PPG0 Operation Mode Control Register

PPG1 Operation Mode Control Register

PPG0 and PPG1 Clock Select Register

16-bit Programable

Pulse

Generator 0/1

Address Maching

Detection Function 1

3B^H

Address Detection Control Register 1

PACSR1

R/W

00000000

3C^H

3DH

3EH

3FH

40^H

41^H

42H

43^H

PPG2 Operation Mode Control Register

PPG3 Operation Mode Control Register

PPG2 and PPG3 Clock Select Register

Clock Output Enable Register

PPGC2

PPGC3

PPG23

CKOE

R/W

0X000XX1

0X000001

000000XX

XXXXXX00

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

Generator 2/3

Clock Output

PPG4 Operation Mode Control Register

PPG5 Operation Mode Control Register

PPG4 and PPG5 Clock Select Register

PPGC4

PPGC5

PPG45

Reserved

16-bit Programable

Pulse

Generator 4/5

(Continued)

22

MB90390 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

44^H

45^H

46^H

47^H

48H

49H

4A^H

4BH

4C^H

4D^H

4E^H

4FH

50H

51^H

52H

53H

54^H

55H

56^H

57H

58H

59^H

5AH

5BH

5CH

5D^H

5EH

5FH

60^H

61H

PPG6 Operation Mode Control Register

PPG7 Operation Mode Control Register

PPG6 and PPG7 Clock Select Register

PPGC6

PPGC7

PPG67

R/W

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

Generator 6/7

Reserved

PPGC8

PPGC9

PPG89

PPG8 Operation Mode Control Register

PPG9 Operation Mode Control Register

PPG8 and PPG9 Clock Select Register

R/W

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

Generator 8/9

Reserved

PPGA Operation Mode Control Register PPGCA

PPGB Operation Mode Control Register PPGCB

R/W

0X000XX1

0X000001

000000XX

16-bit Programable

Pulse

Generator A/B

PPGA and PPGB Clock Select Register

PPGAB

Reserved

TMCSR0

TMCSR1

ICS01

Timer Control Status 0

R/W

00000000

XXXX0000

00000000

XXXX0000

00000000

16-bit Reload Timer

0

Timer Control Status 0

Timer Control Status 1

16-bit Reload Timer

1

Timer Control Status 1

Input Capture Control Status 0/1

Input Capture Control Status 2/3

Input Capture Control Status 4/5

Input Capture 0/1

Input Capture 2/3

Input Capture 4/5

ICS23

ICS45

Reserved

OCS0

Output Compare Control Status 0

Output Compare Control Status 1

Output Compare Control Status 2

Output Compare Control Status 3

Output Compare Control Status 4

Output Compare Control Status 5

Sound Control

R/W

0000XX00

0XX00000

0000XX00

0XX00000

0000XX00

0XX00000

00000000

0XXXXXX0

000XX000

00000000

Output Compare 0/1

Output Compare 2/3

Output Compare 4/5

Sound Generator

Watch Timer

OCS1

OCS2

OCS3

OCS4

OCS5

SGCR

Sound Control

SGCR

Watch Timer Control

WTCR

Watch Timer Control

Stepping Motor

Controller 0

62^H

63^H

64H

65^H

PWM Control 0

PWM Control 1

PWC0

R/W

00000XX0

Reserved

PWC1

Stepping Motor

Controller 1

R/W

00000XX0

Reserved

(Continued)

23

MB90390 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

Stepping Motor

Controller 2

66^H

67H

68^H

69^H

6AH

6B^H

6C^H

PWM Control 2

PWM Control 3

PWM Control 4

PWM Control 5

PWC2

R/W

00000XX0

Reserved

PWC3

Stepping Motor

Controller 3

R/W

00000XX0

Reserved

PWC4

Stepping Motor

Controller 4

Reserved

PWC5

Stepping Motor

Controller 5

6D^H

6EH

6FH

Reserved

ROMM

ROM Mirror

W

ROM Mirror

XXXXXXX1

70^Hto 8FH Reserved for CAN Interface 0/1. Refer to “■ CAN CONTROLLERS”

90H to 9DH

Reserved

Address Maching

Detection Function 0

9E^H

Address Detection Control Register 0

Delayed Interrupt/Release

Low-power Mode

PACSR0

R/W

00000000

XXXXXXX0

00011000

9F^H

DIRR

Delayed Interrupt

Low Power

Controller

A0H

LPMCR

Low Power

Controller

A1^H

Clock Selector

CKSCR

R/W

11111100

A2^Hto A7H

A8H

Reserved

WDTC

Watchdog Control

R/W

Watchdog Timer

Time Base Timer

XXXXX111

1XX00100

A9^H

Time Base Timer Control

TBTC

AA^Hto ADH

Reserved

Flash Control Status

(MB90F394H only. Otherwise reserved)

AE^H

FMCS

R/W

Flash Memory

000X0XX0

AF^H

B0^H

B1H

B2H

B3H

B4H

B5H

B6^H

Reserved

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

R/W

00000111

Interrupt Controller

00000111

(Continued)

24

MB90390 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

B7^H

B8H

B9^H

BA^H

BBH

BC^H

BD^H

BEH

BF^H

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

R/W

00000111

Interrupt Controller

C0H to

FFH

Reserved

3500^H

3501^H

3502H

3503^H

3504H

3505^H

3506^H

3507H

3508^H

3509^H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

PRLL4

PRLH4

PRLL5

PRLH5

PRLL6

PRLH6

PRLL7

PRLH7

PRLL8

PRLH8

PRLL9

PRLH9

PRLLA

PRLHA

PRLLB

PRLHB

R/W

XXXXXXXX

(Continued)

16-bit Programable

Pulse

Generator 0/1

16-bit Programable

Pulse

Generator 2/3

16-bit Programable

Pulse

350AH Reload L

350B^HReload H

350CH Reload L

350DH Reload H

350EH Reload L

350F^HReload H

Generator 4/5

16-bit Programable

Pulse

Generator 6/7

3510H

3511H

3512^H

3513H

3514H

3515^H

3516H

3517H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

Reload L

Reload H

16-bit Programable

Pulse

Generator 8/9

16-bit Programable

Pulse

Generator A/B

25

MB90390 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

3518^H

3519H

Serial Mode Register

Serial Control Register

SMR3

SCR3

R/W

00000000

RDR3/

TDR3

351A^HReception/Transmission Data Register

R/W

00000000

351B^HSerial Status Register

SSR3

ECCR3

ESCR3

BGR03

BGR13

IPCP0

IPCP1

IPCP2

IPCP3

IPCP4

IPCP5

TCDT0

TCCS0

OCCP0

OCCP1

OCCP2

OCCP3

R/W

R

00001000

000000XX

00000X00

UART3

351CH Extended Communication Control Reg.

351D^HExtended Status/Control Register

351E^HBaud Rate Register 0

00000000

351FH Baud Rate Register 1

00000000

3520^H

3521H

3522^H

3523H

3524H

3525^H

3526H

3527H

3528^H

3529^H

Input Capture 0

Input Capture 1

Input Capture 2

Input Capture 3

Input Capture 4

XXXXXXXX

00000000

R

Input Capture 0/1

Input Capture 2/3

Input Capture 4/5

I/O Timer 0

R

352A^HInput Capture 5

352BH Input Capture 5

352CH Timer Data 0

352D^HTimer Data 0

352EH Timer Control 0

352FH Timer Control 0

R

R/W

00000000

0XXXXXXX

XXXXXXXX

3530H

3531^H

3532H

3533H

3534^H

3535H

3536H

3537^H

Output Compare 0

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 0/1

Output Compare 2/3

XXXXXXXX

(Continued)

26

MB90390 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

3538^H

3539H

Output Compare 4

OCCP4

OCCP5

TCDT1

TCCS1

R/W

XXXXXXXX

00000000

Output Compare 4/5

353A^HOutput Compare 5

353B^HOutput Compare 5

353CH Timer Data 1

353D^HTimer Data 1

00000000

I/O Timer 1

353E^HTimer Control 1

353FH Timer Control 1

00000000

0XXXXXXX

TMR0/

TMRLR0

3540^H

3541^H

3542^H

3543^H

Timer 0/Reload 0

Timer 1/Reload 1

R/W

XXXXXXXX

16-bit Reload

Timer 0

TMR0/

TMRLR0

TMR1/

TMRLR1

16-bit Reload

Timer 1

TMR1/

TMRLR1

3544^Hto

3545H

Reserved

3546^H

3547^H

3548^H

3549H

Frequency Dtata

Amplitude Data

Decrement Grade

Tone Count

SGFR

SGAR

R/W

XXXXXXXX

XX000000

XXX00000

XXXXXXXX

00000000

Sound Generator

SGDR

SGTR

354AH Sub-second Data

354B^HSub-second Data

354CH Sub-second Data

354DH Second Data

354EH Minute Data

WTBR

WTSR

WTMR

WTHR

PWC10

PWC20

PWS10

PWS20

PWC11

PWC21

PWS11

PWS21

Watch Timer

354F^HHour Data

3550H

3551^H

3552^H

3553H

3554H

3555^H

3556H

3557H

PWM1 Compare 0

PWM2 Compare 0

PWM1 Select 0

PWM2 Select 0

PWM1 Compare 1

PWM2 Compare 1

PWM1 Select 1

PWM2 Select 1

Stepping Motor

Controller 0

X0000000

XXXXXXXX

00000000

Stepping Motor

Controller 1

X0000000

(Continued)

27

MB90390 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

3558^H

3559^H

PWM1 Compare 2

PWM2 Compare 2

PWC12

PWC22

PWS12

PWS22

PWC13

PWC23

PWS13

PWS23

PWC14

PWC24

PWS14

PWS24

PWC15

PWC25

PWS15

PWS25

OCS6

R/W

XXXXXXXX

00000000

Stepping Motor

Controller 2

355A^HPWM1 Select 2

355B^HPWM2 Select 2

355C^HPWM1 Compare 3

355D^HPWM2 Compare 3

355E^HPWM1 Select 3

355F^HPWM2 Select 3

X0000000

XXXXXXXX

00000000

Stepping Motor

Controller 3

X0000000

XXXXXXXX

00000000

3560^H

3561^H

3562^H

3563^H

3564^H

3565^H

3566^H

3567^H

3568^H

3569^H

PWM1 Compare 4

PWM2 Compare 4

PWM1 Select 4

Stepping Motor

Controller 4

PWM2 Select 4

X0000000

XXXXXXXX

00000000

PWM1 Compare 5

PWM2 Compare 5

PWM1 Select 5

Stepping Motor

Controller 5

PWM2 Select 5

X0000000

0000XX00

XXX00000

XXXXXXXX

XXXXXXX0

XXXX0000

Output Compare Control Status 6

Output Compare Control Status 7

OCS7

356A^HOutput Compare 6

356B^HOutput Compare 6

356C^HOutput Compare 7

356D^HOutput Compare 7

356E^HCAN Direct Mode Register

356F^HCAN RX/TX redirect register

3570^Hto

OCCP6

OCCP7

CDMR

Output Compare 6/7

CAN Clock Sync

CAN 0/1/2/3

CANSWR

Reserved for CAN Interface 2/3/4. Refer to “■ CAN CONTROLLERS”

359FH

35A0^HI²C Bus Status Register

35A1^HI²C Bus Control Register

35A2^H

IBSR

IBCR

R

00000000

XXXXXX00

11111111

00XXXX11

X0000000

01111111

00000000

R/W

ITBAL

ITBAH

ITMKL

ITMKH

ISBA

I²C Ten Bit Slave Address Register

35A3^H

35A4^H

35A5^H

I²C Interface

I²C Ten Bit Address Mask Register

35A6^HI²C Seven Bit Slave Address Register

35A7^HI²C Seven Bit Address Mask Register

35A8^HI²C Data Register

ISMK

IDAR

35A9^Hto

35AAH

Reserved

(Continued)

28

MB90390 Series

Abbrevia-

tion

Address

Register

Access

Resource name

Initial value

35AB^HI²C Clock Control Register

ICCR

R/W

I²C Interface

X0011111

35ACH to

35BFH

Reserved

35C0^HParameter Register Low Byte

35C1^HParameter Register High Byte

35C2H Clock Modulator Control Register

CMPRL

CMPRH

CMCR

R/W

11111101

XX000010

00010000

Clock Modulator

35C3^Hto

35C8H

Reserved

35C9^HInput Capture Edge 0/1

35CAH Input Capture Edge 2/3

35CBH Input Capture Edge 4/5

ICE01

ICE23

ICE45

R/W

R

Input Capture 0/1

Input Capture 2/3

Input Capture 4/5

XXXXX0XX

XXXXXXXX

XXXXX0XX

R/W

35CCH to

35DFH

Reserved

PADR0

PADR1

Reserved

PADR3

PADR4

Detection Address Setting Register 0

(Low-order)

35E0^H

R/W

XXXXXXXX

Detection Address Setting Register 0

(Middle-order)

35E1^H

Detection Address Setting Register 0

(High-order)

35E2^H

Address Maching

Detection Function 0

Detection Address Setting Register 1

(Low-order)

35E3^H

Detection Address Setting Register 1

(Middle-order)

35E4^H

Detection Address Setting Register 1

(High-order)

35E5^H

35E6^Hto

35EFH

Detection Address Setting Register 3

(Low-order)

35F0H

R/W

XXXXXXXX

Detection Address Setting Register 3

(Middle-order)

35F1^H

Detection Address Setting Register 3

(High-order)

35F2H

Address Maching

Detection Function 1

Detection Address Setting Register 4

(Low-order)

35F3^H

Detection Address Setting Register 4

(Middle-order)

35F4^H

Detection Address Setting Register 4

(High-order)

35F5^H

XXXXXXXX

(Continued)

29

MB90390 Series

(Continued)

Abbrevia-

tion

Address

35F6^H

Register

Access

R/W

Resource name

Initial value

XXXXXXXX

Detection Address Setting Register 5

(Low-order)

PADR5

Reserved

Detection Address Setting Register 5

(Middle-order)

Address Maching

Detection Function 1

35F7H

R/W

Detection Address Setting Register 5

(High-order)

35F8^H

R/W

35F9^Hto

35FFH

3600H to

36FFH

Reserved for CAN Interface 0. Refer to “■ CAN CONTROLLERS”

Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

Reserved for CAN Interface 2. Refer to “■ CAN CONTROLLERS”

Reserved for CAN Interface 3. Refer to “■ CAN CONTROLLERS”

Reserved for CAN Interface 4. Refer to “■ CAN CONTROLLERS”

3700^Hto

37FFH

3800^Hto

38FFH

3900^Hto

39FFH

3A00H to

3AFFH

3B00^Hto

3BFF^H

3C00^Hto

3CFFH

3D00H to

3DFFH

3E00^Hto

3EFFH

3F00^Hto

3FFFH

• Explanation on read/write

R/W : Readable and Writeble

R

: Read only

W : Write only

• Explanation on initial values

0 : Initial value is “0”.

1 : Initial value is “1”.

X : Initial value is undefined.

Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved

address results in reading “X”.

30

MB90390 Series

■ CAN CONTROLLERS

The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B

- Supports transmission/reception in standard frame and extended frame formats

• Supports transmitting of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

- 29-bit ID and 8-byte data

- Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message

buffer as ID acceptance mask

- Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)

List of Control Registers (1)

Address

Abbrevia-

Register

Access Initial Value

tion

CAN0

CAN1

CAN2

CAN3

CAN4

000070^H000080H 003570H 003580H 003590H

000071^H000081H 003571H 003581H 003591H

000072H 000082H 003572H 003582H 003592H

000073^H000083H 003573H 003583H 003593H

000074H 000084H 003574H 003584H 003594H

000075^H000085H 003575H 003585H 003595H

000076H 000086H 003576H 003586H 003596H

000077^H000087H 003577H 003587H 003597H

000078H 000088H 003578H 003588H 003598H

000079^H000089H 003579H 003589H 003599H

00007AH 00008AH 00357AH 00358AH 00359AH

00007B^H00008BH 00357BH 00358BH 00359BH

00007CH 00008CH 00357CH 00358CH 00359CH

00007D^H00008DH 00357DH 00358DH 00359DH

00007EH 00008EH 00357EH 00358EH 00359EH

00007F^H00008FH 00357FH 00358FH 00359FH

Message buffer

valid register

00000000

R/W

BVALR

00000000

Transmit request

register

00000000

R/W

TREQR

TCANR

TCR

00000000

Transmit cancel

register

00000000

W

Transmit

complete register

00000000

R/W

00000000

Receivecomplete

register

00000000

R/W

RCR

00000000

Remote request

receiving register

00000000

R/W

RRTRR

ROVRR

RIER

00000000

Receive overrun

register

00000000

R/W

00000000

Receive interrupt

enable register

00000000

R/W

00000000

31

MB90390 Series

List of Control Registers (2)

Address

Abbrevia-

tion

Register

CAN4

Access Initial Value

CAN0

CAN1

CAN2

CAN3

003700^H003900H 003B00H 003D00H 003F00H

003701^H003901H 003B01H 003D01H 003F01H

003702H 003902H 003B02H 003D02H 003F02H

003703^H003903H 003B03H 003D03H 003F03H

003704H 003904H 003B04H 003D04H 003F04H

003705^H003905H 003B05H 003D05H 003F05H

003706H 003906H 003B06H 003D06H 003F06H

003707^H003907H 003B07H 003D07H 003F07H

003708H 003908H 003B08H 003D08H 003F08H

003709^H003909H 003B09H 003D09H 003F09H

00370AH 00390AH 003B0AH 003D0AH 003F0AH

00370B^H00390BH 003B0BH 003D0BH 003F0BH

00370CH 00390CH 003B0CH 003D0CH 003F0CH

Control status

register

00XXX000

R/W, R

CSR

LEIR

0XXXX0X1

Last event

indicator register

XXXXXXXX

R/W

000X0000

Receive/transmit

error counter

00000000

RTEC

BTR

R

Bit timing

register

X1111111

R/W

11111111

XXXXXXXX

R/W

IDE register

IDER

TRTRR

XXXXXXXX

Transmit RTR

register

00000000

R/W

00000000

Remote frame

receive waiting

register

XXXXXXXX

R/W

RFWTR

TIER

XXXXXXXX

00370D^H00390DH 003B0DH 003D0DH 003F0DH

00370EH 00390EH 003B0EH 003D0EH 003F0EH

00370F^H00390FH 003B0FH 003D0FH 003F0FH

Transmit

interrupt enable

register

00000000

R/W

00000000

003710H 003910H 003B10H 003D10H 003F10H

003711^H003911H 003B11H 003D11H 003F11H

003712H 003912H 003B12H 003D12H 003F12H

003713^H003913H 003B13H 003D13H 003F13H

003714H 003914H 003B14H 003D14H 003F14H

003715^H003915H 003B15H 003D15H 003F15H

003716H 003916H 003B16H 003D16H 003F16H

003717^H003917H 003B17H 003D17H 003F17H

003718H 003918H 003B18H 003D18H 003F18H

003719^H003919H 003B19H 003D19H 003F19H

00371AH 00391AH 003B1AH 003D1AH 003F1AH

00371B^H00391BH 003B1BH 003D1BH 003F1BH

XXXXXXXX

R/W

Acceptancemask

select

AMSR

AMR0

AMR1

XXXXXXXX

register

XXXXXXXX

R/W

Acceptancemask

register 0

XXXXXXXX

R/W

Acceptancemask

register 1

XXXXXXXX

32

MB90390 Series

List of Message Buffers (ID Registers) (1)

Register

Address

CAN2

Abbrevia-

Access Initial Value

tion

CAN0

CAN1

CAN3

CAN4

003600^H003800H 003A00H 003C00H 003E00H

to to to to to

XXXXXXXX

General-

purpose RAM

R/W

to

00361FH 00381FH 003A1FH 003C1FH 003E1FH

003620^H003820H 003A20H 003C20H 003E20H

003621^H003821H 003A21H 003C21H 003E21H

003622H 003822H 003A22H 003C22H 003E22H

003623^H003823H 003A23H 003C23H 003E23H

003624H 003824H 003A24H 003C24H 003E24H

003625^H003825H 003A25H 003C25H 003E25H

003626H 003826H 003A26H 003C26H 003E26H

003627^H003827H 003A27H 003C27H 003E27H

003628H 003828H 003A28H 003C28H 003E28H

003629^H003829H 003A29H 003C29H 003E29H

00362AH 00382AH 003A2AH 003C2AH 003E2AH

00362B^H00382BH 003A2BH 003C2BH 003E2BH

00362CH 00382CH 003A2CH 003C2CH 003E2CH

00362D^H00382DH 003A2DH 003C2DH 003E2DH

00362EH 00382EH 003A2EH 003C2EH 003E2EH

00362F^H00382FH 003A2FH 003C2FH 003E2FH

003630H 003830H 003A30H 003C30H 003E30H

003631^H003831H 003A31H 003C31H 003E31H

003632H 003832H 003A32H 003C32H 003E32H

003633^H003833H 003A33H 003C33H 003E33H

003634H 003834H 003A34H 003C34H 003E34H

003635^H003835H 003A35H 003C35H 003E35H

003636H 003836H 003A36H 003C36H 003E36H

003637^H003837H 003A37H 003C37H 003E37H

003638H 003838H 003A38H 003C38H 003E38H

003639^H003839H 003A39H 003C39H 003E39H

00363AH 00383AH 003A3AH 003C3AH 003E3AH

00363B^H00383BH 003A3BH 003C3BH 003E3BH

00363CH 00383CH 003A3CH 003C3CH 003E3CH

00363D^H00383DH 003A3DH 003C3DH 003E3DH

00363EH 00383EH 003A3EH 003C3EH 003E3EH

00363F^H00383FH 003A3FH 003C3FH 003E3FH

XXXXXXXX

ID register 0

ID register 1

ID register 2

ID register 3

ID register 4

ID register 5

ID register 6

ID register 7

IDR0

IDR1

IDR2

IDR3

IDR4

IDR5

IDR6

IDR7

XXXXXXXX

R/W

XXXXXXXX

33

MB90390 Series

List of Message Buffers (ID Registers) (2)

Address

CAN0 CAN1

Address

CAN3

Abbrevia-

tion

Register

Access Initial Value

CAN2

CAN4

003640^H003840H 003A40H 003C40H 003E40H

003641^H003841H 003A41H 003C41H 003E41H

003642H 003842H 003A42H 003C42H 003E42H

003643^H003843H 003A43H 003C43H 003E43H

003644H 003844H 003A44H 003C44H 003E44H

003645^H003845H 003A45H 003C45H 003E45H

003646H 003846H 003A46H 003C46H 003E46H

003647^H003847H 003A47H 003C47H 003E47H

003648H 003848H 003A48H 003C48H 003E48H

003649^H003849H 003A49H 003C49H 003E49H

00364AH 00384AH 003A4AH 003C4AH 003E4AH

00364B^H00384BH 003A4BH 003C4BH 003E4BH

00364CH 00384CH 003A4CH 003C4CH 003E4CH

00364D^H00384DH 003A4DH 003C4DH 003E4DH

00364EH 00384EH 003A4EH 003C4EH 003E4EH

00364F^H00384FH 003A4FH 003C4FH 003E4FH

003650H 003850H 003A50H 003C50H 003E50H

003651^H003851H 003A51H 003C51H 003E51H

003652H 003852H 003A52H 003C52H 003E52H

003653^H003853H 003A53H 003C53H 003E53H

003654H 003854H 003A54H 003C54H 003E54H

003655^H003855H 003A55H 003C55H 003E55H

003656H 003856H 003A56H 003C56H 003E56H

003657^H003857H 003A57H 003C57H 003E57H

003658H 003858H 003A58H 003C58H 003E58H

003659^H003859H 003A59H 003C59H 003E59H

00365AH 00385AH 003A5AH 003C5AH 003E5AH

00365B^H00385BH 003A5BH 003C5BH 003E5BH

00365CH 00385CH 003A5CH 003C5CH 003E5CH

00365D^H00385DH 003A5DH 003C5DH 003E5DH

00365EH 00385EH 003A5EH 003C5EH 003E5EH

00365F^H00385FH 003A5FH 003C5FH 003E5FH

XXXXXXXX

R/W

ID register 8

IDR8

IDR9

XXXXXXXX

R/W

ID register 9

ID register 10

ID register 11

ID register 12

ID register 13

ID register 14

ID register 15

XXXXXXXX

R/W

IDR10

IDR11

IDR12

IDR13

IDR14

IDR7

XXXXXXXX

R/W

XXXXXXXX

R/W

XXXXXXXX

R/W

XXXXXXXX

R/W

XXXXXXXX

R/W

XXXXXXXX

34

MB90390 Series

List of Message Buffers (DLC Registers and Data Registers) (1)

Address

CAN0 CAN1

Address

CAN3

Abbrevia-

tion

Register

Access Initial Value

CAN2

CAN4

003660^H003860H 003A60H 003C60H 003E60H

003661^H003861H 003A61H 003C61H 003E61H

003662H 003862H 003A62H 003C62H 003E62H

003663^H003863H 003A63H 003C63H 003E63H

003664H 003864H 003A64H 003C64H 003E64H

003665^H003865H 003A65H 003C65H 003E65H

003666H 003866H 003A66H 003C66H 003E66H

003667^H003867H 003A67H 003C67H 003E67H

003668H 003868H 003A68H 003C68H 003E68H

003669^H003869H 003A69H 003C69H 003E69H

00366AH 00386AH 003A6AH 003C6AH 003E6AH

00366B^H00386BH 003A6BH 003C6BH 003E6BH

00366CH 00386CH 003A6CH 003C6CH 003E6CH

00366D^H00386DH 003A6DH 003C6DH 003E6DH

00366EH 00386EH 003A6EH 003C6EH 003E6EH

00366F^H00386FH 003A6FH 003C6FH 003E6FH

003670H 003870H 003A70H 003C70H 003E70H

003671^H003871H 003A71H 003C71H 003E71H

003672H 003872H 003A72H 003C72H 003E72H

003673^H003873H 003A73H 003C73H 003E73H

003674H 003874H 003A74H 003C74H 003E74H

003675^H003875H 003A75H 003C75H 003E75H

003676H 003876H 003A76H 003C76H 003E76H

003677^H003877H 003A77H 003C77H 003E77H

003678H 003878H 003A78H 003C78H 003E78H

003679^H003879H 003A79H 003C79H 003E79H

00367AH 00387AH 003A7AH 003C7AH 003E7AH

00367B^H00387BH 003A7BH 003C7BH 003E7BH

00367CH 00387CH 003A7CH 003C7CH 003E7CH

00367D^H00387DH 003A7DH 003C7DH 003E7DH

00367EH 00387EH 003A7EH 003C7EH 003E7EH

00367F^H00387FH 003A7FH 003C7FH 003E7FH

DLC register 0

DLC register 1

DLC register 2

DLC register 3

DLC register 4

DLC register 5

DLC register 6

DLC register 7

DLC register 8

DLC register 9

DLC register 10

DLC register 11

DLC register 12

DLC register 13

DLC register 14

DLC register 15

DLCR0

DLCR1

DLCR2

DLCR3

DLCR4

DLCR5

DLCR6

DLCR7

DLCR8

DLCR9

DLCR10

DLCR11

DLCR12

DLCR13

DLCR14

DLCR15

R/W

XXXXXXXX

35

MB90390 Series

List of Message Buffers (DLC Registers and Data Registers) (2)

Address

CAN0 CAN1

Address

CAN3

Abbrevia-

tion

Register

Access Initial Value

CAN2

CAN4

003680^H003880H 003A80H 003C80H 003E80H

to to to to to

003687H 003887H 003A87H 003C87H 003E87H

XXXXXXXX

Data register 0

(8 bytes)

DTR0

DTR1

DTR2

DTR3

DTR4

DTR5

DTR6

DTR7

DTR8

DTR9

DTR10

DTR11

DTR12

DTR13

R/W

to

XXXXXXXX

003688^H003888H 003A88H 003C88H 003E88H

XXXXXXXX

to

XXXXXXXX

Data register 1

(8 bytes)

to

00368FH 00388FH 003A8FH 003C8FH 003E8FH

003690^H003890H 003A90H 003C90H 003E90H

XXXXXXXX

to

XXXXXXXX

Data register 2

(8 bytes)

to

003697H 003897H 003A97H 003C97H 003E97H

003698H 003898H 003A98H 003C98H 003E98H

XXXXXXXX

to

XXXXXXXX

Data register 3

(8 bytes)

to

00369FH 00389FH 003A9FH 003C9FH 003E9FH

0036A0^H0038A0H 003AA0H 003CA0H 003EA0H

XXXXXXXX

to

XXXXXXXX

Data register 4

(8 bytes)

to

0036A7H 0038A7H 003AA7H 003CA7H 003EA7H

0036A8H 0038A8H 003AA8H 003CA8H 003EA8H

XXXXXXXX

to

XXXXXXXX

Data register 5

(8 bytes)

to

0036AFH 0038AFH 003AAFH 003CAFH 003EAFH

0036B0^H0038B0H 003AB0H 003CB0H 003EB0H

XXXXXXXX

to

XXXXXXXX

Data register 6

(8 bytes)

to

0036B7H 0038B7H 003AB7H 003CB7H 003EB7H

0036B8H 0038B8H 003AB8H 003CB8H 003EB8H

XXXXXXXX

to

XXXXXXXX

Data register 7

(8 bytes)

to

0036BFH 0038BFH 003ABFH 003CBFH 003EBFH

0036C0^H0038C0H 003AC0H 003CC0H 003EC0H

XXXXXXXX

to

XXXXXXXX

Data register 8

(8 bytes)

to

0036C7H 0038C7H 003AC7H 003CC7H 003EC7H

0036C8H 0038C8H 003AC8H 003CC8H 003EC8H

XXXXXXXX

to

XXXXXXXX

Data register 9

(8 bytes)

to

0036CFH 0038CFH 003ACFH 003CCFH 003ECFH

0036D0^H0038D0H 003AD0H 003CD0H 003ED0H

XXXXXXXX

to

XXXXXXXX

Data register 10

(8 bytes)

to

0036D7H 0038D7H 003AD7H 003CD7H 003ED7H

0036D8^H0038D8H 003AD8H 003CD8H 003ED8H

XXXXXXXX

to

XXXXXXXX

Data register 11

(8 bytes)

to

0036DFH 0038DFH 003ADFH 003CDFH 003EDFH

0036E0H 0038E0H 003AE0H 003CE0H 003EE0H

XXXXXXXX

to

XXXXXXXX

Data register 12

(8 bytes)

to

0036E7^H0038E7^H003AE7^H003CE7^H003EE7^H

0036E8^H0038E8H 003AE8H 003CE8H 003EE8H

XXXXXXXX

to

XXXXXXXX

Data register 13

(8 bytes)

to

0036EFH 0038EFH 003AEFH 003CEFH 003EEFH

36

MB90390 Series

List of Message Buffers (DLC Registers and Data Registers) (3)

Address

CAN0 CAN1

Address

CAN3

Abbrevia-

tion

Register

Access Initial Value

CAN2

CAN4

0036F0^H0038F0H 003AF0H 003CF0H 003EF0H

XXXXXXXX

Data register 14

(8 bytes)

to

DTR14

DTR15

R/W

to

0036F7H 0038F7H 003AF7H 003CF7H 003EF7H

XXXXXXXX

0036F8^H0038F8H 003AF8H 003CF8H 003EF8H

XXXXXXXX

to

XXXXXXXX

Data register 15

(8 bytes)

to

0036FFH 0038FFH 003AFFH 003CFFH 003EFFH

37

MB90390 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control

Interrupt vector

Number Address

EI²OS

clear

register

Interrupt cause

Number

Address

Reset

N/A

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

FFFFDC^H

FFFFD8^H

FFFFD4^H

FFFFD0H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64H

INT9 instruction

Exception

Time Base Timer

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

External Interrupt INT0 to INT7

CAN 0 RX

N/A

CAN 0 TX/NS

CAN 1 RX

CAN 1 TX/NS

PPG 0/1 / (CAN 2 RX)

PPG 2/3 / (CAN 2 TX/NS)

PPG 4/5 / (CAN 3 RX)

PPG 6/7 / (CAN 3 TX/NS)

PPG 8/9 / (CAN 4 RX)

PPG A/B / (CAN 4 TX/NS)

16-bit Reload Timer 0

16-bit Reload Timer 1

Input Capture 0/1

Output compare 0/1

Input Capture 2/3 / Output Compare 6

Output Compare 2/3

Input Capture 4/5 / Output Compare 7

Output Compare 4/5 / (I²C)

A/D Converter

I/O Timer 0 / I/O Timer 1 / Watch Timer

Serial I/O

N/A

Sound Generator

UART 0 RX

UART 0 TX

UART 1 RX

0000BDH

UART 1 TX

(Continued)

38

MB90390 Series

(Continued)

Interrupt control

Interrupt vector

EI²OS

clear

register

Interrupt cause

Number

#39

Address

FFFF60^H

FFFF5CH

FFFF58H

FFFF54H

Number

Address

(UART 2 RX) / UART 3 RX

(UART 2 TX) / UART 3 TX

Flash Memory

ICR14

ICR15

0000BEH

#40

N/A

#41

0000BFH

Delayed interrupt

#42

: The interrupt request flag is cleared by the EI²OS interrupt clear signal.

: The interrupt request flag is cleared by the EI²OS interrupt clear signal. A stop request is available.

N/A : The interrupt request flag is not cleared by the EI²OS interrupt clear signal.

Notes : For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags

are cleared by the EI²OS interrupt clear signal.

At the end of EI²OS, the EI²OS clear signal will be asserted for all the interrupt flags assigned to the same

interrupt number. If one interrupt flag starts the EI²OS and in the meantime another interrupt flag is set by

hardware event, the later event is lost because the flag is cleared by the EI²OS clear signal caused by the

first event. So it is recommended not to use the EI²OS for this interrupt number.

If EI²OS is enabled, EI²OS is initiated when one of the two interrupt signals in the same interrupt control

register (ICR) is asserted. This means that different interrupt sources share the same EI²OS Descriptor

which should be unique for each interrupt source. For this reason, when one interrupt source uses the

EI²OS, the other interrupt should be disabled.

39

MB90390 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(VSS = AVSS = 0 V)

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V^CC

VSS − 0.3 VSS + 6.0

V

AVCC

VCC = AVCC*¹

Power supply voltage

AVRH,

AVRL

AVCC ≥ AVRH, AVCC ≥ AVRL,

AVRH ≥ AVRL

VSS − 0.3 VSS + 6.0

V

DV^CC

VI

VSS − 0.3 VSS + 6.0

V

VCC ≥ DVCC

Input voltage

*2

Output voltage

VO

Maximum Clamp Current

Total Maximum Clamp Current

“L” level maximum output current

“L” level average output current

“L” level maximum output current

I^CLAMP

Σ|I^CLAMP|

I^OL1

−2.0

+2.0

20

15

4

mA *5

mA Normal outputs*³

mA Normal outputs, average value

mA High current outputs*⁴

IOLAV1

I^OL2

40

High current outputs, average

value

“L” level average output current

IOLAV2

30

mA

“L” level maximum overall output current

ΣIOL1

100

330

mA Sum of all normal outputs

ΣI^OL2

mA Sum of all high current outputs

Sum of all normal outputs,

average value

“L” level average overall output current

ΣI^OLAV1

ΣI^OLAV2

50

mA

Sum of all high current outputs,

average value

250

mA

“H” level maximum output current

“H” level average output current

“H” level maximum output current

IOH1

IOHAV1

I^OH2

−15

−4

mA Normal outputs*³

mA Normal outputs, average value

mA High current outputs*⁴

−40

High current outputs, average

value

“H” level average output current

IOHAV2

−30

mA

“H” level maximum overall output current

ΣIOH1

−100

−330

mA Sum of all normal outputs

ΣI^OH2

mA Sum of all high current outputs

Sum of all normal outputs,

average value

“H” level average overall output current

ΣIOHAV

−50

mA

Sum of all high current outputs,

average value

−250

mA

Power consumption

Operating temperature

Storage temperature

P^D

TA

800

+85

mW MB90F394H

−40

−55

°C

T^STG

+150

°C

(Continued)

40

MB90390 Series

(Continued)

*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not exceed AVCC when the power is switched on.

*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun

current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI

rating.

*3: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,

P90 to P97, PB0 to PB7

*4: Applicable to pins: P70 to P77, P80 to P87, PA0 to PA7

*5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67

P70 to P77, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB6, PB7

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting

supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input

pins, etc.) cannot accept +B signal input.

• Sample recommended circuits:

• Input/output equivalent circuits

Protective diode

VCC

Limiting

resistance

P-ch

+B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

41

MB90390 Series

2. Recommended Conditions

(VSS = AVSS = 0 V)

Value

Typ

Parameter

Symbol

Unit

Remarks

Min

3.5

3.0

4.5

0.1

−40

Max

5.5

1.0

+85

5.0

V

Under normal operation

Retain RAM data in stop mode

*1

V^CC

Power supply voltage

AV^CC

C^S

Smoothing capacitor

µF *2

°C

Operating temperature

TA

*1 : AV^CCis a voltage at which accuracy is guaranteed. AVCC should not exceed VCC.

*2 : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the V^CCpin, use a bypass

capacitor that has a larger capacity than that of CS.

Refer to the following figure for connection of smoothing capacitor CS.

• C Pin Connection Diagram

C

CS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

42

MB90390 Series

3. DC Characteristics

(TA = −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

Value

Sym-

Parameter

bol

Condition

Unit

Remarks

Min

Typ

Max

Port inputs if CMOS

Hysteresis input

V^IHS

0.8 VCC

VCC + 0.3

V

levels are selected

Port inputs if

Input H

AUTOMOTIVE

Hysteresis input

levels are selected

voltage

(At VCC = 5 V

± 10%)

V^IHA

0.8 VCC

VCC + 0.3

V

RST input pin

(CMOS Hysteresis)

VIHR

0.8 VCC

VCC + 0.3

V

V^IHM

VCC − 0.3

MD input pin

Port inputs if CMOS

Hysteresis input

VILS

VSS − 0.3

0.2 VCC

V

levels are selected

Port inputs if

Input L voltage

(At VCC = 5 V

± 10%)

AUTOMOTIVE

Hysteresis input

levels are selected

V^ILA

VSS − 0.3

0.5 VCC

V

RST input pin

(CMOS Hysteresis)

VILR

V^ILM

VOH1

VSS − 0.3

VCC − 0.5

0.2 VCC

V

VSS + 0.3

MD input pin

Output H

voltage

Normal

outputs

VCC = 4.5 V,

IOH1 = −4.0 mA

V^CC= 4.5 V,

IOH2 = −40.0 mA

T^A= − 40 °C

TA = + 25 °C

T^A= + 85 °C

High

V^OH2current

outputs

Output H

voltage

V^CC= 4.5 V,

IOH2 = −30.0 mA

V^CC− 0.5

V

VCC = 4.5 V,

IOH2 = −30.0 mA

Output L

voltage

Normal

VOL1

VCC = 4.5 V,

IOL1 = 4.0 mA

0.4

0.5

5

outputs

VCC = 4.5 V,

IOL2 = 40.0 mA

TA = − 40 °C

TA = + 25 °C

TA = + 85 °C

High

V^OL2current

outputs

Output L

voltage

VCC = 4.5 V,

IOL2 = 30.0 mA

V

VCC = 4.5 V,

IOL2 = 30.0 mA

Input leak

current

VCC = 5.5 V,

VSS < VI < VCC

I^IL

−5

µA

(Continued)

43

MB90390 Series

(T^A= −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

VCC = 5.0 V,

Internal frequency : 20 MHz,

At normal operation.

50

70

mA MB90F394H

VCC = 5.0 V,

Internal frequency : 24 MHz,

At normal operation.

60

65

75

70

80

22

27

0.3

85

V^CC= 5.0 V,

Internal frequency : 20 MHz,

At writing FLASH memory.

I^CC

V^CC= 5.0 V,

Internal frequency : 24 MHz,

At writing FLASH memory.

100

90

V^CC= 5.0 V,

Internal frequency : 20 MHz,

At erasing FLASH memory.

V^CC= 5.0 V,

Internal frequency : 24 MHz,

At erasing FLASH memory.

105

30

Power supply

current*

VCC

VCC = 5.0 V,

Internal frequency : 20 MHz,

At Sleep mode.

I^CCS

V^CC= 5.0 V,

Internal frequency : 24 MHz,

At Sleep mode.

36

VCC = 5.0 V,

Internal frequency : 2.5 MHz,

At Main Timer mode

I^CTS

0.6

VCC = 5.0 V,

Internal frequency : 20 MHz,

At PLL Timer mode, external

frequency = 5 MHz

I^CTSPLL4

4

6

mA MB90F394H

VCC = 5.0 V,

Internal frequency : 24 MHz,

At PLL Timer mode, external

frequency = 4 MHz

I^CTSPLL6

5

7

VCC = 5.0 V, At Stop mode,

TA = +25°C

I^CCH

100

µA MB90F394H

(Continued)

44

MB90390 Series

(Continued)

(TA = −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min

Typ

Max

Other than C, AVCC,

AVSS, AVRH, AVRL,

VCC, VSS, DVCC, DVSS,

P70 to P77, P80 to P87,

PA0 to PA7

5

15

pF

Input capacity

C^IN

P70 to P77, P80 to P87,

PA0 to PA7

15

30

* : The power supply current is measured with an external clock.

45

MB90390 Series

4. AC Characteristics

(1) Clock Timing

(T^A= −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

3

Typ

Max

8

When using a crystal oscillator

or a ceramic oscilltor*

X0, X1

X0

MHz

Oscillation frequency

f^C

3

12

MHz When using an external clock*

When using a crystal oscillator

or a ceramic oscillator

X0, X1

X0

125

83.33

20

333

ns

Oscillation cycle time

t^CYL

ns When using an external clock

Duty ratio is about 30% to

70%.

Input clock pulse width

P^WH, PWL

tCR, tCF

X0

ns

Input clock rise and fall time

X0

5

ns When using external clock

When using clock modulation,

be sure that the maximum mo-

mentary frequency Fmax does

not exceed 24 MHz. Refer to

Machine clock frequency

f^CP

1.5

24

MHz

the Clock Modulator chapter

of the Hardware Manual.

Machine clock cycle time

tCP

41.67

666

ns

* : When selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as mentioned

in “• Guaranteed PLL operation range”.

• Clock Timing

tCYL

0.8 VCC

X0

0.2 VCC

PWH

PWL

tCF

tCR

46

MB90390 Series

• Guaranteed PLL operation range

Guaranteed operation range

Guaranteed PLL operation range (PLL2=1)

5.5

4.5

Guaranteed A/D converter

operation range

3.5

Guaranteed PLL operation range (PLL2=0)

1.5

4

8

20

24

Machine clock fCP (MHz)

Guaranteed operation range of MB90F394H

• PLL2 (bit 0 in PLLC register) = 0

Guaranteed oscilation frequency range

×4 (CS=11)

×3 (CS=10)

×2 (CS=01)

20

16

12

×1*¹(CS=00)

×1/2 (PLL off)

8

6

4

1.5

3

4

6

8

10

12

External clock fC (MHz)*²

• PLL2 (bit 0 in PLLC register) = 1

Guaranteed oscilation frequency range

×6 (CS=10)

×4 (CS=01)

×2 (CS=00)

24

16

8

6

×1/2 (PLL off)

1.5

3

4

6

8

10

12

External clock fC (MHz)*²

*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 12 MHz.

*2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHz

External clock frequency and Machine clock frequency

47

MB90390 Series

(2) Reset Standby Input

(T^A= −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V)

Value

Parameter Symbol

Unit

Remarks

Min

Max

16 tCP*¹

ns

µs

Under normal operation

In Stop mode

Reset input

t^RSTL

Oscillation time of oscillator*²

RST

time

+ 100µs + 16 tCP*¹

100

In Time Base Timer mode

*1 : “t^CP” represents one cycle time of the machine clock.

No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.

*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.

Inthe crystaloscillator, theoscillationtimeis betweenseveralmsandtotens of ms. InFAR/ ceramic oscillators,

the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.

• Under Normal Operation

tRSTL

RST

0.2 VCC

• In Stop Mode

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operation

clock

16 tCP

Oscillation time

of oscillator

+100 µs

Oscillation setting time

Instruction execution

Internal reset

48

MB90390 Series

(3) Power On Reset

(T^A= −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

Power on rise time

Power off time

t^R

VCC

30

ms

t^OFF

ms Due to repetitive operation

tR

2.7 V

VCC

0.2 V

tOFF

If you change the power supply voltage too rapidly, a power on reset may occur.

We recommend that you startup smoothly by restraining voltages when changing

the power supply voltage during operation, as shown in the figure below. Perform

while not using the PLL clock. However, if voltage drops are within 1 V/s, you can

operate while using the PLL clock.

VCC

We recommend a rise of

50 mV/ms maximum.

Holds RAM data

3 V

VSS

49

MB90390 Series

(4) UART0/1/2/3, Serial I/O Timing

(T^A= −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)

Value

Re-

Sym-

bol

Parameter

Condition

Unit

marks

Min

Max

Serial clock cycle time

t^SCYC

SCK0 to SCK4

8 t^CP

ns

SCK0 to SCK4,

SOT0 to SOT4

SCK ↓ → SOT delay time

t^SLOV

t^IVSH

tSHIX

−80

100

60

+80

Internal clock

operation output

pins are

SCK0 to SCK4,

SIN0 to SIN4

Valid SIN → SCK ↑

ns

CL = 80 pF + 1 TTL.

SCK0 to SCK4,

SIN0 to SIN4

SCK ↑ → Valid SIN hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

SCK0 to SCK4

4 t^CP

ns

tSLSH

4 tCP

SCK0 to SCK4, External clock

SOT0 to SOT4 operation output

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

t^SHIX

150

ns

pins are

CL = 80 pF + 1 TTL.

SCK0 to SCK4,

SIN0 to SIN4

60

SCK0 to SCK4,

SIN0 to SIN4

SCK ↑ → Valid SIN hold time

Notes : • AC characteristic in CLK synchronized mode.

• C^Lis load capacity value of pins when testing.

• t^CPis the machine cycle.

50

MB90390 Series

• Internal Shift Clock Mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

VIH

VIL

VIH

VIL

• External Shift Clock Mode

tSLSH

tSHSL

SCK

VIH

VIL

tSLOV

VIL

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

VIH

VIL

VIH

VIL

51

MB90390 Series

(5) Timer Related Resource Input Timing

(T^A= −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

Max

t^TIWH

t^TIWL

TIN0, TIN1

IN0 to IN5

Input pulse width

4 tCP

ns

• Timer Input Timing

VIH

VIL

tTIWH

tTIWL

(6) Trigger Input Timing

Parameter

(T^A= −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)

Value

Symbol

Condition

Unit

Remarks

Min

5 tCP

1

Max

Under normal

operation

ns

t^TRGH

tTRGL

INT0 to INT7,

ADTG

Input pulse width

µs

In stop mode

• Trigger Input Timing

VIH

VIL

tTRGH

tTRGL

(7) Slew Rate High Current Outputs

Sym-

(T^A= −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)

Value

Parameter

Condition

Unit

Remarks

bol

Min

Typ

Max

P70 to P77,

P80 to P87,

PA0 to PA7

t^R2

tF2

Output Rise/Fall time

15

ns

• Slew Rate Output Timing

VH

VL

VH VOL2 0.9 (VOH2 VOL2)

VL VOL2 0.1 (VOH2 VOL2)

tR2

tF2

52

MB90390 Series

(8) I²C Timing

(T^A= −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)

Fast-mode*⁴

Standard-mode

Parameter

Symbol

Condition

Unit

Min

Max

Min

Max

SCL clock frequency

f^SCL

0

100

0

400

kHz

Hold time (repeated) START condition

SDA ↓ → SCL ↓

t^HDSTA

4.0

0.6

µs

“L” width of the SCL clock

“H” width of the SCL clock

tLOW

4.7

4.0

1.3

0.6

µs

t^HIGH

Set-up time for a repeated START condition

SCL ↑ → SDA ↓

t^SUSTA

t^HDDAT

tSUDAT

tSUSTO

t^BUS

4.7

0

0.6

0

µs

ns

µs

R = 1.3 kΩ,

C = 50 pF*¹

Data hold time

SCL ↓ → SDA ↓ ↑

3.45*²

0.9*³

Data set-up time

SDA ↓ ↑ → SCL ↑

250

4.0

4.7

100

0.6

1.3

Set-up time for STOP condition

SCL ↑ → SDA ↑

Bus free time between a STOP and START

condition

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum t^HDDATonly has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

*3 : A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement

tSUDAT ≥ 250 ns must then be met.

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

SDA

tBUS

tSUDAT

tHDSTA

t^LOW

SCL

tHIGH

tHDSTA

tHDDAT

tSUSTA

tSUSTO

53

MB90390 Series

5. A/D Converter

(TA

= −40 °C to +85 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)

Value

Parameter

Resolution

Symbol

Unit Remarks

Min

Typ

Max

10

bit

Conversion error

Nonlinearity error

±3.0

±2.5

LSB

Differential nonlinearity

error

±1.9

LSB

Zero reading voltage

V^OT

AN0 to AN7 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB

AN0 to AN7 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB

Full scale reading

voltage

V^FST

Compare time

3.3

1.6

−5

66 t^CP

32 t^CP

16500

∞

µs

µA

Sampling time

Analog port input current

I^AIN

AN0 to AN7

+5

Analog input voltage

range

V^AIN

AVRL

AVRH

V

AVRH

AVRL

AVCC

AVRL + 2.7

AV^CC

V

Reference voltage

range

0

AVRH − 2.7

I^A

IAH

I^R

3.5

7.5

5

mA

µA

Power supply current

AVCC

*

AVRH

165

250

5

Reference voltage

current

IRH

Offset between input

channels

AN0 to AN7

4

LSB

* : When not operating A/D converter, this is the current (V^CC= AVCC = AVRH = 5.0 V) .

Terminology

Conversion error

: Absolute maximum conversion deviation with respect to the theoretical conversion

line.

Nonlinearity

: Relative maximum conversion deviation with respect to the theoretical conversion line

connecting to the device unique zero reading voltage and full scale reading voltage.

: Max conversion deviation in any two adjacent reading voltages with respect to the the

oretical LSB conversion step.

Differential nonlinearity

Zero reading voltage

: Input voltage which results in the minimum conversion value.

Full scale reading voltage : Input voltage which results in the maximum coversion value.

Notes : The accuracy gets worse as AVRH − AVRL becomes smaller.

54

MB90390 Series

6. Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Linear error

: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion

characteristics.

Differentiallinear : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

error

value.

Total error

: Difference between an actual value and an ideal value. A total error includes zero transition

error, full-scale transition error, and linear error.

Total error

3FF

1.5 LSB

3FE

3FD

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004

003

002

001

VNT

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

[LSB]

Total error of digital output “N” =

1 LSB

AVRH − AV^SS

1 LSB = (Ideal value)

[V]

1024

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVRH − 1.5 LSB [V]

V^NT: A voltage at which digital output transitions from (N − 1) to N.

(Continued)

55

MB90390 Series

(Continued)

Linear error

Differential linear error

Ideal

characteristics

3FF

Actual conversion

characteristics

3FE

N + 1

Actual conversion

characteristics

{1 LSB × (N − 1)

+ VOT }

3FD

VFST (actual

measurement

value)

N

VNT (actual

measurement value)

004

V (N + 1) T

(actual measurement

value)

Actual conversion

characteristics

N − 1

N − 2

003

002

001

VNT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

VOT (actual measurement value)

Analog input

AVSS

AVRH

AVSS

AVRH

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

[LSB]

Linear error of digital output N =

1 LSB

V ^{(N+1) T}− VNT

−1 LSB [LSB]

1 LSB

Differential linear error of digital output N =

1 LSB =

VFST − VOT

[V]

1022

V^OT: Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

56

MB90390 Series

7. Notes on A/D Converter Section

Use the device with external circuits of the following output impedance for analog inputs :

Recommended output impedance of external circuits are : Approx. 3.1 kΩ or lower (4.5 V ≤ AV^CC≤ 5.5 V)

(sampling period = 1.60 µs at 20 MHz machine clock) .

If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors

and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high

as internal capacitor.

If toutput impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.

• Analog input circuit model

R

Analog input

Comparator

C

R=: 2.35 kΩ, C=: 36.4 pF

Note : Use the values in the figure only as a guideline.

8. Flash Memory Program/Erase Characteristics

Value

Parameter

Conditions

Unit

Remarks

MIn

Typ

Max

Excludes programming

prior to erasure

Sector erase time

Chip erase time

1

9

15

s

T^A= +25 °C

VCC = 5.0 V

Excludes programming

prior to erasure

Word (16 bit width)

programming time

Except for the over head

time of the system

16

3,600

µs

Programs/Erase cycle

10,000

20

cycle

Year

Flash Data Retention

Time

Average

T^A= +85 °C

*

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C) .

57

MB90390 Series

■ EXAMPLE CHARACTERISTICS

ICC − VCC

ICCS − VCC

(Ta = +25 °C)

(fcp = 2.5 MHz, Ta = +25 °C)

14

12

10

8

60

fcp = 20 MHz

50

40

30

20

10

0

fcp = 15 MHz

fcp = 10 MHz

6

fcp = 5 MHz

4

fcp = 2.5 MHz

2

0

2.0

3.0

4.0

5.0

VCC [V]

6.0

7.0

2.0

3.0

4.0

5.0

VCC [V]

6.0

7.0

I^CTS− VCC

ICCH − VCC

(fcp = 2.5 MHz, Ta = +25 °C)

(Ta = +25 °C)

20

18

16

14

12

10

8

600

500

400

300

200

100

0

6

4

2

0

2.0

3.0

4.0

5.0

VCC [V]

6.0

7.0

2.0

3.0

4.0

5.0

VCC [V]

6.0

7.0

58

MB90390 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

120-pin Plastic LQFP

(FPT-120P-M21)

MB90F394HPMT

MB90V390HCR

299-pin Ceramic PGA

(PGA-299C-A01)

For evaluation

59

MB90390 Series

■ PACKAGE DIMENSION

Note 1) * : These dimensions do not include resin protrusion.

Resin protrusion is +0.25 (.010) MAX (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

120-pin Plastic LQFP

(FPT-120P-M21)

18.00±0.20(.709±.008)SQ

+0.40

16.00 –0.10

.630 ⁺^–.^.⁰⁰⁰¹⁴⁶SQ

*

90

61

91

60

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

INDEX

0~8˚

"A"

120

31

0.10±0.05

(.004±.002)

(Stand off)

1

30

LEAD No.

0.145 ⁺–0⁰.^.0⁰3⁵

.006 ⁺^–.^.⁰⁰⁰⁰¹²

0.60±0.15

(.024±.006)

0.22±0.05

(.009±.002)

M

0.50(.020)

0.08(.003)

0.25(.010)

C

2002 FUJITSU LIMITED F120033S-c-4-4

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

60

MB90390 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0405

FUJITSU LIMITED Printed in Japan


型号：	MB90V390HCR
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller CMOS 16位微控制器的专有CMOS 微控制器和处理器外围集成电路时钟
文件：	总61页 (文件大小：770K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90V390HCR [FUJITSU]

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