MB90V390HBCR [FUJITSU]
16-bit Proprietary Microcontroller; 16位微控制器专有
| 型号： | MB90V390HBCR |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit Proprietary Microcontroller |
| 文件： | 总71页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13723-6E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90390 Series
MB90394HA/F394H/F394HA/
MB90V390H/V390HA/V390HB
■ DESCRIPTION
The MB90390-series with up to five FULL-CAN* interfaces and Flash ROM is especially designed for automotive
and industrial applications. Its main feature are up to five on board CAN Interfaces, which conform to V2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a
normal full CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip Flash-ROM
program memory up to 512 Kbytes. An internal voltage booster removes the necessity for a second programming
voltage.
An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features 6 Stepper Motor Controllers with slew rate controlled high current outputs.
Furthermore it features an 8-channel Output Compare Unit and a 6-channel Input Capture Unit with two separate
16-bit free running timers. Up to 4 UARTs constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2002-2006 FUJITSU LIMITED All rights reserved
MB90390 Series
■ FEATURES
• 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instruction execution time)
• New 0.35 µm CMOS Process Technology
• Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures
• Up to five FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, flexible message buffering
(mailbox and FIFO buffering can be mixed)
• Powerful interrupt functions (8 progr. priority levels; 8 external interrupts)
• EI2OS - Automatic transfer function indep.of CPU; 16 channels of intelligent I/O Services
• 18-bit Time-base counter
• Watchdog Timer
• 2 full duplex UARTs; support 10.4 Kbps (USA standard )
• Up to 2 full duplex UARTs (LIN/SCI)
• Serial I/O : 1 channel for synchronous data transfer
• Optional I2C* with 400 Kbps
• A/D Converter : 15 channels analog inputs (Resolution 10 bits or 8 bits)
• 16-bit reload timer × 2 channels
• ICU (Input capture) 16-bit × 6 channels (2 input pins are shared with OCU outputs)
• OCU (Output capture) 16-bit × 8 channels (2 output pins are shared with ICU input pins)
• 16-bit free running timer × 2 channels (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5, OCU 4/5/6/7)
• 8/16-bit Programmable Pulse Generator 6 channels × 16-bit/12 channels × 8-bit
• Stepping Motor Controller 6 channels with slew rate controlled high current outputs
• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
addressing modes; barrel shift; variety of pointers)
• 4-byte instruction execution queue
• signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
• Program Patch Function
• Fast Interrupt processing
• Low Power Consumption mode
Sleep mode
Timebase timer mode
Stop mode
CPU intermittent mode
• Sound Generator
• Real Time Watch Timer
• Built-In Clock Modulation circuit
• Programmable input levels (Automotive Hysteresis / CMOS Hysteresis, initial level is Automotive Hysteresis)
• Package : 120-pin plastic LQFP
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
2
MB90390 Series
■ PRODUCT LINEUP
Part Number
Parameter
MB90F394H
MB90F394HA
MB90V390HA/
MB90V390HB
MB90394HA
MB90V390H
CPU
F2MC-16LX CPU
On-chip PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
System clock
Boot-block
Flash memory 384
ROM memory 384 Kbytes
ROM
RAM
External
Kbytes
Hard-wired reset vector,
points to address
FFA000H
10 Kbytes
16 Kbytes
30 Kbytes
Emulator-specific
power supply*1
⎯
Yes
0.35 µm CMOS with on-
chip
0.35 µm CMOS with
on-chip
voltage regulator for
internal
voltage regulator for in-
ternal power supply +
Flash memory with
On-chip charge pump
for
0.35 µm CMOS with on-chip
voltage regulator for internal power supply
Technology
power supply
programming voltage
3.5 V to 5.5 V
Operating
voltage range
(4.0 V to 5.5 V: during Flash programming
and erasing,
5 V 10%
4.5 V to 5.5 V: if A/D Converter is used)
Temperature range
Package
−40 °C to +85 °C
LQFP-120
⎯
PGA-299
Full duplex double buffer
UART
(2 channels)
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock = 24 MHz
UART (LIN/SCI)
I2C (400 Kbps)
1 channel
2 channels
1 channel
⎯
1 channel
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Serial I/O
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 24 MHz
15 input channels
10-bit or 8-bit resolution
A/D Converter
Conversion time : Min 4.9 µs include sample time (per one channel, depends on machine
clock frequency)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
(2 channels) Supports External Event Count function
(Continued)
3
MB90390 Series
Part Number
Parameter
MB90F394H
MB90F394HA
MB90V390HA/
MB90V390HB
MB90394HA
MB90V390H
Directly operates with the oscillation clock
Watch Timer
Read/Write accessible Second/Minute/Hour registers
Signals interrupts
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0)
16-bit
I/O Timer
(2 channels)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = System clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5, OCU 4/5/6/7
Signals an interrupt when a match with 16-bit I/O Timer
Eight 16-bit compare registers.
A pair of compare registers can be used to generate an output signal.
OCU 6/7 outputs are shared with ICU 3/5 inputs
16-bit
Output Compare
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Six 16-bit Capture registers
Signals an interrupt upon external event
ICU 3/5 inputs are shared with OCU 6/7 outputs
16-bit
Input Capture
(6 channels)
Supports 8-bit and 16-bit operation modes
Twelve 8-bit reload counters
8/16-bit
Twelve 8-bit reload registers for L pulse width
ProgrammablePulse Twelve 8-bit reload registers for H pulse width
Generator
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
(6 channels)
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 µs at fosc = 5 MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
2 channels
5 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full-bit compare/Full-bit mask/Two partial bit masks
Supports up to 1 Mbps
CAN Interface
(up to 5 channels)
MB90F394H, MB90V390H, MB90V390HA :
Do not use CAN message buffer RAM and clock modulator at the same time.
Stepping Motor
Controller
(6 channels)
Four high current outputs with controlled slew rate for each channel
Synchronized two 8-bit PWM’s for each channel
External Interrupt
(8 channels)
Can be programmed edge sensitive or level sensitive
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz at System clock = 16 MHz
Tone frequency : PWM frequency/2/ (reload value + 1)
Sound Generator
(Continued)
4
MB90390 Series
(Continued)
Part Number
Parameter
MB90F394H
MB90F394HA
MB90V390HA/
MB90V390HB
MB90394HA
MB90V390H
Virtually all external pins can be used as general purpose I/O
All push-pull outputs
Bit-wise programmable as input/output or peripheral signal
I/O Ports
Port-wise programmable as CMOS Hysteresis or automotive Hysteresis inputs (default)
Spread spectrum clock modulator for reducing electromagnetic emissions.
Frequency and Phase Modulation modes.
MB90F394H :
Clock Modulator
Do not use frequency modulation.
MB90F394H, MB90V390H, MB90V390HA :
Do not use CAN message buffer RAM and clock modulator at the same time.
Supports automatic
programming,
Embedded Algorith-
mTM*2
Write/Erase/Erase-
Suspend/Resume
commands
A flag indicating com-
pletion of the algorithm
Number of erase cycles
: 10,000 times
Flash
Memory
Data retention time : 20
years*3
⎯
⎯
Hard-wired reset vector
available in order to
point to a fixed boot
sector in Flash Memory
Boot block configura-
tion
Erase can be per-
formed on each block
Block protection with
external programming
voltage
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply
Switching) about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
*3 : This value comes from the technology qualification (using Arrehenius equation to translate high temperature
measurements into normalized value at +85 °C)
5
MB90390 Series
■ PIN ASSIGNMENTS
• MB90V390H
(TOP VIEW)
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P30/RX0
P31/TX0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA
P43/SCL
P44
RST
MD0
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P45/ADTG
VCC
VSS
C
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00/RX2*
P57/PPG01/TX2*
P90
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P91
P92
(FPT-120P-M21)
* : MB90V390H/HA/HB only
6
MB90390 Series
• MB90V390HA/MB90V390HB
(TOP VIEW)
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P30/RX0
P31/TX0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA
P43/SCL
P44
RST
MD0
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P45/ADTG
V
CC
V
SS
C
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00/RX2*1
P57/PPG01/TX2*1
P90/SIN2*2
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P91/SCK2*2
P92/SOT2*2
(FPT-120P-M21)
*1 : MB90V390H/HA/HB only
*2 : MB90V390HA/HB only
7
MB90390 Series
• MB90394HA/MB90F394H/MB90F394HA
(TOP VIEW)
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P30/RX0
P31/TX0
RST
MD0
P32/TIN1
P33/TOT1
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SDA*
P43/SCL*
P44
MD1
MD2
DVSS
DVCC
PA7/PWM2M5
PA6/PWM2P5
PA5/PWM1M5
PA4/PWM1P5
PA3/PWM2M4
PA2/PWM2P4
PA1/PWM1M4
PA0/PWM1P4
DVSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P45/ADTG
V
CC
V
SS
C
DVCC
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P46/INT0
P47/INT1
P50/PPG10
P51/PPG11
P52/PPG12
P53/PPG13
P54/PPG14
P55/PPG15
P56/PPG00
P57/PPG01
P90
DVCC
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P91
P92
(FPT-120P-M21)
* : These pins are not available in MB90F394H/MB90F394HA.
8
MB90390 Series
■ PIN DESCRIPTION
Pin no.
107
Pin name
X1
Circuit type*
Function
Oscillation output
Oscillation input
Reset input
A
B
D
108
X0
90
RST
P00 to P02
IN0 to IN2
P03
General purpose I/O
93 to 95
96
Inputs for the Input Captures 0 to 2
General purpose I/O
IN3
D
D
D
Input for the Input Capture 3
Output for the Output Compare 6
General purpose I/O
OUT6
P04
97
IN4
Input for the Input Capture 4
General purpose I/O
P05
98
IN5
Input for the Input Capture 5
Output for the Output Compare 7
OUT7
P06, P07,
P10 to P13
General purpose I/O
99 to 104
D
OUT0 to OUT5
P14
Outputs for the Output Compares 0 to 5
General purpose I/O
109
110
D
D
D
D
D
D
D
D
D
TIN0
TIN0 input for the 16-bit Reload Timer 0
General purpose I/O
P15
TOT0
P16
TOT0 output for the 16-bit Reload Timer 0
General purpose I/O
111
SGO
SGO output for the Sound Generator
General purpose I/O
P17
112
SGA
SGA output for the Sound Generator
General purpose I/O
P20
113
TX1
TX output for CAN Interface 1
General purpose I/O
P21
114
RX1
RX input for CAN Interface 1
General purpose I/O
P22 to P27
INT2 to INT7
P30
115 to 120
1
External interrupt inputs for INT2 to INT7
General purpose I/O
RX0
RX input for CAN Interface 0
General purpose I/O
P31
2
TX0
TX output for CAN Interface 0
(Continued)
9
MB90390 Series
Pin no.
Pin name
P32
Circuit type*
Function
General purpose I/O
3
D
TIN1
TIN1 input for the 16-bit Reload Timer 1
General purpose I/O
P33
4
5
D
D
D
D
D
D
D
D
TOT1
P34
TOT1 output for the 16-bit Reload Timer 1
General purpose I/O
SOT0
P35
SOT output for UART 0
General purpose I/O
6
SCK0
P36
SCK I/O for UART 0
General purpose I/O
7
SIN0
SIN input for UART 0
P37
General purpose I/O
8
SIN1
SIN input for UART 1
P40
General purpose I/O
9
SCK1
P41
SCK I/O for UART 1
General purpose I/O
10
11
SOT1
P42
SOT output for UART 1
General purpose I/O
SDA
Serial data for I2C interface (except MB90F394H(A))
P43
General purpose I/O
12
13
14
D
D
D
SCL
Serial clock for I2C interface (except MB90F394H(A))
General purpose I/O
P44
P45
General purpose I/O
ADTG
P46, P47
INT0, INT1
P50 to P55
PPG10 to PPG15
P56
External trigger input of the A/D Converter
General purpose I/O
18, 19
D
D
External interrupt inputs for INT0 to INT1
General purpose I/O
20 to 25
Outputs for the Programmable Pulse Generators 10 to 15
General purpose I/O
26
PPG00
RX2
D
Output for the Programmable Pulse Generator 0
RX input for CAN Interface 2 (only MB90V390H/HA/HB)
General purpose I/O
P57
27
28
PPG01
TX2
D
D
Output for the Programmable Pulse Generator 1
TX output for CAN Interface 2 (only MB90V390H/HA/HB)
General purpose I/O
P90
SIN2
SIN input for UART 2 (only MB90V390HA/HB)
(Continued)
10
MB90390 Series
Pin no.
Pin name
P91
Circuit type*
Function
General purpose I/O
29
D
SCK2
P92
SCK input/output for UART 2 (only MB90V390HA/HB)
General purpose I/O
30
31
D
D
D
D
D
E
SOT2
P93
SOT output for UART 2 (only MB90V390HA/HB)
General purpose I/O
SIN3
SIN input for UART 3 (LIN/SCI)
General purpose I/O
P94
32
SCK3
P95
SCK input/output for UART 3 (LIN/SCI)
General purpose I/O
33
SOT3
P96
SOT output for UART 3 (LIN/SCI)
General purpose I/O
34
WOT
P60 to P67
AN0 to AN7
PB0
WOT output for the Watch Timer
General purpose I/O
39 to 46
Inputs for the A/D Converter
General purpose I/O
PPG02
TX3
Output for the Programmable Pulse Generator 2
TX output for CAN Interface 3 (only MB90V390H/HA/HB)
Input for the A/D Converter
48
49
50
E
E
E
AN8
PB1
General purpose I/O
PPG03
RX3
Output for the Programmable Pulse Generator 3
RX input for CAN Interface 3 (only MB90V390H/HA/HB)
Input for the A/D Converter
AN9
PB2
General purpose I/O
PPG04
TX4
Output for the Programmable Pulse Generator 4
TX output for CAN Interface 4 (only MB90V390H/HA/HB)
Input for the A/D Converter
AN10
PB3
General purpose I/O
PPG05
RX4
Output for the Programmable Pulse Generator 5
RX input for CAN Interface 4 (only MB90V390H/HA/HB)
Input for the A/D Converter
51
52
E
E
AN11
PB4
General purpose I/O
SIN4
SIN input for the Serial I/O
AN12
Input for the A/D Converter
(Continued)
11
MB90390 Series
Pin no.
Pin name
PB5
Circuit type*
Function
General purpose I/O
53
SCK4
E
SCK input/output for the Serial I/O
Input for the A/D Converter
General purpose I/O
AN13
PB6
54
SOT4
E
F
SOT output for the Serial I/O
Input for the A/D Converter
General purpose I/O
AN14
P70 to P73
PWM1P0
PWM1M0
PWM2P0
PWM2M0
57 to 60
Output for Stepping Motor Controller channel 0
P74 to P77
General purpose I/O
PWM1P1
PWM1M1
PWM2P1
PWM2M1
61 to 64
67 to 70
71 to 74
77 to 80
F
F
F
F
Output for Stepping Motor Controller channel 1
P80 to P83
General purpose I/O
PWM1P2
PWM1M2
PWM2P2
PWM2M2
Output for Stepping Motor Controller channel 2
P84 to P87
General purpose I/O
PWM1P3
PWM1M3
PWM2P3
PWM2M3
Output for Stepping Motor Controller channel 3
PA0 to PA3
General purpose I/O
PWM1P4
PWM1M4
PWM2P4
PWM2M4
Output for Stepping Motor Controller channel 4
PA4 to PA7
General purpose I/O
PWM1P5
PWM1M5
PWM2P5
PWM2M5
81 to 84
F
Output for Stepping Motor Controller channel 5
PB7
General purpose I/O
91
FRCK0
HCLK
D
FRCK0 input for the 16-bit I/O Timer 0
Oscillation Clock output
(Continued)
12
MB90390 Series
(Continued)
Pin no.
Pin name
P97
Circuit type*
Function
General purpose I/O
92
FRCK1
HCLK
D
FRCK1 input for the 16-bit I/O Timer 1
Inverted Oscillation Clock output
55
65
75
85
Dedicated power supply pins for the high current output buffers
(Pin No. 57 to 84)
DVcc
DVss
⎯
⎯
56
66
76
86
Dedicated ground pins for the high current output buffers
(Pin No. 57 to 84)
35
36
37
38
AVCC
AVRH
AVRL
AVss
⎯
⎯
⎯
⎯
Dedicated power supply pin (5 V) for the A/D converter
Dedicated pos. reference voltage pin for the A/D converter
Dedicated neg. reference voltage pin for the A/D converter
Dedicated power supply pin (0 V) for the A/D converter
These are input pins used to designate the operating mode. They
should be connected directly to VCC or VSS.
88, 89
87
MD1, MD0
MD2
C
G
This is an input pin used to designate the operating mode. It
should be connected directly to VCC or VSS.
15
105
Vcc
⎯
These are power supply (5 V) input pins
16
47
106
Vss
C
⎯
⎯
These are power supply (0 V) input pins
This is the power supply stabilization capacitor pin. It should be
connected to higher than or equal to 0.1 µF (MB90394HA/
MB90F394H(A)/MB90V390H)/0.22 µF (MB90V390HA/HB) ce-
ramic capacitor.
17
* : Refer to “■ I/O CIRCUIT TYPE” for I/O circuit type.
13
MB90390 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Oscillation feedback resistor :
1 MΩ approx.
X1
Clock input
P-ch
N-ch
X0
A
Standby control signal
• CMOS Hysteresis input with pull-up
Resistor :
50 kΩ approx.
V
CC
R (pull-up)
R
B
C
CMOS HYS
• EVA/ROM device :
CMOS Hysteresis input
• Flash device :
R
CMOS HYS
CMOS input.
• CMOS output
• CMOS Hysteresis input
• Automotive Hysteresis input
VCC
P-ch
N-ch
Note : The input characteristic may be
differentfordifferentpins/devices.
Refer to VIHS in “■ ELECTRICAL
CHARACTERISTICS 3.DC
Characteristics”
D
R
R
CMOS HYS
Automotive
HYS
(Continued)
14
MB90390 Series
(Continued)
Type
Circuit
Remarks
• CMOS output
VCC
• CMOS Hysteresis input
• Automotive Hysteresis input
• Analog input
P-ch
N-ch
Note : The input characteristic may be
different for different pins/devices.
Refer to VIHS in “■ ELECTRICAL
CHARACTERISTICS 3.DC
Characteristics”
P-ch
E
Analog input
CMOS HYS
N-ch
R
R
Automotive
HYS
• CMOS high current output
• CMOS Hysteresis input
• Automotive Hysteresis input
DVcc
P-ch
High current
N-ch
F
R
R
CMOS HYS
Automotive
HYS
• EVA/ROM device :
CMOS Hysteresis input with pull-
down Resistor : 50 kΩ approx.
• Flash device :
R
CMOS HYS
G
R (pull-down)
CMOS input without pull-down.
15
MB90390 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Stabilization of supply voltage
• Treatment of unused pins
• Using external clock
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter if A/D Converter is unused.
• Notes on Energization
• Caution on Operations during PLL Clock Mode
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at
commercial frequencies (50/60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of
fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
3. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
4. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90390 Series
X0
X1
16
MB90390 Series
5. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
VCC
MB90390
Series
VCC
VSS
VCC
VSS
6. Pull-up/down resistors
The MB90390 Series does not support internal pull-up/down resistors. Use external components where needed.
7. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14)
after turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable) .
9. Connection of Unused Pins of A/D Converter if A/D Converter is unused
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V) .
11. Notes on During Operation of PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
17
MB90390 Series
■ BLOCK DIAGRAMS
• MB90394HA
X0, X1
Clock
F2MC-16LX
CPU
Controller
RST
I/O Timer 0
FRCK0
RAM
10 Kbytes
Input
Capture
IN5 to IN0
6 channels
ROM
384 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler x 3
I/O Timer 1
SOT3, SOT1, SOT0
SCK3, SCK1, SCK0
SIN3, SIN1, SIN0
UART
3 channels
(1channel
LIN/SCI)
8/16-bit
PPG
6 channels
PPG05 to PPG00
PPG15 to PPG10
Prescaler
Serial I/O
RX1, RX0
TX1, TX0
CAN
2 channels
SOT4
SCK4
SIN4
PWM1M5 to PWM1M0
PWM1P5 to PWM1P0
PWM2M5 to PWM2M0
PWM2P5 to PWM2P0
DVcc
AVcc
AVss
SMC
6 channels
8/10-bit
A/D converter
15 channels
AN14 to AN0
AVRH
DVss
AVRL
ADTG
External
Interrupt
8 channels
INT7 to INT0
16-bit
TIN1, TIN0
Reload Timer
2 channels
TOT1, TOT0
SGO
SGA
Sound
Generator
Watch
Timer
WOT
I2C
Interface
SDA
SCL
18
MB90390 Series
• MB90F394H/MB90F394HA
X0, X1
F2MC-16LX
CPU
Clock
Controller
RST
I/O Timer 0
FRCK0
RAM
10 Kbytes
Input
Capture
IN5 to IN0
6 channels
Flash
384 Kbytes
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler x 3
I/O Timer 1
SOT3, SOT1, SOT0
SCK3, SCK1, SCK0
SIN3, SIN1, SIN0
UART
3 channels
(1channel
LIN/SCI)
PPG05 to PPG00
PPG15 to PPG10
8/16-bit
PPG
6 channels
Prescaler
Serial I/O
RX1, RX0
TX1, TX0
CAN
2 channels
SOT4
SCK4
SIN4
PWM1M5 to PWM1M0
PWM1P5 to PWM1P0
PWM2M5 to PWM2M0
PWM2P5 to PWM2P0
DVcc
AVcc
AVss
SMC
6 channels
8/10-bit
A/D converter
15 channels
AN14 to AN0
AVRH
DVss
AVRL
ADTG
External
Interrupt
INT7 to INT0
8 channels
16-bit
TIN1, TIN0
Reload Timer
2 channels
TOT1, TOT0
SGO
SGA
Sound
Generator
Watch
Timer
WOT
19
MB90390 Series
• MB90V390H
F2MC-16LX
CPU
X0, X1
Clock
Controller
RST
I/O Timer 0
FRCK0
RAM
16 Kbytes
Input
Capture
IN5 to IN0
6 channels
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler x 3
I/O Timer 1
SOT3,SOT1,SOT0
SCK3,SCK1,SCK0
SIN3,SIN1,SIN0
UART
3 channels
(1 channel
LIN/SCI)
8/16-bit
PPG
6 channels
PPG05 to PPG00
PPG15 to PPG10
Prescaler
Serial I/O
RX4 to RX0
TX4 to TX0
CAN
5 channels
SOT4
SCK4
SIN4
PWM1M5 to PWM1M0
PWM1P5 to PWM1P0
PWM2M5 to PWM2M0
PWM2P5 to PWM2P0
DVCC
AVCC
AVSS
SMC
6 channels
8/10-bit
A/D converter
15 channels
AN14 to AN0
AVRH
DVSS
AVRL
ADTG
External
Interrupt
INT7 to INT0
8 channels
16-bit
Reload Timer
2 channels
TIN1, TIN0
TOT1, TOT0
Sound
Generator
SGO
SGA
Watch
Timer
WOT
I2C
Interface
SDA
SCL
20
MB90390 Series
• MB90V390HA/MB90V390HB
F2MC-16LX
CPU
X0, X1
Clock
Controller
RST
FRCK0
I/O Timer 0
RAM
30 Kbytes
Input
Capture
IN5 to IN0
6 channels
Output
Compare
8 channels
OUT7 to OUT0
FRCK1
Prescaler x 4
I/O Timer 1
SOT3 to SOT0
SCK3 to SCK0
SIN3 to SIN0
UART
4 channels
(2 channels
LIN/SCI)
PPG05 to PPG00
PPG15 to PPG10
8/16-bit
PPG
6 channels
Prescaler
Serial I/O
RX4 to RX0
TX4 to TX0
CAN
5 channels
SOT4
SCK4
SIN4
PWM1M5 to PWM1M0
PWM1P5 to PWM1P0
PWM2M5 to PWM2M0
PWM2P5 to PWM2P0
DVcc
AVcc
AVss
SMC
6 channels
8/10-bit
A/D converter
15 channels
AN14 to AN0
AVRH
DVss
AVRL
ADTG
External
Interrupt
INT7 to INT0
8 channels
16-bit
Reload Timer
2 channels
TIN1, TIN0
TOT1, TOT0
SGO
SGA
Sound
Generator
Watch
Timer
WOT
SDA
SCL
I2C
Interface
21
MB90390 Series
■ MEMORY MAP
MB90394HA/
F394H(A)
MB90V390HA/HB
MB90V390H
FFFFFF
H
FFFFFF
H
FFFFFF
H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
FF0000
FEFFFF
H
H
FF0000
FEFFFF
H
H
FF0000
FEFFFF
H
H
FE0000
FDFFFF
H
H
FE0000
FDFFFF
H
H
FE0000
FDFFFF
H
H
FD0000
FCFFFF
H
H
FD0000
FCFFFF
H
H
FD0000
FCFFFF
H
H
FC0000
FBFFFF
H
H
FC0000
FBFFFF
H
H
FC0000
FBFFFF
H
H
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
FB0000
FAFFFF
H
H
FB0000
FAFFFF
H
H
FB0000
FAFFFF
H
H
FA0000
F9FFFF
H
H
FA0000
F9FFFF
H
H
FA0000
F9FFFF
H
H
F90000
H
F90000
F8FFFF
H
H
F90000
F8FFFF
H
H
F80000
H
F80000
H
8017FF
8 0 0 0 0 0
H
H
RAM 6 Kbytes
00FFFF
H
00FFFF
H
00FFFF
0 0 8 0 0 0
H
H
ROM (Image of
FF bank)
ROM (Image of
FF bank)
ROM (Image of
FF bank)
0 0 8 0 0 0
0070FF
0 0 4 1 0 0
H
H
H
0 0 4 0 0 0
or
0 0 8 0 0 0
H
H
0050FF
0 0 4 1 0 0
H
H
RAM 4 Kbytes
Periperal
RAM 12 Kbytes
Periperal
003FFF
H
003FFF
H
003FFF
H
Periperal
RAM 10 Kbytes
Periperal
0 0 3 5 0 0
0028FF
H
H
0 0 3 5 0 0
0030FF
H
H
0 0 3 5 0 0
0030FF
H
H
RAM 12 Kbytes
Periperal
RAM 12 Kbytes
Periperal
0 0 0 1 0 0
H
0 0 0 1 0 0
H
0 0 0 1 0 0
H
0000BF
0 0 0 0 0 0
H
H
0000BF
0 0 0 0 0 0
H
H
0000BF
0 0 0 0 0 0
H
H
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32/48 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF4000H/FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H
and FF3FFFH/FF7FFFH is visible only in bank FF.
In MB90V390H/HA/HB, the image for only ROM data between FF8000H to FFFFFFH is visible in bank 00.
As for MB90F394H(A) and MB90394HA, it is possible to set the FF bank area which looks the 00 bank image
in the ROM mirror function select register (ROMM) .
22
MB90390 Series
■ I/O MAP
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
00H
01H
Port 0 Data Register
Port 1 Data Register
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
PDRB
ADER0
ADER1
ILSR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port 6, A/D
Port B, A/D
Ports
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
11111111B
01111111B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
00000000B
02H
Port 2 Data Register
03H
Port 3 Data Register
04H
Port 4 Data Register
05H
Port 5 Data Register
06H
Port 6 Data Register
07H
Port 7 Data Register
08H
Port 8 Data Register
09H
Port 9 Data Register
0AH
0BH
0CH
0DH
0EH
0FH
10H
Port A Data Register
Port B Data Register
Analog Input Enable 0
Analog Input Enable 1/ ADC Select
Input Level Select Register
Input Level Select Register
Port 0 Direction Register
Port 1 Direction Register
Port 2 Direction Register
Port 3 Direction Register
Port 4 Direction Register
Port 5 Direction Register
Port 6 Direction Register
Port 7 Direction Register
Port 8 Direction Register
Port 9 Direction Register
Port A Direction Register
Port B Direction Register
ILSR
Ports
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
DDRB
Reserved
UMC0
USR0
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH to 1FH
20H
Serial Mode Control 0
Status 0
R/W
R/W
00000100B
00010000B
21H
UART0
UIDR0/
UODR0
22H
23H
Input/Output Data 0
Rate and Data 0
R/W
R/W
XXXXXXXXB
URD0
0000000XB
(Continued)
23
MB90390 Series
Abbrevia-
tion
Address
Register
Serial Mode Control 1
Access
Resource name
Initial value
24H
25H
UMC1
USR1
R/W
R/W
00000100B
00010000B
Status 1
UART1
UIDR1/
UODR1
26H
Input/Output Data 1
Rate and Data 1
R/W
R/W
XXXXXXXXB
0000000XB
27H
28H to 2BH
2CH
2DH
2EH
URD1
Reserved
Serial Mode Control 4
Serial Mode Control 4
Serial Data 4
SMCS4
SMCS4
SDR4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXX0000B
00000010B
XXXXXXXXB
0 X0 X 0000B
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
00000000B
XXXXXXXXB
000010XXB
0X000XX1B
0X000001B
000000XXB
Serial I/O
2FH
Serial I/O Prescaler/Edge Selector 4
External Interrupt Enable
External Interrupt Request
External Interrupt Level
External Interrupt Level
A/D Control Status 0
A/D Control Status 1
A/D Data 0
CDCR4
ENIR
30H
31H
EIRR
External Interrupt
A/D Converter
32H
ELVR
33H
ELVR
34H
ADCS0
ADCS1
ADCR0
ADCR1
35H
36H
37H
A/D Data 1
R/W
R/W
R/W
R/W
38H
PPG0 Operation Mode Control Register PPGC0
PPG1 Operation Mode Control Register PPGC1
16-bitProgrammable
Pulse
39H
Generator 0/1
3AH
PPG0 and PPG1 Clock Select Register
PPG01
Address Match
Detection Function 1
3BH
Address Detection Control Register 1
PACSR1
R/W
00000000B
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
PPG2 Operation Mode Control Register PPGC2
PPG3 Operation Mode Control Register PPGC3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0X000XX1B
0X000001B
000000XXB
XXXXXX00B
0X000XX1B
0X000001B
000000XXB
16-bitProgrammable
Pulse
Generator 2/3
PPG2 and PPG3 Clock Select Register
Clock Output Enable Register
PPG23
CKOE
Clock Output
PPG4 Operation Mode Control Register PPGC4
PPG5 Operation Mode Control Register PPGC5
16-bitProgrammable
Pulse
Generator 4/5
PPG4 and PPG5 Clock Select Register
PPG45
Reserved
PPG6 Operation Mode Control Register PPGC6
PPG7 Operation Mode Control Register PPGC7
R/W
R/W
R/W
0X000XX1B
0X000001B
16-bitProgrammable
Pulse
Generator 6/7
PPG6 and PPG7 Clock Select Register
PPG67
000000XXB
(Continued)
24
MB90390 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
60H
61H
Reserved
PPGC8
PPG8 Operation Mode Control Register
PPG9 Operation Mode Control Register
PPG8 and PPG9 Clock Select Register
R/W
R/W
R/W
0X000XX1B
0X000001B
000000XXB
16-bitProgrammable
Pulse
PPGC9
Generator 8/9
PPG89
Reserved
PPGA Operation Mode Control Register PPGCA
PPGB Operation Mode Control Register PPGCB
R/W
R/W
R/W
0X000XX1B
0X000001B
000000XXB
16-bitProgrammable
Pulse
Generator A/B
PPGA and PPGB Clock Select Register
PPGAB
Reserved
TMCSR0
TMCSR0
TMCSR1
TMCSR1
ICS01
Timer Control Status 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
XXXX0000B
00000000B
XXXX0000B
00000000B
00000000B
00000000B
16-bit Reload Timer
0
Timer Control Status 0
Timer Control Status 1
16-bit Reload Timer
1
Timer Control Status 1
Input Capture Control Status 0/1
Input Capture Control Status 2/3
Input Capture Control Status 4/5
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
ICS23
ICS45
Reserved
OCS0
Output Compare Control Status 0
Output Compare Control Status 1
Output Compare Control Status 2
Output Compare Control Status 3
Output Compare Control Status 4
Output Compare Control Status 5
Sound Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000XX00B
0XX00000B
0000XX00B
0XX00000B
0000XX00B
0XX00000B
00000000B
0XXXXXX0B
000XX000B
00000000B
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Sound Generator
Watch Timer
OCS1
OCS2
OCS3
OCS4
OCS5
SGCR
Sound Control
SGCR
Watch Timer Control
WTCR
WTCR
Watch Timer Control
Stepping Motor
Controller 0
62H
63H
64H
65H
66H
67H
PWM Control 0
PWM Control 1
PWM Control 2
PWC0
R/W
R/W
R/W
00000XX0B
Reserved
PWC1
Stepping Motor
Controller 1
00000XX0B
Reserved
PWC2
Stepping Motor
Controller 2
00000XX0B
Reserved
(Continued)
25
MB90390 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
Stepping Motor
Controller 3
68H
69H
6AH
6BH
6CH
PWM Control 3
PWM Control 4
PWM Control 5
PWC3
R/W
00000XX0B
Reserved
PWC4
Stepping Motor
Controller 4
R/W
R/W
00000XX0B
00000XX0B
Reserved
PWC5
Stepping Motor
Controller 5
6DH
6EH
6FH
Reserved
Reserved
ROMM
ROM Mirror
W
ROM Mirror
XXXXXXX1B
00000000B
70H to 8FH Reserved for CAN Interface 0/1. Refer to “■ CAN CONTROLLERS”
90H to 9DH
Reserved
PACSR0
DIRR
Address Match
Detection Function 0
9EH
Address Detection Control Register 0
Delayed Interrupt/Release
Low-power Mode
R/W
R/W
R/W
9FH
Delayed Interrupt XXXXXXX0B
Low Power
00011000B
Controller
A0H
LPMCR
Low Power
11111100B
Controller
A1H
Clock Selector
CKSCR
R/W
A2H to A7H
A8H
Reserved
WDTC
Watchdog Control
R/W
R/W
Watchdog Timer
Time Base Timer
XXXXX111B
1XX00100B
A9H
Time Base Timer Control
TBTC
AAH to ADH
Reserved
Flash Control Status
(Flash devices only. Otherwise reserved)
AEH
FMCS
R/W
Flash Memory
000X0XX0B
AFH
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
Reserved
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
Interrupt Control Register 00
Interrupt Control Register 01
Interrupt Control Register 02
Interrupt Control Register 03
Interrupt Control Register 04
Interrupt Control Register 05
Interrupt Control Register 06
Interrupt Control Register 07
Interrupt Control Register 08
Interrupt Control Register 09
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
(Continued)
Interrupt Controller
26
MB90390 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
BAH
BBH
Interrupt Control Register 10
Interrupt Control Register 11
Interrupt Control Register 12
Interrupt Control Register 13
Interrupt Control Register 14
Interrupt Control Register 15
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
R/W
R/W
R/W
R/W
R/W
R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
BCH
Interrupt Controller
BDH
BEH
BFH
C0H to FFH
3500H
3501H
3502H
3503H
3504H
3505H
3506H
3507H
3508H
3509H
350AH
350BH
350CH
350DH
350EH
350FH
3510H
3511H
3512H
3513H
3514H
3515H
3516H
3517H
3518H
3519H
Reserved
Reload L
PRLL0
PRLH0
PRLL1
PRLH1
PRLL2
PRLH2
PRLL3
PRLH3
PRLL4
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
PRLL8
PRLH8
PRLL9
PRLH9
PRLLA
PRLHA
PRLLB
PRLHB
SMR3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
16-bitProgrammable
Pulse
Reload H
Reload L
Generator 0/1
Reload H
Reload L
16-bitProgrammable
Pulse
Reload H
Reload L
Generator 2/3
Reload H
Reload L
16-bitProgrammable
Pulse
Reload H
Reload L
Generator 4/5
Reload H
Reload L
16-bitProgrammable
Pulse
Reload H
Reload L
Generator 6/7
Reload H
Reload L
16-bitProgrammable
Pulse
Reload H
Reload L
Generator 8/9
Reload H
Reload L
16-bitProgrammable
Pulse
Reload H
Reload L
Generator A/B
Reload H
Serial Mode Register
Serial Control Register
SCR3
UART3
00000000B
(LIN/SCI)
Reception/Transmission Data Regis-
ter
RDR3/
TDR3
351AH
R/W
00000000B
(Continued)
27
MB90390 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
351BH Serial Status Register
SSR3
ECCR3
ESCR3
BGR03
BGR13
IPCP0
R/W
R/W
R/W
R/W
R/W
R
00001000B
000000XXB
00000X00B
351CH Extended Communication Control Reg.
351DH Extended Status/Control Register
351EH Baud Rate Register 0
UART3
(LIN/SCI)
00000000B
351FH Baud Rate Register 1
00000000B
3520H
3521H
3522H
3523H
3524H
3525H
3526H
3527H
3528H
3529H
Input Capture 0
Input Capture 0
Input Capture 1
Input Capture 1
Input Capture 2
Input Capture 2
Input Capture 3
Input Capture 3
Input Capture 4
Input Capture 4
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
IPCP0
R
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
I/O Timer 0
IPCP1
R
IPCP1
R
IPCP2
R
IPCP2
R
IPCP3
R
IPCP3
R
IPCP4
R
IPCP4
R
352AH Input Capture 5
352BH Input Capture 5
352CH Timer Data 0
352DH Timer Data 0
352EH Timer Control 0
352FH Timer Control 0
IPCP5
R
IPCP5
R
TCDT0
TCDT0
TCCS0
TCCS0
OCCP0
OCCP0
OCCP1
OCCP1
OCCP2
OCCP2
OCCP3
OCCP3
OCCP4
OCCP4
OCCP5
OCCP5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000B
00000000B
0XXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
3530H
3531H
3532H
3533H
3534H
3535H
3536H
3537H
3538H
3539H
Output Compare 0
Output Compare 0
Output Compare 1
Output Compare 1
Output Compare 2
Output Compare 2
Output Compare 3
Output Compare 3
Output Compare 4
Output Compare 4
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
353AH Output Compare 5
353BH Output Compare 5
28
MB90390 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
353CH Timer Data 1
353DH Timer Data 1
353EH Timer Control 1
353FH Timer Control 1
TCDT1
TCDT1
TCCS1
TCCS1
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
0XXXXXXXB
I/O Timer 1
TMR0/
TMRLR0
3540H
3541H
3542H
3543H
Timer 0/Reload 0
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit Reload
Timer 0
TMR0/
TMRLR0
Timer 0/Reload 0
Timer 1/Reload 1
Timer 1/Reload 1
TMR1/
TMRLR1
16-bit Reload
Timer 1
TMR1/
TMRLR1
3544H ,
3545H
Reserved
3546H
3547H
3548H
3549H
Frequency Data
Amplitude Data
Decrement Grade
Tone Count
SGFR
SGAR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XX000000B
XX000000B
XXX00000B
XXXXXXXXB
XXXXXXXXB
00000000B
Sound Generator
SGDR
SGTR
354AH Sub-second Data
354BH Sub-second Data
354CH Sub-second Data
354DH Second Data
354EH Minute Data
WTBR
WTBR
WTBR
WTSR
WTMR
WTHR
PWC10
PWC20
PWS10
PWS20
PWC11
PWC21
PWS11
PWS21
PWC12
PWC22
PWS12
PWS22
Watch Timer
354FH Hour Data
3550H
3551H
3552H
3553H
3554H
3555H
3556H
3557H
3558H
3559H
PWM1 Compare 0
PWM2 Compare 0
PWM1 Select 0
Stepping Motor
Controller 0
PWM2 Select 0
X0000000B
XXXXXXXXB
XXXXXXXXB
00000000B
PWM1 Compare 1
PWM2 Compare 1
PWM1 Select 1
Stepping Motor
Controller 1
PWM2 Select 1
X0000000B
XXXXXXXXB
XXXXXXXXB
00000000B
PWM1 Compare 2
PWM2 Compare 2
Stepping Motor
Controller 2
355AH PWM1 Select 2
355BH PWM2 Select 2
X0000000B
(Continued)
29
MB90390 Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
355CH PWM1 Compare 3
355DH PWM2 Compare 3
355EH PWM1 Select 3
355FH PWM2 Select 3
PWC13
PWC23
PWS13
PWS23
PWC14
PWC24
PWS14
PWS24
PWC15
PWC25
PWS15
PWS25
OCS6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
00000000B
Stepping Motor
Controller 3
X0000000B
XXXXXXXXB
XXXXXXXXB
00000000B
3560H
3561H
3562H
3563H
3564H
3565H
3566H
3567H
3568H
3569H
PWM1 Compare 4
PWM2 Compare 4
PWM1 Select 4
Stepping Motor
Controller 4
PWM2 Select 4
X0000000B
XXXXXXXXB
XXXXXXXXB
00000000B
PWM1 Compare 5
PWM2 Compare 5
PWM1 Select 5
Stepping Motor
Controller 5
PWM2 Select 5
X0000000B
0000XX00B
XXX00000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXX0B
XXXX0000B
Output Compare Control Status 6
Output Compare Control Status 7
OCS7
356AH Output Compare 6
356BH Output Compare 6
356CH Output Compare 7
356DH Output Compare 7
356EH CAN Direct Mode Register
356FH CAN RX/TX redirect register
3570H to
OCCP6
OCCP6
OCCP7
OCCP7
CDMR
Output Compare 6/7
CAN Clock Sync
CAN 0/1/2/3
CANSWR
Reserved for CAN Interface 2/3/4. Refer to “■ CAN CONTROLLERS”
359FH
35A0H I2C Bus Status Register
35A1H I2C Bus Control Register
35A2H
IBSR
IBCR
R
00000000B
00000000B
00000000B
XXXXXX00B
11111111B
00XXXX11B
X0000000B
01111111B
00000000B
XXXXXX01B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ITBAL
ITBAH
ITMKL
ITMKH
ISBA
I2C Ten Bit Slave Address Register
35A3H
35A4H
35A5H
I2C Ten Bit Address Mask Register
I2C Interface*4
35A6H I2C Seven Bit Slave Address Register
35A7H I2C Seven Bit Address Mask Register
35A8H I2C Data Register
ISMK
IDAR
35A9H I2C Noise Filter Configuration Register*2
INFCR
Reserved
ICCR
35AAH
35ABH I2C Clock Control Register
R/W
R/W
I2C Interface*4
X0011111B
35ACH to
35BFH
Reserved
CMPRL
35C0H Parameter Register Low Byte
Clock Modulator
11111101B
(Continued)
30
MB90390 Series
Abbrevi-
ation
Address
Register
Access Resource name
Initial value
35C1H Parameter Register High Byte
35C2H Clock Modulator Control Register
CMPRH
CMCR
R/W
R/W
XX000010B
00010000B
Clock Modulator
35C3H to
35C8H
Reserved
35C9H Input Capture Edge 0/1
35CAH Input Capture Edge 2/3*3
35CBH Input Capture Edge 4/5
ICE01
ICE23
ICE45
R/W
R
Input Capture 0/1 XXXXX0XXB
Input Capture 2/3 XXXXXXXXB
Input Capture 4/5 XXXXX0XXB
R/W
35CCH
to 35CEH
Reserved
35CFH PLL and special configuration control resister PSCCR
W
PLL
XXXX0000B
35D0H to
Reserved
35D7H
35D8H Serial Mode Register
35D9H Serial Control Register
SMR2
SCR2
R/W
R/W
00000000B
00000000B
RDR2/
TDR2
35DAH Reception/Transmission Data Register
R/W
00000000B
UART2*1
(LIN/SCI)
35DBH Serial Status Register
SSR2
ECCR2
ESCR2
BGR02
BGR12
R/W
R/W
R/W
R/W
R/W
00001000B
000000XXB
00000X00B
00000000B
00000000B
35DCH Extended Communication Control Register
35DDH Extended Status/Control Register
35DEH Baud Rate Register 0
35DFH Baud Rate Register 1
Detection Address Setting Register 0
(Low-order)
35E0H
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
Reserved
PADR3
PADR3
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Detection Address Setting Register 0
(Middle-order)
35E1H
Detection Address Setting Register 0
(High-order)
35E2H
Address Match
Detection Function 0
Detection Address Setting Register 1
(Low-order)
35E3H
Detection Address Setting Register 1
(Middle-order)
35E4H
Detection Address Setting Register 1
(High-order)
35E5H
35E6H to
35EFH
Detection Address Setting Register 3
(Low-order)
35F0H
R/W
R/W
XXXXXXXXB
Address Match
Detection Function 1
Detection Address Setting Register 3
(Middle-order)
35F1H
XXXXXXXXB
(Continued)
31
MB90390 Series
(Continued)
Abbrevia-
tion
Address
35F2H
35F3H
35F4H
35F5H
35F6H
35F7H
35F8H
Register
Access
R/W
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Detection Address Setting Register 3
(High-order)
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
Reserved
Detection Address Setting Register 4
(Low-order)
R/W
Detection Address Setting Register 4
(Middle-order)
R/W
Detection Address Setting Register 4
(High-order)
Address Match
Detection Function 1
R/W
Detection Address Setting Register 5
(Low-order)
R/W
Detection Address Setting Register 5
(Middle-order)
R/W
Detection Address Setting Register 5
(High-order)
R/W
35F9H to
35FFH
3600H to
37FFH
Reserved for CAN Interface 0. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Interface 2. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Interface 3. Refer to “■ CAN CONTROLLERS”
Reserved for CAN Interface 4. Refer to “■ CAN CONTROLLERS”
3800H to
39FFH
3A00H to
3BFFH
3C00H to
3DFFH
3E00H to
3FFFH
*1 : UART2 (LIN/SCI) is only available in MB90V390HA/HB.
*2 : I2C Noise Filter Configuration Register is only available in the devices MB90V390HA/HB, MB90394HA.
*3 : Input Capture Edge 2/3 register is different in MB90V390HA/HB, the access is “R/W” and initial value is
“XXXXX0XXB”.
*4 : I2C Interface is not available in MB90F394H(A).
32
MB90390 Series
• Explanation on read/write
R/W : Readable and writable
R
: Read only
W : Write only
• Explanation on initial values
0 : Initial value is “0”.
1 : Initial value is “1”.
X : Initial value is undefined.
Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
address results in reading “X”.
33
MB90390 Series
■ CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmitting of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance mask register 0/acceptance mask register 1 for each
message buffer as ID acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers (1)
Address
Abbrevia-
Register
Access Initial Value
tion
CAN0
CAN1
CAN2
CAN3
CAN4
000070H 000080H 003570H 003580H 003590H
000071H 000081H 003571H 003581H 003591H
000072H 000082H 003572H 003582H 003592H
000073H 000083H 003573H 003583H 003593H
000074H 000084H 003574H 003584H 003594H
000075H 000085H 003575H 003585H 003595H
000076H 000086H 003576H 003586H 003596H
000077H 000087H 003577H 003587H 003597H
000078H 000088H 003578H 003588H 003598H
000079H 000089H 003579H 003589H 003599H
00007AH 00008AH 00357AH 00358AH 00359AH
00007BH 00008BH 00357BH 00358BH 00359BH
00007CH 00008CH 00357CH 00358CH 00359CH
00007DH 00008DH 00357DH 00358DH 00359DH
00007EH 00008EH 00357EH 00358EH 00359EH
00007FH 00008FH 00357FH 00358FH 00359FH
Message buffer
valid register
00000000B
R/W
BVALR
00000000B
Transmit request
register
00000000B
R/W
TREQR
TCANR
TCR
00000000B
Transmit cancel
register
00000000B
00000000B
W
Transmit
complete register
00000000B
R/W
00000000B
Receivecomplete
register
00000000B
R/W
RCR
00000000B
Remote request
receiving register
00000000B
R/W
RRTRR
ROVRR
RIER
00000000B
Receive overrun
register
00000000B
R/W
00000000B
Receive interrupt
enable register
00000000B
R/W
00000000B
34
MB90390 Series
List of Control Registers (2)
Address
CAN2
Abbrevia-
Register
CAN4
Access Initial Value
tion
CAN0
CAN1
CAN3
003700H 003900H 003B00H 003D00H 003F00H
003701H 003901H 003B01H 003D01H 003F01H
003702H 003902H 003B02H 003D02H 003F02H
003703H 003903H 003B03H 003D03H 003F03H
003704H 003904H 003B04H 003D04H 003F04H
003705H 003905H 003B05H 003D05H 003F05H
003706H 003906H 003B06H 003D06H 003F06H
003707H 003907H 003B07H 003D07H 003F07H
003708H 003908H 003B08H 003D08H 003F08H
003709H 003909H 003B09H 003D09H 003F09H
00370AH 00390AH 003B0AH 003D0AH 003F0AH
00370BH 00390BH 003B0BH 003D0BH 003F0BH
00370CH 00390CH 003B0CH 003D0CH 003F0CH
Control status
register
00XXX000B
0XXXX0X1B
CSR
LEIR
R/W, R
R/W
R
Last event
indicator register
XXXXXXXXB
000X0000B
Receive/transmit
error counter
00000000B
00000000B
RTEC
BTR
Bit timing
register
X1111111B
11111111B
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
IDE register
IDER
TRTRR
Transmit RTR
register
00000000B
00000000B
Remote frame
receive waiting
register
XXXXXXXXB
XXXXXXXXB
RFWTR
TIER
R/W
R/W
00370DH 00390DH 003B0DH 003D0DH 003F0DH
00370EH 00390EH 003B0EH 003D0EH 003F0EH
00370FH 00390FH 003B0FH 003D0FH 003F0FH
Transmit
interrupt enable
register
00000000B
00000000B
003710H 003910H 003B10H 003D10H 003F10H
003711H 003911H 003B11H 003D11H 003F11H
003712H 003912H 003B12H 003D12H 003F12H
003713H 003913H 003B13H 003D13H 003F13H
003714H 003914H 003B14H 003D14H 003F14H
003715H 003915H 003B15H 003D15H 003F15H
003716H 003916H 003B16H 003D16H 003F16H
003717H 003917H 003B17H 003D17H 003F17H
003718H 003918H 003B18H 003D18H 003F18H
003719H 003919H 003B19H 003D19H 003F19H
00371AH 00391AH 003B1AH 003D1AH 003F1AH
00371BH 00391BH 003B1BH 003D1BH 003F1BH
XXXXXXXXB
XXXXXXXXB
Acceptancemask
select
AMSR
AMR0
AMR1
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
register
XXXXXXXXB
XXXXXXXXB
Acceptancemask
register 0
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptancemask
register 1
XXXXXXXXB
XXXXXXXXB
35
MB90390 Series
List of Message Buffers (ID Registers) (1)
Address
Abbrevia-
Register
Access Initial Value
tion
CAN0
003600H 003800H 003A00H 003C00H 003E00H
to to to to to
CAN1
CAN2
CAN3
CAN4
XXXXXXXXB
General-
purpose RAM
⎯
R/W
R/W
to
00361FH 00381FH 003A1FH 003C1FH 003E1FH
003620H 003820H 003A20H 003C20H 003E20H
003621H 003821H 003A21H 003C21H 003E21H
003622H 003822H 003A22H 003C22H 003E22H
003623H 003823H 003A23H 003C23H 003E23H
003624H 003824H 003A24H 003C24H 003E24H
003625H 003825H 003A25H 003C25H 003E25H
003626H 003826H 003A26H 003C26H 003E26H
003627H 003827H 003A27H 003C27H 003E27H
003628H 003828H 003A28H 003C28H 003E28H
003629H 003829H 003A29H 003C29H 003E29H
00362AH 00382AH 003A2AH 003C2AH 003E2AH
00362BH 00382BH 003A2BH 003C2BH 003E2BH
00362CH 00382CH 003A2CH 003C2CH 003E2CH
00362DH 00382DH 003A2DH 003C2DH 003E2DH
00362EH 00382EH 003A2EH 003C2EH 003E2EH
00362FH 00382FH 003A2FH 003C2FH 003E2FH
003630H 003830H 003A30H 003C30H 003E30H
003631H 003831H 003A31H 003C31H 003E31H
003632H 003832H 003A32H 003C32H 003E32H
003633H 003833H 003A33H 003C33H 003E33H
003634H 003834H 003A34H 003C34H 003E34H
003635H 003835H 003A35H 003C35H 003E35H
003636H 003836H 003A36H 003C36H 003E36H
003637H 003837H 003A37H 003C37H 003E37H
003638H 003838H 003A38H 003C38H 003E38H
003639H 003839H 003A39H 003C39H 003E39H
00363AH 00383AH 003A3AH 003C3AH 003E3AH
00363BH 00383BH 003A3BH 003C3BH 003E3BH
00363CH 00383CH 003A3CH 003C3CH 003E3CH
00363DH 00383DH 003A3DH 003C3DH 003E3DH
00363EH 00383EH 003A3EH 003C3EH 003E3EH
00363FH 00383FH 003A3FH 003C3FH 003E3FH
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
ID register 0
ID register 1
ID register 2
ID register 3
ID register 4
ID register 5
ID register 6
ID register 7
IDR0
IDR1
IDR2
IDR3
IDR4
IDR5
IDR6
IDR7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
36
MB90390 Series
List of Message Buffers (ID Registers) (2)
Address
CAN0 CAN1
Address
Register
Abbrevia-
Access Initial Value
tion
CAN2
CAN3
CAN4
003640H 003840H 003A40H 003C40H 003E40H
003641H 003841H 003A41H 003C41H 003E41H
003642H 003842H 003A42H 003C42H 003E42H
003643H 003843H 003A43H 003C43H 003E43H
003644H 003844H 003A44H 003C44H 003E44H
003645H 003845H 003A45H 003C45H 003E45H
003646H 003846H 003A46H 003C46H 003E46H
003647H 003847H 003A47H 003C47H 003E47H
003648H 003848H 003A48H 003C48H 003E48H
003649H 003849H 003A49H 003C49H 003E49H
00364AH 00384AH 003A4AH 003C4AH 003E4AH
00364BH 00384BH 003A4BH 003C4BH 003E4BH
00364CH 00384CH 003A4CH 003C4CH 003E4CH
00364DH 00384DH 003A4DH 003C4DH 003E4DH
00364EH 00384EH 003A4EH 003C4EH 003E4EH
00364FH 00384FH 003A4FH 003C4FH 003E4FH
003650H 003850H 003A50H 003C50H 003E50H
003651H 003851H 003A51H 003C51H 003E51H
003652H 003852H 003A52H 003C52H 003E52H
003653H 003853H 003A53H 003C53H 003E53H
003654H 003854H 003A54H 003C54H 003E54H
003655H 003855H 003A55H 003C55H 003E55H
003656H 003856H 003A56H 003C56H 003E56H
003657H 003857H 003A57H 003C57H 003E57H
003658H 003858H 003A58H 003C58H 003E58H
003659H 003859H 003A59H 003C59H 003E59H
00365AH 00385AH 003A5AH 003C5AH 003E5AH
00365BH 00385BH 003A5BH 003C5BH 003E5BH
00365CH 00385CH 003A5CH 003C5CH 003E5CH
00365DH 00385DH 003A5DH 003C5DH 003E5DH
00365EH 00385EH 003A5EH 003C5EH 003E5EH
00365FH 00385FH 003A5FH 003C5FH 003E5FH
XXXXXXXXB
XXXXXXXXB
R/W
ID register 8
ID register 9
ID register 10
ID register 11
ID register 12
ID register 13
ID register 14
ID register 15
IDR8
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
IDR9
IDR10
IDR11
IDR12
IDR13
IDR14
IDR7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
XXXXXXXXB
37
MB90390 Series
List of Message Buffers (DLC Registers and Data Registers) (1)
Address
CAN0 CAN1
Address
CAN3
Abbrevia-
tion
Register
Access Initial Value
CAN2
CAN4
003660H 003860H 003A60H 003C60H 003E60H
003661H 003861H 003A61H 003C61H 003E61H
003662H 003862H 003A62H 003C62H 003E62H
003663H 003863H 003A63H 003C63H 003E63H
003664H 003864H 003A64H 003C64H 003E64H
003665H 003865H 003A65H 003C65H 003E65H
003666H 003866H 003A66H 003C66H 003E66H
003667H 003867H 003A67H 003C67H 003E67H
003668H 003868H 003A68H 003C68H 003E68H
003669H 003869H 003A69H 003C69H 003E69H
00366AH 00386AH 003A6AH 003C6AH 003E6AH
00366BH 00386BH 003A6BH 003C6BH 003E6BH
00366CH 00386CH 003A6CH 003C6CH 003E6CH
00366DH 00386DH 003A6DH 003C6DH 003E6DH
00366EH 00386EH 003A6EH 003C6EH 003E6EH
00366FH 00386FH 003A6FH 003C6FH 003E6FH
003670H 003870H 003A70H 003C70H 003E70H
003671H 003871H 003A71H 003C71H 003E71H
003672H 003872H 003A72H 003C72H 003E72H
003673H 003873H 003A73H 003C73H 003E73H
003674H 003874H 003A74H 003C74H 003E74H
003675H 003875H 003A75H 003C75H 003E75H
003676H 003876H 003A76H 003C76H 003E76H
003677H 003877H 003A77H 003C77H 003E77H
003678H 003878H 003A78H 003C78H 003E78H
003679H 003879H 003A79H 003C79H 003E79H
00367AH 00387AH 003A7AH 003C7AH 003E7AH
00367BH 00387BH 003A7BH 003C7BH 003E7BH
00367CH 00387CH 003A7CH 003C7CH 003E7CH
00367DH 00387DH 003A7DH 003C7DH 003E7DH
00367EH 00387EH 003A7EH 003C7EH 003E7EH
00367FH 00387FH 003A7FH 003C7FH 003E7FH
DLC register 0
DLC register 1
DLC register 2
DLC register 3
DLC register 4
DLC register 5
DLC register 6
DLC register 7
DLC register 8
DLC register 9
DLC register 10
DLC register 11
DLC register 12
DLC register 13
DLC register 14
DLC register 15
DLCR0
DLCR1
DLCR2
DLCR3
DLCR4
DLCR5
DLCR6
DLCR7
DLCR8
DLCR9
DLCR10
DLCR11
DLCR12
DLCR13
DLCR14
DLCR15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
38
MB90390 Series
List of Message Buffers (DLC Registers and Data Registers) (2)
Address
CAN0 CAN1
Address
CAN3
Abbrevia-
tion
Register
Access Initial Value
CAN2
CAN4
003680H 003880H 003A80H 003C80H 003E80H
to to to to to
003687H 003887H 003A87H 003C87H 003E87H
XXXXXXXXB
Data register 0
(8 bytes)
DTR0
DTR1
DTR2
DTR3
DTR4
DTR5
DTR6
DTR7
DTR8
DTR9
DTR10
DTR11
DTR12
DTR13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
to
XXXXXXXXB
003688H 003888H 003A88H 003C88H 003E88H
XXXXXXXXB
to
XXXXXXXXB
Data register 1
(8 bytes)
to
to
to
to
to
00368FH 00388FH 003A8FH 003C8FH 003E8FH
003690H 003890H 003A90H 003C90H 003E90H
XXXXXXXXB
to
XXXXXXXXB
Data register 2
(8 bytes)
to
to
to
to
to
003697H 003897H 003A97H 003C97H 003E97H
003698H 003898H 003A98H 003C98H 003E98H
XXXXXXXXB
to
XXXXXXXXB
Data register 3
(8 bytes)
to
to
to
to
to
00369FH 00389FH 003A9FH 003C9FH 003E9FH
0036A0H 0038A0H 003AA0H 003CA0H 003EA0H
XXXXXXXXB
to
XXXXXXXXB
Data register 4
(8 bytes)
to
to
to
to
to
0036A7H 0038A7H 003AA7H 003CA7H 003EA7H
0036A8H 0038A8H 003AA8H 003CA8H 003EA8H
XXXXXXXXB
to
XXXXXXXXB
Data register 5
(8 bytes)
to
to
to
to
to
0036AFH 0038AFH 003AAFH 003CAFH 003EAFH
0036B0H 0038B0H 003AB0H 003CB0H 003EB0H
XXXXXXXXB
to
XXXXXXXXB
Data register 6
(8 bytes)
to
to
to
to
to
0036B7H 0038B7H 003AB7H 003CB7H 003EB7H
0036B8H 0038B8H 003AB8H 003CB8H 003EB8H
XXXXXXXXB
to
XXXXXXXXB
Data register 7
(8 bytes)
to
to
to
to
to
0036BFH 0038BFH 003ABFH 003CBFH 003EBFH
0036C0H 0038C0H 003AC0H 003CC0H 003EC0H
XXXXXXXXB
to
XXXXXXXXB
Data register 8
(8 bytes)
to
to
to
to
to
0036C7H 0038C7H 003AC7H 003CC7H 003EC7H
0036C8H 0038C8H 003AC8H 003CC8H 003EC8H
XXXXXXXXB
to
XXXXXXXXB
Data register 9
(8 bytes)
to
to
to
to
to
0036CFH 0038CFH 003ACFH 003CCFH 003ECFH
0036D0H 0038D0H 003AD0H 003CD0H 003ED0H
XXXXXXXXB
to
XXXXXXXXB
Data register 10
(8 bytes)
to
to
to
to
to
0036D7H 0038D7H 003AD7H 003CD7H 003ED7H
0036D8H 0038D8H 003AD8H 003CD8H 003ED8H
XXXXXXXXB
to
XXXXXXXXB
Data register 11
(8 bytes)
to
to
to
to
to
0036DFH 0038DFH 003ADFH 003CDFH 003EDFH
0036E0H 0038E0H 003AE0H 003CE0H 003EE0H
XXXXXXXXB
to
XXXXXXXXB
Data register 12
(8 bytes)
to
to
to
to
to
0036E7H 0038E7H 003AE7H 003CE7H 003EE7H
0036E8H 0038E8H 003AE8H 003CE8H 003EE8H
XXXXXXXXB
to
XXXXXXXXB
Data register 13
(8 bytes)
to
to
to
to
to
0036EFH 0038EFH 003AEFH 003CEFH 003EEFH
39
MB90390 Series
List of Message Buffers (DLC Registers and Data Registers) (3)
Address
CAN0 CAN1
Address
CAN3
Abbrevia-
tion
Register
Access Initial Value
CAN2
CAN4
0036F0H 0038F0H 003AF0H 003CF0H 003EF0H
XXXXXXXXB
Data register 14
(8 bytes)
to
to
to
to
to
DTR14
DTR15
R/W
R/W
to
0036F7H 0038F7H 003AF7H 003CF7H 003EF7H
XXXXXXXXB
0036F8H 0038F8H 003AF8H 003CF8H 003EF8H
XXXXXXXXB
to
XXXXXXXXB
Data register 15
(8 bytes)
to
to
to
to
to
0036FFH 0038FFH 003AFFH 003CFFH 003EFFH
40
MB90390 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
Number Address
EI2OS
clear
register
Interrupt cause
Number
Address
Reset
N/A
N/A
N/A
N/A
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception
Time Base Timer
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
External Interrupt INT0 to INT7
CAN 0 RX
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
CAN 0 TX/NS
CAN 1 RX
CAN 1 TX/NS
PPG 0/1 / (CAN 2 RX)
PPG 2/3 / (CAN 2 TX/NS)
PPG 4/5 / (CAN 3 RX)
PPG 6/7 / (CAN 3 TX/NS)
PPG 8/9 / (CAN 4 RX)
PPG A/B / (CAN 4 TX/NS)
16-bit Reload Timer 0
16-bit Reload Timer 1
Input Capture 0/1
Output compare 0/1
Input Capture 2/3 / Output Compare 6
Output Compare 2/3
Input Capture 4/5 / Output Compare 7
Output Compare 4/5 /I2C
A/D Converter
I/O Timer 0/1 / Watch Timer
Serial I/O
N/A
N/A
Sound Generator
UART 0 RX
UART 0 TX
UART 1 RX
0000BDH
UART 1 TX
(Continued)
41
MB90390 Series
(Continued)
Interrupt control
register
Interrupt vector
Number Address
EI2OS
clear
Interrupt cause
Number
Address
(UART 2 RX) / UART 3 RX
(UART 2 TX) / UART 3 TX
Flash Memory
#39
#40
#41
#42
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
ICR14
0000BEH
N/A
N/A
ICR15
0000BFH
Delayed interrupt
: The interrupt request flag is cleared by the EI2OS interrupt clear signal.
: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Note : For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags
are cleared by the EI2OS interrupt clear signal.
At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by
hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the
first event. So it is recommended not to use the EI2OS for this interrupt number.
If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor
which should be unique for each interrupt source. For this reason, when one interrupt source uses the
EI2OS, the other interrupt should be disabled.
42
MB90390 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
AVCC
VCC = AVCC*2
Power supply voltage*1
AVRH,
AVRL
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
VSS − 0.3 VSS + 6.0
V
DVCC
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
V
VCC ≥ DVCC
Input voltage*1
*3
*3
Output voltage*1
VO
Maximum Clamp Current
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum output current
ICLAMP
Σ|ICLAMP|
IOL1
−4.0
⎯
+4.0
40
15
4
mA *6
mA *6
⎯
mA Normal outputs*4
mA Normal outputs, average value
mA High current outputs*5
IOLAV1
IOL2
⎯
⎯
40
High current outputs, average
value
“L” level average output current
IOLAV2
⎯
30
mA
“L” level maximum overall output current
“L” level maximum overall output current
ΣIOL1
ΣIOL2
⎯
⎯
100
330
mA Sum of all normal outputs
mA Sum of all high current outputs
Sum of all normal outputs,
average value
“L” level average overall output current
“L” level average overall output current
ΣIOLAV1
ΣIOLAV2
⎯
⎯
50
mA
Sum of all high current outputs,
average value
250
mA
“H” level maximum output current
“H” level average output current
“H” level maximum output current
IOH1
IOHAV1
IOH2
⎯
⎯
⎯
−15
−4
mA Normal outputs*4
mA Normal outputs, average value
mA High current outputs*5
−40
High current outputs, average
value
“H” level average output current
IOHAV2
⎯
−30
mA
“H” level maximum overall output current
“H” level maximum overall output current
ΣIOH1
ΣIOH2
⎯
⎯
−100
−330
mA Sum of all normal outputs
mA Sum of all high current outputs
Sum of all normal outputs,
average value
“H” level average overall output current
“H” level average overall output current
ΣIOHAV1
ΣIOHAV2
⎯
⎯
−50
mA
Sum of all high current outputs,
average value
−250
mA
Power consumption
Operating temperature
Storage temperature
PD
TA
⎯
800
+85
mW MB90F394H(A)/MB90394HA
−40
−55
°C
TSTG
+150
°C
(Continued)
43
MB90390 Series
(Continued)
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating. For ports P70 to P77, P80 to P87 and PA0 to PA7, VI and VO should not exceed DVCC + 0.3 V.
*4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P90 to P97, PB0 to PB7
*5 : Applicable to pins : P70 to P77, P80 to P87, PA0 to PA7
*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67
P70 to P77, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB7
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Pch
Nch
Limiting
resistance
+B input (0 V to 16 V)
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
44
MB90390 Series
2. Recommended Conditions
(VSS = AVSS = DVSS = 0 V)
Remarks
Value
Typ
Parameter
Symbol
Unit
Min
Max
4.5
5.0
5.5
V
V
Under normal operation
Under normal operation, when not
using the A/D converter
4.0
5.0
5.5
VCC,
AVCC
Power supply voltage
Under normal operation, when not
using the A/D converter and not
programming or erasing Flash
3.5
5.0
5.5
V
V
2.0
0.1
−40
⎯
⎯
⎯
5.5
1.0
+85
Retain RAM data in stop mode
Smoothing capacitor
CS
TA
µF MB90F394H(A)/MB90394HA*
°C
Operating temperature
* : Useaceramiccapacitor,oracapacitorofsimilarfrequencycharacteristics.Onthe VCC pin(pin15),useabypass
capacitor that has a larger capacity than that of CS. On the other VCC pin (pin 105) , use a bypass capacitor of
about 0.1 µF.
Refer to the following figure for connection of smoothing capacitor CS.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
45
MB90390 Series
3. DC Characteristics
Sym-
(TA = −40 °C to +85 °C, VCC = 5.0 V 10%, VSS = AVSS = DVSS = 0.0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
Port inputs if CMOS
Hysteresis input levels
are selected (except
SIN and I2C pins of
MB90394HA)
VIHS
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
MB90394HA :
SIN (UART, SIO) and
I2C input pins if CMOS
Hysteresis levels are
selected
VIHS
⎯
⎯
⎯
⎯
0.7 VCC
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
Input “H”
voltage
Port inputs if
AUTOMOTIVE
Hysteresis input levels
are selected
VIHA
RST input pin (CMOS
Hysteresis)
VIHR
VIHM
⎯
⎯
⎯
⎯
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VCC − 0.3
MD input pin
Port inputs if CMOS
Hysteresis input levels
are selected (except
SIN and I2C pins of
MB90394HA)
VILS
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
MB90394HA :
SIN (UART, SIO) and
I2C input pins if CMOS
Hysteresis levels are
selected
VILS
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.3 VCC
0.5 VCC
V
V
Input “L”
voltage
Port inputs if
AUTOMOTIVE
Hysteresis input levels
are selected
VILA
RST input pin (CMOS
Hysteresis)
VILR
VILM
VOH1
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VCC − 0.5
⎯
⎯
⎯
0.2 VCC
VSS + 0.3
⎯
V
V
V
MD input pin
Output “H”
voltage
Normal
outputs
VCC = 4.5 V,
IOH1 = −4.0 mA
(Continued)
46
MB90390 Series
(TA = −40 °C to +85 °C, VCC = 5.0 V 10%, VSS = AVSS = DVSS = 0.0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min
Typ
Max
DVCC = 4.5 V,
TA = − 40 °C
TA = + 25 °C
TA = + 85 °C
IOH2 = −40.0 mA
High
VOH2 current
outputs
Output “H”
voltage
DVCC = 4.5 V,
IOH2 = −30.0 mA
DVCC − 0.5
⎯
⎯
V
V
V
DVCC = 4.5 V,
IOH2 = −30.0 mA
Normal VCC = 4.5 V,
outputs IOL1 = 4.0 mA
Output “L” voltage VOL1
⎯
⎯
⎯
⎯
0.4
0.5
DVCC = 4.5 V,
IOL2 = 40.0 mA
TA = − 40 °C
TA = + 25 °C
TA = + 85 °C
High
DVCC = 4.5 V,
IOL2 = 30.0 mA
Output “L” voltage VOL2 current
outputs
DVCC = 4.5 V,
IOL2 = 30.0 mA
VCC = 5.5 V,
VSS < VI < VCC
Input leak current
IIL
⎯
−5
⎯
+ 5
µA
VCC = 5.0 V,
Internal frequency :
20 MHz,
MB90394HA/
MB90F394H(A)
⎯
50
70
mA
At normal operation.
VCC = 5.0 V,
Internal frequency :
24 MHz,
MB90394HA/
MB90F394H(A)
⎯
⎯
60
65
85
85
mA
At normal operation.
VCC = 5.0 V,
Internal frequency :
20 MHz,
At writing Flash
memory.
ICC
Power supply
current*
mA MB90F394H(A)
mA MB90F394H(A)
VCC
VCC = 5.0 V,
Internal frequency :
20 MHz,
At erasing Flash
memory.
⎯
⎯
70
27
90
36
VCC = 5.0 V,
Internal frequency :
24 MHz,
MB90394HA/
mA
ICCS
MB90F394H(A)
At Sleep mode.
(Continued)
47
MB90390 Series
(Continued)
(TA = −40 °C to +85 °C, VCC = 5.0 V 10%, VSS = AVSS = DVSS = 0.0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min
Typ
Max
VCC = 5.0 V,
Internalfrequency:
2 MHz,
At Main Timebase
timer mode
MB90394HA/
MB90F394H(A)
ICTS
⎯
0.3
0.55
mA
VCC = 5.0 V,
Internalfrequency:
24 MHz,
At PLL Timebase
timer mode,
external frequency
= 4 MHz
Power supply
current*
VCC
MB90394HA/
MB90F394H(A)
ICTSPLL6
⎯
⎯
5
5
7
mA
VCC = 5.0 V,
At Stop mode,
MB90394HA/
MB90F394H(A)
ICCH
30
µA
T
A
= +25°C
Other than C,
AVCC, AVSS,
AVRH, AVRL,
VCC, VSS, DVCC,
DVSS,
P70 to P77,
P80 to P87,
PA0 to PA7
⎯
⎯
⎯
5
15
30
pF
pF
Input
capacitance
CIN
P70 to P77,
P80 to P87,
PA0 to PA7
⎯
15
* : The power supply current is measured with an external clock.
48
MB90390 Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = DVSS = 0.0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
3
Typ
Max
8
When using a crystal oscillator
or a ceramic oscillator
X0, X1
X0
⎯
MHz
Clock frequency
fC
3
⎯
12
333
333
⎯
MHz When using an external clock
When using a crystal oscillator
or a ceramic oscillator
X0, X1
X0
125
83.33
20
⎯
ns
Clock cycle time
tCYL
⎯
ns When using an external clock
Duty ratio is about 30% to
Input clock pulse width
PWH, PWL
tCR, tCF
X0
⎯
ns
70%.
Input clock rise and fall time
X0
⎯
⎯
5
ns When using external clock
Except programming or eras-
ing Flash memory. When us-
ing clock modulation, be sure
that the maximum momentary
frequency Fmax does not ex-
⎯
1.5
⎯
24
MHz
ceed 24 MHz. Refer to the
Clock Modulator chapter of
the Hardware Manual.
Machine clock frequency
fCP
When programming or eras-
ing Flash memory. Be sure
MHz that the maximum momentary
frequency Fmax does not ex-
ceed 20 MHz.
⎯
1.5
⎯
20
Except programming or eras-
ing Flash memory.
⎯
⎯
41.67
50
⎯
⎯
666
666
ns
Machine clock cycle time
tCP
When programming or eras-
ing Flash memory.
ns
• Clock Timing
t
CYL
0.8 VCC
0.2 VCC
X0
P
WH
P
WL
t
CF
tCR
49
MB90390 Series
• Guaranteed PLL operation range
Guaranteed operation range
Guaranteed PLL operation range (CS2=1)
5.5
4.5
Guaranteed A/D converter
operation range
3.5
Guaranteed PLL operation range (CS2=0)
1.5
4
8
20
24
Machine clock fCP (MHz)
Guaranteed operation range of MB90394HA/MB90F394H(A)
• CS2 (bit 0 in PSCCR register) = 0
Guaranteed oscilation frequency range
×4 (CS=011)
×3 (CS=010)
×2 (CS=001)
20
16
12
×1*1 (CS=000)
×1/2 (PLL off)
8
6
4
1.5
3
4
6
8
10
12
External clock fC (MHz)*2
• CS2 (bit 0 in PSCCR register) = 1
Guaranteed oscilation frequency range
×6 (CS=110)
×4 (CS=101)
×2 (CS=100)
24
16
8
6
×1/2 (PLL off)
1.5
3
4
6
8
10
12
External clock fC
(MHz)*2
*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 12 MHz.
*2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHz
External clock frequency and Machine clock frequency
50
MB90390 Series
(2) Reset Standby Input
Parameter Symbol
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = DVSS = 0.0 V)
Value
Pin
Unit
Remarks
Min
Max
16 tCP*1
⎯
ns
ns
µs
Under normal operation
In Stop mode
Reset input
tRSTL
Oscillation time of oscillator*2
RST
⎯
⎯
time
+ 100 µs + 16 tCP*1
100
In Time Base Timer mode
*1 : tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is betweenseveralmsandtotensof ms. InFAR/ ceramicoscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
• Under Normal Operation
t
RSTL
RST
0.2 VCC
tRSTL
0.2 VCC
• In Stop Mode
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
16 tCP
Oscillation time
of oscillator
+100 µs
Oscillation setting time
Instruction execution
Internal reset
51
MB90390 Series
(3) Power On Reset
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = DVSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
0.05
1
Max
30
Power on rise time
Power off time
tR
VCC
VCC
ms
⎯
tOFF
⎯
ms Wait time until power on
tR
2.7 V
V
CC
0.2 V
0.2 V
0.2 V
tOFF
Note : If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you
start up smoothly by restraining voltages when changing the power supply voltage during operation, as
shown in the figure below.
VCC
We recommend a rise of
50 mV/ms maximum.
3 V
Holds RAM data
VSS
52
MB90390 Series
(4) UART0/1 and Serial I/O Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Value
Sym-
Re-
marks
Parameter
bol
Pin
Condition
Unit
Min Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0, SCK1, SCK4
8 tCP
⎯
ns
ns
SCK0, SCK1, SCK4,
SOT0, SOT1, SOT4
SCK ↓ → SOT delay time
−80 +80
Internal clock
operation output
pins are
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
Valid SIN → SCK ↑
tIVSHI
100
60
⎯
⎯
ns
ns
CL = 80 pF + 1 TTL.
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
SCK ↑ → Valid SIN hold time tSHIXI
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0, SCK1, SCK4
SCK0, SCK1, SCK4
4 tCP
4 tCP
⎯
⎯
ns
ns
SCK0, SCK1, SCK4, External clock
SOT0, SOT1, SOT4 operation output
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOVE
tIVSHE
⎯
60
60
150
⎯
ns
ns
ns
pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
SCK0, SCK1, SCK4,
SIN0, SIN1, SIN4
SCK ↑ → Valid SIN hold time tSHIXE
⎯
Notes : • Above rating is the case of CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
VIH
VIL
VIH
SIN
VIL
53
MB90390 Series
• External Shift Clock Mode
tSLSH
tSHSL
VIH
SCK
VIL
tR
t
F
tSLOVE
2.4 V
0.8 V
SOT
SIN
t
SHIXE
tIVSHE
V
IH
IL
V
V
IH
V
IL
54
MB90390 Series
(5) UART2/3 (LIN/SCI)
• Bit setting : ESCR2/3 : SCES = 0, ECCR2/3 : SCDE = 0
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
5 tCP
−50
CP + 80
0
Max
⎯
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
tF
SCK2/3
SCK2/3, SOT2/3
SCK2/3, SIN2/3
SCK2/3, SIN2/3
SCK2/3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output pins
are
+50
⎯
t
C = 80 pF + 1 TTL.
L
SCK ↑ → Valid SIN hold time
Serial clock “L” pulse width
Serial clock “H” pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
⎯
3 tCP − tR
⎯
SCK2/3
t
t
CP + 10
⎯
⎯
External clock
operation output pins
are
SCK2/3, SOT2/3
SCK2/3, SIN2/3
SCK2/3, SIN2/3
SCK2/3
2 tCP + 60
⎯
30
SCK ↑ → Valid SIN hold time
SCK fall time
CP + 30
⎯
⎯
C = 80 pF + 1 TTL.
L
10
SCK rise time
tR
SCK2/3
⎯
10
Notes : • CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
VIH
VIL
VIH
SIN
VIL
55
MB90390 Series
• External Shift Clock Mode
t
SLSH
tSHSL
V
IH
SCK
V
IL
t
R
t
F
t
SLOVE
2.4 V
0.8 V
SOT
SIN
t
SHIXE
t
IVSHE
V
IH
IL
V
V
IH
V
IL
• Bit setting : ESCR2/3 : SCES = 1, ECCR2/3 : SCDE = 0
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
5 tCP
−50
Max
⎯
Serial clock cycle time
SCK ↑ → SOT delay time
Valid SIN → SCK↓
tSCYC
tSHOVI
tIVSLI
tSLIXI
tSHSL
tSLSH
SCK2/3
SCK2/3, SOT2/3
SCK2/3, SIN2/3
SCK2/3, SIN2/3
SCK2/3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Internal clock
operation output
pins are
+50
⎯
tCP+80
0
CL = 80 pF + 1 TTL
SCK ↓ → Valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↑ → SOT delay time
Valid SIN → SCK↓
⎯
3 tCP−tR
tCP+10
⎯
⎯
SCK2/3
⎯
External clock
operation output
pins are
tSHOVE SCK2/3, SOT2/3
2 tCP+60
⎯
tIVSLE
tSLIXE
tF
SCK2/3, SIN2/3
SCK2/3, SIN2/3
SCK2/3
30
SCK↓ →Valid SIN hold time
SCK fall time
tCP+30
⎯
⎯
CL = 80 pF + 1 TTL
10
SCK rise time
tR
SCK2/3
⎯
10
Notes : • CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
56
MB90390 Series
• Internal Shift Clock Mode
tSCYC
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
0.8 V
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
• External Shift Clock Mode
t
SHSL
tSLSH
V
IH
SCK
V
IL
t
SHOVE
t
F
t
R
2.4 V
0.8 V
SOT
SIN
t
SLIXE
t
IVSLE
V
IH
IL
V
IH
V
V
IL
57
MB90390 Series
• Bit setting : ESCR2/3 : SCES = 0, ECCR2/3 : SCDE = 1
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min
Max
Serial clock cycle time
tSCYC SCK2/3
5 tCP
⎯
ns
ns
MB90394HA,
MB90V390HA/HB
−50
tCP − 60
tCP + 80
100 − tCP
0
+50
SCK ↑ → SOT delay
time
SCK2/3,
tSHOVI
SOT2/3
tSCYC/2 +
70 − tCP
MB90F394H(A),
MB90V390H
ns
ns
ns
ns
ns
ns
ns
MB90394HA,
MB90V390HA/HB
⎯
⎯
⎯
⎯
⎯
⎯
SCK2/3,
tIVSLI
Valid SIN → SCK↓
Internal clock
operation output
pins are
SIN2/3
MB90F394H(A),
MB90V390H
MB90394HA,
MB90V390HA/HB
CL = 80 pF + 1 TTL
SCK ↓ → Valid SIN hold
time
SCK2/3,
tSLIXI
SIN2/3
MB90F394H(A),
MB90V390H
tSCYC/2
3 tCP − 70
tCP − 60
MB90394HA,
MB90V390HA/HB
SOT → SCK ↓ delay
time
SCK2/3,
tSOVLI
SOT2/3
MB90F394H(A),
MB90V390H
Notes : • CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
tSOVLI
2.4 V
0.8 V
2.4 V
0.8 V
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
58
MB90390 Series
• Bit setting : ESCR2/3 : SCES = 1, ECCR2/3 : SCDE = 1
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min
Max
Serial clock cycle time
tSCYC SCK2/3
5 tCP
⎯
ns
ns
MB90394HA,
MB90V390HA/HB
−50
tCP − 60
tCP + 80
100 − tCP
0
+50
SCK ↓ → SOT delay
time
SCK2/3,
tSLOVI
SOT2/3
tSCYC/2 +
70 − tCP
MB90F394H(A),
MB90V390H
ns
ns
ns
ns
ns
ns
ns
MB90394HA,
MB90V390HA/HB
⎯
⎯
⎯
⎯
⎯
⎯
SCK2/3,
tIVSHI
Valid SIN → SCK↓
Internal clock
operation output
pins are
SIN2/3
MB90F394H(A),
MB90V390H
MB90394HA,
MB90V390HA/HB
CL = 80 pF + 1 TTL
SCK ↑ → Valid SIN hold
time
SCK2/3,
tSHIXI
SIN2/3
MB90F394H(A),
MB90V390H
tSCYC/2
3tCP − 70
tCP − 60
MB90394HA,
MB90V390HA/HB
SOT → SCK ↑ delay
time
SCK2/3,
tSOVHI
SOT2/3
MB90F394H(A),
MB90V390H
Notes : • CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB90390 series hardware manual”.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
tSCYC
2.4 V
2.4 V
SCK
SOT
SIN
0.8 V
tSLOVI
tSOVHI
2.4 V
0.8 V
2.4 V
0.8 V
tIVSHI
tSHIXI
VIH
VIH
VIL
VIL
59
MB90390 Series
(6) Timer Related Resource Input Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
tTIWH
tTIWL
TIN0, TIN1
IN0 to IN5
Input pulse width
⎯
4 tCP
⎯
ns
Note : tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Timer Input Timing
VIH
VIH
VIL
VIL
tTIWH
tTIWL
(7) Trigger Input Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
200
Max
⎯
INT0 to INT7
ADTG
⎯
⎯
ns
ns
tTRGH
tTRGL
Input pulse width
tCP + 200
⎯
Note : tCP is the machine clock cycle time. Refer to “ (1) Clock timing”.
• Trigger Input Timing
VIH
VIH
VIL
VIL
tTRGH
tTRGL
(8) Slew Rate High Current Outputs
Sym-
(TA = −40 °C to +85 °C, VCC = DVCC = 3.5 V to 5.5 V, VSS = DVSS = 0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
P70 to P77,
P80 to P87,
PA0 to PA7
tR2
tF2
Output Rise/Fall time
⎯
15
⎯
⎯
ns
• Slew Rate Output Timing
VH
VH
VL
V
L
V
H
L
= VOL2 + 0.9 × (VOH2 − VOL2
= VOL2 + 0.1 × (VOH2 − VOL2
)
V
)
t
R2
tF2
60
MB90390 Series
(9) I2C Timing
(TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
Fast-mode*4
Standard-mode
Parameter
Symbol
Condition
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA ↓ → SCL ↓
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
tHIGH
4.7
4.0
⎯
⎯
1.3
0.6
⎯
⎯
µs
µs
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
tHDDAT
tSUDAT
tSUSTO
tBUS
4.7
0
⎯
3.45*2
⎯
0.6
0
⎯
0.9*3
⎯
µs
µs
ns
µs
µs
R = 1.3 kΩ,
C = 50 pF*1
Data hold time
SCL ↓ → SDA ↓ ↑
Data set-up time
SDA ↓ ↑ → SCL ↑
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL ↑ → SDA ↑
⎯
⎯
Bus free time between a STOP and START
condition
⎯
⎯
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tBUS
tSUDAT
tHDSTA
tLOW
SCL
tHIGH
tHDSTA
tHDDAT
tSUSTA
tSUSTO
61
MB90390 Series
5. A/D Converter
(TA
= −40 °C to +85 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0 V)
Value
Parameter
Resolution
Symbol
Pin
Unit Remarks
Min
⎯
Typ
⎯
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
bit
Conversion error
Nonlinearity error
⎯
⎯
3.0
2.5
LSB
LSB
⎯
⎯
Differential nonlinearity
error
⎯
⎯
⎯
⎯
1.9
LSB
Zero reading voltage
VOT
VFST
AN0 to AN14 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB
AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB
Full scale reading
voltage
3.3
⎯
⎯
16500
⎯
µs
Compare time
⎯
⎯
⎯
⎯
3.3 (= 66 tCP)
3.7 (= 88 tCP)
⎯
µs fCP = 20 MHz
µs fCP = 24 MHz
µs
⎯
⎯
1.6
∞
Sampling time
⎯
⎯
−1
1.6 (= 32 tCP)
2 (= 48 tCP)
⎯
µs fCP = 20 MHz
µs fCP = 24 MHz
µA
⎯
⎯
+1
Analog port input current
IAIN
AN0 to AN14
AN0 to AN14
Analog input voltage
range
VAIN
AVRL
⎯
AVRH
V
⎯
⎯
IA
AVRH
AVRL
AVCC
AVRL + 2.7
⎯
⎯
AVCC
V
V
Reference voltage range
Power supply current
0
AVRH − 2.7
⎯
⎯
⎯
⎯
3.5
⎯
7.5
5
mA
IAH
IR
AVCC
µA
µA
µA
*
*
AVRH
AVRH
165
⎯
250
5
Reference voltage
current
IRH
Offset between input
channels
⎯
AN0 to AN14
⎯
⎯
4
LSB
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) .
Terminology
Conversion error
: Absolute maximum conversion deviation with respect to the theoretical conversion
line.
Nonlinearity
: Relative maximum conversion deviation with respect to the theoretical conversion line
connecting to the device unique zero reading voltage and full scale reading voltage.
: Max conversion deviation in any two adjacent reading voltages with respect to the
theoretical LSB conversion step.
Differential nonlinearity
Zero reading voltage
: Input voltage which results in the minimum conversion value.
Full scale reading voltage : Input voltage which results in the maximum conversion value.
Notes : • The accuracy gets worse as AVRH − AVRL becomes smaller.
• tCP is the machine clock cycle time. Refer to “ (1) Clock timing” in “4. AC Characteristics”.
62
MB90390 Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Linear error
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
Differentiallinear : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
error
value.
Total error
: Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVRH − AVSS
1 LSB = (Ideal value)
[V]
1024
N : A/D converter digital output value
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
(Continued)
63
MB90390 Series
(Continued)
Linear error
Differential linear error
Ideal
characteristics
3FFH
Actual conversion
characteristics
3FEH
N + 1
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
3FDH
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004H
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
003H
002H
001H
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVSS
AVRH
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Linear error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linear error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
N : A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
64
MB90390 Series
7. Notes on A/D Converter Section
• About the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. And,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R
C
2.4 kΩ (Max) 36.4 pF (Max)
MB90394HA/MB90F394H/MB90F394HA
Note : The values are reference values.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
MB90394HA
MB90F394H(A)
MB90394HA
MB90F394H(A)
100
90
80
70
60
50
40
30
20
10
0
20
18
16
14
12
10
8
6
4
2
0
4
0
5
10
15
20
25
30
35
0
1
2
3
5
6
7
8
Minimum sampling time [µs]
Minimum sampling time [µs]
• About the error
The accuracy gets worse as |AVRH − AVRL| becomes smaller.
65
MB90390 Series
8. Flash Memory Program/Erase Characteristics
Value
Parameter
Conditions
Unit
Remarks
MIn
Typ
Max
Excludes 00H program-
ming prior to erasure.
Sector erase time
⎯
1
9
15
s
MB90F394H, Excludes
00H programming prior to
erasure.
TA = +25 °C
VCC = 5.0 V
Chip erase time
⎯
⎯
s
Word (16-bit width)
programming time
Except for the over head
time of the system.
⎯
10000
20
16
⎯
⎯
3600
⎯
µs
Programs/Erase cycle
⎯
cycle
year
Flash Data Retention
Time
Average
TA = +85 °C
⎯
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
66
MB90390 Series
■ EXAMPLE CHARACTERISTICS
ICC - VCC (TA = +25 °C)
70
60
50
40
30
20
10
0
fCP = 5 MHz
fCP = 10 MHz
fCP = 20 MHz
fCP = 24 MHz
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VCC [V]
ICCS - VCC (TA = +25 °C, fC = 4 MHz, fCP = 24 MHz)
30
25
20
15
10
5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
VCC [V]
ICTS - VCC (TA = +25 °C)
450
400
350
300
250
200
150
100
50
fC = 5 MHz,
fCP = 2.5 MHz
fC = 4 MHz,
fCP = 2 MHz
0
3
4
5
6
7
VCC [V]
ICCH - TA
16
14
12
10
8
VCC = 5.5 V
VCC = 4.5 V
VCC = 3.5 V
4
6
2
0
−40.00
−20.00
0.00
20.00
40.00
60.00
80.00
TA [°C]
67
MB90390 Series
• I/O characteristics
(VCC−VOH) − IOH
VOL − IOL
TA = +25 °C, VCC = 4.5 V
TA = +25 °C, VCC = 4.5 V
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
IOH (mA)
Automotive VIN − VCC
CMOS VIN − VCC
Except UART-SIN pins and I2C pins of MB90394HA
TA = +25 °C
TA = +25 °C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
VIHA
VILA
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIHS
VILS
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
CMOS VIN − VCC
UART-SIN pins and I2C pins of MB90394HA
TA = +25 °C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VIHS
VILS
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VCC (V)
68
MB90390 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
It is recommended to use MB90F394HA, because
MB90F394H does not support frequency modulation,
clock modulation and CAN message buffer RAM at
the same time.
120-pin Plastic LQFP
(FPT-120P-M21)
MB90F394HPMT
120-pin Plastic LQFP
(FPT-120P-M21)
MB90F394HAPMT
MB90394HAPMT
120-pin Plastic LQFP
(FPT-120P-M21)
For evaluation
299-pin Ceramic PGA
(PGA-299C-A01)
It is recommended to use MB90V390HB, because
MB90V390HA does not support clock modulation
and CAN message buffer RAM at the same time.
MB90V390HACR
MB90V390HBCR
MB90V390HCR
299-pin Ceramic PGA
(PGA-299C-A01)
For evaluation
For evaluation
299-pin Ceramic PGA
(PGA-299C-A01)
It is recommended to use MB90V390HB, because
MB90V390H does not support clock modulation and
CAN message buffer RAM at the same time.
69
MB90390 Series
■ PACKAGE DIMENSION
120-pin plastic LQFP
Lead pitch
0.50 mm
16.0 × 16.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
M ounting height
Weight
Plastic mold
1.70 mm MAX
0.88 g
Code
(Reference)
(FPT-120P-M21)
P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 0.20(.709 .008)SQ
+0.40
16.00 –0.10 .630 –+..000146 SQ
*
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
0~8
˚
"A"
120
31
0.10 0.05
(.004 .002)
(Stand off)
1
30
LEAD No.
0.145 +–00..0035
0.60 0.15
(.024 .006)
0.22 0.05
(.009 .002)
M
0.50(.020)
0.08(.003)
.006 +–..000012
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002 FUJITSU LIMITED F120033S-c-4-4
70
MB90390 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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The contents of this document are subject to change without notice.
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circuit examples, in this document are presented solely for the
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device based on such information, you must assume any
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Please note that Fujitsu will not be liable against you and/or any
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Any semiconductor devices have an inherent chance of failure. You
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If any products described in this document represent goods or
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of those products from Japan.
Edited
Business Promotion Dept.
F0605
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