MB90V378_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13740-1E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90378 Series

MB90F378/V378

DESCRIPTION

The MB90378 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which

require high-speed real-time processing. The instruction set is designed to be optimized for controller applications

which inheriting the AT architecture of F²MC-16LX family and allow a wide range of control tasks to be processed

efficiently at high speed.

A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices

in computer system. Moreover, SMbus compliant I²C*²and A/D converter implements the smart battery control.

With these features, the MB90378 series matches itself as keyboard controller with smart battery control.

While inheriting the AT architecture of the F²MC*¹family, the instruction set for the F²MC-16LX CPU core of the

MB90378 series incorporates additional instructions for high-level languages, supports extended addressing

modes, and contains enhanced multiplication and division instructions as well as a substantial collection of

improved bit manipulation instructions. In addition, the MB90378 series has an on-chip 32-bit accumulator which

enables processing of long-word data.

*1 : F²MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

*2 : Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system provided that the system conforms to the I²C Standard Specification as defined

by Philips.

PACKAGE

144-pin plastic LQFP

(FPT-144P-M12)

MB90378 Series

FEATURES

Clock

• Embedded PLL clock multiplication circuit

• Operating clock (PLL clock) can selected from divided-by-2 of oscillation or one to four times the oscillation

(at oscillation of 4 MHz to 20 MHz)

• Minimum instruction execution time of 50 ns (at oscillation of 5 MHz, four times the PLL clock, operation at

VCC of 3.3 V)

CPU addressing space of 16 Mbytes

Internal 24-bit addressing

Instruction set optimized for controller applications

• Rich data types (bit, byte, word, long word)

• Rich addressing mode (23 types)

• High code efficiency

• Enhanced precision calculation realized by the 32-bit accumulator

Instruction set designed for high level language (C) and multi-task operations

• Adoption of system stack pointer

• Enhanced pointer indirect instructions

• Barrel shift instructions

Program patch function (2 address pointer)

Improved execution speed

4-byte instruction queue

Powerful interrupt function

• Priority level programmable : 8 levels

• 32 factors of stronger interrupt function

Automatic data transmission function independent of CPU operation

• Extended intelligent I/O service function (EI²OS)

• Maximum 16 channels

Low-power consumption (standby) mode

• Sleep mode (mode in which CPU operating clock is stopped)

• Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped)

• Stop mode (mode in which all oscillations are stopped)

• CPU intermittent operation mode

• Watch mode

Dual operation flash

Upper and lower banks of flash memory can be used to execute erase/program and read operation

concurrently (MB90F378)

Package

LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)

Process

CMOS technology

2

MB90378 Series

PRODUCT LINEUP

Part number

MB90F378

MB90V378

Parameter

Classification

Flash type ROM

128 Kbytes (112 Kbytes 16 Kbytes)

Dual operation

ROM size

RAM size

6 Kbytes

15.6 Kbytes

Number of instruction

: 351

Minimum execution time : 50 ns/5 MHz (PLL x 4)

CPU function

I/O port

Addressing mode

Data bit length

Maximum memory space : 16 Mbytes

: 23

: 1, 8, 16 bits

I/O port (Nch)

I/O port (CMOS)

I/O port (CMOS with pull-up control) : 32

: 25

: 68

Total

: 125

Reload timer : 6 channels

Reload mode, single-shot mode or event count mode selectable

16-bit reload timer

8/16-bit PPG timer

16-bit PPG timer

Bit decoder

PPG timer : 2 channels (8-bit mode, 4 channels)

PPG timer : 3 channels

PWM mode or single-shot mode selectable

Bit decoder : 1 channel

Parity generator : 1 channel

Selectable odd/even parity

Parity generator

PS/2 interface : 3 channels

4 selectable sampling clocks

PS/2 interface

LPC interface

LPC bus interface

Universal peripheral Interface : 4 channels

GA20 output control

Data buffer array

: 1 channel

: for UPI ch 0 only

: 80 bytes

Serial IRQ request : 6 channels

LPC clock monitor/control

Serial IRQ controller

UART

With full-duplex double buffer (variable data length)

Clock asynchronized or clock synchronized transmission (with start and stop

bits) can be selectively used

I²C (SMbus compliant) : 1 channel

Support I²C bus of PHILIPS and the SMbus proposed by Intel I²C bus

Selectable packet error check

I²C

Timeout detection function

Multi-address I²C (SMbus compliant) : 1 channel

Support I²C bus of PHILIPS and the SMbus proposed by Intel I²C bus

Selectable packet error check

Multi-address I²C

Timeout detection function

6 addresses support

ALERT function

(Continued)

3

MB90378 Series

(Continued)

Part number

Parameter

MB90F378

MB90V378

Bridge circuit

Three bus connection routes can be switched by I²C/multi-address I²C

8 independent channels

Selectable causes : Rise/fall edge, fall edge, “L” level or “H” level

DTP/external interrupt

8 multiplex channels 2 set

Selectable causes : Rise/fall edge, fall edge, rise edge or “L” level

Extended external interrupt

Key-on wake-up interrupt

8 independent channels

Causes : “L” level

8/10-bit resolution : 12 channels

Conversion time : Less than 4.2 s (20 MHz internal clock)

8/10-bit A/D converter

8-bit D/A converter

LCD controller/driver

8-bit resolution : 2 channels

Up to 9 SEG 4 COM

Selectable LCD output or CMOS I/O port

Low-power consumption

Process

Stop mode/Sleep mode/CPU intermittent operation mode/Watch mode

CMOS

LQFP-144

PGA299

Package

(FPT-144P-M12 : 0.4 mm pitch)

Operating voltage

2.7 V to 3.6 V at 20 MHz*

* : Varies with conditions such as the operating frequency (see “ ELECTRICAL CHARACTERISTICS”).

Assurance for the MB90V378 is given only for operation with a tool at power supply voltage of 2.7 V to 3.6 V,

an operating temperature of 0 C to 25 C, and an operating frequency of 1 MHz to 20 MHz.

PACKAGE AND CORRESPONDING PRODUCTS

Package

FPT-144P-M12

PGA299

: Available

: Not available

MB90F378

MB90V378

X

Note : For more information about each package, see “ PACKAGE DIMENSIONS”.

DIFFERENCES AMONG PRODUCTS

Memory size

In evaluation with an evaluation product, note the difference between the evaluation product and the product

actually used. The following items must be taken into consideration.

• The MB90V378 does not have an internal ROM, however, operations equivalent to chips with an internal ROM

can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the

development tool.

• In the MB90V378, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are

mapped to bank FF only. (This setting can be changed by the development tool configuration.)

• In the MB90F378, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are

mapped to bank FF only.

4

MB90378 Series

PIN ASSIGNMENT

TOP VIEW

P40/PSCK0

P41/PSDA0

P42/PSCK1

P43/PSDA1

P44/PSCK2

P45/PSDA2

P46/CLKRUN

P47/SERIRQ

P50/GA20

P51/LFRAME

P52/LRESET

P53/LCK

P54/LAD0

P55/LAD1

P56/LAD2

P57/LAD3

RST

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

P77/PPG1

P76/UI3

P75/UO3

P74/UCK3

P73/UI2

P72/UO2

P71/UCK2

P70/UI1

P67/UO1

P66/UCK1

P65/INT5

P64/INT4

P63/INT3

P62/INT2

P61/INT1

P60/INT0

PD7/PPG3

VSS

VCC

PF7/V3*

PF6/V2*

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

VCC

VSS

X0A

X1A

LQFP-144

PA0/EEI0

PA1/EEI1

PA2/EEI2

PA3/EEI3

PA4/EEI4

PA5/EEI5

PA6/EEI6

PA7/EEI7

P83/INT6

P84/INT7

P85

PF5/V1*

PF4/COM3*

PF3/TO6/COM2*

PF2/TIN6/COM1*

PF1/TO5/COM0*

PF0/TIN5/SEG8*

PE7/TO4/SEG7

PE6/TIN4/SEG6

PE5/TO3/SEG5

PE4/TIN3/SEG4

PE3/TO2/SEG3

PE2/TIN2/SEG2

PE1/TO1/SEG1

PE0/TIN1/SEG0

P82/ALERT

P86

PB0/EEI8

PB1/EEI9

PB2/EEI10

74

73

(FPT-144P-M12)

* : Heavy current pins

5

MB90378 Series

PIN DESCRIPTION

Pin no.

I/O

Pin status

during

reset

Pin name

Function

circuit

LQFP-144

128,129

20,21

17

X0,X1

X0A,X1A

RST

A

B

Oscillating Main oscillation I/O pins.

Oscillating Sub-clock oscillation I/O pins.

Reset input External reset input pin.

MD0 to

MD2

Input pin for operation mode specification. Connect this pin

directly to Vcc or Vss.

58, 57, 56

C

Mode input

P00 to P07

General-purpose I/O ports.

109 to 116

D

KSI0 to

KSI7

Can be used as key-on wake-up interrupt input ch 0 to 7. Input

is enabled when 1 is set in EICR : EN0 to 7 in standby mode.

117 to 124 P10 to P17

E

General-purpose I/O ports.

125,

P20 to P27

130 to 136

P30, P31

8/16-bit PPG timer output pins.

8-bit x 2 channels mode use : Event output from PG00/PG01

16-bit x 1channel mode use : Event output from PG00

137, 138

139, 140

E

PG00,

PG01

P32, P33

General-purpose I/O ports.

8/16-bit PPG timer output pins.

8-bit x 2 channels mode use : Event output from PG10/PG11.

16-bit x 1channel mode use : Event output from PG10.

PG10,

PG11

141 to 143 P34 to P36

E

General-purpose I/O ports.

Port input

P37

144

General-purpose I/O port.

ADTG

External trigger input pin (ADTG) for the A/D converter.

General-purpose Nch open-drain I/O port.

P40

1

F

Serial clock I/O pin for PS/2 interface ch 0. This function is

selected when PS/2 interface ch 0 is enabled.

PSCK0

P41

General-purpose Nch open-drain I/O port.

2

Serial data I/O pin for PS/2 interface ch 0. This function is

selected when PS/2 interface ch 0 is enabled.

PSDA0

P42

General-purpose Nch open-drain I/O port.

3

Serial clock I/O pin for PS/2 interface ch 1. This function is

selected when PS/2 interface ch 1 is enabled.

PSCK1

P43

General-purpose Nch open-drain I/O port.

4

Serial data I/O pin for PS/2 interface ch 1. This function is

selected when PS/2 interface ch 1 is enabled.

PSDA1

(Continued)

6

MB90378 Series

Pin no.

Pin status

during

reset

I/O

circuit

Pin name

Function

LQFP-144

P44

PSCK2

P45

General-purpose Nch open-drain I/O port.

5

6

F

Serial clock I/O pin for PS/2 interface ch 2. This function is

selected when PS/2 interface ch 2 is enabled.

General-purpose Nch open-drain I/O port.

Serial data I/O pin for PS/2 interface ch 2. This function is

selected when PS/2 interface ch 2 is enabled.

PSDA2

P46

General-purpose Nch open-drain I/O port.

LPC clock status / restart request I/O pin for serial IRQ

controller. This function is selected when serial IRQ and LPC

clock restart request is enabled.

7

G

CLKRUN

P47

SERIRQ

P50

General-purpose I/O port.

8

9

H

J

Serial IRQ data I/O pin for serial IRQ controller. This function is

selected when serial IRQ is enabled.

General-purpose Nch open-drain I/O port.

GA20 output for LPC interface. This function is selected when

GA20 function is enabled.

GA20

P51

General-purpose I/O port.

10

H

Port input

LFRAME input for LPC interface. This function is selected when

LPC interface is enabled.

LFRAME

P52

General-purpose I/O port.

11

Reset input for LPC interface. This function is selected when

LPC interface is enabled.

LRESET

P53

General-purpose I/O port.

12

Clock input for LPC interface. This function is selected when

LPC interface is enabled.

LCK

P54 to P57

General-purpose I/O ports.

13 to 16

LAD0 to

LAD3

Address/Data I/O for LPC interface. This function is selected

when LPC interface is enabled.

P60 to P65

General-purpose I/O ports.

Can be used as DTP/external interrupt request input ch 0 to 5.

Input is enabled when 1 is set in ENIR: EN0 to 5 in standby

mode.

93 to 98

99

I

INT0 to

INT5

P66

General-purpose I/O port.

Serial clock I/O pin for UART ch 1. This function is enabled

when UART ch 1 enables clock output.

UCK1

(Continued)

7

MB90378 Series

Pin no.

I/O

Pin status

during

Pin name

Function

circuit

LQFP-144

reset

P67

General-purpose I/O port.

100

101

I

Serial data output pin for UART ch 1. This function is

enabled when UART ch 1 enables data output.

UO1

P70

General-purpose I/O port.

Serial data input pin for UART ch 1. While UART ch 1 is

operating for input, the input of this pin is used as required and

must not be used for any other input.

UI1

P71

UCK2

P72

General-purpose I/O port.

102

103

I

Serial clock I/O pin for UART ch 2. This function is enabled

when UART ch 2 enables clock output.

General-purpose I/O port.

Serial data output pin for UART ch 2. This function is

enabled when UART ch 2 enables data output.

UO2

P73

General-purpose I/O port.

Serial data input pin for UART ch 2. While UART ch 2 is

operating for input, the input of this pin is used as required and

must not be used for any other input.

104

I

UI2

Port input

P74

UCK3

P75

General-purpose I/O port.

105

106

I

Serial clock I/O pin for UART ch 3. This function is enabled

when UART ch 3 enables clock output.

General-purpose I/O port.

Serial data output pin for UART ch 3. This function is

enabled when UART ch 3 enables data output.

UO3

P76

General-purpose I/O port.

Serial data input pin for UART ch 3. While UART ch 3 is

operating for input, the input of this pin is used as required and

must not be used for any other input.

107

108

I

UI3

P77

General-purpose I/O port.

Output pin for PPG ch 1. This function is enabled when

PPG ch 1 output is enabled.

PPG1

P80

SCL1

P81

General-purpose Nch open-drain I/O port.

Serial clock I/O pin for multi-address I²C.

General-purpose Nch open-drain I/O port.

71

72

T

SDA1

Serial data I/O pin for multi-address I²C.

(Continued)

8

MB90378 Series

Pin no.

Pin status

during

reset

I/O

circuit

Pin name

Function

LQFP-144

P82

General-purpose Nch open-drain I/O port.

73

J

I

ALERT

P83, P84

ALERT output pin for multi-address I²C.

General-purpose I/O ports.

30, 31

Can be used as DTP/external interrupt request input ch6, 7.

Input is enabled when 1 is set in ENIR: EN6, 7 in standby mode.

INT6, INT7

32

33

P85

P86

I

General-purpose I/O port.

P90

General-purpose Nch open-drain I/O port.

Serial clock I/O pin for bridge circuit.

General-purpose Nch open-drain I/O port.

Serial data I/O pin for bridge circuit.

General-purpose Nch open-drain I/O port.

Serial clock I/O pin for bridge circuit.

General-purpose Nch open-drain I/O port.

Serial data I/O pin for bridge circuit.

General-purpose Nch open-drain I/O port.

Serial clock I/O pin for bridge circuit.

General-purpose Nch open-drain I/O port.

Serial data I/O pin for bridge circuit.

General-purpose I/O ports.

65

66

67

68

69

70

T

SCL2

P91

SDA2

P92

SCL3

P93

Port input

SDA3

P94

SCL4

P95

SDA4

PA0 to PA7

External IRQ input pin for Extend External Interrupt request ch0

to 7.

When IRQ detect, prepare to the CPU Interrupt. (Multiplex)

22 to 29

I

EEI0 to

EEI7

PB0 to PB7

General-purpose I/O ports.

External IRQ input pin for Extend External Interrupt request ch8

to 15.

When IRQ detect, prepare to the CPU Interrupt. (Multiplex)

34 to 41

45 to 52

EEI8 to

EEI15

PC0 to PC7

AN0 to AN7

PD0 to PD3

General-purpose I/O ports.

M

A/D converter analog input pin 0 to 7. This function is enabled

when the analog input specification is enabled (ADER1).

A/D input

General-purpose I/O ports.

53,

59 to 61

AN8 to

AN11

A/D converter analog input pin 8 to 11. This function is enabled

when the analog input specification is enabled (ADER2).

(Continued)

9

MB90378 Series

Pin no.

I/O

Pin status

during

Pin name

Function

General-purpose I/O ports.

circuit

LQFP-144

reset

PD4, PD5

62, 63

64, 92

N

H

D/A converter analog output 1, 2. This function is selected when

D/A converted is enabled.

DA1, DA2

PD6, PD7

General-purpose I/O ports.

PPG2,

PPG3

Output pin for PPG ch 2, 3. This function is selected when PPG

ch 2, 3 output is enabled.

PE0

General-purpose I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

74

75

76

77

78

79

80

SEG0

O

TIN1

PE1

External clock input pin for reload timer 1.

General-purpose I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

SEG1

TO1

PE2

Event output pin for reload timer 1.

General-purpose I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

SEG2

Port input

TIN2

PE3

External clock input pin for reload timer 2.

General-purpose I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

SEG3

TO2

PE4

Event output pin for reload timer 2.

General-purpose I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

SEG4

TIN3

PE5

External clock input pin for reload timer 3.

General-purpose I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

SEG5

TO3

PE6

Event output pin for reload timer 3.

General-purpose I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

SEG6

TIN4

External clock input pin for reload timer 4.

(Continued)

10

MB90378 Series

(Continued)

Pin no.

Pin status

during

I/O

circuit

Pin name

Function

LQFP-144

reset

PE7

General-purpose I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

81

SEG7

O

P

TO4

PF0

Event output pin for reload timer 4.

General-purpose Nch Open-drain I/O port.

Segment output pin for LCD controller/driver. This function is

selected when LCD segment output is enabled.

82

83

84

85

SEG8

TIN5

PF1

External clock input pin for reload timer 5.

General-purpose Nch Open-drain I/O port.

COM output pin for LCD controller/driver. This function is select-

ed when LCD COM output is enabled.

COM0

Port input

TO5

PF2

Event output pin for reload timer 5.

General-purpose Nch Open-drain I/O port.

COM output pin for LCD controller/driver. This function is select-

ed when LCD COM output is enabled.

COM1

TIN6

PF3

External clock input pin for reload timer 6.

General-purpose Nch Open-drain I/O port.

COM output pin for LCD controller/driver. This function is select-

ed when LCD COM output is enabled.

COM2

TO6

PF4

Event output pin for reload timer 6.

General-purpose Nch Open-drain I/O port.

86

P

COM output pin for LCD controller/driver. This function is select-

ed when LCD COM output is enabled.

COM3

PF5 to

PF7

General-purpose Nch Open-drain I/O ports.

87 to 89

Q

Power input

Power input pin for LCD controller/driver. This function is select-

ed when external voltage divider is enabled.

V1 to V3

AVCC

AVR

42

43

44

R

S

R

–

Vcc power input pin for analog circuits.

Vref+ input pin for the A/D converter. This voltage must not

exceed Vcc. Vref- is fixed to AVSS.

AVSS

VSS

Vss power input pin for analog circuits.

Power (0 V) input pin.

19,55,91,

127

Source

Power input

18,54,90,

126

VCC

–

Power (3.3 V) input pin.

11

MB90378 Series

I/O CIRCUIT TYPE

Type

Circuit

Remarks

X1/X1A

X0/X0A

Xout

Nch Pch

Main/Sub clock (main/sub clock crystal oscillator)

• At an oscillation feedback resistor of

approximately 1 M

Pch

Nch

A

Standby mode control

• CMOS hysteresis input

• Pull-up resistor approximately 50 k

R

B

C

CMOS hysteresis input

• CMOS hysteresis input

• CMOS output

R

• CMOS hysteresis input

• Selectable pull-up resistor

approximately 50 k

• IOL 4 mA

Pch

Pull-up control

Pch

Pout

D

Nout

Nch

CMOS hysteresis input

Standby mode control

• CMOS output

• CMOS input

R

Pch

Pull-up control

• Selectable pull-up resistor

approximately 50 k

• IOL 4 mA

Pch

Pout

Nout

E

Nch

CMOS input

Standby mode control

• Nch open-drain output

• CMOS hysteresis input

• IOL 4 mA

Nch

• 5 V tolerant

Nout

F

CMOS hysteresis input

Standby mode control

(Continued)

12

MB90378 Series

Type

Circuit

Remarks

• Nch open-drain output

Pch

Nch

• CMOS input

• IOL 4 mA

Nout

G

CMOS input

Standby mode control

• CMOS output

• CMOS input

• IOL 4 mA

Pch

Nch

Pout

Nout

H

CMOS input

Standby mode control

• CMOS output

• CMOS hysteresis input

• IOL 4 mA

Pch

Nch

Pout

Nout

I

CMOS hysteresis input

Standby mode control

• Nch open-drain output

• CMOS input

• IOL 4 mA

Nch

Nout

• 5 V tolerant

J

CMOS input

Standby mode control

• CMOS output

• CMOS input

• A/D analog input

• IOL 4 mA

Pch

Nch

Pout

Nout

M

CMOS input

Standby mode control

Analog input

(Continued)

13

MB90378 Series

Type

Circuit

Remarks

• CMOS output

• CMOS input

• D/A analog output

• IOL 4 mA

Pch

Nch

Pout

Nout

N

CMOS input

Standby mode control

Analog input

• CMOS output

Pch

Nch

• CMOS hysteresis input

• Segment output

• IOL 4 mA

Pout

Nout

O

CMOS hysteresis input

Standby mode control

Segment output

R

• Nch open-drain output

• CMOS hysteresis input

• Segment output

Nch

• IOL 12 mA

Nout

P

CMOS hysteresis input

Standby mode control

Segment output

R

• Nch open-drain output

• CMOS hysteresis input

• LCD driving power supply

• IOL 12 mA

Nch

Nout

Q

CMOS hysteresis input

Standby mode control

LCD driving power supply

(Continued)

14

MB90378 Series

(Continued)

Type

Circuit

Remarks

• Power supply input protection circuit

Pch

Nch

IN

R

S

• A/D converter reference voltage (AVR) input

pin with protection circuit

Analog input enable

Pch

Nch

IN

Analog input enable

• Nch open-drain output

• CMOS input

Nch

• IOL 4 mA

• 5 V tolerant

Nout

Nch

T

CMOS input

Standby mode control

15

MB90378 Series

HANDLING DEVICES

1. Be sure that the maximum rated voltage is not exceeded (latch-up prevention).

A latch-up may occur on a CMOS IC if a voltage higher than VCC or lower than VSS is applied to an input or output

pin other than medium-to-high voltage pins. A latch-up may also occur if a voltage higher than the rating is

applied between VCC pin and VSS pin. A latch-up causes a rapid increase in the power supply current, which can

result in thermal damage to an element. Take utmost care that the maximum rated voltage is not exceeded.

When turning the power on or off to analog circuits, be sure that the analog supply voltages (AVCC, AVR) and

analog input voltage do not exceed the digital supply voltage (VCC).

2. Stabilize the supply voltages

Even within the operation guarantee range of the VCC supply voltage, a malfunction can be caused if the supply

voltage undergoes a rapid change. For voltage stabilization guidelines, the VCC ripple fluctuations (P-P value)

at commercial frequencies (50 Hz to 60 Hz) should be suppressed to "10%" or less of the reference VCC value.

During a momentary change such as when switching a supply voltage, voltage fluctuations should also be

suppressed so that the "transient fluctuation rate" is 0.1 V/ms or less.

3. Power-on

To prevent a malfunction in the built-in voltage drop circuit, secure "50 s (between 0.2 V and 1.8 V)" or more

for the voltage rise time during power-on.

4. Treatment of unused input pins

An unusedinput pin may cause amalfunctionif it isleft open. Every unused input pin should be pulled up or down.

5. Treatment of A/D converter, and D/A converter power pin

When the A/D converter, D/A converter and comparator is not used, connect the pins as follows: AVCC VCC,

AVSS AVR VSS.

6. Notes on external clock

When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at cancel-

lation of sub-clock mode or stop mode. As shown in diagram below, when an external clock is used, connect

only the X0 pin and leave the X1 pin open.

X0

MB90378 series

X1

Open

16

MB90378 Series

7. Power supply pins

When a device has two or more VCC or VSS pins, the pins that should have equal potential are connected within

the device in order to prevent a latch-up or other malfunction. To reduce extraneous emission, to prevent a

malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current

rating, connect all these power supply pins to an external power supply and ground them.

The current source should be connected to the VCC and VSS pins of the device with minimum impedance. It is

recommended that a bypass capacitor of about 0.1 F be connected near the terminals between VCC and VSS.

8. Analog power-on sequence of A/D converter and D/A converter

The power to the A/D converter and D/A converter (AVCC, AVR) and analog inputs (AN0 to AN11) must be turned

on after the power to the digital circuits (VCC) is turned on. When turning off the power, turn off the power to the

digital circuits (VCC) after turning off the power to the A/D converter, D/A converter and analog inputs. When the

power is turned on or off, AVR should not exceed AVCC. Also, when a pin that is used for A/D analog input is also

used as an input port, the input voltage should not exceed AVCC. (The power to the analog circuits and the power

to the digital circuits can be simultaneously turned on or off.)

17

MB90378 Series

BLOCK DIAGRAM

Other pins

CPU

VSS x 4, VCC x4, MD0 to MD2,

X0, X0A

X1, X1A

Clock control

circuit

F²MC-16LX family core

AVCC, AVSS, AVR

Delayed interrupt generator

Reset circuit

RST

(Watchdog timer)

Interrupt controller

Timebase timer

Nch open-drain I/O port 8, 9

P80/SCL1

P81/SDA1

P82/ALERT

P90/SCL2

P91/SDA2

P92/SCL3

P93/SDA3

P94/SCL4

P95/SDA4

I²C bus

(Multi-address)

8

P00/KSI0 to

P07/KSI7

CMOS I/O port 0, 1, 2, 3*

I²C bus

8

P10 to P17

Key-on wake-up

interrupt

8

6

P20 to P27

8

8/16-bit PPG timer

(ch1, ch2)

P30/PG00 to

P33/PG11

P34 to P36

P37/ADTG

6

Bridge circuit

CMOS I/O port A, B, 8

P40/PSCK0

P41/PSDA0

P42/PSCK1

P43/PSDA1

P44/PSCK2

P45/PSDA2

P46/CLKRUN

P47/SERIRQ

Nch open-drain I/O port 4

(P47 is CMOS I/O port)

Extend external

interrupt 1 (8 channels)

8

PA0/EEI0 to

PA7/EEI7

6

2

3ch PS/2 interface

Extend external

interrupt 2 (8 channels)

PB0/EEI8 to

PB7/EEI15

Serial IRQ (6 channels)

LPC Interface

P83/INT6

P84/INT7

2

DTP/external interrupt

(ch6, ch7)

P50/GA20

P51/LFRAME

P52/LRESET

P53/LCK

GA20 control

P85

P86

UPI

P54/LAD0

(ch0, ch1, ch2, ch3)

7

P55/LAD1

12

2

8/10-bit A/D converter

(12 channels)

PC0/AN0 to

PC7/AN7

PD0/AN8 to

PD3/AN11

PD4/DA1

PD5/DA2

P56/LAD2

P57/LAD3

Nch open-drain I/O P50

CMOS I/O P51 to P57

8-bit D/A converter

(2 channels)

6

P60/INT0 to

P65/INT5

P66/UCK1

P67/UO1

P70/UI1

6

3

6

DTP/external interrupt

ch0, 1, 2, 3, 4, 5

2

16-bit PPG

(ch2, ch3)

PD6/PPG2

PD7/PPG3

UART

P71/UCK2

P72/UO2

P73/UI2

(ch1, ch2, ch3)

CMOS I/O port C, D

P74/UCK3

P75/UO3

P76/UI3

16-bit PPG (ch1)

PE0/TIN1/SEG0

PE1/TO1/SEG1

PE2/TIN2/SEG2

PE3/TO2/SEG3

PE4/TIN3/SEG4

PE5/TO3/SEG5

PE6/TIN4/SEG6

PE7/TO4/SEG7

PF0/SEG8/TIN5*

PF1/COM0/TO5*

PF2/COM1/TIN6*

CMOS I/O port E

Nch open-drain I/O port F

P77/PPG1

CMOS I/O port 6, 7

6

16-bit reload timer

(ch1, ch2, ch3, ch4, ch5, ch6)

RAM 6KB

FLASH 128 KB

16

LCD controller/driver

(9SEG x 4COM)

Mirroring

PF3/COM2/TO6*

PF4/COM3*

PF5/V1* to

Flash security

PF7/V3*

* : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With resistors that can be used as input pull-up resistors.

PF0 to PF7 : High current pins

18

MB90378 Series

MEMORY MAP

Single-chip mode

(with ROM mirroring function)

FFFFFFH

ROM area

Address #1

FC0000H

010000H

ROM area

(FF bank image)

Address #2

004000H

Peripheral area

RAM

003F80H

Address #3

Register

area

000100H

0000F8H

000000H

: Internal access memory

: Access not allowed

Peripheral area

Model

Address #1

FE0000H

Address #2

Address #3

001900H

MB90F378

MB90V378

004000H

004000H*

FE0000H*

003F80H

* : The MB90V378 does not contain ROM. Assume that the development tool uses these area for its ROM decode

areas.

Notes : If single-chip mode (without ROM mirroring function) is selected, see Chapter 32, "ROM Mirroring

Function Selection Module" of the MB90378 series H/W manual.

ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C

compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the table in ROM

can be referenced without the "far" specification. For example, when 00C000H is accessed, the contents

of ROM at FFC000H are actually accessed. The ROM area in the FF bank exceeds 48 Kbytes, and all

areas cannot be seen as images in the 00 bank. Because ROM data from FF4000H to FFFFFFH is seen

as an image at 004000H to 00FFFFH, the ROM data table should be stored in the area from FF4000H to

FFFFFFH.

19

MB90378 Series

F²MC-16LX CPU PROGRAMMING MODEL

• Dedicated registers

AH

AL

Accumulator (A)

USP

User Stack Pointer (USP)

SSP

PS

System Stack Pointer (SSP)

Processor Status (PS)

Program Counter (PC)

PC

DPR

Direct Page Register (DPR)

PCB

DTB

USB

SSB

ADB

Program Bank Register(PCB)

Data Bank Register (DTB)

User Stack Bank Register (USB)

System Stack Bank Register (SSB)

Additional Data Bank Register (ADB)

8-bit

16-bit

32-bit

• General-purpose registers

CPU

Dedicated register

RAM

General-purpose

register

Accumulator

User stack pointer

System stack pointer

Processor status

Program counter

Direct page register

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

20

MB90378 Series

• Processor status (PS)

15

13 12

8 7

0

ILM

000

RP

CCR

PS

Default value

00000

-01XXXXX

7

6

I

5

4

T

3

2

1

0

: CCR

-

S

N

Z

V

C

-

0

1

X

: RP

B4 B3 B2 B1 B0

Default value

0

: ILM

ILM2

0

ILM1

ILM0

0

- : Not used

0

X : Undefined

21

MB90378 Series

I/O MAP

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

000000H

000001H

000002H

000003H

000004H

000005H

000006H

000007H

000008H

000009H

00000AH

00000BH

00000CH

00000DH

00000EH

00000FH

000010H

000011H

000012H

000013H

000014H

000015H

000016H

000017H

000018H

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

PDRB

PDRC

PDRD

PDRE

PDRF

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

PGDR

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

Port B data register

Port C data register

Port D data register

Port E data register

Port F data register

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Parity generator data register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

Port D

Port E

Port F

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

XXXXXXXXB

X1111111B

XXXXXXX1B

XXXXXXXXB

-XXXX111B

--111111B

XXXXXXXXB

11111111B

00000000B

0-------B

0000000-B

00000000B

XXXXXXXXB

Parity

generator

Parity generator control status

register

000019H

PGCSR

R/W

X------0B

00001AH

00001BH

00001CH

00001DH

00001EH

00001FH

DDRA

DDRB

DDRC

DDRD

DDRE

DDR8

Port A direction register

Port B direction register

Port C direction register

Port D direction register

Port E direction register

Port 8 direction register

R/W

Port A

Port B

Port C

Port D

Port E

Port 8

00000000B

-0000---B

(Continued)

22

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

000020H

000021H

SMR1

SCR1

Serial mode register 1

Serial control register 1

R/W

00000-00B

00000100B

SIDR1/

SODR1

Input data register 1/

Output data register 1

000022H

R/W

UART1

XXXXXXXXB

000023H

000024H

SSR1

Serial status register 1

R/W

00001000B

----1000B

M2CR1

Mode 2 control register 1

Communication

prescaler 1

000025H

CDCR1

Clock division control register 1

R/W

00--0000B

000026H

000027H

000028H

000029H

00002AH

00002BH

00002CH

00002DH

00002EH

00002FH

000030H

000031H

000032H

000033H

ENIR

EIRR

Interrupt/DTP enable register

Interrupt/DTP cause register

R/W

R

R/W

R

00000000B

XXXXXXXXB

00000000B

11111111B

----1111B

DTP/external

interrupt

ELVR

Request level setting register

ADER1

ADER2

BRSR

Analog input enable register 1

Analog input enable register 2

Bridge circuit selection register

A/D control register

Port C, A/D

Port D, A/D

Bridge circuit

--000000B

ADC0

00000000B

XXXXXXXXB

00000-XXB

00--------B

ADCR0

ADCR1

ADCS0

ADCS1

SICRL

SICRH

A/D data register

8/10-bit

A/D converter

R/W

A/D control status register

00000000B

Serial interrupt request register

Serial interrupt control register

Serial interrupt frame number

register 1

000034H

000035H

000036H

000037H

SIFR1

SIFR2

SIFR3

SIFR4

R/W

--000000B

Serial interrupt frame number

register 2

Serial IRQ

Serial interrupt frame number

register 3

Serial interrupt frame number

register 4

000038H

000039H

00003AH

00003BH

00003CH

00003DH

00003EH

00003FH

PDCRL1

PDCRH1

PCSRL1

PCSRH1

PDUTL1

PDUTH1

PCNTL1

PCNTH1

R

11111111B

XXXXXXXXB

--000000B

PPG1 down counter register

PPG1 period setting register

PPG1 duty setting register

PPG1 control status register

W

16-bit PPG timer

(ch1)

W

R/W

00000000B

(Continued)

23

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

000040H

000041H

000042H

000043H

000044H

000045H

000046H

000047H

000048H

000049H

00004AH

00004BH

00004CH

00004DH

00004EH

00004FH

000050H

000051H

000052H

000053H

000054H

000055H

000056H

000057H

000058H

000059H

00005AH

00005BH

00005CH

00005D_H

PDCRL2

PDCRH2

PCSRL2

PCSRH2

PDUTL2

PDUTH2

PCNTL2

PCNTH2

PDCRL3

PDCRH3

PCSRL3

PCSRH3

PDUTL3

PDUTH3

PCNTL3

PCNTH3

PSCR0

PSSR0

PSCR1

PSSR1

PSCR2

PSSR2

PSDR0

PSDR1

PSDR2

PSMR

R

11111111B

XXXXXXXXB

PPG2 down counter register

W

PPG2 period setting register

PPG2 duty setting register

PPG2 control status register

PPG3 down counter register

PPG3 period setting register

PPG3 duty setting register

PPG3 control status register

XXXXXXXXB

--000000B

16-bit PPG timer

(ch2)

R/W

R

00000000B

11111111B

XXXXXXXXB

--000000B

R

W

16-bit PPG timer

(ch3)

W

R/W

00000000B

0--00000B

PS/2 interface control register 0

PS/2 interface status register 0

PS/2 interface control register 1

PS/2 interface status register 1

PS/2 interface control register 2

PS/2 interface status register 2

PS/2 interface data register 0

PS/2 interface data register 1

PS/2 interface data register 2

PS/2 interface mode register

D/A converter data register 0

D/A converter data register 1

D/A control register 0

00000000B

0--00000B

00000000B

0--00000B

3-channel PS/2

interface

00000000B

----0000B

DAT0

XXXXXXXXB

-------0B

DAT1

8-bit

D/A converter

DACR0

DACR1

D/A control register 1

-------0_B

(Continued)

24

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

00005EH

00005FH

000060H

000061H

000062H

000063H

000064H

000065H

UPAL1

UPAH1

UPAL2

UPAH2

UPAL3

UPAH3

UPCL

UPI1 address register (lower)

UPI1 address register (upper)

UPI2 address register (lower)

UPI2 address register (upper)

UPI3 address register (lower)

UPI3 address register (upper)

UPI control register (lower)

UPI control register (upper)

R/W

XXXXXXXXB

00000000B

UPCH

-000-000B

UPDI0/

UPDO0

UPI0 data input register/

data output register

000066H

000067H

000068H

000069H

00006AH

00006BH

00006CH

R/W

XXXXXXXXB

00000000B

LPC interface

UPS0

UPI0 status register

UPDI1/

UPDO1

UPI1 data input register/

data output register

XXXXXXXXB

00000000B

UPS1

UPI1 status register

UPDI2/

UPDO2

UPI2 data input register/

data output register

XXXXXXXXB

00000000B

UPS2

UPI2 status register

UPDI3/

UPDO3

UPI3 data input register/

data output register

XXXXXXXXB

00006DH

00006EH

UPS3

LCR

UPI3 status register

LPC control register

R/W

00000000B

-----000B

ROM mirroring function

selection register

ROM mirroring

function

00006FH

000070H

000071H

ROMM

W

-------1B

00000000B

----0000B

Timer control status register

CH1 (lower)

TMCSRL1

TMCSRH1

R/W

16-bit

reload timer

(ch1)

Timer control status register

CH1 (upper)

000072H

000073H

R/W

XXXXXXXXB

TMR1/

TMRD1

16-bit timer/reload register CH1

Timer control status register

CH2 (lower)

000074H

000075H

TMCSRL2

TMCSRH2

R/W

00000000B

----0000B

16-bit

reload timer

(ch2)

Timer control status register

CH2 (upper)

000076H

000077H

R/W

XXXXXXXXB

(Continued)

TMR2/

TMRD2

16-bit timer/reload register CH2

25

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

Timer control status register

CH3 (lower)

000078H

000079H

TMCSRL3

TMCSRH3

R/W

00000000B

16-bit

Timer control status register

CH3 (upper)

----0000B

reload timer

(ch3)

00007AH

00007BH

R/W

XXXXXXXXB

TMR3/

TMRD3

16-bit timer/reload register CH3

Timer control status register

CH4 (lower)

00007CH

00007DH

TMCSRL4

TMCSRH4

R/W

00000000B

----0000B

16-bit

reload timer

(ch4)

Timer control status register

CH4 (upper)

00007EH

00007FH

000080H

000081H

000082H

000083H

000084H

000085H

000086H

000087H

000088H

000089H

00008AH

00008BH

R/W

R

XXXXXXXXB

----0000B

TMR4/

TMRD4

16-bit timer/reload register CH4

IBCRL

IBCRH

IBSRL

IBSRH

IDAR

IADR

ICCR

ITCR

I²C bus control register (lower)

I²C bus control register (upper)

I²C bus status register (lower)

I²C bus status register (upper)

I²C data register

R/W

R

00000000B

--000000B

R/W

XXXXXXXXB

-XXXXXXXB

0-000000B

-0-00000B

I²C address register

I²C

I²C clock control register

I²C timeout control register

I²C timeout clock register

I²C timeout data register

I²C slave timeout register

I²C master timeout register

ITOC

ITOD

ISTO

00000000B

IMTO

Port 0 pull-up resistor setting

register

00008CH

00008DH

00008EH

00008FH

RDR0

RDR1

RDR2

RDR3

R/W

Port 0

Port 1

Port 2

Port 3

00000000B

Port 1 pull-up resistor setting

register

Port 2 pull-up resistor setting

register

Port 3 pull-up resistor setting

register

000090H

to

Prohibited area

00009DH

Program address detect control

status register

Address match

detection

00009EH

00009FH

PACSR

DIRR

R/W

00000000B

Delayed interrupt cause/

clear register

Delayed

interrupt

-------0B

(Continued)

26

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

Low-power consumption mode

register

Low-power

consumption

control register

0000A0H

0000A1H

LPMCR

CKSCR

R/W

00011000B

11111100B

Clock selection register

0000A2H,

0000A3H

Prohibited area

R/W

Clock modulation control

register

Clock

modulation

0000A4H

CKMC

R/W

-------0B

0000A5H

to

0000A7H

Prohibited area

R/W

0000A8H

0000A9H

0000AAH

0000ABH

WDTC

TBTC

WTC

Watchdog control register

R/W

Watchdog timer X-XXX111B

Timebase timer control register

Watch timer control register

R/W

Timebase timer

Watch timer

1--00100B

10001000B

Prohibited area

Wake-up interrupt control

register

0000ACH

0000ADH

0000AEH

EICR

EIFR

R/W

00000000B

-------0B

Key-on wake-up

interrupt

Wake-up interrupt flag register

R/W

Flash memory control status

register

Flash memory

interface circuit

FMCS

000X0000B

0000AFH

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

Prohibited area

R/W

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Interrupt control register 10

Interrupt control register 11

Interrupt control register 12

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

R/W

00000111B

(Continued)

R/W

Interrupt

controller

R/W

27

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

0000C0H

0000C1H

0000C2H

0000C3H

0000C4H

0000C5H

0000C6H

0000C7H

0000C8H

0000C9H

0000CAH

0000CBH

0000CCH

0000CDH

0000CEH

0000CFH

0000D0H

0000D1H

0000D2H

0000D3H

MBCRL

MBCRH

MBSRL

MBSRH

MDAR

MALR

MI²C bus control register (lower) R/W

MI²C bus control register (upper) R/W

R/W

R

----0000B

00000000B

--000000B

MI²C bus status register (lower)

MI²C bus status register (upper) R/W

R

R/W

MI²C data register

R/W

XXXXXXXXB

----0000B

MI²C alert register

MADR1

MADR2

MADR3

MADR4

MADR5

MADR6

MCCR

MTCR

MI²C address register 1

MI²C address register 2

MI²C address register 3

MI²C address register 4

MI²C address register 5

MI²C address register 6

MI²C clock control register

MI²C timeout control register

MI²C timeout clock register

MI²C timeout data register

MI²C slave timeout register

MI²C master timeout register

Serial mode register 2

Serial control register 2

-XXXXXXXB

Multi-address

I²C

-XXXXXXXB

0-000000B

-0-00000B

MTOC

MTOD

MSTO

00000000B

00000-00B

00000100B

MMTO

SMR2

SCR2

SIDR2/

SODR2

Input data register 2/

output data register 2

0000D4H

R/W

UART2

XXXXXXXXB

0000D5H

0000D6H

SSR2

Status register 2

R/W

00001000B

----1000B

M2CR2

Mode 2 control register 2

Communication

prescaler 2

0000D7H

CDCR2

Clock division control register 2

R/W

00--0000B

0000D8H

0000D9H

0000DAH

0000DBH

0000DCH

0000DDH

0000DEH

0000DFH

0000E0H

EENR1

EERR1

Interrupt enable register

Interrupt cause register

R/W

00000000B

XXXXXXXXB

00000000B

XXXXXXXXB

00000000B

Extend External

Interrupt 1

EELR1

Request level setting register

EENR2

EERR2

Interrupt enable register

Interrupt cause register

Extend External

Interrupt 2

EELR2

PDL3

Request level setting register

Port 3 data latch register

R/W Port 3 data latch 00000000B

(Continued)

28

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Bit data register

Resource name Initial value

0000E1H

0000E2H

0000E3H

0000E4H

0000E5H

BDR

BRRL

BRRH

SMR3

SCR3

R/W

R

R/W

R

----XXXXB

XXXXXXXXB

00000-00B

Bit result register (lower)

Bit result register (upper)

Serial mode register 3

Serial control register 3

Bit decoder

UART3

R

R/W

00000100B

SIDR3 /

SODR3

Input data register 3/

output data register 3

0000E6H

R/W

XXXXXXXXB

0000E7H

0000E8H

SSR3

Status register 3

R/W

00001000B

----1000B

M2CR3

Mode 2 control register 3

Communication

prescaler 3

0000E9H

0000EAH

0000EBH

CDCR3

TMCSRL5

TMCSRH5

Clock division control register 3

R/W

00--0000B

00000000B

----0000B

Timer control status register

CH5 (lower)

16-bit

reload timer

(ch5)

Timer control status register

CH5 (upper)

0000ECH

0000EDH

0000EEH

0000EFH

R/W

XXXXXXXXB

00010000B

00000000B

TMR5/

TMRD5

16-bit timer/reload register CH5

LCRL

LCRH

LCD control register 0

LCD control register 1

R/W

LCD

0000F0H

to

controller/driver

VRAM

LCD display RAM

R/W

-

XXXXXXXXB

0000F4H

0000F5H

to

0000F7H

Prohibited area

External area

0000F8H

to

0000FFH

000100H

to

Prohibited area (RAM area)

0018FFH

Program address detection

register 0

001FF0H

001FF1H

001FF2H

R/W

XXXXXXXXB

Program address detection

register 1

Address match

detection

PADR0

Program address detection

register 2

XXXXXXXXB

(Continued)

29

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

Program address detection

register 3

001FF3H

001FF4H

001FF5H

R/W

XXXXXXXXB

Address match

Program address detection

register 4

PADR1

XXXXXXXXB

detection

Program address detection

register 5

XXXXXXXXB

001FF6H

to

003F7FH

Prohibited area

R/W

003F80H

003F81H

003F82H

003F83H

003F84H

003F85H

003F86H

003F87H

003F88H

003F89H

003F8AH

003F8BH

003F8CH

003F8DH

003F8EH

003F8FH

003F90H

003F91H

003F92H

003F93H

003F94H

003F95H

003F96H

003F97H

003F98H

003F99H

003F9AH

003F9BH

UDRL10

UDRH10

UDRL11

UDRH11

UDRL12

UDRH12

UDRL13

UDRH13

UDRL14

UDRH14

UDRL15

UDRH15

UDRL16

UDRH16

UDRL17

UDRH17

UDRL18

UDRH18

UDRL19

UDRH19

UDRL1A

UDRH1A

UDRL1B

UDRH1B

UDRL1C

UDRH1C

UDRL1D

UDRH1D

UP data register 10 (lower)

R/W

XXXXXXXXB

UP data register 10 (upper)

UP data register 11 (lower)

UP data register 11 (upper)

UP data register 12 (lower)

UP data register 12 (upper)

UP data register 13 (lower)

UP data register 13 (upper)

UP data register 14 (lower)

UP data register 14 (upper)

UP data register 15 (lower)

UP data register 15 (upper)

UP data register 16 (lower)

UP data register 16 (upper)

UP data register 17 (lower)

UP data register 17 (upper)

UP data register 18 (lower)

UP data register 18 (upper)

UP data register 19 (lower)

UP data register 19 (upper)

UP data register 1A (lower)

UP data register 1A (upper)

UP data register 1B (lower)

UP data register 1B (upper)

UP data register 1C (lower)

UP data register 1C (upper)

UP data register 1D (lower)

UP data register 1D (upper)

R/W

XXXXXXXXB

(Continued)

LPC data buffer

array-Extend

30

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

003F9CH

003F9DH

003F9EH

003F9FH

UDRL1E

UDRH1E

UDRL1F

UDRH1F

UP data register 1E (lower)

UP data register 1E (upper)

UP data register 1F (lower)

UP data register 1F (upper)

R/W

XXXXXXXXB

LPC data buffer

array-Extend

LPC data buffer

array

003FA0H

003FA1H

003FA2H

DBACLR

Data buffer array clear register

R/W

-----000B

Prohibited area

FLASH programming control

register 0

FWR0

R/W

00000000B

Dual operating

FLASH

FLASH programming control

register 1

003FA3H

003FA4H

FWR1

SSR0

R/W

00000000B

Sector switching register

00XXXXX0B

003FA5H

to

Prohibited area

003FAEH

003FAFH

003FB0H

003FB1H

003FB2H

003FB3H

003FB4H

003FB5H

003FB6H

PCKCR

PRLL2

PRLH2

PRLL3

PRLH3

PPGC2

PPGC3

PCS23

PLL clock control register

W

PLL

XXXX0000B

XXXXXXXXB

00000001B

PPG reload register (lower)

PPG reload register (upper)

PPG reload register (lower)

PPG reload register (upper)

PPG control register ch2

PPG control register ch3

PPG clock control register

R/W

8/16-bit

PPG timer 2

00000001B

000000XXB

003FB7H

to

Prohibited area

003FBFH

003FC0H

003FC1H

003FC2H

003FC3H

003FC4H

003FC5H

003FC6H

003FC7H

003FC8H

003FC9H

UDRL0

UDRH0

UDRL1

UDRH1

UDRL2

UDRH2

UDRL3

UDRH3

UDRL4

UDRH4

UP data register 0 (lower)

UP data register 0 (upper)

UP data register 1 (lower)

UP data register 1 (upper)

UP data register 2 (lower)

UP data register 2 (upper)

UP data register 3 (lower)

UP data register 3 (upper)

UP data register 4 (lower)

UP data register 4 (upper)

R/W

XXXXXXXXB

(Continued)

LPC data buffer

array

31

MB90378 Series

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

003FCAH

003FCBH

003FCCH

003FCDH

003FCEH

003FCFH

003FD0H

003FD1H

003FD2H

003FD3H

003FD4H

003FD5H

003FD6H

003FD7H

003FD8H

003FD9H

003FDAH

003FDBH

003FDCH

003FDDH

003FDEH

003FDFH

003FE0H

003FE1H

003FE2H

003FE3H

003FE4H

003FE5H

003FE6H

003FE7H

003FE8H

003FE9H

003FEAH

003FEBH

003FECH

003FEDH

UDRL5

UDRH5

UDRL6

UDRH6

UDRL7

UDRH7

UDRL8

UDRH8

UDRL9

UDRH9

UDRLA

UDRHA

UDRLB

UDRHB

UDRLC

UDRHC

UDRLD

UDRHD

UDRLE

UDRHE

UDRLF

UDRHF

DNDL0

DNDH0

DNDL1

DNDH1

DNDL2

DNDH2

DNDL3

DNDH3

DNDL4

DNDH4

DNDL5

DNDH5

DNDL6

DNDH6

UP data register 5 (lower)

UP data register 5 (upper)

UP data register 6 (lower)

UP data register 6 (upper)

UP data register 7 (lower)

UP data register 7 (upper)

UP data register 8 (lower)

UP data register 8 (upper)

UP data register 9 (lower)

UP data register 9 (upper)

UP data register A (lower)

UP data register A (upper)

UP data register B (lower)

UP data register B (upper)

UP data register C (lower)

UP data register C (upper)

UP data register D (lower)

UP data register D (upper)

UP data register E (lower)

UP data register E (upper)

UP data register F (lower)

UP data register F (upper)

DOWN data register 0 (lower)

DOWN data register 0 (upper)

DOWN data register 1 (lower)

DOWN data register 1 (upper)

DOWN data register 2 (lower)

DOWN data register 2 (upper)

DOWN data register 3 (lower)

DOWN data register 3 (upper)

DOWN data register 4 (lower)

DOWN data register 4 (upper)

DOWN data register 5 (lower)

DOWN data register 5 (upper)

DOWN data register 6 (lower)

DOWN data register 6 (upper)

R/W

R

R/W

R

XXXXXXXXB

(Continued)

LPC data buffer

array

R

32

MB90378 Series

(Continued)

Byte

access access

Word

Address Abbreviation

Register

Resource name Initial value

003FEEH

003FEFH

DNDL7

DNDH7

DOWN data register 7 (lower)

DOWN data register 7 (upper)

R

XXXXXXXXB

LPC data buffer

array

Data buffer array address

register (lower)

003FF0H

003FF1H

DBAAL

DBAAH

R/W

XXXXXXXXB

Data buffer array address

register (upper)

003FF2H,

003FF3H

Prohibited area

Timer control status register

CH6 (lower)

003FF4H

003FF5H

TMCSRL6

TMCSRH6

R/W

00000000B

----0000B

16-bit

reload timer

(ch6)

Timer control status register

CH6 (upper)

003FF6H

003FF7H

003FF8H

003FF9H

003FFAH

003FFBH

003FFCH

003FFDH

003FFEH

003FFFH

R/W

XXXXXXXXB

00000001B

TMR6/

TMRD6

16-bit timer/reload register CH6

PRLL0

PRLH0

PRLL1

PRLH1

PPGC0

PPGC1

PCS01

PPG reload register (lower)

PPG reload register (upper)

PPG reload register (lower)

PPG reload register (upper)

PPG control register ch0

PPG control register ch1

PPG clock control register

R/W

8/16-bit

PPG timer 1

00000001B

000000XXB

Prohibited area

• Meaning of abbreviations used for reading and writing

R/W : Readable and writable

R

W

: Read-only

: Write-only

• Explanation of initial values

0 : The bit is initialized to 0.

1 : The bit is initialized to 1.

X : The initial value of the bit is undefined.

-

: The bit is not used. Its initial value is undefined.

• Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003F80H to 003FFFH.

33

MB90378 Series

INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control

EI²OS

support

Interrupt vector

Priority*²

register

Interrupt cause

Number

Address

ICR Address

Reset

#08 08H FFFFDCH

#09 09H FFFFD8H

#10 0AH FFFFD4H

#11 0BH FFFFD0H

#12 0CH FFFFCCH

#13 0DH FFFFC8H

#14 0EH FFFFC4H

#15 0FH FFFFC0H

#16 10H FFFFBCH

#17 11H FFFFB8H

#18 12H FFFFB4H

#19 13H FFFFB0H

#20 14H FFFFACH

#21 15H FFFFA8H

#22 16H FFFFA4H

#23 17H FFFFA0H

#24 18H FFFF9CH

#25 19H FFFF98H

#26 1AH FFFF94H

#27 1BH FFFF90H

#28 1CH FFFF8CH

High

INT9 instruction

Exception processing

A/D converter conversion termination

Timebase timer

ICR00 0000B0H*¹

ICR01 0000B1H*¹

ICR02 0000B2H*¹

ICR03 0000B3H*¹

ICR04 0000B4H*¹

ICR05 0000B5H*²

ICR06 0000B6H*¹

ICR07 0000B7H*¹

ICR08 0000B8H*¹

UPI0 IBF/LPC reset

UPI1 IBF

UPI2 IBF

UPI3 IBF

DTP/ext. interrupt channels 0/1 detection

DTP/ext. interrupt channels 2/3 detection

DTP/ext. interrupt channels 4/5 detection

Key-on wake-up interrupt detection

UPI0/1/2/3 OBE

16-bit PPG timer 1 / 8/16-bit PPG timer 0/1

PS/2 interface 0/1

PS/2 interface 2

Watch timer

I²C transfer complete / bus error

16-bit PPG timer 2/3

DTP/ext. interrupt channels 6/7 detection

Multi-address I²C transfer complete / bus

error

#29 1DH FFFF88H

ICR09 0000B9H*¹

Extend External Interrupt 00 to 07/08 to 15

I²C timeout / standby wake-up

16-bit reload timer 1/2/5 underflow

Multi-address I²C timeout / standby wake-up

16-bit reload timer 3/4/6 underflow

UART1 receive

#30 1EH FFFF84H

#31 1FH FFFF80H

#32 20H FFFF7CH

#33 21H FFFF78H

#34 22H FFFF74H

#35 23H FFFF70H

#36 24H FFFF6CH

#37 25H FFFF68H

#38 26H FFFF64H

#39 27H FFFF60H

#40 28H FFFF5CH

#41 29H FFFF58H

#42 2AH FFFF54H

ICR10 0000BAH*¹

ICR11 0000BBH*¹

ICR12 0000BCH*¹

ICR13 0000BDH*¹

ICR14 0000BEH*¹

ICR15 0000BFH*¹

UART1 send

UART2 receive

UART2 send

UART3 receive

UART3 send

Flash memory status

Low

Delayed interrupt generator module

(Continued)

34

MB90378 Series

(Continued)

: Can be used and interrupt request flag is cleared by EI²OS interrupt clear signal.

: Cannot be used.

: Can be used and support the EI²OS stop request.

: Can be used.

*1 :

For peripheral functions that share the ICR register, the interrupt level will be the same.

If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register

with another peripheral function, the service can be started by either of the function. And if EI²OS clear is

supported, both interrupt request flags for the two interrupt causes are cleared by EI²OS interrupt clear

signal. It is recommended to mask either of the interrupt request during the use of EI²OS.

EI²OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt

is masked during EI²OS operation. It is recommended to mask either of the interrupt requests during the

use of EI²OS.

*2 : This priority is applied when interrupts of the same level occur simultaneously.

35

MB90378 Series

ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Rating

Rating

Symbol

Unit

Remarks

Parameter

Min

Max

VCC

VSS 0.3 VSS 4.0

V

Power supply voltage*¹

AVCC

VCC AVCC *²

A/D converter reference

input voltage*¹

AVR

V1 to V3

VI1

VSS 0.3 VSS 4.0

V

AVCC AVR, AVR AVSS

LCD power supply

voltage*¹

V1 to V3 must not exceed VCC

All pins except P40 to P45,

P80 to P82, P90 to P95 *³

Input voltage*¹

VI2

VO

VSS 0.3 VSS 6.0

VSS 0.3 VSS 4.0

V

P40 to P45, P80 to P82, P90 to P95

Output voltage*¹

*3

*5

Maximum clamp current

ICLAMP

2.0

20

mA

Total maximum clamp

current

|ICLAMP|

mA

*5

IOL1

IOL2

10

20

mA

All pins except PF0 to PF7 *⁴

PF0 to PF7 *⁴

“L” level maximum output

current

All pins except PF0 to PF7

IOLAV1

IOLAV2

4

mA

Average output current operating

current operating efficiency

“L” level average output

current

PF0 to PF7

Average output current operating

current operating efficiency

12

“L” level total maximum

output current

IOL

IOLAV

IOH

100

50

10

3

mA

“L” level total average

output current

Average output current operating

current operating efficiency

“H” level maximum output

current

*4

“H” level average output

current

Average output current operating

current operating efficiency

IOHAV

IOH

“H” level total maximum

output current

100

50

“H” level total average

output current

Average output current operating

current operating efficiency

IOHAV

Power consumption

Operating temperature

Storage temperature

PD

TA

200

85

mW

C

40

55

Tstg

150

C

(Continued)

36

MB90378 Series

(Continued)

*1 : This parameter is based on VSS AVSS 0.0 V.

*2 : Set AVCC and VCC at the same voltage. Take care so that AVR does not exceed VCC 0.3 V when the power is

turned on.

*3 : VI and VO shall never exceed VCC 0.3 V.

*4 : The maximum output current is a peak value for a corresponding pin.

*5 :

Use within recommended operating conditions.

Use at DC voltage (current).

The B signal should always be applied a limiting resistance placed between the B signal and the

microcontroller.

The value of the limiting resistance should be set so that when the B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

Note that when the microcontroller drive current is low, such as in the power saving modes, the B input

potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect

other devices.

Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power

supply is provided from the pins, so that incomplete operation may result.

Note that if the B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to poerate the power-on reset.

Care must be taken not to leave the B input pin open.

Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept

B signal input.

Sample recommended circuits :

Input/output equivalent circuits

Protective diode

VCC

Pch

Limiting

resistance

B input (0 V to 16 V)

Nch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

37

MB90378 Series

2. Recommended Operating Conditions

(VSS AVSS 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

2.7 *¹

Max

3.6

VCC

V

Normal operation assurance range

Retains the RAM state in stop mode

Power supply voltage *²

1.8

3.6

A/D converter reference

input voltage *³

AVR

0

AVCC

V

Normal operation assurance range

V1 to V3 pins

LCD power supply voltage V1 to V3

Operating temperature

VSS

VCC

V

C

(The optimum value is dependent on the

LCD element in use.)

TA

40

85

*1 : The operating voltage varies with the operation frequency.

*2 : Set AVCC and VCC at the same voltage.

*3 : Take care so that AVR does not exceed VCC + 0.3 V when power is turned on.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

38

MB90378 Series

3. DC Characteristics

Parameter Symbol

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Typ

Pin name

Condition

Unit Remarks

Min

Max

P10 to P17, P20 to P27,

P30 to P37, P46, P47,

P51 to P57, PC0 to PC7,

PD0 to PD7

CMOS

V

VIH

0.7 VCC

VCC 0.3

input pins

P00 to P07, P60 to P67,

P70 to P77, P83 to P86,

PA0 to PA7, PB0 to PB7,

PE0 to PE7, PF0 to PF7,

RST

CMOS

hysteresis

input pins

VIHS

0.8 VCC

VCC 0.3

V

“H” level

input voltage

5Vtolerant

CMOS

hysteresis

input pins

VIHS5

P40 to P45

0.8 VCC

0.7 VCC

VSS 5.5

V

5Vtolerant

CMOS

input pins

P50,

P82

VIH5

P80, P81,

P90 to P95

SMbus

input pins

VIHSM

VIHM

2.1

VSS 5.5

VCC 0.3

V

MD0 to MD2

VCC 0.3

Mode pins

P10 to P17, P20 to P27,

P30 to P37, P46, P47,

P50 to P57, P82,

CMOS

input pins

VIL

VSS 0.3

0.3 VCC

V

PC0 to PC7, PD0 to PD7

P00 to P07, P40 to P45,

P60 to P67, P70 to P77,

P83 to P86, PA0 to PA7,

PB0 to PB7, PE0 to PE7,

PF0 to PF7, RST

CMOS

hysteresis

input pins

“L” level

input voltage

VILS

0.2 VCC

V

P80, P81,

P90 to P95

SMbus

input pins

VILSM

VILM

VD5

VSS 0.3

0.8

V

MD0 to MD2

VSS 0.3

VSS 5.5

Mode pins

Open-drain

output pin

application

voltage

P40 to P45, P50,

P80 to P82, P90 to P95

VD

P46, PF0 to PF7

VSS 0.3

V_CC0.5

VCC 0.3

V

All port pins except

P40 to P46, P50,

P80 to P82, P90 to P95, IOH1

PF0 to PF7

“H” level

output

voltage

VCC 3.0 V

VOH1

4.0 mA

All port pins except

PF0 to PF7

“L” level

output

voltage

VOL1

VOL2

IOL1 4.0 mA

0.4

V

PF0 to PF7

IOL2 12.0 mA

(Continued)

39

MB90378 Series

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min Typ Max

Input leakage

current

(Hi-Z output

leakage current)

VCC 3.3 V,

IIL

All input pins

5

A

VSS

VI VCC

Open-drain

output leakage

current

P40 to P46, P50,

P80 to P82, P90 to P95,

PF0 to PF7

ILEAK

ICC

5

A

VCC 3.3 V,

Internal operation

at 20 MHz

56

23

68

mA

VCC 3.3 V,

Internal operation

at 20 MHz,

ICCS

30

80

mA

A

In sleep mode

VCC 3.3 V,

External 32 kHz,

Internal operation

at 8 kHz,

In sub-clock

mode,

ICCL

23

10

Power supply

current*

VCC

TA

25 C

VCC 3.3 V,

External 32 kHz,

Internal operation

at 8 kHz,

In sub-clock sleep

mode,

ICCLS

50

A

TA

25 C

VCC 3.3 V,

External 32 kHz,

Internal operation

at 8 kHz,

ICCWAT

1.5

2.0

30

3

In watch mode,

TA

25 C

VCC 3.3 V,

Internal operation

at 20 MHz,

In timebase timer

mode

ICCT

mA

A

Power supply

current*

VCC

V_CC3.3 V,

In stop mode,

ICCH

CIN

1

20

80

TA

25 C

Input

capacitance

All input pins except

VCC, AVCC, VSS, AVSS

10

pF

(Continued)

40

MB90378 Series

(Continued)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min Typ Max

Between VCC andV3

at VCC 3.3 V

100 200 400

LCD divided

resistance

Between V3 and V2

Between V2 and V1

Between V1 and VSS

at VCC 3.3 V

RLCD

k

50 100 200

COM0toCOM3

output

impedance

RVCOM COM0 to COM3

5

k

V1 to V3 3.3 V

SEG0 to SEG8

output

impedance

RVSEG

LLCDL

RUP

SEG0 to SEG8

V1 to V3,

COM0 to COM3,

SEG0 to SEG8

LCD leakage

current

1

A

P00 to P07,P10 to P17,

P20 to P27,P30 to P37,

RST

Pull-up

resistance

25

50

100

k

Pull-down

resistance

MB90V378

only

RDOWN MD2

* : The current value is preliminary value and may be subject to change for enhanced characteristics without

previous notice. The power supply current is measured with an external clock.

41

MB90378 Series

4. AC Characteristics

(1) Clock Timings

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Remarks

Value

Typ

Parameter

Clock frequency

Clock cycle time

Symbol Pin name Condition

Unit

Min

Max

1/2(When PLL stops)

MHz When using an

oscillation circuit

3

16

PLL 1 When using an

oscillation circuit

4

16

10

MHz

PLL 2 When using an

oscillation circuit

PLL 3 When using an

oscillation circuit

6.67 MHz

PLL 4 When using an

oscillation circuit

5

MHz

fCH

X0, X1

1/2(When PLL stops)

MHz When using an external

clock

3

32

PLL 1 When using an

MHz

4

20

10

external clock

PLL 2 When using an

MHz

external clock

PLL 3 When using an

external clock

6.67 MHz

PLL 4 When using an

external clock

5

MHz

fCL

X0A, X1A

X0, X1

32.768

30.5

kHz

ns

s

tHCYL

tLCYL

31.25

333

X0A, X1A

Frequency

fluctuation rate

locked*

f

5

%

PWH

PWL

Recommend duty

ratio of 30% to 70%

X0

X0A

X0

5

ns

s

Input clock pulse

width

PWHL

PWLL

Recommend duty

ratio of 30% to 70%

15.2

Input clock rise/fall

time

tCR

tCF

External clock

operation

5

ns

fCP

fLCP

tCP

1.5

50

20

MHz Main clock operation

kHz Sub-clock operation

ns Main clock operation

Internal operating

clock frequency

8.192

122.1

666

Internal operating

clock cycle time

tLCP

s

Sub-clock operation

42

MB90378 Series

X0, X1 clock timing

tHCYL

0.8 VCC

0.2 VCC

X0

0.2 VCC

PWL

PWH

tCF

tCR

X0A, X1A clock timing

tLCYL

0.8 VCC

X0A

0.2 VCC

PWLL

0.2 VCC

tCR

PWHL

tCF

43

MB90378 Series

PLL operation guarantee range

Relationship between machine clock frequency and power supply voltage

3.6

3.0

2.7

1.5 3 4

16

20

Machine clock fCP (MHz)

Operation guarantee range of PLL

Normal operation guarantee range

Guaranteed oscillation frequency range

Relationship between external clock frequency and machine clock frequency

Guaranteed oscillation frequency range

3

2

4

1

20

16

12

8

1

2

(PLL off)

4

1.5

3

4

5

6.67 8

10

12

16

20

24

32

External clock FC (MHz)*

* : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.

44

MB90378 Series

The AC ratings are measured for the following measurement reference voltages :

Output signal waveform

Input signal waveform

Hysteresis input pin

Output pin

0.8 VCC

0.2 VCC

2.4 V

0.8 V

CMOS input pin

0.7 VCC

0.3 VCC

SMbus input pin

2.1 V

0.8 V

45

MB90378 Series

(2) Reset Input Timing

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Parameter

Symbol Pin name Condition

Unit

Remarks

Min

Max

Normal

operation

16 tCP

ns

Reset input time

tRSTL

RST

In stop mode

ms and sub-clock

mode

Oscillation time of

oscillator* 16 tCP

* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal

oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time

is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms.

Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.

In stop mode

tRSTL

RST

0.2 VCC

90% of

oscillation

amplitude

X0

Internal operation

clock

16 tCP

Oscillation time

of oscillator

Oscillation stabilization time

Instruction execution

Internal reset

46

MB90378 Series

(3) Power-on Reset

Parameter

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Symbol Pin name Condition

Unit

Remarks

Min

Max

Power supply rise time

tR

VCC*

50

ms

Due to repeated

operations

Power supply cut-off time

tOFF

1

* : VCC must be kept lower than 0.2 V before power-on.

Notes : The above values are used for causing a power-on reset.

Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn

on the power supply using the above values.

Make sure that power supply rises within the selected oscillation stabilization time. If the power supply

voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

tR

tOFF

2.2 V

0.2 V

VCC

Sudden changes in the power supply voltage may cause a power-on reset.

To change the power supply voltage while the device is in operation, it is recommended

to raise the voltage smoothly to suppress fluctuations as shown below. In this case,

change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer

per second, however, you can use the PLL clock.

VCC

It is recommended to keep the

rising speed of the supply voltage

at 50 mV/ms or slower.

1.8 V

VSS

RAM data hold

47

MB90378 Series

(4) UART1 to UART3

(VCC = 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Max

Serial clock cycle time

tSCYC

tSLOV

UCK1 to UCK3

4 tCP

ns

UCK1 to UCK3,

UO1 to UO3

UCK

UO delay time

UCK

80

CL 80 pF 1 TTL

for an output pin of

internal shift clock

mode

UCK1 to UCK3,

UI1 to UI3

Valid UI

UCK

tIVSH

tSHIX

100

ns

UCK1 to UCK3,

UI1 to UI3

valid UI hold time

tCP

Serial clock “H” pulse width

Serial clock “L” pulse width

tSHSL

tSLSH

UCK1 to UCK3

4 tCP

ns

UCK1 to UCK3, CL 80 pF 1 TTL

UCK

UO delay time

UCK

tSLOV

tIVSH

tSHIX

150

ns

UO1 to UO3

for an output pin of

external shift clock

mode

UCK1 to UCK3,

UI1 to UI3

Valid UI

UCK

60

UCK1 to UCK3,

UI1 to UI3

valid UI hold time

Notes : These are AC ratings in the CLK synchronous mode.

CL is the load capacitance value connected to pins while testing.

tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.

48

MB90378 Series

Internal shift clock mode

tSCYC

UCK

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

UO

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

UI

Internal shift clock mode

tSLSH

tSHSL

UCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

UO

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

UI

49

MB90378 Series

(5) Resources Input Timing

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min

Max

tTIWH

tTIWL

Timer input pulse width

TIN1 to TIN6

4 tCP

ns

Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.

0.8 VCC

0.2 VCC

TIN1 to TIN6

0.2 VCC

tTIWH

tTIWL

(6) Trigger Input Timing

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Parameter

Symbol

Pin name

Condition

Unit

Remarks

Min

Max

ADTG,

5 tCP

ns Normal operation

tTRGH

tTRGL

INT0 to INT7,

EEI0 to EEI15,

KSI0 to KSI7

Input pulse width

1

s

Stop mode

Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.

0.8 VCC

0.2 VCC

INT0 to INT7

EEI0 to EEI15

0.2 VCC

KSI0 to KSI7

tTRGH

tTRGL

0.7 VCC

0.3 VCC

ADTG

0.3 VCC

tTRGH

tTRGL

50

MB90378 Series

(7) I²C / Multi-address I²C Timing

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Parameter

Symbol Pin name

Unit Remarks

Min

Max

SCL,

SDA

Master

ns

Start condition output

Stop condition output

Start condition detect

Stop condition detect

Restart condition output

Restart condition detect

SCL output “L” width

tSTA

tSTO

tCP (m x n/2 1) 20 tCP (m x n/2 1) 20

mode

SCL,

SDA

Master

ns

tCP (m x n/2 3) - 20 tCP (m x n/2 3) 20

mode

SCL,

SDA

tSTA

tCP 40

ns

SCL,

SDA

tSTO

tCP 40

SCL,

SDA

Master

ns

tSTASU

tLOW

tCP (m x n/2 3) 20 tCP (m x n/2 3) 20

mode

SCL,

SDA

tCP 40

ns

Master

ns

SCL

tCP x m x n/2 20

mode

Master

ns

SCL output “H” width

tHIGH

tDO

SCL

SDA

tCP (m x n/2 2) 20 tCP (m x n/2 2) 20

mode

SDA output delay

tCP x 3 20

tCP x m x n/2 20

tCP x 4 20

tCP x 3 40

tCP 40

tCP x 3 20

ns

ns *1

ns *2

ns

SDA output setup time

after interrupt

tDOSU

SDA

SCL input “L” pulse

SCL input “H” pulse

SDA output setup time

SDA hold time

tLOW

tHIGH

tSU

SCL

SDA

ns

40

ns

tHO

0

ns

Notes : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.

m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4, CS3)” and “MCCR register

(CS4, CS3)”. Please refer to the MB90378 series H/W manual for details.

n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 to CS0)” and “MCCR register

(CS2 to CS0)”. Please refer to the MB90378 series H/W manual for details.

tDOSU is shown in the interrupt time is longer than the “L” width of SCL.

SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”.

*1 : At the stop condition or transferring of next byte.

*2 : After setting register bit IBCRH : SCC at restart.

51

MB90378 Series

Data transmit (master/slave)

tDO

tSU

tHO

tDOSU

tDO

ACK

9

SDA

SCL

tSTASU

tSTA

tLOW

tHO

1

Data receive (master/slave)

tSU

tHO

tDO

tDOSU

ACK

SDA

SCL

tHIGH

tLOW

tSTO

6

7

8

9

52

MB90378 Series

(8) PS/2 Interface Timing

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS 0.0 V, TA

40 C to 85 C)

Value

Typ

Parameter

PSCK clock

Symbol

Pin name

Condition

Unit Remarks

Min

Max

PSCK0 to PSCK2,

PSDA0 to PSDA2

tPCYC

tPLOV

tPIVSH

tPHIX

4 tCP

ns

cycle time

PSCK0 to PSCK2,

PSDA0 to PSDA2

PSCK

PSDA

Transmission Mode 2 tCP

Valid PSDA

PSCK

PSCK0 to PSCK2,

PSDA0 to PSDA2

1 tCP

Reception Mode

1 tCP

PSCK0 to PSCK2,

PSDA0 to PSDA2

PSCK

valid

PSDA hold time

PSCK clock

“H” pulse width

PSCK0 to PSCK2,

PSDA0 to PSDA2

tPHSL

tPLSH

2 tCP

PSCK0 to PSCK2,

PSDA0 to PSDA2

PSCK clock

“L” pulse width

Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.

tPCYC

0.8 VCC

PSCK0

PSCK1

PSCK2

0.2 VCC

tPLOV

Transmission Mode

2.4 V

0.8 V

PSDA0

PSDA1

PSDA2

tPIVSH

tPHIX

Reception Mode

0.8 VCC

PSDA0

PSDA1

PSDA2

0.2 VCC

53

MB90378 Series

(9) LPC Timing

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Typ

Parameter

Symbol Pin name Condition

Unit Remarks

Min

30

Max

LCLK cycle time

LCLK high time

LCLK low time

tCYCLE

tHIGH

tLOW

ns

12

LCLK AC timing

tCYCLE

tHIGH

0.7 VCC

0.3 VCC

LCLK

tLOW

54

MB90378 Series

Value

Typ

Parameter

Symbol Pin name Condition

Unit

Remarks

Min

2

Max

Output valid delay

Float to active delay

Active to float delay

Input setup time

tVAL

tON

tOFF

tS

12

ns

2

28

7

0

Input hold time

tH

LAD, LFRAME, GA20 AC timing

0.4 VCC

LCLK

tVAL

OUTPUT

Delay

tON

Tri-state

OUTPUT

tOFF

0.4 VCC

LCLK

tS

tH

INPUT

55

MB90378 Series

5. A/D Converter Electrical Characteristics

(2.7 V AVR AVSS, VCC AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Remarks

Value

Typ

name

Parameter

Resolution

Symbol

Unit

Min

Max

10

bit

Total error

3.0

2.5

LSB

Non-linear error

Differential linearity

error

1.9

LSB

mV

AVSS

5.5 LSB

For MB90V378

Zero transition

voltage

AN0 to

AN11

AVSS

1.5 LSB

AVSS

0.5 LSB

VOT

AVSS

2.5 LSB

For MB90F378

Full-scale transition

voltage

AN0 to

AN11

AVR

3.5 LSB

AVR

1.5 LSB

AVR

0.5 LSB

VFST

Actual value is specified as

a sum of values specified in

ADCR0 : CT1, CT0 and

ADCR0 : ST1, ST0. Be sure

that the setting value is

Conversion time

Sampling period

3.1

2

s

greater than the min value

Actual value is specified in

ADCR0 : ST1, ST0 bits. Be

sure that the setting value is

greater than the min value

Analog port input

current

AN0 to

AN11

IAIN

0.1

10

A

V

Analog input

voltage

AN0 to

AN11

VAIN

AVSS

AVR

Reference voltage

AVR AVSS 2.7

AVCC

6.4

5

V

mA

A

IA

IAH

IR

1.4

94

Power supply

current

*

300

5

A

Reference voltage

supply current

AVR

IRH

A

Offset between

channels

AN0 to

AN11

—

4

LSB

*: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC AVCC AVR 3.0 V).

56

MB90378 Series

6. A/D Converter Glossary

Resolution : Analog changes that are identifiable with the A/D converter.

Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000”

“00 0000 0001”) with the full-scale transition point (“11 1111 1110”

“11 1111 1111”) from

actual conversion characteristics.

Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value.

Total error : The total error is defined as a difference between the actual value and the theoretical value, which

includes zero-transition error/full-scale transition error and linearity error.

Total error

3FF

3FE

3FD

H

0.5 LSB

Actual conversion

value

{1 LSB (N 1) 0.5 LSB}

004

003

002

001

H

V

NT

(Measured value)

Actual conversion

value

Theoretical

characteristics

0.5 LSB

AVRL

AVRH

Analog input

VNT {1 LSB (N 1) 0.5 LSB}

1 LSB

Total error for digital output N

1 LSB (Theoretical value)

[LSB]

AVR AVss

1024

[V]

VOT (Theoretical value) AVss 0.5 LSB [V]

VFST (Theoretical value) AVR 1.5 LSB [V]

VNT : Voltage at a transition of digital output from (N 1) to N

(Continued)

57

MB90378 Series

(Continued)

Differential linearity error

Linearity error

Theoretical

characteristics

3FFH

Actual conversion

value

3FEH

N

1

N

1

{1 LSB (N 1)

Actual conversion

value

VOT }

3FDH

VFST

(Measured value)

VNT

(Measured value)

004H

V (N 1) T

(Measured value)

Actual conversion

value

N

003H

002H

001H

VNT

(Measured value)

Theoretical characteristics

Actual conversion

value

2

VOT (Measured value)

AVRL

AVRH

AVRL

AVRH

Analog input

Linearity error of

digital output N

VNT {1 LSB (N 1) VOT}

1 LSB

[LSB]

Differential linearityerror

of digital output N

V (N 1) T VNT

1 [LSB]

1 LSB

VFST

VOT

1 LSB

[V]

1022

VOT : Voltage at transition of digital output from “000H” to “001H”

VFST : Voltage at transition of digital output from “3FEH” to “3FFH”

58

MB90378 Series

7. Notes on Using A/D Converter

• About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

• Analog input circuit model

R

Analog input

Comparator

C

During sampling : ON

R

C

MB90F378/V378

1.9 k (Max)

25 pF (Max)

Note : The values are reference values.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

• The relationship between the external impedance and minimum sampling time

[External impedance 0 k to 100 k ]

[External impedance 0 k to 20 k ]

20

100

90

80

70

60

50

40

18

16

14

12

10

8

30

6

MB90F378/V378

20

MB90F378/V378

4

10

0

2

0

25

35

15

20

30

5

10

0

5

7

0

2

3

4

6

8

1

Minimum sampling time ( s)

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin.

• About errors

As |AVR AVSS| becomes smaller, values of relative errors grow larger.

59

MB90378 Series

8. D/A Electrical Characteristics

(VCC AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Parameter

Resolution

Symbol Pin name Condition

Unit Remarks

Min

Typ

Max

8

bit

Differential linearity error

Non-linearity error

0.9

1.5

LSB

Conversion time

0.6

2.9

s

*

Analog output impedance

2.0

3.8

k

IDVR

AVCC

460

A

Power supply current

IDVRS

0.1

D/A stops

* : With load capacitance is 20 pF.

9. Serial IRQ Electrical Characteristics

(VCC 2.7 V to 3.6 V, AVCC 2.7 V to 3.6 V, VSS AVSS 0.0 V, TA

40 C to 85 C)

Value

Parameter

Symbol Pin name Condition

Unit Remarks

Min

0.7 VCC

VSS

Typ

Max

VCC

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

VIH

VIL

V

0.3 VCC

VOH

VOL

VCC 0.5

0.4

10. Flash Memory Program/Erase Characteristics

Value

Parameter

Condition

Unit

Remarks

Min

Typ

Max

Sector erase time

(4 Kbytes sector)

Excludes 00H programming prior

to erasure

0.2

0.5

s

Sector erase time

(16 Kbytes sector)

Excludes 00H programming prior

to erasure

0.5

4.6

32

7.5

TA

25 C

VCC 3.0 V

Excludes 00H programming prior

to erasure

Chip erase time

Byte (8-bit width)

programing time

Except for the over head time of

the system

3,600

Program/Erase cycle

10,000

cycle

60

MB90378 Series

EXAMPLE CHARACTERISTICS (MB90F378)

• Power Supply Current

TA

25 [ C]

TA

25 [ C]

ICCS [mA]

ICC [mA]

50.0

Fcin = 16 MHz

Fcin = 12 MHz

18.0

Fcin = 16 MHz

16.0

40.0

30.0

20.0

10.0

14.0

12.0

10.0

Fcin = 12 MHz

Fcin = 10 MHz

Fcin = 8 MHz

Fcin = 10 MHz

Fcin = 8 MHz

8.0

6.0

Fcin = 4 MHz

Fcin = 2 MHz

Fcin = 4 MHz

4.0

2.0

0.0

Fcin = 2 MHz

VCC [V]

4.0

0.0

2.0

2.5

3.0

3.5

2.0

2.5

3.0

3.5

4.0

T

A

25 [ C]

I

CCH [ A]

2.5

2.0

1.5

1.0

0.5

V

CC [V]

0.0

2.5

3.0

3.5

4.0

(Continued)

61

MB90378 Series

(Continued)

TA

25 [ C]

TA

25 [ C]

VCC VOH2 [V]

0.7

VCC VOH1 [V]

2.0

0.6

0.5

0.4

0.3

1.5

1.0

0.5

0.0

VCC = 2.5 [V]

VCC = 3.0 [V]

VCC = 3.5 [V]

VCC = 4.0 [V]

VCC = 3.0 [V]

VCC = 3.5 [V]

VCC = 4.0 [V]

0.2

0.1

IOH2 [mA]

IOH1 [mA]

0.0

2

4

6

8

10

0

2

4

6

8

10

0

TA

25 [ C]

TA

25 [ C]

VOL1 [V]

VOL2 [V]

0.8

0.6

0.3

0.2

0.1

0.0

VCC = 2.5 [V]

VCC = 3.0 [V]

VCC = 4.0 [V]

VCC = 3.5 [V]

VCC = 2.5 [V]

VCC = 3.0 [V]

VCC = 3.5 [V]

VCC = 4.0 [V]

0.4

0.2

0.0

IOL1 [mA]

IOL2 [mA]

0

2

4

6

8

10

0

2

4

6

8

10

62

MB90378 Series

ORDERING INFORMATION

Part number

Package

Remarks

144-pin Plastic LQFP

(FPT-144P-M12)

MB90F378PFF-GE1

63

MB90378 Series

PACKAGE DIMENSION

144-pin plastic LQFP

(FPT-144P-M12)

Note 1) * : These dimensions include resin protrusion.

Resin protrusion is +0.25(.010)Max(each side).

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

18.00±0.20(.709±.008)SQ

+0.40

16.00

.630 ⁺–^..0⁰0¹4⁶SQ

*

–0.10

73

108

72

109

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

INDEX

0~8˚

37

144

"A"

0.10±0.05

(.004±.002)

(Stand off)

0.60±0.15

(.024±.006)

1

LEAD No.

36

0.25(.010)

0.145 ⁺–0⁰.^.003⁵

0.40(.016)

0.18±0.035

.007±.001

M

0.07(.003)

.006 –⁺.^.0⁰⁰01²

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F144024S-c-3-3

64

MB90378 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0504

2005 FUJITSU LIMITED Printed in Japan


型号：	MB90V378
厂家：	FUJITSU
描述：	16-BIT PROPRIETARY MICROCONTROLLER 16位微控制器专有微控制器
文件：	总65页 (文件大小：471K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90V378 [FUJITSU]

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