MB90V340S [FUJITSU]
16-bit general-purpose microcontroller; 16位的通用微控制器
| 型号： | MB90V340S |
| 厂家： | 
FUJITSU |
| 描述： | 16-bit general-purpose microcontroller |
| 文件： | 总62页 (文件大小：818K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13732-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90860A Series
MB90F867A (S) , MB90867A (S)
■ DESCRIPTION
The MB90860A-series is Fujitsu 16-bit general-purpose microcontroller which enhances each kind of timers and
communication macros. With the new 0.35 µm CMOS technology, Fujitsu now offers 128 Kbytes on-chip FLASH-
ROM program memory. An internal voltage booster removes the necessity for a second programming voltage.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free
running timers. 4 UARTs constitute additional functionality for communication purposes.
Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
■ PACKAGES
100-pin Plastic QFP
100-pin Plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB90860A Series
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without
S-suffix only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi-
plied PLL clock).
• 16 Mbyte CPU memory space
• 24-bit internal addressing
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
• 4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
• Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
• Process
• CMOS technology
• I/O port
• General-purpose input/output port (CMOS output)
- 80 ports (devices without S-suffix)
- 82 ports (devices with S-suffix)
(Continued)
2
MB90860A Series
(Continued)
• Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 8 channels
- 16-bit output compare : (OCU) : 8 channels
• UART (LIN/SCI) : 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
• I2C interface* : 2 channels
• Up to 400 kbit/s transfer rate
• DTP/External interrupt : 16 channels, CAN wakeup : 2 channels
• Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt.
• Delay interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter : 24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
• Program patch function
• Address matching detection for 6 address pointers.
• Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
• Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
• ROM security function
• Protects the content of ROM (MASK ROM device only)
• Flash security function
• Protects the content of Flash (Flash device only)
• External bus interface
• Clock monitor function
* : I2C license :
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-
ponents in an I2C system provided that the system conforms to the I2C standard Specification as defined by
Philips.
3
MB90860A Series
■ PRODUCT LINEUP
Part Number
MB90F867A (S) , MB90867A (S)
MB90V340(S)
Parameter
CPU
F2MC-16LX CPU
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
System clock
Boot-block,Flash memory
128 Kbytes
ROM
RAM
External
30 Kbytes
Yes
6 Kbytes
Emulator-specific
power supply*1
0.35 µm CMOS with on-chip voltage regulator for internal
power supply + Flash memory with
On-chip charge pump for programming voltage
0.35 µm CMOS with
on-chip voltage regulator
for internal power supply
Technology
3.5 V to 5.5 V : at normal operating (not using A/D converter)
4.0 V to 5.5 V : at using A/D converter/Flash programming
4.5 V to 5.5 V : at using external bus
Operating
voltage range
5 V ± 10%
Temperature range
Package
−40 °C to +105 °C
QFP-100, LQFP-100
PGA-299
4 channels
5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
UART
I2C (400 Kbit/s)
2 channel
24 input channels
A/D
Converter
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
16-bit Reload Timer Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
(4 channels)
Supports External Event Count function
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit
I/O Timer
(2 channels)
16-bit Output
Compare
Signals an interrupt when 16-bit I/O Timer match output compare registers.
(8 channels (16-bit) / A pair of compare registers can be used to generate an output signal.
16 channels (8-bit) )
16-bit Input Capture Rising edge, falling edge or rising & falling edge sensitive
(8 channels)
Signals an interrupt upon external event
(Continued)
4
MB90860A Series
(Continued)
Part Number
MB90F867A (S) , MB90867A (S)
Supports 8-bit and 16-bit operation modes
MB90V340(S)
Parameter
Sixteen 8-bit reload counters
8/16-bit
Sixteen 8-bit reload registers for L pulse width
ProgrammablePulse Sixteen 8-bit reload registers for H pulse width
Generator
(8 channels)
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
CAN Interface
3 channels
External Interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded inteligent I/O services (EI2OS) and DMA
D/A converter
2 channels
Up to100 kHz
Subclock for low
power operation
devices with ‘S’-suffix
devices without ‘S’-suffix : with subclock
: without subclock
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
I/O Ports
Bit-wise settable as input/output or peripheral signal
Settable in pin-wise of 8 as CMOS schmitt trigger/ automotive inputs (default)
TTL input level settable for external bus (32-pin only for external bus)
Supports automatic programming, Embedded AlgorithmTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 20 years
Boot block configuration
Flash
Memory
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
MB90860A Series
■ PIN ASSIGNMENTS
• MB90F867A (S) , MB90867A (S)
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
P12/AD10/SIN3/NT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
QFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVss
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
AVRL
AVRH
AVcc
P57/AN15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
* : MB90F867A, MB90867A : X0A, X1A
MB90F867AS, MB90867AS : P40, P41
(Continued)
6
MB90860A Series
(Continued)
(TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
P01/AD01/INT9
P02/AD02/INT10
P03/AD03/INT11
P04/AD04/INT12
P05/AD05/INT13
P06/AD06/INT14
P07/AD07/INT15
P10/AD08/TIN1
P11/AD09/TOT1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MD1
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
MD2
P75/AN21/INT5
P74/AN20/INT4
P73/AN19/INT3
P72/AN18/INT2
P71/AN17/INT1
P70/AN16/INT0
Vss
P12/AD10/SIN3/NT11R
P13/AD11/SOT3
P14/AD12/SCK3
Vcc
P67/AN7/PPGE(F)
P66/AN6/PPGC(D)
P65/AN5/PPGA(B)
P64/AN4/PPG8(9)
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P61/AN1/PPG2(3)
P60/AN0/PPG0(1)
AVss
LQFP - 100
Vss
X1
X0
P15/AD13
P16/AD14
P17/AD15
AVRL
P20/A16/PPG9(8)
P21/A17/PPGB(A)
P22/A18/PPGD(C)
P23/A19/PPGF(E)
P24/A20/IN0
P25/A21/IN1
AVRH
AVcc
P57/AN15
P56/AN14
P55/AN13
P54/AN12/TOT3
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
(FPT-100P-M05)
* : MB90F867A, MB90867A : X0A, X1A
MB90F867AS, MB90867AS : P40, P41
7
MB90860A Series
■ PIN DESCRIPTION
Pin No.
Pin name
Circuit
type
Function
LQFP100*2 QFP100*1
90
91
52
92
93
54
X1
X0
Oscillation output
Oscillation input
Reset input
A
E
RST
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P00 to P07
75 to 82
77 to 84
G
G
G
I/O pins for 8 lower bits of the external address/data bus.
This function is enabled when the external bus is enabled.
AD00 to AD07
INT8 to INT15
External interrupt request input pins for INT8 to INT15.
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P10
83
85
I/O pin for bit 8 of the external address/data bus.
This function is enabled when the external bus is enabled.
AD08
TIN1
Event input pin for the reload timer 1
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P11
84
86
I/O pin for bit 9 of the external address/data bus.
This function is enabled when the external bus is enabled.
AD09
TOT1
Output pin for the reload timer 1
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P12
I/O pin for bit 10 of the external address/data bus.
This function is enabled when the external bus is enabled.
85
87
N
AD10
SIN3
Serial data input pin for UART3
INT11R
Sub external interrupt request input pin for INT11
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P13
86
87
88
89
G
G
I/O pin for bit 11 of the external address/data bus.
This function is enabled when the external bus is enabled.
AD11
SOT3
Serial data output pin for UART3
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P14
I/O pin for bit 12 of the external address/data bus.
This function is enabled when the external bus is enabled.
AD12
SCK3
Clock I/O pin for UART3
(Continued)
8
MB90860A Series
Pin No.
LQFP100*2 QFP100*1
Circuit
type
Pin name
Function
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P15
92
93
94
94
95
96
G
G
G
I/O pin for bit 13 of the external address/data bus.
This function is enabled when the external bus is enabled.
AD13
SIN4
Serial data input pin for UART4 (MB90V340 only)
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P16
I/O pin for bit 14 of the external address/data bus.
This function is enabled when the external bus is enabled.
AD14
SOT4
Serial data output pin for UART4 (MB90V340 only)
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled in single-chip
mode.
P17
I/O pin for bit 15 of the external address/data bus. This function
is enabled when the external bus is enabled.
AD15
SCK4
Clock I/O pin for UART4 (MB90V340 only)
General purpose I/O. The register can be set to select whether
to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
P20 to P23
A16 to A19
Output pins for A16 to A19 of the external address bus. When
the corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A16 to A19).
95 to 98
97 to 100
G
PPG9,PPGB,
PPGD,PPGF
Output pins for PPGs
General purpose I/O. The register can be set to select whether
to use a pull-up resistor.In external bus mode, the pin is
enabled as a general-purpose I/O port when the corresponding
bit in the external address output control register (HACR) is 1.
P24 to P27
A20 to A23
99 to 2
1 to 4
G
Output pins for A20 to A23 of the external address bus. When
the corresponding bit in the external address output control
register (HACR) is 0, the pins are enabled as high address
output pins (A20 to A23).
IN0 to IN3
P30
Data sample input pins for input captures ICU0 to ICU3
General purpose I/O.The register can be set to select whether
to use a pull-up resistor.This function is enabled in single-chip
mode.
3
5
G
Address latch enable output pin. This function is enabled when
the external bus is enabled.
ALE
IN4
Data sample input pin for input capture ICU4
(Continued)
9
MB90860A Series
Pin No.
Pin name
Circuit
type
Function
LQFP100*2 QFP100*1
General purpose I/O.The register can be set to select whether to
use a pull-up resistor.This function is enabled in single-chip
mode.
P31
4
6
G
Read strobe output pin for the data bus. This function is enabled
when the external bus is enabled.
RD
IN5
Data sample input pin for input capture ICU5
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the WR/WRL pin output disabled.
P32
Write strobe output pin for the data bus. This function is enabled
when both the external bus and the WR/WRL pin output are en-
abled. WRL is used to write-strobe 8 lower bits of the data bus in
16-bit access while WR is used to write-strobe 8 bits of the data
bus in 8-bit access.
5
7
G
WRL / WR
RX2
RX input pin for CAN2 Interface (MB90V340 only)
Sub external interrupt request input pin for INT10
INT10R
General purpose I/O. The register can be set to select whether to
use a pull-up resistor.This function is enabled either in single-chip
mode or with the WRH pin output disabled.
P33
Write strobe output pin for the 8 higher bits of the data bus. This
function is enabled when the external bus is enabled, when the
external bus 16-bit mode is selected, and when the WRH output
pin is enabled.
6
8
G
WRH
TX2
P34
TX Output pin for CAN2 (MB90V340 only)
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the hold function disabled.
7
8
9
9
G
G
G
Hold request input pin. This function is enabled when both the ex-
ternal bus and the hold function are enabled.
HRQ
OUT4
Waveform output pin for output compare OCU4
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the hold function disabled.
P35
10
11
Hold acknowledge output pin. This function is enabled when both
the external bus and the hold function are enabled.
HAK
OUT5
Waveform output pin for output compare OCU5
General purpose I/O. The register can be set to select whether to
use a pull-up resistor. This function is enabled either in single-chip
mode or with the external ready function disabled.
P36
Ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
RDY
OUT6
Waveform output pin for output compare OCU6
(Continued)
10
MB90860A Series
Pin No.
LQFP100*2 QFP100*1
Circuit
type
Pin name
Function
General purpose I/O. The register can be set to select whether
to use a pull-up resistor. This function is enabled either in
single-chip mode or with the CLK output disabled.
P37
CLK
10
12
G
CLK output pin. This function is enabled when both the
external bus and CLK output are enabled.
OUT7
P40 , P41
X0A , X1A
P42
Waveform output pin for output compare OCU7
General purpose I/O (devices with S-suffix)
Oscillator input pins for sub-clock (devices without S-suffix)
General purpose I/O
F
B
11 to 12
16
13 to 14
18
IN6
Data sample input pin for input capture ICU6
RX input pin for CAN1 (MB90V340 (S) only)
Sub external interrupt request input pin for INT10
General purpose I/O
F
RX1
INT9R
P43
17
18
19
19
20
21
IN7
F
H
H
Data sample input pin for input capture ICU7
TX Output pin for CAN1 (MB90V340 (S) only)
General purpose I/O
TX1
P44
SDA0
FRCK0
P45
Serial data I/O pin for I2C 0
Input for the 16-bit I/O Timer 0
General purpose I/O
Serial clock I/O pin for I2C 0
SCL0
FRCK1
P46
Input for the 16-bit I/O Timer 1
General purpose I/O
Serial data I/O pin for I2C 1
20
21
22
23
H
H
SDA1
P47
General purpose I/O
Serial clock I/O pin for I2C 1
SCL1
P50
General purpose I/O
22
23
24
25
24
25
26
27
AN8
O
I
Analog input pin for the A/D converter
Serial data input pin for UART2
General purpose I/O
SIN2
P51
AN9
Analog input pin for the A/D converter
Serial data output pin for UART2
General purpose I/O
SOT2
P52
AN10
SCK2
P53
I
Analog input pin for the A/D converter
Clock I/O pin for UART2
General purpose I/O
AN11
TIN3
I
Analog input pin for the A/D converter
Event input pin for the reload timer 3
(Continued)
11
MB90860A Series
Pin No.
Pin name
Circuit
type
Function
LQFP100*2 QFP100*1
P54
General purpose I/O
26
27
28
29
AN12
TOT3
I
I
Analog input pin for the A/D converter
Output pin for the reload timer 3
General purpose I/O
P55
AN13
Analog input pin for the A/D converter
General purpose I/O
P56 to P57
AN14 to AN15
DA00 to DA01
P60 to P67
AN0 to AN7
28, 29
30, 31
J
Analog input pin for the A/D converter
D/A converter analog output pins (MB90V340 only)
General purpose I/O
Analog input pins for the A/D converter
34 to 41
36 to 43
I
I
PPG0, 2, 4, 6,
8, A, C, E
Output pins for PPGs
P70 to P77
AN16 to AN23
INT0 to INT7
P80
General purpose I/O
43 to 48,
53, 54
45 to 50,
55, 56
Analog input pins for the A/D converter (devices with C-suffix)
External interrupt request input pins for INT0 to INT7
General purpose I/O
TIN0
Event input pin for the reload timers 0
Trigger input pin for the A/D converter
Sub external interrupt request input pin for INT12
General purpose I/O
55
56
57
57
58
59
F
F
ADTG
INT12R
P81
TOT0
Output pin for the reload timer 0
Output pin for the clock monitor
Sub external interrupt request input pin for INT13
General purpose I/O
CKOT
INT13R
P82
SIN0
Serial data input pin for UART0
Event input pin for the reload timers 2
Sub external interrupt request input pin for INT14
General purpose I/O
M
TIN2
INT14R
P83
58
59
60
61
SOT0
TOT2
F
F
Serial data output pin for UART0
Output pin for the reload timer 2
General purpose I/O
P84
SCK0
INT15R
P85
Clock I/O pin for UART0
Sub external interrupt request input pin for INT15
General purpose I/O
60
61
62
63
M
F
SIN1
Serial data input pin for UART1
General purpose I/O
P86
SOT1
Serial data output pin for UART1
(Continued)
12
MB90860A Series
(Continued)
Pin No.
LQFP100*2 QFP100*1
Circuit
type
Pin name
Function
P87
General purpose I/O
Clock I/O pin for UART1
General purpose I/O
Output pins for PPGs
General purpose I/O
62
64
F
F
SCK1
P90 to P93
PPG1, 3, 5, 7
P94 to P97
65 to 68
67 to 70
Waveform output pins for output compares OCU0 to OCU3.
This function is enabled when the OCU enables waveform
output.
69 to 72
71 to 74
F
F
OUT0 to
OUT3
PA0
RX0
General purpose I/O
73
75
RX input pin for CAN0 (MB90V340 (s) only)
Sub external interrupt request input pin for INT8
General purpose I/O
INT8R
PA1
74
30
76
32
F
K
TX0
TX Output pin for CAN0 (MB90V340 (s) only)
Vcc power input pin for analog circuits
AVCC
Reference voltage input for the A/D Converter. This power
supply must be turned on or off while a voltage higher than or
equal to AVRH is applied to AVCC.
31
33
AVRH
L
32
33
34
35
AVRL
AVSS
K
K
Lower reference voltage input for the A/D Converter
Vss power input pin for analog circuits
Input pins for specifying the operating mode. The pins must be
directly connected to Vcc or Vss
50, 51
49
52, 53
51
MD1, MD0
MD2
C
D
Input pin for specifying the operating mode. The pins must be
directly connected to Vcc or Vss.
13
63
88
15
65
90
VCC
VSS
C
Power (3.5 V to 5.5 V) input pins
14
42
64
89
16
44
66
91
Power (0V) input pins
This is the power supply stabilization capacitor pin. It should be
connected to a higher than or equal to 0.1 µF ceramic capaci-
15
17
K
tor.
*1 : FPT-100P-M06
*2 : FPT-100P-M05
13
MB90860A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Oscillation circuit
• High-speed oscillation feedback
resistor = approx. 1 MΩ
X1
X0
Xout
A
Standby control signal
Oscillation circuit
X1A
X0A
Xout
• Low-speed oscillation feedback
resistor = approx. 10 MΩ
B
C
Standby control signal
Mask ROM and EVA device:
• CMOS Hysteresis input pin
R
R
Hysteresis
inputs
Flash device:
• CMOS input pin
Mask ROM and EVA device:
• CMOS Hysteresis input pin
• Pull-down resistor valule: approx. 50 kΩ
Hysteresis
inputs
D
Pull-down
Resistor
Flash device:
• CMOS input pin
• No Pull-down
CMOS Hysteresis input pin
• Pull-up resistor valule: approx. 50 kΩ
Pull-up
E
Resistor
R
Hysteresis
inputs
(Continued)
14
MB90860A Series
Type
Circuit
Remarks
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the stand-
by-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
Pout
Nout
R
F
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the stand-
by-time input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
pull-up control
Pout
Nout
• TTL input (With the standby-time input
shutdown function)
• Programmalble pullup resistor: 50 kΩ
approx.
R
G
Hysteresis inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• CMOS level output(IOL = 3 mA, IOH = −3 mA)
• CMOS hysteresis inputs (With the stand-
by-time input shutdown function)
Pout
• Automotive input (With the standby-time
input shutdown function)
Nout
R
H
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
15
MB90860A Series
Type
Circuit
Remarks
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time in-
put shutdown function)
Pout
Nout
• A/D analog input
R
I
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• D/A analg output
Pout
• CMOS hysteresis inputs (With the standby-
time input shutdown function)
• Automotive input (With the standby-time in-
put shutdown function)
Nout
R
• A/D analog input
Hysteresis inputs
J
Automotive inputs
Standby control for
input shutdown
Analog input
Analog output
• Power supply input protection circuit
K
• A/D converter reference voltage power
supply input pin, with the protection circuit
• Flash devices do not have a protection cir-
cuit against VCC for pin AVRH
ANE
AVR
L
ANE
(Continued)
16
MB90860A Series
(Continued)
Type
Circuit
Pout
Remarks
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
Nout
R
M
CMOS inputs
Automotive inputs
Standby control for
input shutdown
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
pull-up control
Pout
• TTL input (With the standby-time input
shutdown function)
Nout
Programmable pullup registor:50 kΩ
approx.
R
N
CMOS inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• CMOS level output(IOL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
Pout
Nout
• A/D analog input
R
O
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
17
MB90860A Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
• Initialization
• Port0 to port3 output during Power-on(External-bus mode)
• Flash security Function
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital
power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90860A Series
X0
Open
X1
4. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
18
MB90860A Series
5. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
VCC and VSS in the vicinity of VCC and VSS pins of the device
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90860A
Series
Vcc
Vss
Vcc
Vss
7. Pull-up/down resistors
The MB90860A Series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
8. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23)
after turning-on the digital power supply (VCC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously
is acceptable) .
10. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
19
MB90860A Series
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at
50 µs or more (0.2 V to 2.7 V)
12. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply
voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,
turn on the power again.
14. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.
V 5
DD
DD
V 3
Port0 to Port3
Port0 to 3 outputs
might be unstable
Port0 to 3 outputs = Hi-Z
15. Flash security Function
The security byte is located in the area of the flash memory.
If protection code 01H is written in the security byte, the flash memory is in the protected state by security.
Therefore please do not write 01H in this address if you do not use the security function.
Please refer to following table for the address of the security byte.
Flash memory size
Address for security byte
MB90F867A (S)
Embedded 1 Mbit Flash Memory
FE0001H
20
MB90860A Series
■ BLOCK DIAGRAMS
MB90V340(S)
X0,X1
X0A,X1A*
Clock
16LX
CPU
RST
Controller
FRCK0
IO Timer 0
RAM 30 K
Input
Capture
8 ch
IN7 to IN0
Output
Compare
8 ch
OUT7 to OUT0
FRCK1
Prescaler
5 ch
IO Timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
Controller
3 ch
UART
5 ch
RX2 to RX0
TX2 to TX0
AVCC
16-bit Reload
Timer 4 ch
TIN3 to TIN0
AVSS
TOT3 to TOT0
10-bit ADC
24 ch
AN23 to AN0
AVRH
AD15 to AD00
A23 to A16
ALE
AVRL
ADTG
RD
10-bit
DAC
2 ch
External
Bus
Interface
WRL
DA01, DA00
WRH
HRQ
HAK
8/16-bit
PPG
16 ch
PPGF to PPG0
RDY
CLK
I2C
Interface
2 ch
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
External
Interrupt
INT7 to INT0
DMAC
Clock
CKOT
Monitor
* : Only for MB90V340 ( without ‘S’ Suffix )
21
MB90860A Series
MB90F867A (S) , MB90867A (S)
X0,X1
X0A,X1A*
RST
Clock
16LX
CPU
Controller
FRCK0
IO Timer 0
RAM
6 K
Input
Capture
8 ch
IN7 to IN0
ROM/Flash
128 K
Output
Compare
8 ch
OUT7 to OUT0
FRCK1
Prescaler
4 ch
IO Timer 1
SOT3 to SOT0
SCK3 to SCK0
SIN3 to SIN0
UART
4 ch
AVCC
16-bit Reload
Timer 4 ch
TIN3 to TIN0
AVSS
TOT3 to TOT0
10-bit ADC
16/24 ch
AN15 to AN0
AN23 to AN16
AVRH
AD15 to AD00
A23 to A16
ALE
AVRL
ADTG
RD
External
Bus
Interface
WRL
WRH
8/16-bit
PPG
16 ch
HRQ
PPGF to PPG0
HAK
RDY
CLK
I2C
Interface
2 ch
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
External
Interrupt
(INT15R to INT8R)
INT7 to INT0
DMAC
Clock
Monitor
CKOT
* : Only for devices without ‘S’ Suffix
22
MB90860A Series
■ MEMORY MAP
MB90867A (S)
MB90F867A (S)
MB90V340 (S)
FFFFFFH
FFFFFFH
ROM(FF bank)
ROM(FE bank)
ROM(FF bank)
ROM(FE bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FE0000H
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH
ROM
00FFFFH
ROM
(Image of FF bank)
(Image of FF bank)
008000H
007FFFH
008000H
007FFFH
Peripheral
Peripheral
007900H
0078FFH
007900H
RAM 30 K
0018FFH
000100H
RAM 6 K
000100H
0000EFH
000000H
0000EFH
000000H
Peripheral
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
23
MB90860A Series
■ I/O MAP
Abbrevia-
tion
Address
Register
Port 0 Data Register
Access
Resource name
Initial value
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
ADER5
ADER6
ADER7
ILSR0
ILSR1
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
11111111
11111111
11111111
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000100
Port 1 Data Register
Port 2 Data Register
Port 2
Port 3 Data Register
Port 3
Port 4 Data Register
Port 4
Port 5 Data Register
Port 5
Port 6 Data Register
Port 6
Port 7 Data Register
Port 7
Port 8 Data Register
Port 8
Port 9 Data Register
Port 9
Port A Data Register
Port A
Port 5, A/D
Port 6, A/D
Port 7, A/D
Ports
Port 5 Analog Input Enable Register
Port 6 Analog Input Enable Register
Port 7 Analog Input Enable Register
Input Level Select Register 0
Input Level Select Register 1
Port 0 Direction Register
Port 1 Direction Register
Port 2 Direction Register
Port 3 Direction Register
Port 4 Direction Register
Port 5 Direction Register
Port 6 Direction Register
Port 7 Direction Register
Port 8 Direction Register
Port 9 Direction Register
Port A Direction Register
Ports
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Reserved
Port 0 Pullup Control Register
Port 1 Pullup Control Register
Port 2 Pullup Control Register
Port 3 Pullup Control Register
PUCR0
PUCR1
PUCR2
PUCR3
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
00000000
00000000
00000000
00000000
(Continued)
24
MB90860A Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
20H
21H
Serial Mode Register 0
Serial Control Register 0
SMR0
SCR0
W, R/W
W, R/W
00000000
00000000
RDR0/
TDR0
22H
23H
24H
Reception/Transmission Data Register 0
Serial Status Register 0
R/W
00000000
00001000
000000XX
SSR0
R, R/W
UART0
R, W,
R/W
Extended Communication Control Reg. 0 ECCR0
25H
26H
27H
28H
29H
Extended Status/Control Register 0
Baud Rate Generator Register 00
Baud Rate Generator Register 01
Serial Mode Register 1
ESCR0
BGR00
BGR01
SMR1
R/W
R/W
00000100
00000000
00000000
00000000
00000000
R/W
W, R/W
W, R/W
Serial Control Register 1
SCR1
RDR1/
TDR1
2AH
2BH
2CH
Reception/Transmission Data Register 1
Serial Status Register 1
R/W
00000000
00001000
000000XX
SSR1
R, R/W
UART1
R, W,
R/W
Extended Communication Control Reg. 1 ECCR1
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
Extended Status Control Register 1
Baud Rate Generator Register 10
Baud Rate Generator Register 11
ESCR1
BGR10
BGR11
R/W
R/W
00000100
00000000
00000000
0X000XX1
0X000001
000000X0
R/W
PPG 0 Operation Mode Control Register PPGC0
PPG 1 Operation Mode Control Register PPGC1
W, R/W
W, R/W
R/W
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
PPG 01 Clock Select Register
PPG01
Reserved
PPG 2 Operation Mode Control Register PPGC2
PPG 3 Operation Mode Control Register PPGC3
W, R/W
W, R/W
R/W
0X000XX1
0X000001
000000X0
PPG 23 Clock Select Register
PPG23
Reserved
PPG 4 Operation Mode Control Register PPGC4
PPG 5 Operation Mode Control Register PPGC5
W, R/W
W, R/W
R/W
0X000XX1
0X000001
000000X0
PPG 4 and PPG 5 Clock Select Register
PPG45
Program Address Detection Control
Status Register 1
Address Match
Detection 1
3BH
PACSR1
R/W
00000000
3CH
3DH
3EH
3FH
PPG 6 Operation Mode Control Register PPGC6
PPG 7 Operation Mode Control Register PPGC7
W, R/W
W, R/W
R/W
0X000XX1
0X000001
000000X0
16-bit PPG 6/7
PPG 67 Clock Select Register
PPG67
Reserved
(Continued)
25
MB90860A Series
Abbrevi-
ation
Address
Register
Access
Resource name
Initial value
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
PPG 8 Operation Mode Control Register
PPG 9 Operation Mode Control Register
PPG 89 Clock Select Register
PPGC8 W, R/W
PPGC9 W, R/W
0X000XX1
0X000001
000000X0
16-bit PPG 8/9
PPG89
R/W
Reserved
PPG A Operation Mode Control Register
PPG B Operation Mode Control Register
PPG AB Clock Select Register
PPGCA W, R/W
PPGCB W, R/W
0X000XX1
0X000001
000000X0
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
PPGAB
R/W
Reserved
PPG C Operation Mode Control Register
PPG D Operation Mode Control Register
PPG CD Clock Select Register
PPGCC W, R/W
PPGCD W, R/W
0X000XX1
0X000001
000000X0
PPGCD
R/W
Reserved
PPG E Operation Mode Control Register
PPG F Operation Mode Control Register
PPG EF Clock Select Register
PPGCE W, R/W
PPGCF W, R/W
0X000XX1
0X000001
000000X0
PPGEF
R/W
Reserved
Input Capture Control Status Register 0/1 ICS01
Input Capture Edge Register 0/1 ICE01
Input Capture Control Status Register 2/3 ICS23
Input Capture Edge Register 2/3 ICE23
Input Capture Control Status Register 4/5 ICS45
Input Capture Edge Register 4/5 ICE45
Input Capture Control Status Register 6/7 ICS67
Input Capture Edge Register 6/7 ICE67
R/W
R/W, R
R/W
R
00000000
XXX0X0XX
00000000
XXXXXXXX
00000000
XXXXXXXX
00000000
XXX000XX
0000XX00
0XX00000
0000XX00
0XX00000
0000XX00
0XX00000
0000XX00
0XX00000
(Continued)
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
R/W
R
R/W
R/W, R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Compare Control Status Register 0 OCS0
Output Compare Control Status Register 1 OCS1
Output Compare Control Status Register 2 OCS2
Output Compare Control Status Register 3 OCS3
Output Compare Control Status Register 4 OCS4
Output Compare Control Status Register 5 OCS5
Output Compare Control Status Register 6 OCS6
Output Compare Control Status Register 7 OCS7
26
MB90860A Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
60H
61H
Timer Control Status Register 0
Timer Control Status Register 0
Timer Control Status Register 1
Timer Control Status Register 1
Timer Control Status Register 2
Timer Control Status Register 2
Timer Control Status Register 3
Timer Control Status Register 3
A/D Control Status Register 0
A/D Control Status Register 1
A/D Data Register 0
TMCSR0
TMCSR0
TMCSR1
TMCSR1
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00000000
XXXX0000
00000000
XXXX0000
00000000
XXXX0000
00000000
XXXX0000
000XXXX0
0000000X
00000000
XXXXXX00
00000000
00000000
16-bit Reload Timer 0
62H
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
63H
64H
65H
66H
67H
68H
69H
ADCS1
6AH
ADCR0
A/D Converter
6BH
A/D Data Register 1
ADCR1
R
6CH
ADC Setting Register 0
ADSR0
R/W
R/W
6DH
ADC Setting Register 1
ADSR1
6EH
Reserved
ROMM
Reserved
Reserved
6FH
ROM Mirroring Register
W
ROM Mirror
XXXXXXX1
70H to 8FH
90H to 9AH
DMA Descriptor Channel Specification
Register
9BH
DCSR
R/W
00000000
DMA
9CH
9DH
DMA Status Register L
DMA Status Register H
DSRL
DSRH
R/W
R/W
00000000
00000000
Program Address Detection Control
Status Register 0
Address Match
Detection 0
9EH
9FH
A0H
PACSR0
DIRR
R/W
R/W
00000000
XXXXXXX0
00011000
Delayed Interrupt/Release
Delayed Interrupt
Low Power
Controller
Low-power Mode Control Register
LPMCR
W, R/W
Low Power
Controller
A1H
Clock Selection Register
CKSCR
R, R/W
11111100
A2H, A3H
A4H
Reserved
DMA Stop Status Register
DSSR
ARSR
HACR
ECSR
WDTC
TBTC
R/W
W
DMA
00000000
0011XX00
00000000
0000000X
XXXXX111
1XX00100
(Continued)
A5H
Automatic Ready Function Select Reg.
External Address Output Control Reg.
Bus Control Signal Selection Register
Watchdog Control Register
External Memory
Access
A6H
W
A7H
W
A8H
R, W
W, R/W
Watchdog Timer
Time Base Timer
A9H
Timebase Timer Control Register
27
MB90860A Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
AAH
ABH
ACH
ADH
Watch Timer Control Register
WTC
R, R/W
Watch Timer
1X001000
Reserved
DMA Enable Register L
DMA Enable Register H
DERL
DERH
R/W
R/W
00000000
00000000
DMA
Flash Control Status Register
(FlashDevices only.
AEH
FMCS
R, R/W
Flash Memory
000X0000
Otherwise reserved)
AFH
B0H
Reserved
Interrupt Control Register 00
Interrupt Control Register 01
Interrupt Control Register 02
Interrupt Control Register 03
Interrupt Control Register 04
Interrupt Control Register 05
Interrupt Control Register 06
Interrupt Control Register 07
Interrupt Control Register 08
Interrupt Control Register 09
Interrupt Control Register 10
Interrupt Control Register 11
Interrupt Control Register 12
Interrupt Control Register 13
Interrupt Control Register 14
Interrupt Control Register 15
D/A Converter Data 0
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
DAT0
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
R/W
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
00000111
XXXXXXXX
XXXXXXXX
XXXXXXX0
XXXXXXX0
B1H
B2H
B3H
B4H
B5H
B6H
B7H
Interrupt Controller
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
C0H
C1H
C2H
C3H
C4H, C5H
D/A Converter Data 1
DAT1
R/W
D/A Converter
D/A Control 0
DACR0
DACR1
R/W
D/A Control 1
R/W
Reserved
External Interrupt Request Enable
Register 0
C6H
ENIR0
R/W
00000000
C7H
C8H
C9H
External Interrupt Request Register 0
External Interrupt Level Register 0
External Interrupt Level Register 0
EIRR0
ELVR0
ELVR0
R/W
R/W
R/W
XXXXXXXX
00000000
00000000
(Continued)
External Interrupt 0
28
MB90860A Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
External Interrupt Request Enable
Register 1
CAH
ENIR1
R/W
00000000
CBH
CCH
CDH
External Interrupt Request Register 1
External Interrupt Level Register 1
External Interrupt Level Register 1
EIRR1
ELVR1
ELVR1
R/W
R/W
R/W
XXXXXXXX
00000000
00000000
External Interrupt 1
External Interrupt Source Select
Register
CEH
EISSR
R/W
00000000
CFH
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
PLL/Subclock Control Register
DMA Buffer Address Pointer L
DMA Buffer Address Pointer M
DMA Buffer Address Pointer H
DMA Control Register
PSCCR
BAPL
BAPM
BAPH
DMACS
IOAL
W
R/W
PLL
XXXX0000
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
R/W
R/W
R/W
DMA
I/O Register Address Pointer L
I/O Register Address Pointer H
Data Counter L
R/W
IOAH
R/W
DCTL
DCTH
SMR2
SCR2
R/W
Data Counter H
R/W
Serial Mode Register 2
W, R/W
W, R/W
Serial Control Register 2
00000000
Reception/Transmission Data
Register 2
RDR2/
TDR2
DAH
DBH
DCH
R/W
00000000
00001000
000000XX
Serial Status Register 2
SSR2
R, R/W
UART2
Extended Communication Control
Register 2
R, W,
R/W
ECCR2
DDH
DEH
Extended Status/Control Register 2
Baud Rate Reload Register 20
Baud Rate Reload Register 21
ESCR2
BGR20
BGR21
R/W
R/W
R/W
00000100
00000000
00000000
DFH
E0H to EFH
F0H to FFH
Reserved
External
(Continued)
29
MB90860A Series
Abbrevia-
tion
Address
Register
Reload Register L0
Access
Resource name
Initial value
7900H
7901H
7902H
7903H
7904H
7905H
7906H
7907H
7908H
7909H
PRLL0
PRLH0
PRLL1
PRLH1
PRLL2
PRLH2
PRLL3
PRLH3
PRLL4
PRLH4
PRLL5
PRLH5
PRLL6
PRLH6
PRLL7
PRLH7
PRLL8
PRLH8
PRLL9
PRLH9
PRLLA
PRLHA
PRLLB
PRLHB
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
(Continued)
Reload Register H0
Reload Register L1
Reload Register H1
Reload Register L2
Reload Register H2
Reload Register L3
Reload Register H3
Reload Register L4
Reload Register H4
16-bit PPG 0/1
16-bit PPG 2/3
16-bit PPG 4/5
16-bit PPG 6/7
16-bit PPG 8/9
16-bit PPG A/B
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
790AH Reload Register L5
790BH Reload Register H5
790CH Reload Register L6
790DH Reload Register H6
790EH Reload Register L7
790FH Reload Register H7
7910H
7911H
7912H
7913H
7914H
7915H
7916H
7917H
7918H
7919H
Reload Register L8
Reload Register H8
Reload Register L9
Reload Register H9
Reload Register LA
Reload Register HA
Reload Register LB
Reload Register HB
Reload Register LC
Reload Register HC
791AH Reload Register LD
791BH Reload Register HD
791CH Reload Register LE
791DH Reload Register HE
791EH Reload Register LF
791FH Reload Register HF
7920H
7921H
7922H
7923H
Input Capture Data Register 0
Input Capture Data Register 0
Input Capture Data Register 1
Input Capture Data Register 1
R
R
R
30
MB90860A Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
7924H
7925H
7926H
7927H
7928H
7929H
Input Capture Data Register 2
Input Capture Data Register 2
Input Capture Data Register 3
Input Capture Data Register 3
Input Capture Data Register 4
Input Capture Data Register 4
IPCP2
IPCP2
R
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
R
Input Capture 2/3
IPCP3
R
IPCP3
R
IPCP4
R
IPCP4
R
Input Capture 4/5
Input Capture 6/7
Output Compare 0/1
Output Compare 2/3
Output Compare 4/5
Output Compare 6/7
I/O Timer 0
792AH Input Capture Data Register 5
792BH Input Capture Data Register 5
792CH Input Capture Data Register 6
792DH Input Capture Data Register 6
792EH Input Capture Data Register 7
792FH Input Capture Data Register 7
IPCP5
R
IPCP5
R
IPCP6
R
IPCP6
R
IPCP7
R
IPCP7
R
7930H
7931H
7932H
7933H
7934H
7935H
7936H
7937H
7938H
7939H
Output Compare Register 0
Output Compare Register 0
Output Compare Register 1
Output Compare Register 1
Output Compare Register 2
Output Compare Register 2
Output Compare Register 3
Output Compare Register 3
Output Compare Register 4
Output Compare Register 4
OCCP0
OCCP0
OCCP1
OCCP1
OCCP2
OCCP2
OCCP3
OCCP3
OCCP4
OCCP4
OCCP5
OCCP5
OCCP6
OCCP6
OCCP7
OCCP7
TCDT0
TCDT0
TCCSL0
TCCSH0
TCDT1
TCDT1
TCCSL1
TCCSH1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
793AH Output Compare Register 5
793BH Output Compare Register 5
793CH Output Compare Register 6
793DH Output Compare Register 6
793EH Output Compare Register 7
793FH Output Compare Register 7
7940H
7941H
7942H
7943H
7944H
7945H
7946H
7947H
Data Register 0
Data Register 0
00000000
Control Status Register 0
Control Status Register 0
Data Register 1
00000000
0XXXXXXX
00000000
Data Register 1
00000000
I/O Timer 1
Control Status Register 1
Control Status Register 1
00000000
0XXXXXXX
(Continued)
31
MB90860A Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
7948H
7949H
794AH
794BH
794CH
794DH
794EH
794FH
7950H
7951H
R/W
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
TMR0/
TMRLR0
16-bit Reload
Timer 0
Timer Register 0/Reload Register 0
R/W
TMR1/
TMRLR1
16-bit Reload
Timer 1
Timer Register 1/Reload Register 1
Timer Register 2/Reload Register 2
Timer Register 3/Reload Register 3
R/W
R/W
TMR2/
TMRLR2
16-bit Reload
Timer 2
R/W
R/W
TMR3/
TMRLR3
16-bit Reload
Timer 3
R/W
Serial Mode Register 3
Serial Control Register 3
SMR3
SCR3
W, R/W
W, R/W
00000000
RDR3/
TDR3
7952H
7953H
7954H
Reception/Transmission Data Register 3
Serial Status Register 3
R/W
00000000
00001000
000000XX
SSR3
R, R/W
UART3
R, W,
R/W
Extended Communication Control Reg. 3 ECCR3
7955H
7956H
7957H
7958H
7959H
Extended Status/Control Register 3
Baud Rate Reload Register 30
Baud Rate Reload Register 31
Serial Mode Register 4
ESCR3
BGR30
BGR31
SMR4
R/W
R/W
00000100
00000000
00000000
00000000
00000000
R/W
W, R/W
W, R/W
Serial Control Register 4
SCR4
RDR4/
TDR4
795AH Reception/Transmission Data Register 4
795BH Serial Status Register 4
R/W
00000000
00001000
000000XX
SSR4
R, R/W
UART4
R, W,
R/W
795CH Extended Communication Control Reg. 4 ECCR4
795DH Extended Status/Control Register 4
795EH Baud Rate Reload Register 40
795FH Baud Rate Reload Register 41
ESCR4
BGR40
BGR41
R/W
R/W
R/W
00000100
00000000
00000000
7960H to
796BH
Reserved
796CH Clock Output Enable Register
CLKR
R/W
Clock Monitor
XXXX0000
(Continued)
796DH to
796FH
Reserved
32
MB90860A Series
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
7970H
7971H
7972H
7973H
7974H
7975H
7976H
7977H
7978H
I2C Bus Status Register 0
I2C Bus Control Register 0
IBSR0
IBCR0
ITBAL0
ITBAH0
ITMKL0
ITMKH0
ISBA0
R
W, R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000
00000000
00000000
00000000
11111111
00111111
00000000
01111111
00000000
I2C 10-bit Slave Address Register 0
I2C Interface 0
I2C 10-bit Slave Address Mask Register 0
I2C 7-bit Slave Address Register 0
I2C 7-bit Slave Address Mask Register 0
I2C Data Register 0
ISMK0
IDAR0
7979H,
797AH
Reserved
797BH I2C Clock Control Register 0
ICCR0
R/W
I2C Interface 0
00011111
797CH to
797FH
Reserved
7980H
7981H
7982H
7983H
7984H
7985H
7986H
7987H
7988H
I2C Bus Status Register 1
I2C Bus Control Register 1
IBSR1
IBCR1
ITBAL1
ITBAH1
ITMKL1
ITMKH1
ISBA1
R
W, R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00000000
00000000
00000000
00000000
11111111
00111111
00000000
01111111
00000000
I2C 10-bit Slave Address Register 1
I2C Interface 1
I2C 10-bit Slave Address Mask Register 1
I2C 7-bit Slave Address Register 1
I2C 7-bit Slave Address Mask Register 1
I2C Data Register 1
ISMK1
IDAR1
7989H,
798AH
Reserved
ICCR1
798BH I2C Clock Control Register 1
R/W
I2C Interface 1
Clock Modulator
00011111
0001X000
(Continued)
798CH to
79C1H
Reserved
CMCR
79C2H Clock Modulator Control Register
R, R/W
79C3H to
79DFH
Reserved
33
MB90860A Series
(Continued)
Abbrevia-
tion
Address
Register
Access
Resource name
Initial value
79E0H Program Address Detection Register 0
79E1H Program Address Detection Register 0
79E2H Program Address Detection Register 0
79E3H Program Address Detection Register 1
79E4H Program Address Detection Register 1
79E5H Program Address Detection Register 1
79E6H Program Address Detection Register 2
79E7H Program Address Detection Register 2
79E8H Program Address Detection Register 2
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Address Match
Detection 0
79E9H to
79EFH
Reserved
79F0H Program Address Detection Register 3
79F1H Program Address Detection Register 3
79F2H Program Address Detection Register 3
79F3H Program Address Detection Register 4
79F4H Program Address Detection Register 4
79F5H Program Address Detection Register 4
79F6H Program Address Detection Register 5
79F7H Program Address Detection Register 5
79F8H Program Address Detection Register 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Address Match
Detection 1
79F9H to
7FFFH
Reserved
Notes : • Initial value of “X” represents unknown value.
• Addresses in the range 0000H to 00BFH, which are not listed in the table, are reserved for the primary
functions of the MCU. A read access to these reserved addresses results reading “X” and any write
access should not be performed.
34
MB90860A Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
EI2OS
clear
DMA ch
number
register
Interrupt cause
Number
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
Address
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
Number
Address
Reset
N
N
INT9 instruction
Exception
N
(Reserved)
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
(Reserved)
N
Input Capture 6
Y1
Y1
N
Input Capture 7
I2C0
(Reserved)
N
16-bit Reload Timer 0
16-bit Reload Timer 1
16-bit Reload Timer 2
16-bit Reload Timer 3
PPG 0/1/4/5
Y1
Y1
Y1
Y1
N
0
1
2
PPG 2/3/6/7
N
PPG 8/9/C/D
N
PPG A/B/E/F
N
Time Base Timer
External Interrupt 0 to 3, 8 to 11
Watch Timer
N
Y1
N
3
External Interrupt 4 to 7, 12 to 15
A/D Converter
Y1
Y1
N
4
5
I/O Timer 0 / I/O Timer 1
Input Capture 4/5 / I2C1
Output Compare 0/1/4/5
Input Capture 0 to 3
Output Compare 2/3/6/7
UART 0 RX
Y1
Y1
Y1
Y1
Y2
Y1
Y2
Y1
6
7
8
9
10
11
12
13
UART 0 TX
UART 1 RX / UART 3 RX
UART 1 TX / UART 3 TX
0000BDH
(Continued)
35
MB90860A Series
(Continued)
Interrupt control
register
Interrupt vector
Number Address
EI2OS
clear
DMA ch
number
Interrupt cause
Number
Address
UART 2 RX / UART 4 RX
UART 2 TX / UART 4 TX
Flash Memory
Y2
Y1
N
14
15
#39
#40
#41
#42
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
ICR14
0000BEH
0000BFH
ICR15
Delayed interrupt
N
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N
: Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.
• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.
36
MB90860A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0 V)
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
AVCC
VCC = AVCC *1
Power supply voltage
AVRH,
AVRL
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH ≥ AVRL
VSS − 0.3 VSS + 6.0
V
Input voltage
VI
VO
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
*2
*2
Output voltage
Maximum Clamp Current
ICLAMP
Σ|ICLAMP|
IOL
−4.0
+4.0
40
mA *4
mA *4
mA *3
mA *3
mA *3
mA *3
mA *3
mA *3
mA *3
mA *3
mW MB90F867A
°C
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level average overall output current
Power consumption
15
IOLAV
ΣIOL
4
100
50
ΣIOLAV
IOH
−15
−4
IOHAV
ΣIOH
ΣIOHAV
PD
−100
−50
340
+105
+150
Operating temperature
TA
−40
−55
Storage temperature
TSTG
°C
(Continued)
37
MB90860A Series
(Continued)
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun
current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating.
*3: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67
P70 to P77, P80 to P87, P90 to P97, PA0 to PA1
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
MB90860A Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
4.0
5.0
5.5
V
V
Under normal operation
Under normal operation, when not
using the A/D converter and not
Flash programming.
3.5
5.0
5.0
5.5
VCC,
AVCC
Power supply voltage
4.5
3.0
5.5
5.5
V
V
When External bus is used.
Maintains RAM data in stop mode
Use a ceramic capacitor or capac-
itor of better AC characteristics.
Capacitor at the VCC should be
greater than this capacitor.
Smooth capacitor
CS
0.1
1.0
µF
°C
Operating temperature
TA
−40
+105
C
CS
C Pin Connection Diagram
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
39
MB90860A Series
3. DC Characteristics
Sym-
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
Port inputs if CMOS
hysteresis input levels
are selected (except
UART SIN input pins
and I2C input pins)
VIHS
0.8 VCC
VCC + 0.3
V
Port inputs if
AUTOMOTIVE input
levels are selected
VIHA
VIHT
VIHS
0.8 VCC
2.0
VCC + 0.3
VCC + 0.3
VCC + 0.3
V
V
V
Input H
voltage
(At VCC =
5 V ± 10%)
Port inputs if TTL input
levels are selected
UART SIN inputs if
CMOS input levels are
selected
0.7 VCC
I2C Port inputs if CMOS
hysteresis input levels
are selected
VIHI
0.7 VCC
VCC + 0.3
V
RST input pin (CMOS
hysteresis)
VIHR
0.8 VCC
VCC + 0.3
VCC + 0.3
V
V
VIHM
VCC − 0.3
MD input pin
Port inputs if CMOS
hysteresis input levels
are selected (except
UART SIN input pins
and I2C input pins)
VILS
VSS − 0.3
0.2 VCC
V
Port inputs if
AUTOMOTIVE input
levels are selected
VILA
VILT
VILS
VSS − 0.3
VSS − 0.3
VSS − 0.3
0.5 VCC
0.8
V
V
V
Input L
voltage
(At VCC =
5 V ± 10%)
Port inputs if TTL
input levels are selected
UART SIN inputs if
CMOS input levels are
selected
0.3 VCC
I2C Port inputs if CMOS
hysteresis input levels
are selected
VILI
VSS − 0.3
0.3 VCC
V
RST input pin (CMOS
hysteresis)
VILR
VILM
VOH
VSS − 0.3
VSS − 0.3
VCC − 0.5
0.2 VCC
V
V
V
VSS + 0.3
MD input pin
Output H
voltage
Normal
outputs
VCC = 4.5 V,
IOH = −4.0 mA
Output H
voltage
I2Ccurrent VCC = 4.5 V,
VOHI
VOL
VOLI
VCC − 0.5
V
V
V
outputs
IOH = −3.0 mA
Output L
voltage
Normal
outputs
VCC = 4.5 V,
IOL = 4.0 mA
0.4
0.4
Output L
voltage
I2Ccurrent VCC = 4.5 V,
outputs IOL = 3.0 mA
(Continued)
40
MB90860A Series
(Continued)
(TA = −40 °C to +105, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit Remarks
Min Typ Max
Input leak current
IIL
VCC = 5.5 V, VSS < VI < VCC
−1
1
µA
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
Pull-up
resistance
RUP
25
50
100 kΩ
100 kΩ
Pull-down
resistance
ExceptFlash
devices
RDOWN
MD2
25
50
55
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
70
85
90
35
0.8
mA MB90F867A
mA MB90F867A
mA MB90F867A
mA MB90F867A
mA MB90F867A
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing FLASH memory.
ICC
70
75
25
0.3
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing FLASH memory.
VCC = 5.0 V,
Internal frequency : 24 MHz,
At Sleep mode.
ICCS
VCC = 5.0 V,
Internal frequency : 2 MHz,
At Main Timer mode
ICTS
VCC = 5.0 V,
Power supply
current*
Internal frequency : 24 MHz,
At PLL Timer mode,
external frequency = 4 MHz
VCC
ICTSPLL6
4
7
mA MB90F867A
VCC = 5.0V
Internal frequency: 8 kHz,
At sub operation
TA = +25°C
ICCL
170
20
360 µA MB90F867A
VCC = 5.0V
Internal frequency: 8 kHz,
At sub sleep
ICCLS
50
35
µA MB90F867A
µA MB90F867A
TA = +25°C
VCC = 5.0V
Internal frequency: 8 kHz,
At watch mode
TA = +25°C
ICCT
10
VCC = 5.0 V,
At Stop mode,
TA = +25°C
ICCH
7
5
25
15
µA MB90F867A
Other than C, AVCC, AVSS,
AVRH, AVRL, VCC, VSS,
Input capacity
CIN
pF
* : Current values are tentative. They are subject to change without notice according to improvements in the
characteristics. The power supply current is measured with an external clock.
41
MB90860A Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
When using an oscillation
circuit
X0, X1
3
16
MHz
fC
Clock frequency
When using an external
clock*
X0
3
24
MHz
kHz
ns
fCL
X0A, X1A
X0, X1
—
32.768 100
333
When using an oscillation
circuit
62.5
tCYL
Clock cycle time
When using an external
clock
X0
41.67
333
ns
tCYLL
PWH, PWL
PWHL, PWLL
tCR, tCF
fCP
X0A, X1A
X0
10
10
5
30.5
15.2
—
µs
ns
µs
ns
Duty ratio is about 30% to
70%.
Input clock pulse width
X0A
Input clock rise and fall time
X0
5
When using external clock
1.5
24
MHz When using main clock
kHz When using sub clock
Internal operating clock
frequency (machine clock)
fCPL
8.192
122.1
50
tCP
41.67
20
666
ns
When using main clock
When using sub clock
Internal operating clock
cycle time (machine clock)
tCPL
µs
* : Whem selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as
mentioned in “Relation among external clock frequency and machine clock frequency”.
tCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCF
tCR
tCYLL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
tCF
tCR
Clock Timing
42
MB90860A Series
• Guaranteed PLL operation range
Guaranteed operation range
Guaranteed PLLL operation range (CS2=1)
5.5
4.5
Guaranteed A/D converter
operation range
3.5
Guaranteed PLL operation range (CS=0)
1.5
4
8
20
24
Machine clock fCP (MHz)
Guaranteed operation range of MB90860A Series
CS2 (bit0 in PSCCR reigster) = 0
Guaranteed operation frequency range*2
×4
×3
×2
(CS=11) (CS=10) (CS=01)
×1
(CS=00)
20
16
12
8
×1/2
(PLL off)
4.0
1.5
3
4
8
12
20
24
16
1
External clock fC (MHz)
CS2 (bit0 in PSCCR reigster) = 1
Guaranteed operation frequency range*2
×6
×4
×2
(CS=10) (CS=01)
(CS=00)
24
16
12
8
×1/2
(PLL off)
4.0
1.5
3
4
8
12
24
16
1
External clock fC (MHz)
*1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 20 MHz.
*2 : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.
External clock frequency and Machine clock frequency
43
MB90860A Series
(2) Reset Standby Input
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Value
Parameter Symbol
Pin
Unit
Remarks
Min
Max
500
ns
Under normal operation
In Stop mode, Sub Clock
mode, Sub Sleep mode
and Watch mode
Reset input
tRSTL
Oscillation time of oscillator*
RST
ns
time
+ 100 µs
100
µs
In Time Timer mode
* : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators,
the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation:
tRSTL
RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100
s
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
44
MB90860A Series
(3) Power On Reset
(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
0.05
1
Max
Power on rise time
Power off time
tR
VCC
VCC
30
ms
tOFF
ms Due to repetitive operation
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
Holds RAM data
3 V
VSS
45
MB90860A Series
(4) Bus Timing (Read)
(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Value
Sym-
bol
Parameter
ALE pulse width
Valid address
Pin
Condition
Unit Remarks
Min
Max
tLHLL
ALE
tCP/2 − 10
ns
ALE, A23 to
A16, AD15
to AD00
ALE ↓ time
tAVLL
tCP/2 − 15
tCP/2 − 15
tCP − 15
ns
ns
ns
ALE, AD15
to AD00
ALE ↓
Address valid time
tLLAX
A23 toA16,
AD15 to
Valid address
RD ↓ time
tAVRL
AD00, RD
A23 to A16,
AD15 to
AD00
Valid address
input
Valid data
tAVDV
5 tCP/2 − 40
3 tCP/2 − 50
ns
RD pulse width
tRLRH
tRLDV
RD
3 tCP/2 − 20
ns
ns
RD, AD15 to
AD00
RD ↓
Valid data input
Data hold time
RD, AD15 to
AD00
RD ↑
RD ↓
RD ↑
tRHDX
tRHLH
tRHAX
0
ns
ns
ns
ALE ↑ time
RD, ALE
tCP/2 − 15
tCP/2 − 10
RD, A23 to
A16
Address valid time
A23 to A16,
AD15 to
Valid address
CLK ↑ time
tAVCH
tCP/2 − 15
ns
AD00, CLK
RD ↓
CLK ↑ time
RD ↓ time
tRLCH
tLLRL
RD, CLK
ALE, RD
tCP/2 − 15
tCP/2 − 15
ns
ns
ALE ↓
46
MB90860A Series
tRLCH
tAVCH
2.4 V
2.4 V
CLK
ALE
RD
tLLAX
tAVLL
tRHLH
2.4 V
2.4 V
0.8 V
2.4 V
tLHLL
tAVRL
tRLRH
2.4 V
0.8 V
tLLRL
tRHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tRLDV
tRHDX
tAVDV
2.4 V
0.8 V
VIH
VIL
2.4 V
0.8 V
VIH
VIL
AD15 to AD00
Address
Read data
47
MB90860A Series
(5) Bus Timing (Write)
(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Value
Parameter
Symbol
Pin
Condition
Unit Remarks
Min
Max
A23 to A16,
AD15 to AD00,
WR
Valid address
WR ↓ time
WR ↑
tAVWL
tCP−15
ns
WR pulse width
tWLWH
tDVWH
WR
3 tCP/2 − 20
3 tCP/2 − 20
ns
ns
Valid data output
time
AD15 to AD00,
WR
AD15 to AD00,
WR
WR ↑
WR ↑
Data hold time
tWHDX
tWHAX
15
ns
ns
A23 to A16,
WR
Address valid time
tCP/2 − 10
WR ↑
WR ↓
ALE ↑ time
CLK ↑ time
tWHLH
tWLCH
WR, ALE
WR, CLK
tCP/2 − 15
tCP/2 − 15
ns
ns
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tAVWL
tWLWH
2.4 V
WR (WRL, WRH)
0.8 V
tWHAX
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A16
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to AD00
Address
Write data
48
MB90860A Series
(6) Ready Input Timing
Parameter
(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Value
Sym-
bol
Test
Condition
Pin
Units Remarks
Min
45
0
Max
RDY setup time
RDY hold time
tRYHS
RDY
RDY
ns
ns
tRYHH
Note : If the RDY setup time is insufficient, use the auto-ready function.
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
VIH
VIH
RDY
When WAIT is not used.
RDY
VIL
When WAIT is used.
49
MB90860A Series
(7) Hold Timing
(TA = –40°C to +85°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V, Machine Clock ≤ 16 MHz)
Value
Parameter
Symbol
Pin
Condition
Units
Remarks
Min
Max
Pin floating
time
HAK ↓
tXHAL
tHAHV
HAK
HAK
30
tCP
ns
ns
HAK ↑ time
time
Pin valid
tCP
2 tCP
Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed.
2.4V
HAK
0.8V
tHAHV
tXHAL
High-Z
2.4V
0.8V
2.4V
0.8V
Each pin
50
MB90860A Series
(8) UART0/1/2/3/4
Parameter
(TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)
Value
Symbol
Pin
Condition
Unit Remarks
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK4
8 tCP
ns
ns
SCK0 to SCK4,
SOT0 to SOT4
SCK ↓ → SOT delay time
tSLOV
−80
100
60
+80
Internal clock
operation output
pins are
SCK0 to SCK4,
SIN0 to SIN4
Valid SIN → SCK ↑
tIVSH
tSHIX
ns
ns
CL = 80 pF + 1 TTL.
SCK0 to SCK4,
SIN0 to SIN4
SCK ↑ → Valid SIN hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
SCK0 to SCK4
SCK0 to SCK4
4 tCP
ns
ns
tSLSH
4 tCP
SCK0 to SCK4, External clock
SOT0 to SOT4 operation output
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOV
tIVSH
tSHIX
150
ns
ns
ns
pins are
CL = 80 pF + 1 TTL.
SCK0 to SCK4,
SIN0 to SIN4
60
60
SCK0 to SCK4,
SIN0 to SIN4
SCK ↑ → Valid SIN hold time
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine cycle (Unit : ns)
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
tSHIX
VIH
VIL
VIH
VIL
SIN
Internal Shift Clock Mode
51
MB90860A Series
tSLSH
tSHSL
VIH
VIH
SCK
SOT
VIL
tSLOV
VIL
2.4 V
0.8 V
tIVSH
tSHIX
VIH
VIL
VIH
VIL
SIN
External Shift Clock Mode
(9) Trigger Input Timing
(TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
INT0 to INT15,
INT0R to INT15R,
ADTG
tTRGH
tTRGL
Input pulse width
5 tCP
ns
VIH
VIH
INT0 to INT15,
VIL
VIL
INT0R to INT15R,
ADTG
tTRGH
tTRGL
52
MB90860A Series
(10) Timer Related Resource Input Timing
(TA = −40 °C to +105 °C, VCC = 4.5 V to 5.5 V, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
tTIWH
tTIWL
TIN0 to TIN3
IN0 to IN7
Input pulse width
4 tCP
ns
VIH
VIH
VIL
VIL
TIN0 to TIN3,
IN0 to IN7
tTIWH
tTIWL
(11) Timer Related Resource Output Timing
(TA = –40° to +105°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Remarks
Min
Max
TOT0 to TOT3,
PPG0 to PPGF
CLK ↑
TOUT change time
tTO
30
ns
2.4 V
CLK
2.4 V
0.8 V
TOT0 to TOT3,
PPG0 to PPGF
tTO
53
MB90860A Series
(12) I2C Timing
(TA = –40°C to +105°C, VCC = 4.5 V to 5.5 V, VSS = 0.0 V)
Fast-mode*4
Standard-mode
Parameter
Symbol Condition
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA ↓ → SCL ↓
tHDSTA
4.0
0.6
µs
“L” width of the SCL clock
“H” width of the SCL clock
tLOW
4.7
4.0
1.3
0.6
µs
µs
tHIGH
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
4.7
0
0.6
0
µs
µs
ns
µs
µs
R = 1.7 kΩ,
C = 50 pF*1
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
3.45*2
0.9*3
Data set-up time
SDA ↓ ↑ → SCL ↑
tSUDAT
tSUSTO
tBUS
250
4.0
4.7
100
0.6
1.3
Set-up time for STOP condition
SCL ↑ → SDA ↑
Bus free time between a STOP and START
condition
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tBUS
tSUDAT
tHDSTA
tLOW
SCL
tHIGH
tHDSTA
tHDDAT
tSUSTA
tSUSTO
54
MB90860A Series
5. A/D Converter
(T
A
= −40 °C to +105 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
10
Resolution
bit
Total error
±3.0
±2.5
LSB
LSB
Nonlinearity error
Differential
nonlinearity error
±1.9
LSB
Zero reading
voltage
VOT
AN0 to AN23 AVRL − 1.5 AVRL + 0.5 AVRL + 2.5 LSB
Full scale reading
voltage
VFST
AN0 to AN23 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB
1.0
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
16,500
µs
µs
2.0
0.5
1.2
∞
Analog port input
current
IAIN
AN0 to AN23
AN0 to AN23
−0.3
+0.3
µA
Analog input
voltage range
VAIN
AVRL
AVRH
V
AVRH
AVRL
AVCC
AVRL + 2.7
AVCC
V
V
Reference
voltage range
0
AVRH − 2.7
IA
IAH
IR
3.5
7.5
5
mA
µA
µA
µA
Power supply
current
AVCC
*
*
AVRH
AVRH
600
900
5
Reference
voltage current
IRH
Offset between
input channels
AN0 to AN23
4
LSB
* : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as AVRH − AVRL becomes smaller.
55
MB90860A Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity
error
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
Total error
: Difference between an actual value and an ideal value. A total error includes zero transition
error, full-scale transition error, and linear error.
Zero reading
voltage
: Input voltage which results in the minimum conversion value.
Full scale
: Input voltage which results in the maximum conversion value.
reading voltage
Total error
3FF
1.5 LSB
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004
003
002
001
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
(Continued)
56
MB90860A Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
3FE
3FD
Actual conversion
characteristics
{1 LSB × (N − 1)
N + 1
Actual conversion
characteristics
+ VOT }
VFST (actual
measurement
value)
N
VNT (actual
measurement value)
004
003
002
001
V (N + 1) T
(actual measurement
value)
Actual conversion
characteristics
N − 1
N − 2
VNT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
VOT (actual measurement value)
Analog input
AVRL
AVRH
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
57
MB90860A Series
7. Notes on A/D Converter Section
Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period ≤ 0.5 µs)
if the output inpedance exceeds 1.5 kΩ, set a longer sampling time or add an external capacitor compensate
the output inpedance. About setting of sampling time, please refer to hardware manual of MB90860A series.
If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient.
• Analog input circuit model
R
Analog input
Comparator
C
4.5 V ≤ AVCC ≤ 5.5 V : R=: 2.52 kΩ, C=: 10.7 pF
4.0 V ≤ AVCC < 4.5 V : R=: 13.6 kΩ, C=: 10.7 pF
Note : Use the values in the figure only as a guideline.
8. Flash Memory Program/Erase Characteristics
Value
Parameter
Conditions
Unit
Remarks
Min
Typ
Max
Excludes programming
prior to erasure
Sector erase time
Chip erase time
1
15
s
s
TA = +25 °C
VCC = 5.0 V
Excludes programming
prior to erasure
9
Word (16 bit width)
programming time
Except for the over head
time of the system
16
3,600
µs
Programs/Erase cycle
10,000
20
cycle
Year
Flash Data Retention
Time
Average
TA = +85 °C
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
58
MB90860A Series
■ ORDERING INFORMATION
Part number
MB90F867APF
Package
Remarks
MB90F867ASPF
MB90867APF
100-pin Plastic QFP
(FPT-100P-M06)
MB90867ASPF
MB90F867APFV
MB90F867ASPFV
MB90867APFV
MB90867ASPFV
100-pin Plastic LQFP
(FPT-100P-M05)
MB90V340
MB90V340S
299-pin Ceramic PGA
(PGA-299C-A01)
For evaluation
59
MB90860A Series
■ PACKAGE DIMENSIONS
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness including plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
100-pin Plastic QFP
(FPT-100P-M06)
23.90±0.40(.941±.016)
*
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00 +–00..2305
.118 +–..000184
(Mounting height)
0~8˚
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.17±0.06
(.007±.002)
M
0.13(.005)
0.25±0.20
(.010±.008)
(Stand off)
0.80±0.20
(.031±.008)
"A"
0.88±0.15
(.035±.006)
C
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
60
MB90860A Series
(Continued)
100-pin Plastic LQFP
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
(FPT-100P-M05)
16.00±0.20(.630±.008)SQ
*
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +–00..1200 .059 –+..000048
(Mounting height)
INDEX
0.10±0.10
(.004±.004)
(Stand off)
100
26
0˚~8˚
"A"
0.50±0.20
(.020±.008)
0.25(.010)
1
25
0.60±0.15
(.024±.006)
0.50(.020)
0.20±0.05
(.008±.002)
0.145±0.055
(.0057±.0022)
M
0.08(.003)
C
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
61
MB90860A Series
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0405
FUJITSU LIMITED Printed in Japan
相关型号：
©2020 ICPDF网 联系我们和版权申明