FPD1050 [FILTRONIC]

0.75W POWER PHEMT; 0.75W功率pHEMT制
FPD1050
型号: FPD1050
厂家: FILTRONIC COMPOUND SEMICONDUCTORS    FILTRONIC COMPOUND SEMICONDUCTORS
描述:

0.75W POWER PHEMT
0.75W功率pHEMT制

晶体 晶体管 放大器
文件: 总2页 (文件大小:178K)
中文:  中文翻译
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FPD1050  
0.75W POWER PHEMT  
SOURCE  
BOND  
DRAIN  
FEATURES  
BOND  
PAD (2x)  
28.5 dBm Linear Output Power at 12 GHz  
11 dB Power Gain at 12 GHz  
14 dB Maximum Stable Gain at 12 GHz  
41 dBm Output IP3  
PAD (2X)  
GATE  
BOND  
45% Power-Added Efficiency  
PAD (1X)  
DIE SIZE: 470 x 440 µm  
DIE THICKNESS: 100 µm  
BONDING PADS: >85 x 60 µm  
DESCRIPTION AND APPLICATIONS  
The FPD1050 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT),  
featuring a 0.25 µm by 1050 µm Schottky barrier gate, defined by high-resolution stepper-based  
photolithography. The recessed and offset Gate structure minimizes parasitics to optimize  
performance. The epitaxial structure and processing have been optimized for reliable high-power  
applications. The FPD750 also features Si3N4 passivation and is also available in a low cost plastic  
SOT89 plastic package.  
Typical applications include commercial and other narrowband and broadband high-performance  
amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output  
amplifiers, and medium-haul digital radio transmitters.  
ELECTRICAL SPECIFICATIONS AT 22°C  
Parameter  
Symbol  
Test Conditions  
Min  
Typ  
Max Units  
RF SPECIFICATIONS MEASURED AT f = 12 GHz USING CW SIGNAL  
Power at 1dB Gain Compression  
Maximum Stable Gain (S21/S12)  
Power Gain at P1dB  
P1dB  
MSG  
G1dB  
PAE  
VDS = 8 V; IDS = 50% IDSS  
VDS = 8 V; IDS = 50% IDSS  
VDS = 8 V; IDS = 50% IDSS  
27.5  
10.0  
28.5  
14.0  
11.0  
45  
dBm  
dB  
dB  
%
Power-Added Efficiency  
V
DS = 8 V; IDS = 50% IDSS  
;
POUT = P1dB  
Output Third-Order Intercept Point  
IP3  
V
DS = 10V; IDS = 50% IDSS  
(from 15 to 5 dB below P1dB  
)
Matched for optimal power  
Tuned for best IP3  
39  
41  
dBm  
Saturated Drain-Source Current  
Maximum Drain-Source Current  
Transconductance  
Gate-Source Leakage Current  
Pinch-Off Voltage  
Gate-Source Breakdown Voltage  
Gate-Drain Breakdown Voltage  
Thermal Resistivity (see Notes)  
IDSS  
IMAX  
GM  
IGSO  
|VP|  
VDS = 1.3 V; VGS = 0 V  
VDS = 1.3 V; VGS +1 V  
VDS = 1.3 V; VGS = 0 V  
VGS = -5 V  
VDS = 1.3 V; IDS = 1 mA  
IGS = 1 mA  
250  
315  
520  
280  
15  
1.0  
18  
375  
mA  
mA  
mS  
µA  
V
|VBDGS  
|VBDGD  
|
|
16  
16  
V
V
IGD = 1 mA  
18  
45  
V
DS > 6V  
θJC  
°C/W  
Phone: +1 408 850-5790  
Fax: +1 408 850-5766  
http:// www.filcs.com  
Revised: 8/05/04  
Email: sales@filcsi.com  
FPD1050  
0.75W POWER PHEMT  
ABSOLUTE MAXIMUM RATINGS*  
Parameter  
Drain-Source Voltage  
Gate-Source Voltage  
Drain-Source Current  
Gate Current  
Symbol  
Test Conditions  
-3V < VGS < +0V  
0V < VDS < +8V  
Min  
Max  
10  
-3  
IDSS  
10  
175  
175  
150  
3.4  
5
Units  
V
V
mA  
mA  
mW  
ºC  
ºC  
W
dB  
%
VDS  
VGS  
IDS  
IG  
PIN  
TCH  
TSTG  
PTOT  
Comp.  
For VDS > 2V  
Forward or reverse current  
Under any acceptable bias state  
Under any acceptable bias state  
Non-Operating Storage  
See De-Rating Note below  
Under any bias conditions  
2 or more Max. Limits  
RF Input Power  
Channel Operating Temperature  
Storage Temperature  
-40  
Total Power Dissipation  
Gain Compression  
Simultaneous Combination of Limits**  
80  
*TAmbient = 22°C unless otherwise noted  
**Users should avoid exceeding 80% of 2 or more Limits simultaneously  
Notes:  
Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device.  
Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib.  
Power Dissipation defined as: PTOT (PDC + PIN) – POUT, where  
P
DC: DC Bias Power  
PIN: RF Input Power  
POUT: RF Output Power  
Absolute Maximum Power Dissipation to be de-rated as follows above 22°C:  
PTOT= 3.4W – (0.022W/°C) x THS  
where THS = heatsink or ambient temperature above 22°C  
Example: For a 85°C heatsink temperature: PTOT = 3.4W – (0.022 x (85 – 22)) = 2.01W  
HANDLING PRECAUTIONS  
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic  
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and  
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.  
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.  
ASSEMBLY INSTRUCTIONS  
The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage  
temperature should be 280-290°C; maximum time at temperature is one minute. The recommended  
wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm)  
gold wire. Stage temperature should be 250-260°C.  
APPLICATIONS NOTES & DESIGN DATA  
Complete design data, including S-parameters, noise data, and large-signal models are available on  
the Filtronic web site.  
All information and specifications are subject to change without notice.  
Phone: +1 408 850-5790  
Fax: +1 408 850-5766  
http:// www.filcs.com  
Revised: 8/05/04  
Email: sales@filcsi.com  

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