FPD1050_1 [FILTRONIC]
0.75W POWER PHEMT; 0.75W功率pHEMT制
| 型号： | FPD1050_1 |
| 厂家： | 
FILTRONIC COMPOUND SEMICONDUCTORS |
| 描述： | 0.75W POWER PHEMT |
| 文件： | 总3页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet v3.0
0.75W POWER PHEMT
FEATURES:
LAYOUT:
•
•
•
•
•
28.5 dBm Linear O/p Power at 12 GHz
11 dB Power Gain at 12 GHz
14 dB Maximum Stable Gain at 12 GHz
41 dBm Output IP3
45% Power-Added Efficiency
GENERAL DESCRIPTION:
The
FPD1050
is
an
Electron
AlGaAs/InGaAs
Mobility
pseudomorphic
High
Transistor (PHEMT), featuring a 0.25 µm by
1050 µm Schottky barrier gate, defined by high
-resolution stepper-based photolithography.
The double recessed gate structure minimizes
TYPICAL APPLICATIONS:
•
Narrowband and broadband high-
performance amplifiers
parasitics to optimize performance.
The
•
•
SATCOM uplink transmitters
PCS/Cellular low-voltage high-efficiency
output amplifiers
epitaxial structure and processing have been
optimized for reliable high-power applications.
The FPD1050 is also available in the low cost
plastic SOT89 package.
•
Medium-haul digital radio transmitters
1
ELECTRICAL SPECIFICATIONS :
PARAMETER
SYMBOL
P1dB
CONDITIONS
MIN TYP
MAX
UNITS
dBm
Power at 1dB Gain Compression
Maximum Stable Gain (S21/S12)
VDS = 8 V; IDS = 50% IDSS
VDS = 8 V; IDS = 50% IDSS
27.5
28.5
14.0
MSG
dB
Power Gain at P1dB
G1dB
PAE
VDS = 8 V; IDS = 50% IDSS
10.0
11.0
45
dB
%
Power-Added Efficiency
VDS = 8 V; IDS = 50% IDSS; POUT = P1dB
Output Third-Order Intercept Point
(from 15 to 5 dB below P1dB)
VDS = 8V; IDS = 50% IDSS
39
41
IP3
Matched for optimal power; Tuned for best IP3
dBm
mA
Saturated Drain-Source Current
IDSS
VDS = 1.3 V; VGS = 0 V
260
325
385
Maximum Drain-Source Current
Transconductance
IMAX
GM
520
280
15
mA
mS
µA
V
VDS = 1.3 V; VGS ≅ +1 V
VDS = 1.3 V; VGS = 0 V
VGS = -5 V
Gate-Source Leakage Current
Pinch-Off Voltage
IGSO
|VP|
VDS = 1.3 V; IDS = 1 mA
IGS = 1 mA
1.0
Gate-Source Breakdown Voltage
Gate-Drain Breakdown Voltage
Thermal Resistivity (see Notes)
|VBDGS|
|VBDGD|
θJC
12.0
14.5
14.0
16.0
45
V
IGD = 1 mA
V
VDS > 6V
°C/W
Note:1 TAmbient = 22°C; RF specifications measured at f = 12 GHz using CW signal
1
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
Datasheet v3.0
1
ABSOLUTE MAXIMUM RATING :
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Drain-Source Current
Gate Current
SYMBOL
VDS
TEST CONDITIONS
ABSOLUTE MAXIMUM
6
-3V < VGS < -0.5V
10V
VGS
0V < VDS < +8V
For VDS < 2V
-3V
IDS
IDss
IG
Forward or reverse current
Under any acceptable bias state
Under any acceptable bias state
Non-Operating Storage
See De-Rating Note below
2 or more Max. Limits
10mA
RF Input Power
PIN
23dBm
175°C
-65°C to 150°C
3.4W
Channel Operating Temperature
Storage Temperature
Total Power Dissipation
TCH
TSTG
PTOT
4
Simultaneous Combination of Limits
80%
Notes:
1TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause
permanent damage to the device
2Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT
,
where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power
3Total Power Dissipation to be de-rated as follows above 22°C:
PTOT= 3.4 - (0.022W/°C) x THS
where THS= heatsink or ambient temperature above 22°C
Example: For a 85°C carrier temperature: PTOT = 3.4 - (0.022 x (85 – 22)) = 2.01W
4Users should avoid exceeding 80% of 2 or more Limits simultaneously
5 Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib.
6 Operating at absolute maximum VD continuously is not recommended. If operation at 10V is considered then
IDS must be reduced in order to keep the part within it's thermal power dissipation limits. Therefore VGS is
restricted to < -0.5V.
PAD LAYOUT:
PAD
DESCRIPTION
PIN
COORDINATES
(µm)
B
A
C
A
B
C
Gate Pad
Drain Pad
Source Pad
130, 220
380, 220
Note: Co-ordinates are referenced from the bottom left hand corner of the die to the centre of bond pad opening
DIE SIZE
(µm)
MIN. BOND PAD OPENING
DIE THICKNESS (µm)
(µm x µm )
470 x 440
75
85 x 60
2
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
Datasheet v3.0
PREFERRED ASSEMBLY INSTRUCTIONS:
PART NUMBER
DESCRIPTION
GaAs devices are fragile and should be
handled with great care. Specially designed
collets should be used where possible.
FPD1050
Die
The recommended die attach is gold/tin
eutectic solder under a nitrogen atmosphere.
Stage temperature should be 280-290°C;
maximum time at temperature is one minute.
The recommended wire bond method is
thermo-compression wedge bonding with 0.7
or 1.0 mil (0.018 or 0.025 mm) gold wire.
Stage temperature should be 250-260°C.
HANDLING
PRECAUTIONS:
To avoid damage to the devices care should
be exercised during handling.
Proper
Electrostatic Discharge (ESD) precautions
should be observed at all stages of storage,
handling, assembly, and testing.
These
devices should be treated as Class 0 (0-250 V)
as defined in JEDEC Standard No. 22-A114.
Further information on ESD control measures
can be found in MIL-STD-1686 and MIL-
HDBK-263.
APPLICATION NOTES & DESIGN DATA:
Application Notes and design data including S-
parameters, and device model are available
on request.
DISCLAIMERS:
This product is not designed for use in any
space based or life sustaining/supporting
equipment.
ORDERING INFORMATION:
3
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
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