FPD1050SOT89_1 [FILTRONIC]
LOW NOISE HIGH LINEARITY PACKAGED PHEMT; 低噪声高线性度PACKAGED PHEMT
| 型号： | FPD1050SOT89_1 |
| 厂家： | 
FILTRONIC COMPOUND SEMICONDUCTORS |
| 描述： | LOW NOISE HIGH LINEARITY PACKAGED PHEMT |
| 文件： | 总3页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet v3.0
LOW NOISE HIGH LINEARITY PACKAGED PHEMT
PACKAGE:
FEATURES (1.8GHZ):
•
•
•
•
•
•
26 dBm Output Power (P1dB)
17.5 dB Small-Signal Gain (SSG)
1.1 dB Noise Figure
40 dBm Output IP3
50% Power-Added Efficiency
FPD1050SOT89E: RoHS compliant
(Directive 2002/95/EC)
GENERAL DESCRIPTION:
TYPICAL APPLICATIONS:
The FPD1050SOT89 is a packaged depletion
mode AlGaAs/InGaAs pseudomorphic High
Electron Mobility Transistor (pHEMT). It
utilizes a 0.25 µm x 1050 µm Schottky barrier
Gate, defined by high-resolution stepper-
based photolithography. The recessed and
offset Gate structure minimizes parasitics to
optimize performance, with an epitaxial
structure designed for improved linearity over
a range of bias conditions and i/p power levels.
•
Drivers or output stages in PCS/Cellular
base station transmitter amplifiers
High intercept-point LNAs
•
•
WLL and WLAN systems, and other types
of wireless infrastructure systems.
ELECTRICAL SPECIFICATIONS:
PARAMETER
Power at 1dB Gain Compression
Small-Signal Gain
SYMBOL
CONDITIONS
MIN
24.5
16
TYP
26
MAX
UNITS
dBm
P1dB
VDS = 5 V; IDS = 50% IDSS
VDS = 5 V; IDS = 50% IDSS
SSG
17.5
dB
Power-Added Efficiency
Noise Figure
PAE
NF
VDS = 5 V; IDS = 50% IDSS;
POUT = P1dB
50
%
VDS = 5 V; IDS = 50% IDSS
VDS = 5 V; IDS = 25% IDSS
0.9
1.1
dB
Output Third-Order Intercept Point
(from 15 to 5 dB below P1dB)
IP3
VDS = 5V; IDS = 50% IDSS
Matched for optimal power
Matched for best IP3
37
39
40
dBm
Saturated Drain-Source Current
Maximum Drain-Source Current
Transconductance
IDSS
IMAX
VDS = 1.3 V; VGS = 0 V
260
320
520
270
1
385
mA
mA
mS
VDS = 1.3 V; VGS ≅ +1 V
VDS = 1.3 V; VGS = 0 V
VGS = -5 V
GM
Gate-Source Leakage Current
Pinch-Off Voltage
IGSO
15
µA
V
|VP|
VDS = 1.3 V; IDS = 1.05 mA
IGS = 1.05 mA
0.7
12
12
1.0
16
1.3
Gate-Source Breakdown Voltage
Gate-Drain Breakdown Voltage
Thermal Resistance
|VBDGS|
|VBDGD|
RθJC
V
IGD = 1.05 mA
16
V
76
°C/W
Note: TAMBIENT = 22°; RF specification measured at f = 1850 MHz using CW signal (except as noted)
1
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
Datasheet v3.0
1
ABSOLUTE MAXIMUM RATING :
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Drain-Source Current
Gate Current
SYMBOL
VDS
TEST CONDITIONS
-3V < VGS < +0V
ABSOLUTE MAXIMUM
8V
VGS
0V < VDS < +8V
-3V
IDS
For VDS > 2V
IDss
IG
Forward or reverse current
Under any acceptable bias state
Under any acceptable bias state
Non-Operating Storage
See De-Rating Note below
Under any bias conditions
2 or more Max. Limits
10mA
2
RF Input Power
PIN
260mW
175°C
-40°C to 150°C
2.0W
Channel Operating Temperature
Storage Temperature
TCH
TSTG
PTOT
Comp.
Total Power Dissipation
Gain Compression
5dB
3
Simultaneous Combination of Limits
Notes:
1TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause
permanent damage to the device
2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Users should avoid exceeding 80% of 2 or more Limits simultaneously
4Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT
,
where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power
Total Power Dissipation to be de-rated as follows above 22°C:
PTOT= 2.0 - (0.013W/°C) x TPACK
where TPACK= source tab lead temperature above 22°C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C carrier temperature: PTOT = 2.0W – (0.013 x (65 – 22)) = 1.44W
BIASING GUIDELINES:
•
Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate
•
•
Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage
supply for depletion-mode devices.
Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source
bias voltage, and such circuits provide some temperature stabilization for the device. A nominal
value for circuit development is 3.6 Ω for a 50% of IDSS operating point.
•
For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at 50%
of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25% to
33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3 performance.
2
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
Datasheet v3.0
PACKAGE OUTLINE:
(dimensions in millimeters – mm)
PREFERRED ASSEMBLY INSTRUCTIONS:
Available on request.
HANDLING PRECAUTIONS:
To avoid damage to
the
devices
care
should be exercised
during
Proper
handling.
Electrostatic
Discharge
(ESD)
precautions should be observed at all stages of
storage, handling, assembly, and testing.
These devices should be treated as Class (0-
250 V) as defined in JEDEC Standard No. 22-
A114. Further information on ESD control
measures can be found in MIL-STD-1686 and
MIL-HDBK-263.
APPLICATION NOTES & DESIGN DATA:
Application Notes and design data including S-
parameters are available on request.
PCB Foot Print
DISCLAIMERS:
This product is not designed for use in any
space based or life sustaining/supporting
equipment.
ORDERING INFORMATION:
PART NUMBER
FPD1050SOT89
DESCRIPTION
Packaged pHEMT
FPD1050SOT89E
RoHS compliant Packaged pHEMT
Units in inches
NOTE: Drawing available on request
3
Specifications subject to change without notice
Filtronic Compound Semiconductors Ltd
Tel: +44 (0) 1325 301111
Fax: +44 (0) 1325 306177
Email: sales@filcs.com
Website: www.filtronic.com
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