FPD1000V [FILTRONIC]

1W POWER PHEMT; 1W功率pHEMT制
FPD1000V
型号: FPD1000V
厂家: FILTRONIC COMPOUND SEMICONDUCTORS    FILTRONIC COMPOUND SEMICONDUCTORS
描述:

1W POWER PHEMT
1W功率pHEMT制

晶体 晶体管
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PRELIMINARY  
FPD1000V  
1W POWER PHEMT  
DRAIN  
BOND  
FEATURES (1.8 GHz)  
31 dBm Linear Output Power  
16 dB Power Gain  
PAD (2X)  
Useable Gain to 10 GHz  
41 dBm Output IP3  
Maximum Stable Gain of 20 dB  
50% Power-Added Efficiency  
10V Operation / Plated Source Thru-Vias  
GATE  
BOND  
DIE SIZE (µm): 650 x 800  
DIE THICKNESS: 75µm  
PAD (2X)  
BONDING PADS (
µm): >70 x 65  
DESCRIPTION AND APPLICATIONS  
The FPD1000V is a discrete depletion mode AlGaAs/InGaAs pseudomorphic High Electron  
Mobility Transistor (pHEMT), optimized for power applications in L- and C-Bands. The  
FPD1000V includes Source plated thru-vias, and does not require wire bonds to the Source.  
Typical applications include drivers or output stages in PCS/Cellular base station transmitter  
amplifiers, as well as other power applications in WLL/WLAN amplifiers.  
ELECTRICAL SPECIFICATIONS AT 22°C  
Parameter  
Symbol  
Test Conditions  
Min  
Typ Max Units  
RF SPECIFICATIONS MEASURED AT f = 1.85 GHz USING CW SIGNAL  
Power at 1dB Gain Compression  
P1dB  
G1dB  
MSG  
PAE  
IM3  
VDS = 10V; IDS = 200 mA  
ΓS and ΓL tuned for Optimum IP3  
VDS = 10V; IDS = 200 mA  
ΓS and ΓL tuned for Optimum IP3  
VDS = 10 V; IDS = 200mA  
PIN = 0dBm, 50system  
VDS = 10V; IDS = 200 mA  
ΓS and ΓL tuned for Optimum IP3  
30  
31  
16.0  
20  
dBm  
Power Gain at dB Gain Compression  
14.5  
Maximum Stable Gain  
S21/S12  
Power-Added Efficiency  
at 1dB Gain Compression  
3rd-Order Intermodulation Distortion  
ΓS and ΓL tuned for Optimum IP3  
dB  
%
50  
V
DS = 10V; IDS = 200 mA  
POUT = 19 dBm (single-tone level)  
-46  
-44  
dBc  
Saturated Drain-Source Current  
Maximum Drain-Source Current  
Transconductance  
Gate-Source Leakage Current  
Pinch-Off Voltage  
Gate-Source Breakdown Voltage  
Gate-Drain Breakdown Voltage  
Thermal Resistivity  
IDSS  
IMAX  
GM  
IGSO  
|VP|  
VDS = 1.3 V; VGS = 0 V  
VDS = 1.3 V; VGS +1 V  
VDS = 1.3 V; VGS = 0 V  
VGS = -3 V  
VDS = 1.3 V; IDS = 2.4 mA  
IGS = 2.4 mA  
480  
650  
1100  
720  
20  
0.9  
8
720  
mA  
mA  
mS  
µA  
V
50  
1.4  
0.7  
6
20  
|VBDGS  
|VBDGD  
|
|
V
V
IGD = 2.4 mA  
See Note on following page  
22  
22  
ΘCC  
°C/W  
Phone: +1 408 850-5790  
Fax: +1 408 850-5766  
http://www.filtronic.co.uk/semis  
Revised: 4/29/05  
Email: sales@filcsi.com  
PRELIMINARY  
FPD1000V  
1W POWER PHEMT  
RECOMMENDED OPERATING BIAS CONDITIONS  
Drain-Source Voltage:  
Quiescent Current:  
From 5V to 10V  
From 25% IDSS to 55% IDSS  
1
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Drain-Source Voltage  
Gate-Source Voltage  
Symbol  
Test Conditions  
-3V < VGS < +0V  
0V < VDS < +8V  
Min  
Max  
12  
-3  
IDSS  
+20/-20  
575  
175  
150  
7.0  
Units  
V
V
mA  
mA  
mW  
ºC  
ºC  
W
dB  
%
VDS  
VGS  
IDS  
IG  
PIN  
TCH  
TSTG  
PTOT  
Comp.  
Drain-Source Current  
For VDS > 2V  
Gate Current  
Forward or reverse current  
Under any acceptable bias state  
Under any acceptable bias state  
Non-Operating Storage  
See De-Rating Note below  
Under any bias conditions  
2 or more Max. Limits  
RF Input Power2  
Channel Operating Temperature  
Storage Temperature  
-40  
Total Power Dissipation  
Gain Compression  
5
80  
Simultaneous Combination of Limits3  
1TAmbient = 22°C unless otherwise noted  
2Max. RF Input Limit must be further limited if input VSWR > 2.5:1  
3Users should avoid exceeding 80% of 2 or more Limits simultaneously  
Notes:  
Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device.  
Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib.  
Power Dissipation defined as: PTOT (PDC + PIN) – POUT, where  
P
DC: DC Bias Power  
PIN: RF Input Power  
POUT: RF Output Power  
Absolute Maximum Power Dissipation to be de-rated as follows above 22°C:  
PTOT= 7.0W – (0.046W/°C) x THS  
where THS = heatsink or ambient temperature above 22°C  
Example: For a 85°C heatsink temperature: PTOT = 7.0W – (0.046 x (85 – 22)) = 4.1W  
HANDLING PRECAUTIONS  
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic  
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and  
testing. This product has be tested to Class 1A (> 250V but < 500V) using JESD22 A114, Human  
Body Model, and to Class A, (< 200V) using JESD22 A115, Machine Model.  
ASSEMBLY INSTRUCTIONS  
The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage  
temperature should be 280-290°C; maximum time at temperature is one minute. The recommended  
wire bond method is thermo-compression wedge bonding with 1.0 mil (0.025 mm) gold wire. Stage  
temperature should be 250-260°C.  
Phone: +1 408 850-5790  
Fax: +1 408 850-5766  
http://www.filtronic.co.uk/semis  
Revised: 4/29/05  
Email: sales@filcsi.com  
PRELIMINARY  
FPD1000V  
1W POWER PHEMT  
APPLICATIONS NOTES & DESIGN DATA  
Applications Notes are available from your local Filtronic Sales Representative or directly from the  
factory. Complete design data, including S-parameters, noise data, and large-signal models are  
available on the Filtronic web site.  
BONDING DIAGRAM  
Note: 25 µm (0.001 in.) gold wire is recommended. No Source wire bonds are needed, device  
features Source thru-vias.  
All information and specifications are subject to change without notice.  
Phone: +1 408 850-5790  
Fax: +1 408 850-5766  
http://www.filtronic.co.uk/semis  
Revised: 4/29/05  
Email: sales@filcsi.com  

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