IMIC9870G [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
| 型号： | IMIC9870G |
| 厂家： | 
ETC |
| 描述： | Clocks and Buffers
|
| 文件： | 总25页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
•
•
•
•
•
•
3 Differential CPU Clocks
Product Features
SMBus Support with Read-back Capabilities
Spread Spectrum EMI Reduction
Dial-a-Frequency™ Features
Dial-a-dB™ Features
•
•
•
Supports Pentium® 4 Type CPUs
3.3 Volt Power Supply
10 Copies of PCI Clocks
56 Pin SSOP and TSSOP Package
Frequency Table
S2
S1 S0 CPU
(0:2)
3V66
66BUFF(0:2)/
3V66(0:4)
66IN
66IN/
3V66-5
66MHz clock input
66MHz clock input
66MHz clock input
66MHZ clock input
PCI_F
PCI
REF
USB/
DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
1
1
1
1
0
0
0
0
M
M
M
M
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
66M
100M
200M
133M
66M
100M
200M
133M
Hi-Z
66M
66M
66M
66M
66M
66M
66M
66M
Hi-Z
66IN/2
66IN/2
66IN/2
66IN/2
33 M
33 M
33 M
33 M
Hi-Z
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
Hi-Z
66IN
66IN
66IN
66M
66M
66M
66M
Hi-Z
66M
66M
66M
66M
Hi-Z
TCLK/4
50M
55.5M
TCLK/2
150M
166.6M
TCLK/4
50M
55.5M
TCLK/4
50M
55.5M
TCLK/8
25M
27.7M
TCLK
14.318M
14.318M
TCLK/2
48M
48M
Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts
If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register.
Block Diagram
Pin Configuration
XIN
XOUT
REF
VDD
XIN
XOUT
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
S1
S0
CPU_STP#
CPU0
CPU/0
VDD
CPU1
CPU/1
VSS
VDD
CPU2
CPU/2
MULT0
IREF
VSSIREF
S2
48MUSB
48MDOT
VDD
CPU(0:2)
CPU/(0:2)
VSS
PLL1
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
CPU_STP#
IREF
VSSIREF
9
3V66_0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
S(0:2)
3V66_1/VCH
MULT0
VTT_PG#
PCI_STP#
/2
PCI(0:6)
PCI_F(0:2)
48M USB
48M DOT
PLL2
PD#
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VSS
WD
Logic
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
I2C
Logic
SDATA
SCLK
VDDA
VSSA
VTT_PG#
66B[0:2]/3V66[2:4]
66IN/3V66-5
Power
Up Logic
VDDA
SDATA
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 1 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Pin Description
PIN
NAME
PWR
I/O
I
O
Description
2
3
XIN
XOUT
Oscillator Buffer Input. Connect to a crystal or to an external clock.
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
Differential host output clock pairs. See the frequency table on page one
of this data sheet for frequencies and functionality.
VDD
VDD
52, 51, 49,
48, 45, 44
10, 11, 12,
13, 16, 17,
18
CPU, CPU/
(0:2)
PCI(0:6)
O
O
VDDP
PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See
Frequency Table on page one of this data sheet.
5, 6, 7
PCIF (0:2)
VDD
O
33Mhz PCI clocks, which are ÷2 copies of 66IN or 3V66 clocks, may be
free running (not stopped when PCI_STP# is asserted low) or may be
stoppable depending on the programming of SMBus register Byte3, Bits
(3:5).
56
42
REF
IREF
VDD
VDD
O
I
Buffered Output copy of the device’s XIN clock.
Current reference programming input for CPU buffers. A resistor is
connected between this pin and VSSIREF. See CPU Clock current Select
Table in page 18 of this data sheet.
28
VTT_PG#
VDD
I
Qualifying input that latches S (0:2) and MULT0. When this input is at a
logic low, the S (0:2) and MULT0 are latched
39
38
33
35
48MUSB
48MDOT
3V66_0
VDD48
VDD48
VDD
O
O
O
O
Fixed 48MHz USB Clock Outputs.
Fixed 48MHZ DOT Clock Outputs.
3.3 Volt 66 MHz fixed frequency clock.
3.3 volt clock selectable with SMBus byte0, Bit5, when Byte5, Bit5. When
Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When
byte0, Bit5 is a logic 0, then this is a 66M output clock (default).
This pin is a power down mode pin. A logic low level causes the device to
3V66_1/VCH
VDD
25
PD#
VDD
I
PU enter a power down state. All internal logic is turned off except for the
SMBus logic. All output buffers are stopped. See the Power Down section
of this data sheet.
43
MULT0
I
Programming input selection for CPU clock current multiplier. See CPU
PU Clock Current Select Function Table.
55, 54
29
S(0,1)
SDATA
I
I
I
I
Frequency Select Inputs. See Frequency Table on page 1.
Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See application
note AN-0022
30
40
34
SCLK
S2
I
I
Serial Clock Input. Conforms to the SMBus specification. See application
note AN-0022.
Frequency Select input. See Frequency Table on page 1. This is a Tri
level input that is driven high, low or driven to an intermediate level.
PCI Clock Disable Input. When asserted low, PCI (0:6) clocks are
VDD
VDD
I
T
I
PCI_STP#
PU synchronously disabled in a low state. This pin does not effect PCIF (0:2)
clocks’ outputs if they are programmed to be PCIF clocks via the device’s
SMBus interface.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 2 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Pin Description (Cont.)
PIN
NAME
PWR
I/O
Description
53
CPU_STP#
VDD
I
CPU Clock Disable Input. When asserted low, CPU (0:2) clocks are
synchronously disabled in a high state and CPU/(0:2) clocks are
synchronously disabled in a low state.
PU
24
66IN/3V66_5
VDD
VDD
I/O
O
Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or output
clock for fixed 66 MHz clock if S2=0. See table on page 1
3.3 volt clock outputs. These clocks are buffered copies of the 66IN
clock or fixed at 66 MHz. See table on page 1
21, 22, 23
66B(0:2)/
3V66(2:4)
VDD
1, 8, 14, 19,
32, 37, 46, 50
4, 9, 15, 20,
27, 31, 36, 47
41
PWR 3.3V Power Supply
VSS
PWR Common Ground
VSSIREF
PWR Current reference programming input for CPU buffers. A resistor is
connected between this pin and IREF. See CPU Clock current Select
Table in page 18 of this data sheet. This pin should also be returned to
device VSS.
26
VDDA
-
PWR Analog power input. Used for PLL and internal analog circuits. Is also
specifically used to detect and determine when power is at an
acceptable level to enable the device to operate.
PU = Internal Pull-Up. PD = Internal Pull-Down. T = Tri level logic input with valid logic voltages of LOW=<0.8V, T=1.0-1.8V and
HIGH=>2.0V
2-Wire SMBus Control Interface
The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See
Application Note AN-0022).
The device will accept data written to the D2 address and data may read back from address D3. It will not respond to
any other addresses, and previously set control registers are retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in the command is considered “don’t care”; it must be sent and will be acknowledged.
After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2)
described below will be valid and acknowledged.
Note: The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at
power up.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 3 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Serial Control Registers (Cont.)
Byte 0: CPU Clock Register
Bit
@Pup
Pin#
Description
7
0
-
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
6
5
0
0
-
35
Reserved
3V66_1/VCH frequency Select
0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read Only.
4
3
Pin 53
Pin 34
44,45,48,49,
51,52
10,11,12,13,
16,17,18
Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a
logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read Only.
Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read Only.
Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read Only.
2
1
0
Pin 40
Pin 55
Pin 54
-
-
-
Byte 1: CPU Clock Register
Bit
7
6
@Pup
Pin 43
0
0
Pin#
-
-
Description
MULT0 (Pin 43) Value. This bit is Read Only.
Reserved
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
5
44,45
4
3
0
0
48,49
51,52
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
Controls CPU0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
2
1
0
1
1
1
44,45
48,49
51,52
CPU2 Output Control, 1 = enabled, 0 = disable HIGH and CPU/2 disables LOW
This is a Read and Write control bit.
CPU1 Output Control, 1 = enabled, 0 = disable HIGH and CPU/1 disables LOW
This is a Read and Write control bit.
CPU0 Output Control, 1 = enabled, 0 = disable HIGH and CPU/0 disables LOW
This is a Read and Write control bit.
Byte 3: PCI_F Clock and 48M Control Register
(all bits are read and write functional)
Byte 2: PCI Clock Control Register
(all bits are read and write functional)
Bit
7
@Pup
1
Pin#
38
Description
Bit
7
6
@Pup
0
1
Pin#
-
18
Description
Reserved
PCI6 Output Control
1 = enabled, 0 = forced LOW
PCI5 Output Control
1 = enabled, 0 = forced LOW
PCI4 Output Control
1 = enabled, 0 = forced LOW
PCI3 Output Control
1 = enabled, 0 = forced LOW
PCI2 Output Control
1 = enabled, 0 = forced LOW
PCI1 Output Control
1 = enabled, 0 = forced LOW
PCI0 Output Control
48MDOT Output Control
1 = enabled, 0 = forced LOW
48MUSB Output Control
1 = enabled, 0 = forced LOW
PCI_STP#, control of PCI_F2.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
PCI_STP#, control of PCI_F1.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
PCI_STP#, control of PCI_F0.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
PCI_F2 Output Control
1=running, 0=forced LOW
6
5
1
0
39
7
5
4
3
2
1
0
1
1
1
1
1
1
17
16
13
12
11
10
4
3
0
0
6
5
2
1
0
1
1
1
7
6
5
1 = enabled, 0 = forced LOW
PCI_F1 Output Control
1= running, 0=forced LOW
PCI_F0 Output Control
1= running, 0=forced LOW
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 4 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Byte 4: DRCG Control Register
(all bits are read and write functional)
Byte 5: Clock control register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
Bit
7
6
5
4
@Pup
Pin#
Description
7
0
-
SS2 Spread Spectrum control bit
(0=down spread, 1=Center spread)
Reserved
3V66_0 Output Enabled
1 = enabled, 0 = disabled
3V66_1/VCH Output Enable
1 = enabled, 0 = disabled
3V66_5 Output Enable
1 = enabled, 0 = disabled
66B2/3V66_4 Output Enabled
1 = enabled, 0 = disabled
66B1/3V66_3 Output Enabled
1 = enabled, 0 = disabled
66B0/3V66_2 Output Enabled
1 = enabled, 0 = disabled
0
1
0
0
0
0
-
-
-
-
-
-
SS1 Spread Spectrum control bit
SS0 Spread Spectrum control bit
66IN to 66M delay Control MSB, See table
66IN to 66M delay Control LSB, See table
Reserved
48MDOT edge rate control. When set to 1,
the edge is slowed by 15%.
Reserved
6
5
0
1
-
33
4
3
2
1
0
1
1
1
1
1
35
24
23
22
21
3
2
1
0
0
0
-
-
USB edge rate control. When set to 1, the
edge is slowed by 15%
Byte 7: Watch Dog Time Stamp Register
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 6: Silicon Signature Register
(all bits are read only)
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
0
0
0
0
0
0
1
1
-
-
-
-
-
-
-
-
Vendor Code
011 = IMI
Byte 9: Dial-a-Frequency™ Control Register R
(all bits are read and write functional)
Note: When writing to this register the device will acknowledge the
write operation, but the data itself will be ignored.
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
R6 MSB
R5
R4
R3
R2
R1
R0, LSB
R and N register load gate 0=gate closed
(data is latched), 1=gate open (data is
loading from SMBus registers into R and
N)
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Byte 8: Dial-a-Frequency™ Control Register N
(all bits are read and write functional)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
N7, MSB
N6
N5
N4
N3
N2
N3
N0, LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
66IN to 66M Delay Control Table
Byte5
Delay (ns)
Bit5
0
Bit4
0
4.29
0
1
4.43
1
1
0
1
3.95 (default)
3.95
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 5 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Dial-a-Frequency™ Feature
SMBus Dial-a-frequency feature is available in this device via Byte8 and Byte9. See our App Note AN-0025 for details
on our Dial-a-Frequency™ feature.
P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors
(S1, S0). P value may be determined from the following table:
S(1:0)
0 0
0 1
1 0
1 1
P
32005333
48008000
96016000
64010667
Table 1
Dial-a-dB™ Features
SMBus Dial-a-dB™ feature is available in this device via Byte8 and Byte9. See our App Note AN-0026 for details on
the Dial-a-dB™.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to minimizing Electro-Magnetic Interference (EMI) radiation
generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is
generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore
causing the average energy at any one point in this band to decrease in value. This technique is achieved by
modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of
EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control
Bytes. See applications note AN-0024 for a more in depth description of Spread spectrum modulation and see the
SMBus register section of this data sheet for the exact bit and byte functionally. The following table is a listing of the
modes and percentages of Spread Spectrum modulation that this device incorporates.
SS2
SS1
SS0
Spread Mode
Spread %
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Down
Down
Down
Down
Center
Center
Center
Center
0, -1.00
0, -1.20
0, -0.50
0, -1.50
+0.50, -0.50
+0.60, -0.60
+0.25, -0.25
+0.75, -0.75
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 6 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
AC Parameters
66 MHz
100 MHz
133 MHz
200 MHz
Symbol
TDC
TPeriod
Parameter
Xin Duty Cycle
Xin period
Units
%
nS
Notes
1, 11, 14
1, 2, 4, 11
Min
47.5
69.841
Max
52.5
71.0
Min
47.5
69.841
Max
52.5
71.0
Min
47.5
69.841
Max
52.5
71.0
Min
47.5
69.841
Max
52.5
71.0
VHIGH
VLOW
Tr / Tf
Xin High Voltage
Xin Low Voltage
Xin rise and fall
times
.7Vdd
0
-
Vdd
.3Vdd
10.0
.7Vdd
0
-
Vdd
.3Vdd
10.0
.7Vdd
0
-
Vdd
.3Vdd
10.0
.7Vdd
0
-
Vdd
.3Vdd
10.0
Volts
Volts
nS
13
TCCJ
Xin Cycle to Cycle
Jitter
-
500
-
500
-
500
-
-
500
pS
2, 5, 11
CPU at 0.7 Volts Timing
TSKEW
TCCJ
Any CPU to CPU
clock Skew
CPU Cycle to
Cycle Jitter
CPU and CPU#
Duty Cycle
CPU and CPU#
period
-
-
100
150
55
-
-
100
150
55
-
100
150
55
100
150
55
pS
pS
%
2, 5, 17
2, 17, 22
5, 17, 22
5, 17, 22
5, 6, 25
-
TDC
45
45
45
45
TPeriod
Tr / Tf
14.85
175
15.3
700
9.85
175
10.2
700
7.35
175
7.65
700
4.85
175
5.1
700
nS
ps
CPU and CPU#
rise and fall times
Rise.Fall Matching
Rise Time Variation
Fall Time Variation
crossing point
-
-
-
20%
125
125
430
-
-
-
20%
125
125
430
20%
125
125
430
-
20%
125
125
430
-
6, 21, 22
6, 22
6, 22
DeltaTr
DeltaTf
Vcross
-
-
ps
ps
mV
-
280
280
280
280
5, 22
voltage at 0.7 V
swing
CPU at 1.0 Volts Timing
TSKEW
TCCJ
Any CPU to any
CPU clock Skew
CPU Cycle to
Cycle Jitter
CPU and CPU#
Duty Cycle
-
-
100
150
55
-
-
100
150
55
-
100
150
55
-
100
150
55
pS
pS
%
2, 5, 17
2, 17
5, 17
5, 17
5, 25
7, 26
-
TDC
45
45
45
45
TPeriod
CPU and CPU#
period
14.85
175
15.3
467
325
9.85
175
10.2
467
325
7.35
175
7.65
467
325
4.85
175
5.1
467
325
nS
ps
ps
Differential
Tr / Tf
SE-
DeltaSlew
CPU and CPU#
rise and fall times
Absolute Single-
ended rise/fall
waveform
symmetry
Vcross
Cross point at 1.0
Volt swing
510
760
510
760
510
760
510
760
mV
26
TDC
TPeriod
THIGH
TLOW
Tr / Tf
3V66 Duty Cycle
3V66 period
3V66 high time
3V66 low time
3V66 rise and fall
times
45
55
15.3
-
45
55
15.3
-
45
55
15.3
-
45
55
15.3
-
%
2, 4
1, 2, 4
19
20
3
15.0
4.95
4.55
0.5
15.0
4.95
4.55
0.5
15.0
4.95
4.55
0.5
15.0
4.95
4.55
0.5
nS
nS
nS
nS
-
-
-
-
2.0
2.0
2.0
2.0
Tskew
Unbuffered
Tskew
Buffered
TCCJ
3V66 to 3V66 clock
skew
3V66 to 3V66 clock
skew
DRCG Cycle to
Cycle Jitter
-
-
-
500
250
250
-
-
-
500
250
250
-
-
-
500
250
250
-
-
-
500
250
250
pS
pS
pS
2, 4
2, 4
2, 4
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AC Parameters (Cont.)
66 MHz
100 MHz
133 MHz
200 MHz
Symbol
Parameter
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
TDC
66B(0:2) Duty
Cycle
66B(0:2) rise and
fall times
Any 66B to any
66B Skew
66IN to 66B(0:2)
propagation delay
66B(0:2) Cycle to
Cycle Jitter
45
0.5
-
55
45
0.5
-
55
45
0.5
-
55
45
55
%
2, 4
Tr / Tf
TSKEW
Tpd
2.0
175
4.5
2.0
175
4.5
2.0
175
4.5
0.5
2.0
175
4.5
nS
pS
nS
pS
2, 3
2, 4
2.5
-
2.5
-
2.5
-
2.5
-
2, 4
TCCJ
100
100
100
100
2, 4, 18
TDC
TPeriod
THIGH
TLOW
Tr / Tf
PCI_F(0:2) PCI
(0:6) Duty Cycle
PCI_F(0:2) PCI
(0:6) period
PCI_F(0:2) PCI
(0:6) high time
PCI_F(0:2) PCI
(0:6) low time
PCI_F(0:2) PCI
(0:6) rise and fall
times
45
55
45
55
45
55
45
30
55
%
2, 4
1, 2, 4
19
30.0
12.0
12.0
0.5
-
-
30.0
12.0
12.0
0.5
-
-
30.0
12.0
12.0
0.5
-
-
-
-
nS
nS
nS
nS
12.0
12.0
0.5
-
-
-
-
20
2.0
2.0
2.0
2.0
3
TSKEW
TCCJ
Any PCI clock to
Any PCI clock
Skew
PCI_F(0:2) PCI
(0:6) Cycle to
Cycle Jitter
-
-
500
250
-
-
500
250
-
-
500
250
-
-
500
250
pS
pS
2, 4
2, 4
TDC
USB48M Duty
Cycle
45
55
45
55
45
55
45
55
%
2, 4
TPeriod
Tr / Tf
USB48M period
USB48M rise and
fall times
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333
nS
nS
2, 4
2, 3
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.10
TCCJ
TDC
USB48M Cycle to
Cycle Jitter
-
350
-
350
-
350
-
350
pS
%
1, 2, 4
2, 4
DOT48 Duty
Cycle
45
55
45
55
45
55
45
55
TPeriod
Tr / Tf
DOT48 period
DOT48 rise and
fall times
20.837
0.5
20.837
0.5
20.837
0.5
20.837
0.5
nS
nS
2, 4
2, 4
1.0
1.0
1.0
1.0
TCCJ
DOT48Cycle to
Cycle Jitter
-
350
-
350
-
350
-
350
pS
2, 4
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AC Parameters (Cont.)
66 MHz
100 MHz
133 MHz
200 MHz
Symbol
Parameter
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
TDC
TPeriod
Tr / Tf
REF Duty Cycle
REF period
REF rise and fall
times
45
69.8413
1.0
55
71.0
4.0
45
69.8413
1.0
55
71.0
4.0
45
69.8413
1.0
55
71.0
4.0
45
69.8413
1.0
55
71.0
4.0
%
nS
nS
2, 4
2, 4
2, 3
TCCJ
REF Cycle to
Cycle Jitter
-
1000
-
1000
-
1000
-
1000
pS
2, 4
tpZL, tpZH
tpLZ, tpZH
tstable
Output enable
delay (all outputs)
Output disable
delay (all outputs)
All clock
1.0
1.0
-
10.0
10.0
3
1.0
1.0
-
10.0
10.0
3
1.0
1.0
-
10.0
10.0
3
1.0
1.0
-
10.0
10.0
3
nS
nS
11
11
11
mS
Stabilization from
power-up
tss
tsh
tsu
Stopclock Set Up
Time
Stopclock Hold
Time
Oscillator startup
time
10.0
-
-
10.0
-
-
10.0
-
-
10.0
-
-
nS
nS
10
10
12
0
-
0
-
0
-
0
-
X
X
X
X
mS
(VDD = VDDA = 3.3V ±5%, TA = 0°C to +70°C)
Note 1: This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
Note 2: All outputs loaded as per table 5 below.
Note 3: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement
setup section of this data sheet)
Note 4: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (see test and measurement setup section of this
data sheet).
Note 5: This measurement is applicable with Spread ON or Spread OFF.
Note 6: Measured from Vol = 0.175V to Voh = 0.525V.
Note 7: Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the
instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk#
fall (rise) time”. This parameter is designed form waveform symmetry.
Note 8: The time specified is measured from when all VDD’s reach their supply rail (3.3V) till the frequency output is stable and operating within
the specifications.
Note 9: Measured from when both SEL1 and SEL0 are low
Note 10: CPU_STP# and PCI_STP# setup time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next
PCI_F clock’s rising edge.
Note 11: When Xin is driven from an external clock source.
Note 12: When Crystal meets minimum 40 ohm device series resistance specification.
Note 13: Measured between 0.2Vdd and .7Vdd
Note 14: This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to
30/70 but the REF clock duty cycle will not be within data sheet specifications.
Note 15: Vpullup(external)=1.5V, Min=(Vpullup(external)/2)-150mV, Max=(Vpullup(external)/2)+150mV
Note 16: Vp = V pull-up (external), Vdif specifies the minimum input differential voltage (Vtr-Vcp) required for switching, where Vtr is the true input
level and Vcp is the compliment input level.
Note 17: Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0 volts.
Note 18: This figure is additive to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500 ps jitter figure is
specified.
Note 19: THIGH is measured at 2.4V for non host outputs.
Note 20: TLOW is measured at 0.4V for all outputs.
Note 21: Determined as a fraction of 2*(Trise-Tfall)/ (Trise+Tfall).
Note 22: Test load is Rta=33.2 ohms, Rd=49.9 ohms.
Note 23: These crossing points refer to only crossing points containing a rising edge of a Host output.
Note 24: This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
Note 25: Measurement taken from differential waveform, from –0.35V to +0.35V.
Note 26: Measured in absolute voltage, i.e. single-ended measurement.
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Maximum Lumped Capacitive Output Loads
Maximum Ratings¹
Clock
PCI Clocks
3V66 (0,1)
66B(0:2)
48MUSB Clock
48MDOT
Max Load
Units
pF
pF
pF
pF
Input Voltage Relative to VSS:
VSS-0.3V
30
30
30
20
10
30
Input Voltage Relative to VDDQ or AVDD: VDD+0.3V
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-65°C to + 150°C
0°C to +85°C
3.5V
pF
pF
REF Clock
Table 5
Note 1: The voltage on any input or I/O pin cannot exceed the
power pin during power-up. Power supply sequencing is NOT
required.
Test and Measurement Setup
For Differential CPU Output Signals
The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CLK Measurement Point
TPCB
CLK
RtA1
RtB1
RLA1
RLB1
CLA
RD
Mult0
CLK Measurement Point
TPCB
CLK#
RtA2
RtB2
CLB
RLA2
RLB2
Rref
Lumped Test Load Configuration
Component
RtA1, RtA2
RLA1, RLA2
TPCB
RLB1, RLB2
RD
0.7 Volt Amplitude Value
1.0 Volt Amplitude Value
33 Ω
49.9 Ω
3” 50 ΩZ
0 Ω
∞
3” 50 ΩZ
63 Ω
∞
∞
470 Ω
RtB1, RtB2
CLA, CLB
Rref
0 Ω
2pF
33 Ω
2 pF
221 Ω w/mult0=0
475 Ω w/mult0=1
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Test and Measurement Setup (Cont.)
For single Ended Output Signals
Output under Test
Probe
Load Cap
3.3V signals
tDC
-
-
3.3V
2.4V
1.5V
0.4V
0V
Tr
Tf
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference circuit details are contained in the previous table of this
data sheet. The following parameters are used to specify output buffer characteristics:
1. Output impedance of the current mode buffer circuit - Ro (see figure below).
2. Minimum and maximum required voltage operation range of the circuit – Vop (see figure below).
3. Series resistance in the buffer circuit – Ros (see figure below).
4. Current accuracy at given configuration into nominal test load for given configuration.
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VDD3 (3.3V +/- 5%)
Slope ~ 1/R0
Ro
Iout
Ros
0V
1.2V
Iout
Vout = 1.2V max
Vout
Host Clock (HCSL) Buffer Characteristics
Characteristic
Ro
Minimum
3000 Ohms (recommended)
Maximum
N/A
Ros
Vout
N/A
1.2V
Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage
at the pin of the device.
The various output current configurations are shown in the host swing select functions table. For all configurations, the
deviation from the expected output current is +/- 7% as shown in the current accuracy table.
CPU Clock Current Select Function
Mult0
Board Target Trace/Term Z
50 Ohms
Reference R, Iref – Vdd (3*Rr) Output Current Voh @ Z
0
1
Rr = 221 1%, Iref = 5.00mA
Rr = 475 1%, Iref = 2.32mA
Ioh = 4*Iref
Ioh = 6*Iref
1.0V @ 50
0.7V @ 50
50 Ohms
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Group Timing Relationship and Tolerances
Offset
Tolerance
±1.0 nS
±1.0 nS
±1.0 nS
Conditions
3V66 to PCI
2.5 nS
3V66 Leads PCI (un-buffered mode)
0 degrees phase shift
USB to DOT 48M Skew
66B(0:2) to PCI offset
0.0 nS
2.5 nS
66B leads PCI (buffered mode)
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is understood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for VCH (48MHz) operation it is also in phase with the USB
and DOT outputs.
USB48M
DOT48M
48MUSB and 48MDOT Phase Relationship Figure
66IN to 66B(0:2) Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown below.
66IN
Tpd
66CB0:2)
66IN to 66B(0:2) Output Delay Figure
The Tpd is the prop delay from the input pin (66IN) to the output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The measurement taken at 1.5 volts.
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66BUF to PCI Buffered Clock Skew
The following figure shows the difference (skew) between the 3V33(0:5) outputs when the 66M clocks are connected
to 66IN. This offset is described in the Group Timing Relationship and Tolerances section of this data sheet. The
measurements were taken at 1.5 volts.
66BUF(0:2)
1.5-
3.5ns
PCI(0:6)
PCIF(0:2)
Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
3V66 to PCI Un-Buffered Clock Skew
The following figure show the timing relationship between 3V66_(0:5) and PCI(0:6) and PCIF(0:2) when configured to
run in the un-buffered mode.
3V66_(0:5)
1.5-
3.5ns
PCI(0:6)
PCIF(0:2)
Un-buffered Mode - 3V66_(0:5) to PCI (0:6) and PCIF(0:2) Phase Relationship
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Special Functions
PCI_F and IOAPIC Clock Outputs
The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. ANY 2 of the
PCI_F clock outputs can be used as IOAPIC 33Mhz clock outputs. They are 3.3V outputs will be divided down via a
simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event these clocks
are not required, then these clocks can be used as general PCI clocks or disabled via the assertion of the PCI_STP#
pin.
3V66_1/VCH Clock Output
The 3V66_1/VCH pin has a dual functionality, which is selectable via SMBus.
Configured as DRCG (66M), SMBus Byte0, Bit 5 = ‘0’
The default condition for this pin is to power up in a 66M operation. In 66M operation this output is SSCG capable and
when spreading is turned on, this clock will be modulated.
Configured as VCH (48M), SMBus Byte0, Bit 5 = ‘1’
In this mode, the output is configured as a 48Mhz non-spread spectrum output. This output is phase aligned with the
other 48M outputs (USB and DOT), to within 1ns pin to pin skew. The switching of 3V66_1/VCH into VCH mode
occurs at system power on. When the SMBus Bit 5 of Byte 0 is programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH
output may glitch while transitioning to 48M output mode.
CPU_STP# Clarification
The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while
the rest of the clock generator continues to function.
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CPU_STP# - Assertion (transition from logic ‘1’ to logic ‘0’)
When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via
assertion of CPU_STP# will be stopped after being sampled by 2 falling CPU clock edges. The final state of the
stopped CPU signals is CPU = high and CPU0# = Low. There is no change to the output drive current values during
the stopped state. The CPU is driven high with a current value equal to (Mult 0 ‘select’) x (Iref), and the CPU# signal
will not be driven. Due to external pulldown circuitry CPU# will be low during this stopped state.
CPU_STP#
CPU
CPU#
Assertion CPU_STP# Waveform Figure
CPU_STP# Functionality Table
CPU_STP#
CPU#4
Normal
Iref*Mult
CPU
Normal
Float
DRCG
66M
66M
66CLK(0:2)
66Input
66Input
PCI_F/PCI
66Input/2
66Input/2
PCI
66Input/2
66Input/2
USB/DOT
48M
1
0
48M
CPU_STP# De-assertion (transition from logic ‘0’ to logic ‘1’)
The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation
in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produces
when the clock resumes. The maximum latency from the de-assertion to active outputs is no more than 2 CPU clock
cycles.
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PCI_STP# Clarification
The PCI_STP# signal is an active low input used for synchronous stopping and starting the PCI outputs while the rest
of the clock generator continues to function. The setup time for capturing PCI_STP# going low is 10 nsec (tsetup). The
PCI_F (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be
free running.
t setup
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
PCI_STP# Waveform Figure
PCI_STP# - De-assertion (transition from logic ‘0’ to logic ‘1’)
The de-assertion of the PCI_STP# signal will cause all PCI(0:6) and stoppable PCI_F(0:2) clocks to resume running
in a synchronous manner within 2 PCI clock periods after PCI_STP# transitions to a high level.
Note that the PCI STOP function is controlled by 2 inputs. One is the device PCI_STP# pin number 34 and the other
is SMBus byte 0 bit 3. These 2 inputs to the function are logically ANDed. If either the external pin or the internal
SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte
0 Bit 3 will return a 0 value if either of these control bits are set low thereby indicating the devices stoppable PCI
clocks are not running.
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PD# (Power Down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an
asynchronous active low input. This signal is synchronized internally to the device powering down the clock
synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a
low value and held there and the VCO and PLL’s are also powered down. All clocks are shut down in a synchronous
manner so has not to cause glitches while transitioning to the low ‘stopped’ state.
PD# Functionality
PD#
1
0
CPU
Normal
Iref*2
CPU#
Normal
Float Low
DRCG
66M
Low
66CLK (0:2)
66Input
Low
PCI_F/PCI
66Input/2
Low
PCI
66Input/2
Low
USB/DOT
48M
Low
PD# - Assertion (transition from logic ’l’ to logic ‘0’)- Buffered Mode
When PD# is sampled low by two consecutive rising edges of the CPU# clock, then on the next high to low transition
of PCIF, the PCIF clock is stopped low. On the next high to low transition of 66Buff, the 66Buff clock is stopped low.
From this time, each clock will stop low on it’s next high to low transition, except the CPU clock. The CPU clocks are
held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# un-driven. After the last clock has stopped,
the rest of the generator will be shut down.
66Buff[0..2]
PCIF
PWRDWN#
CPU 133MHz
CPU# 133MHz
3V66
66In
USB 48MHz
REF 14.318MHz
Power Down Assertion Timing Waveforms Figure – Buffered Mode
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PCI 33MHz
PWRDWN#
CPU 133MHz
CPU# 133MHz
3V66
USB 48MHz
REF 14.318MHz
Power Down Assertion Timing Waveforms Figure – Non-Buffered Mode
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PD# - De-assertion (transition from logic ‘0’ to logic ‘1’)
The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 mS.
30uS min
100uS max
<3mS
66Buff1 / GMCH
66Buff[0,2]
PCIF / APIC
33MHz
PCI 33MHz
PWRDWN#
CPU 133MHz
CPU# 133MHz
3V66
66In
USB 48MHz
REF 14.318MHz
Power Down De-Assertion Timing Waveforms Figure
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VTT_PWRGD# Timing Diagram
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
0.2-0.3mS
Delay
Wait for
VTT_GD#
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
(Note A)
On
Clock Outputs
Clock VCO
On
Off
Note A: Device is not effected, VTT_PWRGD# is ignored.
Clock Generator PowerUp/Run State Diagram
#
D
G
R
w
o
L
W
P
T
S1
S2
=
T
V
Sample
Inputs (pins
54,55)
Delay 0.25mS
Enable Outputs
VDDA = 2.0V
S0
S3
Normal
Operation
Power Off
VDD3.3 = Off
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DC Characteristics
Current Accuracy
Conditions
Configuration
Load
Min
Max
Iout
VDD = nominal (3.30V) M0 = 0 or 1 and Rr shown in Nominal test load for
-7% Inom
+ 7% Inom
Table
given configuration
Nominal test load for
given configuration
Iout
VDD = 3.30 +/- 5%
All combinations of M0 or 1
and Rr shown in Table
-12% Inom + 12% Inom
Note: Inom refers to the expected current based on the configuration of the device.
DC Component Parameters (VDD = 3.3V ±5%, TA = 0°C to +70°C)
Characteristic
Symbol Min
Typ
Max
280
Units
Conditions
Dynamic Supply Current
Idd3.3V
-
-
mA
All frequencies at maximum values,
Note 1
Power Down Supply
current
Ipd3.3V
-
-
See
Note 2
mA
PD# Asserted
Input pin capacitance
Output pin capacitance
Pin Inductance
Cin
Cout
Lpin
Cxtal
-
-
-
-
5
6
pF
pF
nH
pF
-
-
7
Crystal pin capacitance
30
36
42
Measured from the Xin or Xout Pin to
Ground.
Note1: All outputs loaded as per maximum capacitive load table.
Note2: Absolute value = ((Programmed CPU Iref) (7)) + 10 ma
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Document#: 38-07108 Rev. *A
12/26/2002
Page 22 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Package Drawing and Dimensions
56 Pin SSOP Outline Dimensions
C
INCHES
MILLIMETERS
L
SYMBOL
MIN
NOM
MAX
MIN
2.41
NOM
2.59
MAX
2.79
A
A1
A2
B
0.095
0.008
0.088
0.008
0.005
0.720
0.291
0.102
0.110
0.016
0.092
0.0135
0.010
0.730
0.299
H
E
0.012
0.203 0.305 0.406
-
2.24
0.203
0.127
-
-
-
2.34
-
0.343
0.254
a
D
C
D
E
-
0.725
18.29 18.42 18.54
A2
A
0.295
7.39
7.49
7.60
A1
e
0.025 BSC
0.635 BSC
e
B
H
L
0.395
0.020
0º
-
-
-
0.420
0.040
8º
10.03
0.508
0º
-
-
-
10.67
1.016
8º
a
56 Pin TSSOP Outline Dimensions
INCHES
MILLIMETERS
SYMBOL
MIN
NOM
MAX
MIN
-
NOM
MAX
1.20
0.15
1.05
0.27
0.20
A
A1
A2
B
-
-
0.047
0.006
0.041
0.011
0.008
0.555
0.244
-
0.002
0.031
0.007
0.004
0.547
0.236
-
0.039
-
0.05
0.80
0.17
0.09
-
1.00
-
-
C
D
E
-
0.551
0.240
0.02 BSC
0.319
0.024
-
13.90 14.00 14.10
6.00
6.10
0.50 BSC
8.10
6.20
e
H
L
0.315
0.018
0º
0.323
0.030
8º
8.00
0.45
0º
8.20
0.75
8º
0.60
a
-
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 23 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Ordering Information
Part Number
C9870GY
Package Type
56 Pin SSOP
56 Pin TSSOP
Product Flow
Commercial, 0° to 85°C
Commercial, 0° to 85°C
C9870GT
Marking: Example:
C9870GY
IMI
C9870
Date Code, Lot #
Package
Y = SSOP
T = TSSOP
Revision
Device Number
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,
performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in
life supporting and medical applications where the failure or malfunction of the product could cause failure of the life
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is
requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use
of its products in the life supporting and medical applications.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 24 of 25
Approved Product
C9870G
High Performance Pentium® 4 Clock Synthesizer
Document Title: C9870G High Performance Pentium® 4 Clock Synthesizer
Document Number: 38-07108
Rev
ECN
No.
Issue
Date
Orig. of
Change
Description of Change
**
*A
107512
122786
06/14/01 NDP
12/26/02 RBI
Convert from IMI to Cypress
Add power up requirements to maximum ratings
information.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 25 of 25
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