IMICB664ETB [CYPRESS]

Low Skew Clock Driver, B Series, 7 True Output(s), 0 Inverted Output(s), PDSO16;


型号：	IMICB664ETB
厂家：	CYPRESS
描述：	Low Skew Clock Driver, B Series, 7 True Output(s), 0 Inverted Output(s), PDSO16 驱动光电二极管逻辑集成电路
文件：	总5页 (文件大小：71K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CB664

I²C Clock Distribution Buffer for 3 Banks of Mobile SDRAM

Approved Product

PRODUCT FEATURES

PRODUCT DESCRIPTION

The device is a high fanout system clock buffer. Its primary

application is to distribute clocks needed to support a wide

range of applications such as SDRAM clocks. This device

provides low Skew distribution clock heavily loaded. One

important application of this component is where long traces

are used to transport clocks from their generating devices to

their loads. The creation of EMI and the degradation of

waveform rise and fall times is greatly reduced by running a

single reference clock trace to this device and then using it to

regenerate the clock that drives shorter traces. When using

these devices EMI is therefore minimized and board real

estate is saved.

7 output buffer for high clock fanout applications

Output may be individually disabled with I2C

VDD=3.3 volts

Ouput frequency range 10 Mhz to 100 Mhz

< 250ps skew between output clocks.

16-pin SSOP and TSSOP package

BLOCK DIAGRAM

PIN OUT

VDD

I2C Control

VDD

SDR0

SDR1

VSS

CLKIN

SDR2

VDD

SDR6

SDR5

VSS

SDATA

SCLK

SDR[0,1]

SDR2

VDD

SDR4

SDR3

VSS

REFIN

SDR[3,4]

SDR[5,6]

SDATA

SCLK

PIN DESCRIPTION

No.

Name

CLKIN

PWR I/O TYPE

Description

VDD

PAD This pin is connected to the input reference clock. This clock must be in

the range of 10.0 to 100.0 Mhz.

2,3,6,11,12,15,16

VDD

I/O

BUF1 Low skew output clock .

SDR(0:6)

SDATA

SCLK

VSS

PAD serial data of I²C 2-wire control interface. Has internal pull-up resistor.

PAD Serial clock of I²C 2-wire control interface. Has internal pull-up resistor.

4, 10,14

1, 7, 13

COMMON Ground.

Power for output clock buffers and core logic.

VDD

MAXIMUM RATINGS

Voltage Relative to VSS:

Voltage Relative to VDD:

Storage Temperature:

Operating Temperature:

Maximum Power Supply:

-0.3V

0.3V

0ºC to + 125ºC

0ºC to +70ºC

This device contains circuitry to protect the inputs against

damage due to high static voltages or electric field; however,

precautions should be taken to avoid application of any

voltage higher than the maximum rated voltages to this

circuit. For proper operation, Vin and Vout should be

constrained to the range: VSS<(Vin or Vout)<VDD

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev.1.5

5/6/1999

Page 1 of 5

CB664

I²C Clock Distribution Buffer for 3 Banks of Mobile SDRAM

Approved Product

2-WIRE I²C CONTROL INTERFACE

The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub-addressing is

not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control

interface allows each clock output to be individually enabled or disabled.

During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK

is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the

start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer

cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer

cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.

The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on

the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions.

Previously set control registers are retained.

SERIAL CONTROL REGISTERS

NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true

power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.

Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:

1) “Command Code “ byte, and

2) “Byte Count” byte.

Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.

After the Command Code and the Count bytes have been acknowledged, the below desrcibed sequence (Byte

0, Byte 1, Byte2, ....) will be valid and acknowledged.

Byte 0: (1 = enable, 0 = Stopped)

Byte 1: (1 = enable, 0 = Stopped)

Bit

@Pup

Pin#

Description

SDR2 (enable = 1, stopped =0)

Reserved

SDR1 (enable = 1, stopped =0)

SDR0 (enable = 1, stopped =0)

Reserved

Bit

@Pup

Pin#

Description

SDR6 (enable = 1, stopped =0)

SDR5 (enable = 1, stopped =0)

Reserved

SDR4 (enable = 1, stopped =0)

SDR3 (enable = 1, stopped =0)

Reserved

See Application note AN664-01 for further reducing power

consumption with I2C.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev.1.5

5/6/1999

Page 2 of 5

CB664

I²C Clock Distribution Buffer for 3 Banks of Mobile SDRAM

Approved Product

ELECTRICAL CHARACTERISTICS

Characteristic

Symbol

Min

Typ

Max

0.8

Units

Vdc

Conditions

Input Low Voltage

VIL

VIH

IIL

Input High Voltage

2.0

-66

Vdc

µA

Input Low Current

Input High Current

IIH

100

140

µA

Tri-State leakage Current

Dynamic Supply Current

(all outputs loaded with 30pF)

Static Supply Current

Short Circuit Current

Input Rise Time

Ioz

µA

Idd₆₆

Idd₁₀₀

Isdd

ISC

VIR

Input frequency = 66 Mhz

Input frequency 100 Mhz

All outputs disabled no input clock

1 output at a time - 30 seconds

.8 to 2.4 volts

2.4

VDD = VDD1 thru VDD6 =3.3V ±5%, , TA = 0ºC to +70ºC

SWITCHING CHARACTERISTICS

Characteristic

Symbol

Min

Typ

Max

Units

Conditions

Measured at 1.5V (50/50 in)

Output Duty Cycle

Buffer out/out Skew All Buffer

Outputs

tSKEW

250

35 pF Load Measured at 1.5V

Buffer input to output Skew

Jitter Cycle to Cycle*

tSKEW

TJCC

2.0

5.0

@ 35 pF loading

Jitter Absolute (Peak to Peak)*

TJabs

150

VDD = VDD1 thru VDD6 = 3.3V ±5%, , TA = 0ºC to +70ºC

*this jitter is additive to the input clock’s jitter.

BUFFER CHARACTERISTICS (ALL CLOCK OUTPUTS)

Characteristic

Symbol

Min

Typ

Max

-54

Units

Conditions

Pull-Up Current Min

Pull-Up Current Max

Pull-Down Current Min

Pull-Down Current Max

IOH_min

IOH_max

IOL_min

IOL_max

TRF_min

Vout = 1.0 V

Vout = 2.6 V

Vout = 1.2 V

Vout = 0.4 V

30 pF Load

Rise/Fall Time Min

1.33

Between 0.4 V and 2.4 V

Rise/Fall Time Max

TRF_max

1.33

30 pF Load

Between 0.4 V and 2.4 V

VDD = VDD1 thru VDD6 =3.3V ±5%, , TA = 0ºC to +70ºC

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev.1.5

5/6/1999

Page 3 of 5

CB664

I²C Clock Distribution Buffer for 3 Banks of Mobile SDRAM

Approved Product

PCB LAYOUT SUGGESTION

Via to VDD Plane

Via to GND Plane

Void (cut) in power plane

FB1 or R1

VCC

6.8 to 22 uF

This is only a layout recommendation for best performance and lower EMI. The designer may choose a different approach but

C1, C2, C3, (all are 0.1 uf) should always be used and placed as close to their VDD pins as is physically possible. FB1 or R1 is

a Ferrite Bead or resistor as needed to reduce conducted EMI from the device into the systems power circuitry.

PACKAGE DRAWING AND DIMENSIONS

16 PIN SSOP OUTLINE DIMENSIONS

INCHES

MILLIMETERS

SYMBOL

MIN

NOM

MAX

MIN NOM MAX

A₁

A₂

0.068

0.002

0.066

0.010

0.005

0.239

0.205

0.073

0.005

0.078

0.008

0.070

0.015

0.009

0.249

0.212

1.73 1.86

0.05 0.13

1.68 1.73

0.25 0.30

0.13 0.15

6.07 6.20

5.20 5.30

1.99

0.21

1.78

0.38

0.22

6.33

5.38

0.068

0.012

0.006

0.244

0.209

A₂

0.0256 BSC

0.307

0.65 BSC

0.301

0°

0.311

8°

7.65 7.80

0° 4°

0.55 0.75

7.90

A₁

4°

8°

0.95

0.022

0.030

0.037

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev.1.5

5/6/1999

Page 4 of 5

CB664

I²C Clock Distribution Buffer for 3 Banks of Mobile SDRAM

Approved Product

PACKAGE DRAWING AND DIMENSIONS (Cont.)

R0.1

16 PIN TSSOP DIMENSIONS

INCHES

MILLIMETERS

SYMBOL

MIN

NOM

MAX

MIN

NOM

MAX

1.20

0.0433

1.10

0.15

0.95

0.75

1.10

0.0019 0.0039 0.0059

0.0346 0.0354 0.0374

0.0196 0.0236 0.0275

0.0354 0.0393 0.0433

0.05

0.85

0.50

0.90

0.09

0.10

0.90

0.60

1.00

-B-

1.50

SURFACES ROUGHNESS: 6+ 27n(RZ)

[10° TYP

R0.15

0.0035

0.0076

-C-

0.07

0.0108 0.195

0.275

0.245

0.175

0.0076 0.0086 0.0096 0.195

0.0041 0.0068 0.105

0.22

R0.15

14° TYP

1.0

0.05 MAX.

0.0041 0.0049 0.0057 0.105 0.125 0.145

0°

8°

0°

8°

0.026 BSC

0.65 BSC

1.0

0.05 MAX.

0.1948 0.1968 0.1988

0.2480 0.2519 0.2559

0.1712 0.1732 0.1752

4.95

6.3

5.0

6.4

4.4

5.05

6.5

4.45

4.35

0.20

.08

0.0078

8°

0.25

DETAIL

DETAIL B

ORDERING INFORMATION

Part Number

Package Type

16 PIN SSOP

16 PIN TSSOP

Production Flow

IMICB664EYB

IMICB664ETB

Commercial, 0ºC to +70ºC

Note:

The ordering part number is formed by a combination of device number, device revision, package style, and

screening.

Purchase of I²C components of International Microcircuits, Inc. or one of its sublicensed Associated Companies conveys a license under the Phillips

I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by

Phillips.

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571

Rev.1.5

5/6/1999

Page 5 of 5

IMICB664ETB [CYPRESS]

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