IMICB660EYB [CYPRESS]
Processor Specific Clock Generator, CMOS, PDSO28, SSOP-28;
| 型号： | IMICB660EYB |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, CMOS, PDSO28, SSOP-28 光电二极管 外围集成电路 |
| 文件： | 总8页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CB660
I2C System Clock Buffer for Mobile Applications
Approved Product
PRODUCT FEATURES
PRODUCT DESCRIPTION
10 output buffer for high clock fanout applications
Each output can be internally disabled for EMI and
power consumption reduction.
The device is a high fanout system clock regenerator.
Its primary application is to create the large quantity of
clocks needed to support a wide range of applications
that require a large number of clock loads that are
referenced to a single existing clock. Loads of up to 30
pF are supported. One of the chief applications of this
component is where long traces are used to transport
clocks from their generating devices to their loads.
The creation of EMI and the degradation of waveform
rise and fall times is greatly reduced by running a
single reference clock trace to this device and then
using it to regenerate the clock that drives shorter
traces by using the IMICB660 to generate the clocks at
the target devices EMI is therefore minimized and
board real estate is saved.
Separate power supply for each group of 2 clock
outputs for mixed voltage application.
< 250ps skew between output clocks.
28-pin SSOP & TSSOP packages for minimum
boad space
Single Clock Enable pin for testability
CONNECTION DIAGRAM
BLOCK DIAGRAM
VDDB
28
SDRAM(0:1)
1
VDDB
SDRAM0
SDRAM1
VSS
VDDB
2
27
26
25
24
23
22
21
20
19
18
17
16
15
SDRAM9
SDRAM8
VSS
3
SDRAM(2:3)
4
5
VDDB
VDDB
6
SDRAM2
SDRAM3
VSS
SDRAM7
SDRAM6
VSS
SDRAM4
7
8
FIN
9
FIN
OE
SDRAM5
10
11
12
13
14
VDDB
VDDB
SDRAM4
VSS
SDRAM5
VSS
VDD
SDRAM(6:7)
VDD
VSS
SDATA
SCLOCK
SDATA
SCLOCK
SDRAM(8:9)
OE
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 1 of 8
CB660
I2C System Clock Buffer for Mobile Applications
Approved Product
PIN DESCRIPTION
PIN
No.
9
Pin
Name
FIN
PWR
-
I/O
I
TYPE
Description
PAD
This pin is connected to the input reference clock. This
clock must be in the range of 10.0 to 100.0 Mhz.
2,3
6, 7
11
SDRAM(0:1)
SDRAM(2:3)
SDRAM4
VDDB
VDDB
VDDB
VDDB
VDDB
VDDB
-
O
O
O
O
O
O
I
BUF1 Low skew output clock .
BUF1 Low skew output clock .
BUF1 Low skew output clock .
BUF1 Low skew output clock .
BUF1 Low skew output clock .
BUF1 Low skew output clock .
18
SDRAM5
22, 23
26,27
20
SDRAM(6:7)
SDRAM(8:9)
OE
PAD
Buffer Output Enable pin. This pin is low it is used to place
all output clocks (CLK1:10) in a tri state condition. This
feature facilitates in production board level testing to be
easily implemented for the clocks that this device produces.
Has internal pull-up resistor.
14
15
SDATA
SCLOCK
VSS
VDD
VDD
I/O
I
PAD
PAD
-
Serial data of I2C 2-wire control interface. Has internal pull-
up resistor.
Serial clock of I2C 2-wire control interface. Has internal
pull-up resistor.
4, 8, 12,
16, 17,
21, 25
1, 5, 10,
19, 24,
28
PWR
Ground pins for clock output buffers. These pins must be
returned to the same potential to reduce output clock skew.
VDDB
VDD
-
-
PWR
PWR
-
-
Power for output clock buffers.
Pin for device core logic.
13
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 2 of 8
CB660
I2C System Clock Buffer for Mobile Applications
Approved Product
2-WIRE I2C CONTROL INTERFACE
The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub-
addressing is not supported, thus all preceeding bytes must be sent in order to change one of the control bytes. The 2-
wire control interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when
SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to
indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of
a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first
byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low)
signal on the SDATA wire following reception of each byte. The device will not respond to any other control interface
conditions. Previously set control registers are retained.
SERIAL CONTROL REGISTERS
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below desrcibed sequence (Byte
0, Byte 1, Byte2, ....) will be valid and acknowledged.
Byte 0: Function Select Register(1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
-
-
-
-
7
6
3
2
Description
reserved
reserved
reserved
1
1
1
1
1
1
1
1
reserved
SDRAM3 (Active = 1, Forced low = 0)
SDRAM2 (Active = 1, Forced low = 0)
SDRAM1 (Active = 1, Forced low = 0)
SDRAM0 (Active = 1, Forced low = 0)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 3 of 8
CB660
I2C System Clock Buffer for Mobile Applications
Approved Product
SERIAL CONTROL REGISTERS (Cont.)
Byte 1: Clock Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
1
1
1
1
1
1
1
1
27
26
23
22
-
-
-
-
SDRAM9 (Active = 1, Forced low = 0)
SDRAM8 (Active = 1, Forced low = 0)
SDRAM7 (Active = 1, Forced low = 0)
SDRAM6 (Active = 1, Forced low = 0)
reserved
reserved
reserved
reserved
Byte 4: Clock Register ( 1 = enable, 0 = Stopped )
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Description
SDRAM5 (Active = 1, Forced low = 0)
SDRAM4 (Active = 1, Forced low = 0)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
0
0
0
0
0
0
1
1
18
11
-
-
-
-
-
-
MAXIMUM RATINGS
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
0ºC to + 125ºC
0ºC to +70ºC
7V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 4 of 8
CB660
I2C System Clock Buffer for Mobile Applications
Approved Product
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Min
Typ
Max
0.8
Units
Conditions
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
VIL
VIH
IIL
-
-
-
Vdc
Vdc
µA
-
-
2.0
-66
-
IIH
66
µA
Output Low Voltage
IOL = 4mA
VOL
-
-
-
0.4
Vdc
All Outputs (see buffer spec)
Output High Voltage
IOH = 4mA
VOH
2.4
-
Vdc
All Outputs Using 3.3V Power
(see buffer spec)
Tri-State leakage Current
Ioz
-
-
-
-
10
µA
Idd66
140
mA
Input frequency = 66 Mhz - All outputs
on and at 30 pF load
Dynamic Supply Current
Idd100
-
-
180
mA
Input frequency 100 Mhz - All outputs on
and at 30 pF load
Static Supply Current
Short Circuit Current
Input Rise Time
Isdd
ISC
TIR
-
-
-
-
1
-
mA
mA
nS
All outputs disabled no input clock
1 output at a time - 30 seconds
.8 to 2.4 volts
25
2.4
-
VDD = VDD1 thru VDD5 =3.3V ±5%, , TA = 0ºC to +70ºC
SWITCHING CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Measured at 1.5V (50/50 in)
Output Duty Cycle
-
45
-
50
-
55
%
Buffer out/out Skew All
Buffer Outputs
tSKEW
250
pS
35 pF Load Measured at 1.5V
Buffer input to output Skew
Jitter Cycle to Cycle*
tSKEW
TJCC
2.0
4.0
5.0
50
nS
pS
pS
@ 35 pF loading
@ 35 pF loading
Jitter Absolute (Peak to
Peak)*
TJabs
150
VDD = VDD1 thru VDD5 = 3.3V ±5%, , TA = 0ºC to +70ºC
*This jitter is additive to the input clock’s jitter.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 5 of 8
CB660
I2C System Clock Buffer for Mobile Applications
Approved Product
TYPE 1 BUFFER CHARACTERISTICS (ALL CLOCK OUTPUTS)
Characteristic
Symbol
Min
Typ
Max
-54
Units
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
TRFmin
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
nS
Vout = 1.0 V
-30
54
Vout = 2.6 V
Vout = 1.2 V
Vout = 0.4 V
30 pF Load
23
Rise/Fall Time Min
1.33
Between 0.4 V and 2.4 V
Rise/Fall Time Max
TRFmax
-
-
1.33
nS
30 pF Load
Between 0.4 V and 2.4 V
VDD = VDD1 thru VDD5 =3.3V ±5%, , TA = 0ºC to +70ºC
PACKAGE DRAWING AND DIMENSIONS
28 PIN SSOP OUTLINE DIMENSIONS
INCHES
NOM
MILLIMETERS
C
SYMBOL
MIN
MAX
MIN
NOM
MAX
L
A
A1
A2
B
0.068
0.002
0.066
0.010
0.005
0.397
0.205
0.073
0.005
0.078 1.73
0.008 0.05
0.070 1.68
0.015 0.25
0.009 0.13
0.407 10.07
0.212 5.20
1.86
0.13
1.99
0.21
1.78
0.38
0.22
10.33
5.38
H
E
0.068
1.73
0.012
0.30
C
D
E
0.006
0.15
0.402
10.20
5.30
D
a
0.209
A2
A
e
0.0256 BSC
0.307
0.65 BSC
7.80
H
a
0.301`
0.311 7.65
7.90
A1
0
°
4
°
8
°
0
°
4
°
8
°
e
B
L
0.022
0.030
0.037 0.55
0.75
0.95
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 6 of 8
CB660
I2C System Clock Buffer for Mobile Applications
Approved Product
PACKAGE DRAWING AND DIMENSIONS
D
R0.1
28 PIN TSSOP DIMENSIONS
INCHES
MILLIMETERS
E1
SYMBOL
MIN
NOM
MAX
MIN
NOM
MAX
BO
L20
A
A1
A2
L
-
-
0.004
0.039
0.023
0.039
-
0.047
0.006
0.041
0.029
0.043
0.011
0.010
0.007
0.006
-
-
0.10
1.00
0.60
1.00
-
1.20
0.15
1.05
0.75
1.10
0.30
0.25
0.175
0.145
0.002
0.037
0.019
0.035
0.007
0.007
0.004
0.004
0.05
0.95
0.50
0.90
0.19
0.19
0.105
0.105
-B-
385
SURFACES ROUGHNESS: 6+ 27n(RZ)
4
RD
[10° TYP
L1
b
-C-
0.07
C
B
e
b1
c
0.008
-
0.22
-
R1.30
1.0
c1
θ
0.005
-
0.125
-
0.00 ~ 0.05
0.10~0.15
0
°
8
°
0
°
8
°
e
0.026 BSC
0.382
0.252
0.173
-
0.65 BSC
9.7
D
0.378
0.244
0.169
0.035
0.386
0.260
0.177
-
9.6
6.2
4.3
0.9
9.8
6.6
4.5
-
SECTION V-V
E
6.4
E1
R
4.4
R0.15
14°TYP
-
1.0
0.05 MAX.
1.0
0.05 MAX.
A
E
b
.08
C B
A
8°
R
A
A2
c
c1
0.25
L
b1
A1
L1
DETAIL A
DETAIL B
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 7 of 8
CB660
I2C System Clock Buffer for Mobile Applications
Approved Product
ORDERING INFORMATION
Part Number
IMICB660EYB
IMICB660ETB
Package Type
28 PIN SSOP
28 PIN TSSOP
Production Flow
Commercial, 0ºC to +70ºC
Commercial, 0ºC to +70ºC
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
CB660EYB
Date Code, Lot #
IMICB660EYB
Flow
B = Commercial, 0ºC to + 70ºC
Package
Y = SSOP
T = TSSOP
Revision
IMI Device Number
Purchase of I2C components of International Microcircuits, Inc. or one of its sublicensed Associated Companies conveys a license under the Phillips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Phillips.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
2/2/98
Page 8 of 8
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