IMIC9914BY [CYPRESS]
Processor Specific Clock Generator, CMOS, PDSO28, SSOP-28;
| 型号： | IMIC9914BY |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, CMOS, PDSO28, SSOP-28 光电二极管 外围集成电路 |
| 文件： | 总13页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Frequency Table(MHz)
Product Features
HFS#
SEL 100/66#
CPU(1:2)
PCI(_F,1:5)
•
•
•
•
•
•
•
•
•
•
•
•
Supports Intel 440BX, and VIA Promedia chipsets
Supports mobile Pentium®II and Pentium®III
2 REF clocks
1
1
0
0
0
1
0
1
66.6
100
150
33.3
33.3
37.5
33.3
133.3
2 Low Skew (<175pS) CPU clocks
Table 1
6 PCI Clocks (1 free running, 5 manageable)
1 48MHz fixed clock
1 selectable 48 or 24 MHz fixed clock
Separate supply pins for mixed 3.3/2.5V application.
High Speed host bus operation, up to 150MHz
IMI Spread Spectrum technology for reducing EMI
Rich Power Management Functions.
28-pin SSOP & TSSOP packages for minimum
board space.
Pin Configuration
Block Diagram
36pF
36pF
XIN
VDDR
VDDR
VDDC
VSS
XIN
XOUT
PCI_F
PCI1
PCI2
VSS
VDDP
PCI3
PCI4
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDR
REF2/SS#
REF1/SEL48#
CPU(0:1)
1
1
2
XB
UF
300K
REF1/SEL48#
REF2/SS#
VDDC
CPU1
CPU2
VSS
VSS
PS#
VDD
CS#
XOUT
Rin
cpu
pci
HFS#
s100/66#
9
SEL100/66#
10
11
12
13
14
PD#
CS#
PS#
PD#
CS#
PS#
VDDP
VDDF
PCI5
VDDF
48M
6
1
PCI(_F,1:5)
48MHz
PD#
SEL100/66#
VSS
SS#
48_24/HFS#
PLL1
VDDF
0
1
Rin
48
24
48_24/HFS#
1
PD#
PLL2
Fig.1
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 1 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Pin Description
PIN No.
Pin Name
PWR
I/O
Description
2
XIN
VDD
I
On-chip reference oscillator input pin. Requires either an external parallel
resonant crystal (nominally 14.318 MHz) or externally generated
reference signal
3
XOUT
VDD
O
O-chip reference oscillator output pin. Drives an external parallel
resonant crystal (14.318 MHz) when an externally generated reference
signal is used.
19
23, 24
17
18
16
VDD
CPU(2,1)
PD#
CS#
SEL100/66#
-
P
O
I
I
I
3.3 volt power supply for core logic.
VDDC
CPU Clock outputs. See frequency table page 1.
-
-
-
Powers down device when LOW(1)
When signal is LOW, stops CPU clocks in low state. (1)
Frequency select input pins. See frequency select table 1 on page 1. NO
INTERNAL PULLUP RESISTOR AT THIS INPUT.
2.5V power for CPU and Host clock outputs.
Free running PCI clock 3.3V. Does not stop when PS# is at a logic LOW
level
25
4
VDDC
PCI_F
-
P
O
VDDP
5,6,9,
10,11
20
8
13
PCI(1:5)
VDDP
O
PCI output clocks. See frequency table of page 1.
PS#
VDDP
48M
-
-
I
P
O
When signal is LOW, stops all PCI clocks in low state. (1)
3.3 Volt power supply pins for free running PCI clock output buffer.
Fixed 48 MHz clock.
VDDF
VDDF
14
48-24MHZ /
HFS#
I/O This is a Power up Bi-directional pin. During power up, this pin is an
HFS# input. HFS# is a High Frequency Select line for programming the
CPU/PCI output clock frequency, see table 1 page 1. For strapping
resistor, see application note page 5. When the power reaches the rail,
this pin becomes an SIO or USB clock output depending on the state of
pin 27, SEL48#. If SEL48# is strapped high, then the frequency is
24MHz, SIO. If SEL48# is strapped low, then the frequency is 48MHz,
USB. (1)
26
27
REF1 / SS#
VDDR
VDDR
I/O At power up this pin determines if the device’s spread spectrum
modulation feature is enabled or disabled. After power up this pin
becomes a reference clock output. A 0 (logic low) enables SSCG and a 1
(logic high) disables SSCG. (1)
I/O At power up this pin determine the frequency of the clock at pin 14. If it is
LOW, the clock will be 48 MHz, if HIGH the clock will be 24 MHz. After
power up this pin will become a reference clock output. (Default high)
REF2 /
SEL48#
12
1,7,15,
21,22
28
VDDF
VSS
-
-
P
P
Power for fixed clock output buffer.
Ground pins for device.
VDDR
-
P
Power for Reference Oscillator output buffer.
Note:
1. Pins have internal pullup resistors that will guarantee to a logic 1 (high) level if no connection is made to the device’s pin. Other pins do not
contain this function and must be electrically connected to VDD or VSS by external circuitry to ensure a valid logic 1 or 0 is sensed.
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 2 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Power Management Functions
PS#
X
CS#
X
PD#
CPU (1:2)
LOW
LOW
ON
48M, 48_24M
PCI (1:5)
LOW
ON
PCI_F
LOW
ON
REF (1:2)
LOW
ON
VCOs
OFF
ON
0
1
1
1
1
LOW
ON
1
0
0
1
ON
LOW
LOW
ON
ON
ON
ON
0
0
LOW
ON
ON
ON
ON
ON
1
1
ON
ON
ON
ON
CS# is the CPU stop control pin. It is used to turn off the CPU clocks for low power operation. CS# is asserted
asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU Clock)
and must be internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU
clocks are disabled. The CPU clocks will always be stopped in a low state and started in such a manner as to guarantee
that the high pulse width is a full pulse. CPU clock on latency need to be 2 or 3 CPU clocks periods in time and CPU
clock off latency needs to be 2 or 3 CPU clocks periods in time.
CPU
CS#
CPU STOP TIMING
CPU
PCI
REF
48M
PD#
POWER DOWN TIMING
PCI
PS#
PCI STOP TIMING
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 3 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Power Management Functions (Cont.)
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal clocks are not running
after the device is put in power down. When PD# is active low, all clocks need to be driven to a low value and held prior
to turning off the VCO’s and the Crystal. The power-up latency needs to be less than 3 mS. The power down latency
should be as short as possible but conforming to the sequence requirements shown below. AS# and CS# are
considered to be don’t cares during the power down operations.
Power Management Timing
Latency
Signal
Signal State
0 (disabled)
No. of rising edges of free running PCI
CLOCK (PCIF)
CS#
1
1
1 (enabled)
PD#
1 (cold start/normal operation)
0 (power down)
3 mS
1
NOTES: Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable goes low/high to the
first valid clock comes out of the device.
Power on Bi-Directional Pins
Power Up Condition:
Pins 14, 26, and 27 are Power up bi-directional pins and are used for different features in this device (see Pin description,
Page 2). During power-up, these pins are in input mode (see Fig 2, below), therefore, they are considered input select
pins internal to the IC. After a settling time, the Selection data is latch into internal control registers and these pins
become toggling clock outputs.
VDD Rail
Power Supply
Ramp
48_24MHz/HFS#
REF1/SS#
-
Hi-Z Inputs
Toggle Outputs
REF2/SEL48#
Select Data is latched into register then pin becomes clock output signal.
Fig. 2
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 4 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Vdd
Strapping Resistor Options for pins with internal
Pull-ups:
Rup
50K
IMI C9914
The power up bidirectional pins have a large value pull-
up each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
3mS settling time), then it is recommended to use an
Rd
Load
Bidirectional
JP1
JUMPER
external Pullup (Rup)
in order to insure a high
selection. In this case, the designer may choose one of
two configurations, see Fig. 3A and Fig. 3B.
Fig.3A
Rdn
5K
Fig. 3A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.3A. Please note the selection resistors (Rup, and
Rdn) are placed before the Damping resistor (Rd)
close to the pin.
JP2
Vdd
3 Way Jumper
Rsel
10K
Fig. 3B represent a single resistor 10KΩ connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
IMI C9914
Rd
Load
Bidirectional
Fig.3B
Spectrum Spread Clocking
Non -Spread
Reduction
Spread
Spectrum Analysis
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 5 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Spectrum Spreading Selection Table
Min
(MHz)
Center
(MHz)
Max
(MHz)
CPU
Frequency
% OF FREQUENCY
SPREADING
MODE
99.3
66.13
132.4
148.95
99.65
66.37
100
66.6
100
66
.7% (-.7% + 0%)
.7% (-.7% + 0%)
.7% (-.7% + 0%)
.7% (-.7% + 0%)
Down Spread
Down Spread
Down Spread
Down Spread
132.87
149.48
133.33
150
133.3
150
Test and Measurement Condition
Output
Buffer
Test Point
Specified Test Load Condition
CL
Clock Output Wave Form
3.3 V Clocking Interface
2.5 V Clocking Interface
CPU (1,2)
PCI (_F,1:5) , 48-24M, 48 M, REF(1,2)
tHKP
tHKP
Duty Cycle
DutyCycle
3.3 V
2.5 V
2.0 V
1.25 V
0.4 V
0.0 V
2.4 V
1.5 V
0.4 V
0.0 V
tr
tf
tr
tf
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 6 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Absolute Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65ºC to + 150ºC
0ºC to +85ºC
2KV
VSS<(Vin or Vout)<VDD
5.5V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Electrical Characteristics
Characteristic
Symbol Min
Typ
Max
0.8
Units
Vdc
Vdc
µA
Conditions
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
VIL
VIH
IIL
-
-
-
2.0
-
-66
5
IIH
µA
Output Low Voltage
IOL = 4mA
VOL
-
-
-
0.4
Vdc
All Outputs (see buffer spec)
Output High Voltage
IOH = 4mA
VOH
2.4
-
Vdc
All Outputs Using 3.3V Power
(see buffer spec)
Dynamic Supply Current
(2.5 Volt Supply)
Idd266
Idd266
Idd3100
Idd3100
I2.5PD
I3.3PD
-
-
-
-
-
-
-
-
-
-
-
-
70
40
70
50
50
4.5
mA
mA
mA
mA
µA
CPU = 66.6M
CPU = 66.6M
Dynamic Supply Current
(3.3 Volt Supply)
CPU = 100M
CPU = 100M
Power Down Mode
Power Down Mode
PD# at logic low level
PD# at logic low level
mA
VDD = VDDF = VDDP=VDDR =3.3V ±5%, VDDC = 2.5V ±5%, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
Rev. 1.0
2/4/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Page 7 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
AC Switching Characteristics
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
CPU= Measured at 1.25V
Output Duty Cycle
-
45
50
55
%
all others measured at 1.50V
CPU to PCI Offset
(CPU leads)
tOFF
1.5
-
4
ns
CPU=20 pF load Measured at 1.25V
PCI=30 pF load Measure at 1.50V
-
-
pS
PCI Only
∆Period Adjacent Cycles
∆P
±500
VDD = VDDF = VDDP =VDDR =3.3V ±5%, VDDC = 2.5V ±5%, TA = 0ºC to +70ºC
AC Skew Requirements
Characteristic
CPU (20pF)
48 MHz
Bank Skew
175pS
n/a
Cycle to Cycle Jitters VDD
Skew, Jitters Measure Point
250pS
500pS
500pS
500pS
2.5V
3.3V
3.3V
3.3V
1.25V
1.5V
1.5V
1.5V
PCI, PCI_F (30pF)
REF
500pS
n/a
Buffer Characteristics
Buffer Characteristics for CPU Outputs
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
TR
-27
-
mA
mA
mA
mA
nS
Vout = 1.0 V
Vout = 2.375 V
Vout = 1.2 V
Vout = 0.3 V
20 pF Load
-27
27
-
-
-
-
-
30
1.6
Rise Time
0.4
Between 0.4 V and 2.0 V
Fall Time
TF
0.5
-
1.6
nS
20 pF Load
Between 0.4 V and 2.0 V
VDD = VDDF = VDDP = VDDR =3.3V ±5%, VDDC = 2.5V ±5%, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
Rev. 1.0
2/4/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Page 8 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Buffer Characteristics for 48M, 48-24M and REF Outputs
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
TR
-29
-
-
-
-
-
-
-
mA
mA
mA
mA
nS
Vout = 1.0 V
Vout = 3.135 V
Vout = 1.95 V
Vout = 0.4 V
20 pF Load
-63
20
-
-
27
2.0
Rise Time
0.5
Between 0.4 V and 2.4 V
Fall Time
TF
0.5
-
2.0
nS
20 pF Load
Between 0.4 V and 2.4 V
DC Buffer Characteristics for PCI_F, PCI (1:5)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
TR
-33
-
-
-
-
-
-
-
-100
-
mA
mA
mA
mA
nS
Vout = 1.0 V
Vout = 3.135 V
Vout = 1.95 V
Vout = 0.4 V
30 pF Load
20
-
38
2.0
Rise Time
0.5
Between 0.4 V and 2.4 V
Fall Time
TF
0.5
-
2.0
nS
30 pF Load
Between 0.4 V and 2.4 V
VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%, TA = 0ºC to +70ºC
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 9 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Suggested Oscillator Crystal Parameters
Characteristic
Symbol
Min
Typ
Max
Units
MHz
PPM
PPM
Conditions
Frequency
Fo
14.17
14.31818
14.46
Tolerance
TC
-
-
-
-
-
-
-
+/-100
Note 1
Frequency Stability
Operating Mode
Load Capacitance
TS
+/- 100
Stability (TA -10 to +60C) Note 1
Parallel Resonant, Note 1
The crystal’s rated load. Note 1
Note 2
-
-
-
-
-
CXTAL
RESR
20
40
pF
Effective Series
Ohms
Resistance (ESR)
Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen
crystal meets or exceeds these specifications
Note 2: Larger values may cause this device to exibit oscillator startup problems
To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the
effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit trace
capacitance (CPCB), and any onboard discrete load capacitance (CDISC).
The following formula and schematic illustrates the application of the loading specification of a crystal (CXTAL)for a design.
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC
)
)
Where:
CXTAL
= the load rating of the crystal
CXOUTFTG = the clock generators XIN pin effective device internal capacitance to ground
CXOUTFTG = the clock generators XOUT pin effective device internal capacitance to ground
CXINPCB
CXOUTPCB = the effective capacitance to ground of the crystal to device PCB trace
CXINDISC = any discrete capacitance that is placed between the XIN pin and ground
= the effective capacitance to ground of the crystal to device PCB trace
CXOUTDISC = any discrete capacitance that is placed between the XOUT pin and ground
XIN
CXINPCB
CXINDISC
CXINFTG
CXOUTPCB
CXOUTDISC
CXOUTFTG
XOUT
Clock Generator
As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC) and each
of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as:
CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF) = 40 X 40
(4pF + 36pF + 0pF) + (4pF + 36pF + 0pF) 40 + 40
= 1600
80
= 20pF
Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you
should specify a parallel cut crystal that is designed to work into a load of 20pF
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 10 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Package Drawings and Dimensions
28 Pin SSOP Outline Dimensions
INCHES
MILLIMETERS
SYMBOL
A
MIN
NOM
MAX
MIN
NOM
1.86
MAX
1.99
C
0.068
0.073
0.005
0.068
0.012
0.006
0.402
0.209
0.025 BSC
0.307
4°
0.078 1.73
0.008 0.05
0.070 1.68
0.015 0.25
0.009 0.13
0.407 10.07
0.212 5.20
L
A1
A2
B
0.002
0.066
0.010
0.005
0.397
0.205
0.13
1.73
0.21
1.78
0.38
0.22
10.33
5.38
H
E
0.30
C
D
E
0.15
10.20
5.30
a
D
e
0.635 BSC
7.80
A2
A
H
a
0.301`
0°
0.311 7.65
7.90
8°
A1
8°
0°
4°
e
B
L
0.022
0.030
0.037 0.55
0.75
0.95
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 11 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Package Drawings and Dimensions
D
28 Pin TSSOP Dimensions
R0.1
INCHES
MILLIMETERS
SYMBOL
MIN
NOM
MAX
MIN
NOM
MAX
A
-
-
0.047
-
-
1.20
0.15
1.05
0.75
1.10
0.30
0.25
0.175
A1
A2
L
0.002
0.037
0.019
0.035
0.007
0.007
0.004
0.004
0°
0.004
0.039
0.023
0.039
-
0.006
0.041
0.029
0.043
0.011
0.010
0.007
0.006
8°
0.05
0.95
0.50
0.90
0.19
0.19
0.105
0.10
1.00
0.60
1.00
-
E1
BO
L20
L1
b
-B-
385
SURFACES ROUGHNESS: 6+ 27n(RZ)
b1
c
0.008
-
0.22
-
4
RD
[10° TYP
c1
θ
0.005
-
0.105 0.125 0.145
-C-
0.07
C
B
e
-
0°
8°
e
0.026 BSC
0.382
0.252
0.173
-
0.65 BSC
R1.30
1.0
D
0.378
0.244
0.169
0.035
0.386
0.260
0.177
-
9.6
6.2
4.3
0.9
9.7
6.4
4.4
-
9.8
6.6
4.5
-
0.00
~ 0.05
0.10~0.15
E
E1
R
SECTION V-V
R0.15
14° TYP
1.0
0.05 MAX.
1.0
0.05 MAX.
A
E
b
.08
C
B
A
8°
R
A
A2
c
c1
0.25
L
b1
A1
L1
DETAIL A
DETAIL B
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 12 of 13
C9914
Clock Generator for 100MHz and 133.3MHz Mobile Applications
Preliminary
Ordering Information
Part Number
IMIC9914BY
IMIC9914BT
Package Type
Production Flow
Commercial, 0°C to + 85°C
Commercial, 0°C to + 85°C
28 PIN SSOP
28 PIN TSSOP
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
C9914
Date Code, Lot #
IMIC9914BY
Package
Y = SSOP
T = TSSOP
Revision
IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC., 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX: 408-263-6571
http://WWW.IMICORP.COM/
Rev. 1.0
2/4/2000
Page 13 of 13
相关型号：
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