IMIC9915AYT [CYPRESS]
Processor Specific Clock Generator, 133.3MHz, CMOS, PDSO48, SSOP-48;
| 型号： | IMIC9915AYT |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 133.3MHz, CMOS, PDSO48, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总18页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C9915
®
Low EMI Clock Generator for Intel 133-MHz/2-DIMM Chipset Systems
Features
• Meets Intel 133-MHz/SDRAM chipset specification
• Three copies of CPU clock (CPU[0:1] and CPU2_ITP)
• Nine copies of SDRAM clock (SDRAM[0:7] and DCLK)
• Seven copies of PCI clock
• One REF clock
• One USB clock (non-SSC)
• One DOT clock (non-SSC)
• Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
• Three copies of 3V66 clock
• SMBus support with read back
• 56-pin SSOP/TSSOP package
• Two copies of IOAPIC clock
Table 1. Frequency Table (MHz) [1]
SEL2
SEL1
SEL0
CPU
SDRAM
X
PCI
0
X
X
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
Three-State
Test Mode
66.6 MHz
100 MHz
X
0
100 MHz[2]
100 MHz[2]
133.3 MHz
100 MHz[2]
33.3
33.3
33.3
33.3
133.3 MHz
133.3 MHz
Pin Configuration
Block Diagram
XIN
56
REF/SEL2
VDD
1
2
3
4
5
6
7
8
VSS
36pF
36pF
IOAPIC0
IOAPIC1
VDDI
CPU0
VDDC
CPU1
CPU2(ITP)
VSS
55
54
53
52
51
50
49
300K
XIN
XOUT
VSS
XOUT
VDD
REF / SEL2
IOAPIC(0:1)
1
VSS
3V66_0
3V66_1
3V66_2(AGP)
VDD
VDDI
9
48
47
46
45
s2
apic
cpu
2
3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
VSS
I
M
I
C
9
9
1
5
VDD
PCI0(ICH)
PCI1
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
SDRAM6
SDRAM7
VSS
VDDC
CPU(0:2)
44
43
42
41
Rin
VSS
PCI2
PCI3
VSS
PCI4
PCI5
PCI6
VDD
VDDA
VSSA
VSS
USB
DOT
VDD
SEL0
SCLK
SDATA
i2c-clk
i2c-data
VDDS
VDD
SEL1
SEL0
SDRAM(0:7), DCLK
3V66(0:2)
s1
s0
sdram
3V66
pci
9
2
40
39
38
37
36
pwr_dwn#
PWRGD/
PWRDN#
VDD
VDD
VDD
35
34
33
PCI(0:6)
DOT
8
1
1
DCLK
VDD
PWRGD/PWRDN#
SCLK
SDATA
PLL1
Rin
24
25
26
27
32
31
30
48
PD#
USB
28
SEL1
29
i2c-clk
i2c-data
PLL2
Notes:
1. The following clocks remain fixed frequencies except in Test Mode: 3V66 = 66.6 MHz, USB/DOT = 48 MHz, REF = 14.318 MHz, and IOAPIC = 33.3 MHz.
2. SMBus programmable to 133 MHz, Byte 3, Bit 0.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07123 Rev. *B
Revised December 14, 2002
C9915
Pin Description[3]
Pin
Name
PWR
VDD
I/O
Description
1
SEL2/REF
I/O This is a bidirectional pin. At power-up, it is an input pin Sel2 for selecting
the CPU/SDRAM frequencies (see Table 1). When the power reaches the
rail, the state of Sel2 is latched, and this pin becomes REF, a buffer output
of the signal applied at Xin, typically 14.318 MHz. This pin has an Internal
pull-down. Typical 50 KΩ (range 20 KΩ to 70 KΩ).
3
4
XIN
VDD
VDD
VDD
I
On-chip Reference Oscillator Input Pin. Requires either an external
parallel resonant crystal (nominally 14.318 MHz) or externally generated
reference signal
XOUT
PCI0_ICH
O
O
On-chip Reference Oscillator Pin. Drives an external parallel resonant
crystal. When an externally generated reference signal is used at Xin, this
pin remains unconnected.
12,13,15,
16,18,19, 20 PCI(1..6)
3.3V PCI Clock Outputs. They are synchronous to CPU clocks. See
Figure 11).
7, 8, 9
25
3V66(0:2)
USB
VDD
VDD
VDD
VDD
O
O
O
I
3.3V Fixed 66.6 MHz Clock Outputs. See Figure 11.
3.3V Fixed 48 MHz clock outputs.
26
DOT
3.3V Fixed 48 MHz clock outputs.
28, 29
SEL(0,1)
3.3V LVTTL Inputs for Logic Selection. This pin has an internal pull-up.
Typical 250 KΩ (range 200 KΩ to 500 KΩ)
30
SDATA
VDD
I/O Serial Data Input Pin. Conforms to the SMBus specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an
open drain output when acknowledging or transmitting data. See SMBus
function description.
31
32
SCLK
VDD
I
I
Serial Clock Input Pin. Conforms to the SMBus specification.
PWRGD/PWR VDD
DN#
This is a Dual Function Pin. During power-up, it serves as a power-down
control. After PWRGD has gone HIGH once, whenever pin 32 goes LOW,
the device will go into power-down mode.
34
DCLK
VDD
O
O
O
O
3.3V SDRAM Feedback Clock. See Table 1 for frequency selection. See
Figure 11 for timing relationship.
36,37,39,40, SDRAM(7..0) VDDS
42,43,45, 46
3.3V SDRAM DIMM Clocks. See Table 1 for frequency selection. See
Figure 11 for timing relationship.
49, 50, 52
CPU(2)_ITP,C VDDC
PU(1,0)
2.5V Host Clock Outputs. See Table 1 for frequency selection.
54, 55
IOAPIC(1,0)
VDD
VDDI
2.5V IOAPIC Clock Outputs. See Figure 11 for timing relationship.
2,10, 11, 21,
27, 33
3.3V Common Power Supply
22
VDDA
Analog Circuitry 3.3V Power Supply
Analog Circuitry Power Supply Ground Pins
2.5V Power Supply
23
VSSA
51, 53
VDDC, VDDI
5, 6,14, 17, 24, VSS
35, 41, 47, 48,
56
Common Ground Pins
38, 44
VDDS
3.3V Power Support for SDRAM Clock Output Drivers
Note:
3. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins their high
frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07123 Rev. *B
Page 2 of 18
C9915
SDATA while SCLK is HIGH is used to indicate the start of a
data transfer cycle. A LOW-to-HIGH transition on SDATA while
SCLK is HIGH indicates the end of a data transfer cycle. Data
is always sent as complete eight-bit bytes, after which an
acknowledge is generated. The first byte of a transfer cycle is
an eight-bit address. The LSB address Byte = 0 in write mode.
Two-Wire SMBus Control Interface
The two-wire control interface implements a Read/Write
slave-only interface, according to SMBus specification. (See
Figure 1 and Figure 2, below). The device can be read back
by using standard SMBus command bytes. Subaddressing is
not supported, thus all preceding bytes must be sent in order
to change one of the control bytes. The two-wire control
interface allows each clock output to be individually enabled
or disabled. 100 Kbits/second (standard mode) data transfer
is supported.
The device will respond to transfers of 10 bytes (max) of data.
The device will generate an acknowledge (LOW) signal on the
SDATA wire following reception of each byte. Data is trans-
ferred MSB first at a max. rate of 100kbits/S. This device will
also respond to a D3 address which sets it in a read mode. It
will not respond to any other control interface conditions, and
previously set control registers are retained.
During normal data transfer, the SDATA signal only changes
when the SCLK signal is low, and is stable when SCLK is high.
There are two exceptions to this. A HIGH-to-LOW transition on
Transmit
ACK
ACK
ACK
ACK
ACK
Receive
COMMAND BYTE
BYTE COUNT
BYTE 0
(Valid)
BYTE N
(Valid)
1
1
0
1
0
0
1
0
(Don’t Care)
(Don’t Care)
SDATA
MSB
LSB
8
8
8
8
SCLK
START CONDITION
STOP CONDITION
Figure 1. SMBus Communication Waveform (Write)
Transmit
ACK BYTE COUNT
BYTE 0
BYTE1
BYTE N
Receiv
ACK
ACK
ACK
ACK
1
1
0
1
0
1
0
1
(Valid)
(Valid)
(Valid)
(Valid)
SDATA
MSB
LSB
8
8
8
8
SCLK
START CONDITION
STOP CONDITION
Figure 2. SMBus Communication Waveform (Read)
Serial Control Registers
Byte 4: CPU Clock Register
Bit
7
@Pup
H/W Setting
H/W Setting
H/W Setting
H/W Setting
0
Pin#
14
4
Name
FS3
FS2
FS1
FS0
Description
For selecting frequencies in Table 1
For selecting frequencies in Table 1
For selecting frequencies in Table 1
For selecting frequencies in Table 1
0 = HW, 1 = SW Frequency Selection
For selecting frequencies in Table 1
6
5
3
4
2
3
2
H/W Setting
1
15
FS4
1
SSCG
Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
0
0
0 = running; 1= three-state all outputs
Byte 5: CPU Clock Register (All bits are Read-only)
Bit @Pup
Pin#
Name
Description
7
6
5
4
0
Reserved
Reserved
0
X
X
26
15
MULTO
FS4
MULT0 (pin 26) value. This bit is Read-only.
FS4 read back. This bit is Read-only.
Document #: 38-07123 Rev. *B
Page 3 of 18
C9915
Byte 5: CPU Clock Register (All bits are Read-only) (continued)
Bit @Pup
Pin#
14
Name
FS3
Description
FS3 read back. This bit is Read-only.
3
2
1
0
X
X
X
X
4
3
2
FS2
FS1
FS0
FS2 read back. This bit is Read-only.
FS1 read back. This bit is Read-only.
FS0 read back. This bit is Read-only.
Byte 6: CPU Clock Register
Bit @Pup
Pin#
Name
Description
7
6
5
0
0
0
Function Test Bit, always program to 0.
Reserved.
14
15
PCI_F0
PCI_F1
PCI_STP# control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is
LOW.
4
3
0
1
PCI_STP# control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is
LOW.
40,39
CPU0T/C
Controls CPU0T and CPU0C functionality when CPU_STP# is asserted LOW
0 = Free Running, 1 + Stopped with CPU_STP# asserted LOW. This is a Read- and
Write-Control bit.
2
0
44,43
CPU1T/C
Controls CPU1T and CPU1C functionality when CPU_STP# is asserted LOW
0 = Free Running, 1 Stopped with CPU_STP# asserted LOW. This and Read- and
Write-control Bit.
1
0
1
1
40,39
44,43
CPU0T/C
CPU1T/C
CPU0T, CPU0C Output Control, 1= enabled, 0 = disabled. This is a Read- and
Write-control bit.
CPU1T, CPU1C Output Control, 1= enabled, 0 = disabled. This is a Read- and
Write-control bit.
Byte 7: PCI Clock Register (All bits are Read and Write functional)
Bit @Pup
Pin#
15
Name
PCI_F0
PCI_F1
PCI5
Description
PCI_F0 Output Control 1 = enabled, 0 = forced LOW
PCI_F1 Output Control 1 = enabled, 0 = forced LOW
PCI5 Output Control 1 = enabled, 0 = forced LOW
PCI4 Output Control 1 = enabled, 0 = forced LOW
PCI3 Output Control 1 = enabled, 0 = forced LOW
PCI2 Output Control 1 = enabled, 0 = forced LOW
PCI1 Output Control 1 = enabled, 0 = forced LOW
PCI0 Output Control 1 = enabled, 0 = forced LOW
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
14
23
22
PCI4
21
PCI3
20
PCI2
17
PCI1
16
PCI0
Byte 8: Silicon Signature Register
Bit
7
@Pup
Description
1
0
0
0
0
0
0
0
Vendor ID
1000 = Cypress
6
5
4
3
Revision ID
2
1
0
Document #: 38-07123 Rev. *B
Page 4 of 18
C9915
Byte 9: Peripheral Control Register (All bits are Read-only)
Bit
7
@Pup
Pin#
Name
Description
PD# Enable. 0 = enable, 1 = disable
1
0
33
PD#
6
0 = when PD# asserted LOW, CPU(0:1)T stop in a high state, CPU(0:1)C stop in a
low state. 1 = when PD# asserted LOW, CPU(0:1)T and CPU(0:1)C stop in H-Z.
5
4
3
2
1
0
1
1
1
0
0
0
27
26
26
48M
48M Output Control 1 = enabled, 0 = forced LOW
48M_24M 48M_24M Output Control 1 = enabled, 0 = forced LOW
48M_24M 48M_24M, 0 = pin28 output is 24 MHz, 1= pin28 output is 48 MHz.
SS2 Spread Spectrum control bit (0 = down spread, 1= Center spread)
SS1 Spread Spectrum control bit. See Table 6.
SS0 Spread Spectrum control bit. See Table 6.
Byte 10: Peripheral Control Register (All bits are Read-only)
Bit
7
@Pup
Pin#
47
4
Name
SDCLK
REF2
Description
SDCLK Output Enable 1 = enabled, 0 = disabled
REF2 Output Control 1 = enabled, 0 = forced LOW
REF1 Output Control 1 = enabled, 0 = forced LOW
REF0 Output Control 1 = enabled, 0 = forced LOW
ZCLK1 Output Enable 1 = enabled, 0 = disabled
ZCLK0 Output Enabled 1 = enabled, 0 = disabled
AGP1 Output Enabled 1 = enabled, 0 = disabled
AGP0 Output Enabled 1 = enabled, 0 = disabled
1
1
1
1
1
1
1
1
6
5
3
REF1
4
2
REF0
3
10
9
ZCLK1
ZCLK0
AGP1
AGP0
2
1
30
31
0
Byte 11: Dial-a-Skew™ and Dial-a-Ratio™ Control Register
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
DARSD2
DARSD1
DARSD0
DARAG2
DARAG1
DARAG0
DASSD1
DASSD0
Programming these bits allow modifying the frequency ratio of the SDCLK clock
relative to the VCO. See Table 2.
6
5
4
Programming these bits allow modifying the frequency ratio of the AGP(1:0),
PCI(5:0) and PCIF(0:1) clocks relative to the VCO. See Table 3.
3
2
1
Programming these bits allow shifting skew between CPU and SDCLK signals. See
Table 4.
0
Table 2. Dial-a-Ratio SDCLK
DARSD (2:0)
000
VC0/SDCLK Ratio
Frequency Selection Default
001
2
3
4
5
6
8
9
010
011
100
101
110
111
Document #: 38-07123 Rev. *B
Page 5 of 18
C9915
Table 3. Dial-a-Ratio AGP(0:1)[4]
DARAG (2:0)
VC0/AGP ratio
000
001
010
011
100
101
110
111
Frequency Selection Default
6
7
8
9
10
10
10
Table 4. Dial-a-Skew SDCLK CPU
DASSD (1:0)
SDCLK-CPU Skew
0 ps (Default)[5]
00
01
10
11
+150 ps (CPU lag)*
+300 ps (CPU lag)*
+450 ps (CPU lag)*
Byte 12: Watchdog Time Stamp Register
Bit
@Pup
Name
Description
7
1
SRESET#/PCI_STP#. 1 = Pin 12 is the input pin as PCI_STP# signal. 0 = Pin 12 is the output pin
as SRESET# signal.
6
0
Frequency Revert. This bit allows setting the Revert Frequency once the system is rebooted due
to Watchdog time out only.0 = selects frequency of existing H/W setting1 = selects frequency of the
second to last S/W setting. (the software setting prior to the one that caused a system reboot).
5
4
0
0
WDTEST. For WD-Test, ALWAYS program to “0.”
WD Alarm. This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system
clears the WD time stamps (WD3:0).
3
2
1
0
0
0
0
0
WD3
WD2
WD1
WD0
This bits selects the Watchdog Time Stamp Value. See Table 5.
Table 5. Watchdog Time Stamp Table
WD(3:0)
0000
0001
0010
0011
FUNCTION
Off
1 second
2 seconds
3 seconds
4 seconds
5 seconds
6 seconds
7 seconds
0100
0101
0110
0111
Notes:
4. The ratio of AGP to PCI is retained at 2:1.
5. See Figure 10 for CPU measurement point. See Figure 11 for SDCLK measurement point.
Document #: 38-07123 Rev. *B
Page 6 of 18
C9915
Table 5. Watchdog Time Stamp Table (continued)
WD(3:0)
1000
1001
1010
1011
1100
1101
1110
FUNCTION
8 seconds
9 seconds
10 seconds
11 seconds
12 seconds
13 seconds
14 seconds
15 seconds
1111
Byte 13: Dial-a-Frequency™ Control Register N (All bits are Read and Write functional)[6]
Bit
7
@Pup
Description
0
0
0
0
0
0
0
0
Reserved
N6, MSB
N5
6
5
4
N4
3
N3
2
N2
1
N3
0
N0, LSB
Byte 14: Dial-a-Frequency Control Register R (All bits are Read and Write functional)[6]
Bit
7
@Pup
Description
0
0
0
0
0
0
0
0
Reserved
R5 MSB
R4
6
5
4
R3
3
R2
2
R1
1
R0, LSB
0
R and N register load gate 0 = gate closed (data is latched), 1 = gate open (data
is loading from SMBus registers into R and N.)#
Note:
6. Byte 13 and Byte 14 should be Write together in every case.
Document #: 38-07123 Rev. *B
Page 7 of 18
C9915
Dial-a-Frequency Feature
System Self Recovery Clock Management
SMBus Dial-a-Frequency feature is available in this device via
Byte13 and Byte14. P is a large value PLL constant that
depends on the frequency selection achieved through the
hardware selectors (FS4, FS0). P value may be determined
from the following table.
This feature is designed to allow the system designer to
change frequency while the system is running and reboot the
operation of the system in case of a hang up due to the
frequency change.
When the system sends an SMBus command requesting a
frequency change through Byte 4 or through bytes 13 and 14,
it must have previously sent a command to byte 12, for
selecting which time out stamp the Watchdog must perform,
otherwise the System Self Recovery feature will not be appli-
cable. Consequently, this device will change frequency and
then the Watchdog timer starts timing. Meanwhile, the system
BIOS is running its operation with the new frequency. If this
device receives a new SMBus command to clear the bits origi-
nally programmed in Byte 12, bits (3:0) (reprogram to 0000),
before the Watchdog times out, then this device will keep
operating in its normal condition with the new selected
frequency. If the Watchdog times out the first time before the
new SMBus reprograms Byte 12, bits (3:0) to (0000), then this
device will send a low system reset pulse, on SRESET# (see
byte12, bit7), and changes WD alarm (Byte12, Bit4) status to
“1” then restarts the Watchdog timer again. If the Watchdog
times out a second time, then this device will send another low
pulse on SRESET#, will relatch original hardware strapping
frequency (or second to last software selected frequency, see
byte12, bit6) selection, set WD alarm bit (Byte12, bit4) to “1,”
then start WD timer again. The above-described sequence will
keep repeating until the BIOS clears the SMBus byte12 bits
(3:0). Once the BIOS sets Byte 12 bits (3:0) = 0000, then the
Watchdog timer is turned off and the WD alarm bit (Byte 12,
bit4) is reset to “0.”
FS(4:0)
P
00110, 01000, 01010, 01100, 11001, 11011,
01101
32005333
00100, 00101, 10000, 10001, 10101, 10111,
11000, 11010, 11100, 11101, 11110, 11111
38406400
48008000
64010667
00000, 00001, 00010, 00111, 01001, 01011,
01110, 01111, 10010, 10100, 10110
00011, 10011
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to
minimizing EMI radiation generated by repetitive digital
signals. A clock presents the greatest EMI energy at the center
frequency it is generating. Spread Spectrum distributes this
energy over a specific and controlled frequency bandwidth
therefore causing the average energy at any one point in this
band to decrease in value. This technique is achieved by
modulating the clock away from its resting frequency by a
certain percentage (which also determines the amount of EMI
reduction). In this device, Spread Spectrum is enabled by
setting specific register bits in the SMBus control Bytes. See
the SMBus register section of this data sheet for the exact bit
and byte functionally. Table 6 is a listing of the modes and
percentages of Spread Spectrum modulation that this device
incorporates.
Table 6. Spread Spectrum
SS2
0
SS1
0
SS0
0
Spread Mode
Spread %
0, -0.50
Down
Down
Down
Down
Center
Center
Center
Center
0
0
1
+0.12, -0.62
+0.25, -0.75
+0.50, -1.00
+0.25, -0.25
+0.37, -0.37
+0.50, -0.50
+0.75, -0.75
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Document #: 38-07123 Rev. *B
Page 8 of 18
C9915
S y s t e m r u n n in g w it h
o rig in a lly s e le c te d
f re q u e n c y v ia
h a r d w a r e s t r a p p in g .
N o
F re q u e n c y w ill c h a n g e b u t S y s t e m S e lf
R e c e iv e F r e q u e n c y
C h a n g e R e q u e s t v ia
R e c o v e r y n o t a p p lic a b le (n o t im
e
s t a m
p
Y e s
s e le c t e d a n d b y t e 1 2 , b it (3 :0 ) is s t ill
" 0 0 0 0 "
=
S M B u s B y t e 4 o r V ia D ia l-
a -f r e q u e n c y ?
C h a n g e t o
a n e w
f re q u e n c y
N o
I s S M B u s B y t e 9 , t im
e o u t
s t a m
p
e n a b le d
(3 : 0 )
- ( b y t e 1 2 , b it
0 0 0 0 ) ?
Y e s
1 ) S e n d a n o t h e r 3 m
S lo w p u ls e o n S R E S E T
2 ) R e la t c h o r ig in a l h a r d w a r e s t r a p p in g s e le c t io n
f o r r e tu rn to o r ig in a l f re q u e n c y s e t t in g s .
S t a r t in t e r n a l w a t c h d o g t im e r .
3 ) S e t
W
D
A la rm b it (b y t e 1 2 , B it4 ) t o " 1 "
D t im e r
4 ) S t a r t
W
Y e s
1 ) S e n d S R E S E T
p u ls e
Y e s
W
a tc h D o g t im e o u t?
2 ) S e t
( b y te 1 2 , b it 4 ) t o ’1 ’
3 ) S t a r t tim e r
W D b it
W
a t c h D o g t im e o u t ?
W
D
N o
N o
S M B u s b y te 1 2 t im
e
o u t s t a m d is a b le d ?
p
N o
S M B u s b y t e
s t a m d is a b le d , B y t e
1 2 , b it (3 : 0 ) (0 0 0 0 ) ?
9 t im e o u t
Y e s
p
Y e s
N o
=
T u r n o ff w a tc h d o g tim e r.
K e e p n e w f re q u e n c y s e t t in g . S e t
b it ( b y te 1 2 , b it 4 ) t o ’’0 ’
W
D a la rm
CPU_STP# Clarification
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the de-Assertion to
active outputs is no more than 2 CPU clock cycles.
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
PCI_STP# Assertion
CPU_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tsetup). (See
Figure 5.) The PCI_F (0:2) clocks will not be affected by this
pin if their control bits in the SMBus register are set to allow
them to be free running.
When CPU_STP# pin is asserted, all CPU outputs that are set
with the SMBus configuration to be stoppable via assertion of
CPU_STP# will be stopped after being sampled by two falling
CPU clock edges. The final state of the stopped CPU signals
is CPU = HIGH and CPU0# = LOW. There is no change to the
output drive current values during the stopped state. The CPU
is driven HIGH with a current value equal to (Mult 0 “select”) x
(Iref), and the CPU# signal will not be driven. Due to external
pull-down circuitry CPU# will be LOW during this stopped
state.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI(0:6)
and stoppable PCI_F(0:2) clocks to resume running in a
synchronous manner within 2 PCI clock periods after
PCI_STP# transitions to a HIGH level.
CPU_STP# Deassertion
The de-assertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
Document #: 38-07123 Rev. *B
Page 9 of 18
C9915
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 3. Deassertion CPU_STP# Waveform
CPU_STP#
CPUT
CPUC
Figure 4. Assertion CPU_STP# Waveform
t setup
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
Figure 5. Assertion PCI_STP# Waveform
t setup
PCI_STP#
PCI_F(0:2)
PCI(0:6)
Figure 6. Deassertion PCI_STP# Waveform[7]
Note:
7. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus Byte 0,Bit 3. These two inputs are
logically ANDed. If either the external pin or the internal SMBus register bit is set LOW, the stoppable PCI clocks will be stopped in a logic LOW state. Reading
SMBus Byte 0,Bit 3 will return a 0 value if either of these control bits are set LOW, thereby indicating that the device’s stoppable PCI clocks are not running.
Document #: 38-07123 Rev. *B
Page 10 of 18
C9915
PD# (Power-down) Clarification
The PD# pin is used to shut off ALL clocks prior to shutting off
power to the device. PD# is an asynchronous active LOW
input. This signal is synchronized internally to the device
powering down the clock synthesizer. PD# is an asynchronous
function for powering up the system. When PD# is LOW, all
clocks are driven to a LOW value and held there; the VCO and
PLLs are also powered down. All clocks are shut down in a
synchronous manner so has not to cause glitches while transi-
tioning to the LOW “stopped” state.
be held LOW on their next HIGH-to-LOW transition. CPUT
clocks must be hold with CPUT clock pin driven high with a
value of 2× Iref and CPUC undriven.
Due to the state of internal logic, stopping and holding the REF
clock outputs in the LOW state may require more than one
clock cycle to complete.
PD# – Deassertion (Transition from Logic “0” to Logic “1”)
The power-up latency between PD# rising to a valid logic “1”
level and the starting of all clocks is less than 3.0 ms.
PD# – Assertion (Transition from Logic “1” to Logic “0”)
When PD# is sampled LOW by two consecutive rising edges
of CPUC clock, all clock outputs (except CPUT) clocks must
CPU_STP#
CPU(0:1)T
CPU(0:1)C
CPU Internal
CPU# Internal
Figure 7. Power-down Assertion/Deassertion Timing Waveforms – Nonbuffered Mode
VID (0:3),
SEL (0,1)
VTTPWRGD
PWRGD
0.2-0.3mS
Delay
Wait for
VTT_GD#
Sample Sels
VDD Clock Gen
Clock State
State 0
Off
State 1
State 2
State 3
(Note A)
On
Clock Outputs
Clock VCO
On
Off
Figure 8. VTTPWRGD Timing Diagram[8]
Note:
8. Device is not affected, VTTPWRGD is ignored.
Document #: 38-07123 Rev. *B
Page 11 of 18
C9915
S1
S2
W ait for
1.146m s
Sam ple
Inputs
FS(3:0)
Enable
Outputes
Delay 0.25m S
VDDA = 2.0V
S0
S3
Norm al
Operation
Power Off
VDD3.3 = Off
Figure 9. Clock Generator Power Up/Run State Diagram
Document #: 38-07123 Rev. *B
Page 12 of 18
C9915
Maximum Ratings[9.]
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature: ................................... 0°C to +70°C
Maximum Power Supply:................................................ 3.5V
DC Characteristics
Current Accuracy[10]
Parameter
Iout
Description
Conditions
Min.
Max.
Load
VDD = nominal (3.30V) M0 = 0 or 1 and Rr shown in table –7% Inom +7% Inom Nominal test load for
given configuration
Iout
VDD = 3.30 ±5%
All combinations of M0 or 1 and Rr –12% Inom +12% Inom Nominal test load for
shown in table given configuration
DC Component Parameters (VDD = 3.3V±5%, TA = 0°C to 70°C)
Symbol
Idd3.3V
Description
Dynamic Supply Current
Power-down Supply Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Conditions
All frequencies at maximum values[11]
PD# Asserted
Min.
Typ.
Max.
Unit
mA
280
Ipd3.3V
Cin
See Note 11 mA
5
6
pF
pF
nH
pF
Cout
Lpin
7
Cxtal
Crystal Pin Capacitance
Measured from the XIN or XOUT pin to
Ground
30
36
42
Table 7. Maximum Lumped Capacitive Output Loads
Clock
PCI(0:5), PCI_F(0:1)
AGP (0:1), SDCLK
ZCLK (0:1)
Max. Load
Unit
30
30
30
20
30
2
pF
pF
pF
pF
pF
pF
48M_24, 48M Clock
REF (0:2)
CPU(0:1)T
CPU(0:1) C
Notes:
9. Multiple Supplies The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
10. Inom refers to the expected current based on the configuration of the device.
11. Absolute value = (Programmed CPU Iref 97) +10 mA.
Document #: 38-07123 Rev. *B
Page 13 of 18
C9915
AC Parameters[12]
100 MHz
133 MHz
Parameters
Crystal
Description
Min.
Max.
Min.
Max.
Unit
Notes
TDC
X
IN Duty Cycle
XIN Period
XIN HIGH Voltage
IN LOW Voltage
47.5
69.841
0.7VDD
0
52.5
71.0
47.5
69.841
0.7VDD
0
52.5
71.0
%
ns
V
13,21
TPeriod
VHIGH
VLOW
Tr/Tf
13,14,16,21
VDD
VDD
X
0.3VDD
10.0
0.3VDD
10.0
V
XIN Rise and Fall Times
XIN Cycle-to-Cycle Jitter
ns
ps
TCCJ
500
500
14,17,21
CPU at 0.7V Timing
TSKEW
Any CPU to CPU Clock Skew
CPU Cycle-to-Cycle Jitter
CPU and CPUC Duty Cycle
150
150
55
150
150
55
ps
ps
%
17, 24, 28
17, 24, 28
17, 24, 28
17, 24, 28
17, 18
TCCJ
TDC
45
9
45
TPeriod
Tr / Tf
CPU and CPUC Period
CPU and CPUC Rise and Fall Times
Rise/Fall Matching
10.2
700
20%
125
125
430
7.35
175
7.65
700
20%
125
125
430
ns
ps
175
18, 27, 28
18, 28
DeltaTr
DeltaTf
Vcross
Rise Time Variation
ps
ps
Fall Time Variation
18, 28
Crossing Point Voltage at 0.7V Swing
280
280
mV
18, 24, 28
AGP
TDC
AGP Duty Cycle
45
55
15.3
–
45
55
%
ns
ns
ns
ns
ps
14, 16
14, 16
25
TPeriod
THIGH
TLOW
Tr / Tf
AGP Period
15.0
5.25
5.05
0.5
15.0
5.25
5.05
0.5
15.3
AGP HIGH Time
AGP LOW Time
–
26
AGP Rise and Fall Times
Any AGP to Any AGP Clock Skew
1.6
175
1.6
14, 15
14, 16
Tskew
175
Unbuffered
TCCJ
AGP Cycle-to-Cycle Jitter
250
250
ps
14, 16
ZCLK
TDC
ZCLK(0:1) Duty Cycle
45
55
1.6
45
55
%
ns
ps
ps
14, 16
14, 15
14, 16
14,16
Tr / Tf
ZCLK(0:1) Rise and Fall Times
Any ZCLK(0:1) to Any ZCLK(0:1) Skew
ZCLK(0:1)Cycle-to-Cycle Jitter
0.5
0.5
1.6
175
250
TSKEW
TCCJ
175
250
PCI
TDC
PCI_F(0:1) PCI (0:5) Duty Cycle
PCI_F(0:1) PCI (0:5) Period
45
55
45
55
%
14, 16
13,14,16
25
TPeriod
THIGH
TLOW
Tr / Tf
30.0
12.0
12.0
0.5
30.0
12.0
12.0
0.5
nS
nS
nS
nS
pS
ps
PCI_F(0:1) PCI (0:5) HIGH Time
PCI_F(0:1) PCI (0:5) LOW Time
PCI_F(0:1) PCI (0:5) Rise and Fall Times
Any PCI Clock to Any PCI Clock Skew
PCI_F(0:1) PCI (0:5) Cycle-to-Cycle Jitter
26
2.0
500
250
2.0
500
250
14, 15
14, 16
14, 16
TSKEW
TCCJ
SDCLK
TDC
SDCLK Duty Cycle
SDCLK Period
45
7.4
3.0
55
15
45
7.4
55
15
%
ns
ns
14, 16
14, 16
25
TPeriod
THIGH
SDCLK HIGH Time
1.87
Document #: 38-07123 Rev. *B
Page 14 of 18
C9915
AC Parameters[12] (continued)
100 MHz
133 MHz
Parameters
Description
SDCLK LOW Time
Min.
Max.
Min.
Max.
Unit
ns
Notes
26
TLOW
Tr / Tf
TCCJ
2.8
0.4
-
1.67
0.4
-
SDCLK Rise and Fall Times
SDCLK Cycle-to-Cycle Jitter
1.6
1.6
ns
14, 15
14, 15
250
250
ps
48M
TDC
48M Duty Cycle
45
55
45
55
%
ns
ns
ps
14, 16
14, 16
14, 15
14, 16
TPeriod
Tr / Tf
TCCJ
48M Period
20.829 20.834 20.829 20.834
48M Rise and Fall Times
48M Cycle-to-Cycle Jitter
1.0
2.0
1.0
2.0
350
350
24M
TDC
24MHz Duty Cycle
45
41.66
1.0
55
41.67
4.0
45
41.66
1.0
55
41.67
4.0
%
ns
ns
ps
14, 16
14, 16
14, 15
14, 16
TPeriod
Tr / Tf
TCCJ
24MHz Period
24MHz Rise and Fall Times
24MHz Cycle-to-Cycle Jitter
500
500
REF
TDC
REF Duty Cycle
45
69.8413
1.0
55
45
55
%
ns
ns
ps
14, 16
14, 16
14, 15
14, 16
TPeriod
Tr / Tf
TCCJ
REF Period
71.0 69.8413 71.0
REF Rise and Fall Times
REF Cycle-to-Cycle Jitter
4.0
1.0
4.0
1000
1000
ENABLE/DISABLE and SETUP
tpZL, tpZH
tpLZ, tpZH
tstable
tss
Output Enable Delay (all outputs)
1.0
1.0
10.0
10.0
1.5
1.0
1.0
10.0
10.0
1.5
ns
ns
ms
ns
ns
Output Disable Delay (all outputs)
All Clock Stabilization from Power-up
Stopclock Set-up Time
19
20
10.0
0
10.0
0
tsh
Stopclock Hold Time
Notes:
12. All outputs loaded as per maximum capacitive load table. See Table 7.
13. This parameter is measured as an average over 1µs duration with a crystal center frequency of 14.318 MHz.
14. All outputs loaded per Table 7, below.
15. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data
sheet).
16. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).
17. This measurement is applicable with Spread On or Spread OFF.
18. Measured from VOL = 0.175 to VOH = 0.525V.
19. The time specified is measured from when all VDDs reach their supply rail (3.3V) until the frequency output is stable and operating within the specifications.
20. CPU_STP# and PCI_STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock’s rising edge.
21. When XIN is driven from an external clock source.
22. When crystal meets minimum 40-ohm device series resistance specification.
23. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
24. Measured at crossing point (Vx) or where subtraction of CLK–CLK# crosses 0V.
25. THIGH is measured at 2.4V for all non-host outputs.
26. TLOW is measured at 0.4V for all non-host outputs.
27. Determined as a fraction of 2*(Trise-Tfall)/ (Trise+Tfall).
28. For CPU load. See Figure 10.
Document #: 38-07123 Rev. *B
Page 15 of 18
C9915
Test and Measurement Set-up
For Differential CPU Output Signals
The following diagram shows lumped test load configurations
for the differential host clock outputs.
TPCB
33Ω
Measurement Point
Measurement Point
CPUT
49.9Ω
2pF
2pF
MULTSEL
CPUC
IREF
475Ω
TPCB
33Ω
49.9Ω
Figure 10. 0.7V Configuration
O u tp u t u nd e r T e st
P ro b e
L o a d C a p
3 .3 V s ig n a ls
tD C
-
-
3 .3 V
2 .4V
1 .5V
0 .4V
0 V
T r
T f
Figure 11. Lumped LoadFor Single-Ended Output Signals (for AC Parameters Measurement)
Table 8. CPU Clock Current Select Function
Mult0
Board Target Trace/Term Z
50 ohms (not used)
50 ohms
Reference R, Iref – Vdd (3*Rr)
Rr = 221 1%, Iref = 5.00 mA
Rr = 475 1%, Iref = 2.32 mA
Output Current
Ioh = 4*Iref
V
OH @ Z
0
1
1.0V @ 50
0.7V @ 50
Ioh = 6*Iref
Table 9. Group Timing Relationship and Tolerances
Tolerance (or
Offset
Range)
Conditions
CPU leads
CPU leads
CPU leads
CPU leads
Notes
CPU to SDCLK
CPU to AGP
CPU to ZCLK
TypicaL 0 ns
TypicaL 2 ns
TypicaL 2 ns
Typical 2 ns
±2 ns
Note 29
Note 29
Note 29
Note 29
1–4 ns
1–4 ns
1–4 ns
CPU to PCI
Note:
29. See Figure 10 for CPU clocks measurement point. SeeFigure 11 for SDCLK, AGP, ZCLK and PCI Outputs measurement point.
Document #: 38-07123 Rev. *B
Page 16 of 18
C9915
Ordering Information
Part Number
IMIC9915AY
Package Type
Product Flow
48-Pin Shrunk Small Outline package (SSOP)
48-Pin Shrunk Small Outline package (SSOP) – Tape and Reel
Commercial, 0° to 70°C
Commercial, 0° to 70°C
IMIC9915AYT
Package Drawing and Dimensions
48-lead Shrunk Small Outline Package O48
51-85061-C
Intel is a registered trademark of Intel Corporation. Dial-a-Skew, Dial-a-Frequency, and Dial-a-Ratio are trademarks of Cypress
Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07123 Rev. *B
Page 17 of 18
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
C9915
Document Title: C9915 Low EMI Clock Generator for Intel® 133-MHz/2-DIMM Chipset Systems
Document Number: 38-07123
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
112009
117409
122792
Description of Change
New Data Sheet
03/01/02
08/20/02
12/14/02
DMG
RGL
RBI
*A
Corrected the Ordering Information to match the Dev Master
Add Power up Requirements to Operating Conditions Information
*B
Document #: 38-07123 Rev. *B
Page 18 of 18
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