IMIC9950_技术文档

C9950

3.3V, 180-MHz, Multi-Output Clock Driver

Table 1. Frequency Table^[1]

Product Features

• 180-MHz Clock Support

FB_SEL = 1

QC

FB_SEL = 1

QC QD

• Supports PowerPC™, Intel^®, and RISC Processors

• 9 Clock Outputs: Frequency Configurable

• Oscillator or Crystal Reference Input

• Output Disable Control

SEL

QD

(A:D) QA QB (0,1) (0:4) QA QB (0,1) (0:4)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

4x

2x

x

2x

x

2x

x

8x 4x

8x 2x

4x 4x

4x 2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

• Spread Spectrum Compatible

• Pin Compatible with MPC950

• Industrial Temp. Range: –40°C to +85°C

• 32-Pin TQFP Package

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

Note:

1. x = is the reference input frequency

Pin Configuration

Block Diagram

SELA

PLL_EN

TCLK

REF_SEL

VCO

200-

480MHz

Phase

Detector

QA

QB

2/

4/

4

8

XIN

XOUT

OSC

VDD

FB_SEL

SELA

SELB

SELC

SELD

VSS

1

2

3

4

5

6

7

8

24

23

22

21

QC0

VDDC

QC1

LPF

8/ 16

VSS

C9950 20 QD0

FB_SEL

SELB

QC0

QC1

19

18

17

VDDC

4/

8

QD1

VSS

SELC

XIN

MR/OE#

Power-On Reset

QD0

QD1

SELD

QD2

QD3

QD4

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07072 Rev. *C

Revised December 21, 2002

C9950

Pin Description^[2]

8

Name

PWR

I/O

I

Type

Description

Oscillator Input. Connect to a crystal.

Oscillator Output. Connect to a crystal.

External Test Clock Input.

XIN

XOUT

TCLK

QA

9

0

30

I

28

VDDC

O

I

Clock Output. See Frequency Table.

Clock Outputs. See Frequency Table.

Feedback Select Input.

26

QB

22, 24

QC(1,0)

12, 14, 16, 18, 20 QD(4:0)

2

FB_SEL

PD

If FB_SEL = 1, then the (÷8) counter is selected in the PLL feed-

back loop.

If FB_SEL = 0, then the (÷16) counter is selected in the PLL

feedback loop.

10

MR/OE#

I

Master Reset/Output Enable Input. When asserted HIGH, resets

all of the internal flip-flops and also disables all of the outputs.

When pulled LOW, releases the internal flip-flops from reset and

enables all of the outputs.

31

32

PLL_EN

REF_SEL

SEL(A:D)

I

PLL Enable Input. When asserted HIGH, PLL is enabled. And

when set LOW, PLL is bypassed.

Reference Select Input. WhenHIGH, TCLK is thereference clock

and when LOW, the crystal oscillator is selected.

3, 4, 5, 6

Frequency Select Inputs. See Frequency Table.

If SEL_ = 1, then QA divider = ÷4, QB:D divider = ÷8

If SEL_ = 0, then QA divider = ÷2, QB:D divider = ÷4

11, 15, 19, 23, 27

1

VDDC

VDD

VSS

3.3V Power Supply for Output Clock Buffers.

3.3V Power Supply for PLL

Common Ground

7, 13, 17, 21, 25,

29

Note:

2. PD = Internal Pull-Down, PU = Internal Pull-Up.

Document #: 38-07072 Rev. *C

Page 2 of 7

C9950

the outputs Q(B:D) depending on the configuration (see Table

2). The use of even dividers ensures that the output duty cycle

remains at 50%.

Description

The C9950 has an integrated PLL that provides low skew and

low jitter clock outputs for high-performance microprocessors.

The PLL is ensured stable operation given that the VCO is

configured to run between 200 MHz and 480 MHz. This allows

a wide range of output frequencies from 25 MHz to 180 MHz.

The internal VCO frequency is divided by 8 or 16 and com-

pared to the input reference clock. These selectable dividers

allow for input reference clock flexibility. The internal VCO is

running at 2x or 4x the high speed output (QA), and 4x or 8x

Output Frequency

The C9950 generates outputs with programmable frequency

relationships. As a result, the input reference frequency is a

function of the desired output frequency (Table 1). The follow-

ing block diagram illustrates the corresponding parameters

that are needed to calculate the output frequency.

VCO

/N

Fref

Qn

Phase

Detector

LPF

/m

Figure 1.

Fref = FVCO/m, FVCO = FQn x N

Fref = (FQn x N) / m

Where m = 8 (FB_SEL = 1) or m = 16 (FB_SEL = 0), and N = 2, 4, or 8 depending on SEL_ as shown in Table 1.

Table 2.

INPUTS

OUTPUTS

SELA

SELB

SELC

SELD

QA

QB

QC

QD

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VCO/2

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

Document #: 38-07072 Rev. *C

Page 3 of 7

C9950

Table 3. Suggested Oscillator Crystal Parameters

Parameter

T_C

Description

Conditions

Min.

Typ.

Max.

±100

Unit

PPM

Frequency Tolerance

FrequencyTemperature (T_A–10 to +60°C)^[3]

Note 1

-

T_S

-

Stability

T_A

Aging

(first 3 years @ 25°C)^[3]

The crystal’s rated load^[3]

Note 4

-

5

-

PPM/Yr

pF

C_L

Load Capacitance

20

40

R_ESR

Effective Series

80

Ohms

Resistance (ESR)

Notes:

3. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meets or exceeds these

specifications

4. Larger values may cause this device to exhibit oscillator startup problems

Document #: 38-07072 Rev. *C

Page 4 of 7

C9950

Maximum Ratings^[5]

This device contains circuitry to protect the inputs against

damage due to high static voltages or electric field; however,

precautions should be taken to avoid application of any volt-

age higher than the maximum rated voltages to this circuit. For

proper operation, V_inand V_outshould be constrained to the

range:

Maximum Input Voltage Relative to V_SS: ............ V_SS– 0.3V

Maximum Input Voltage Relative to V_DD:.............V_DD+ 0.3V

Storage Temperature: ................................–65°C to + 150°C

Operating Temperature:................................–40°C to +85°C

Maximum ESD protection .............................................. 2 KV

Maximum Power Supply: ................................................5.5V

Maximum Input Current:..................................................±20 mA

V_SS< (V_inor V_out) < V_DD

Unused inputs must always be tied to an appropriate logic volt-

age level (either V_SSor V_DD).

DC Parameters: V_DD= V_DDC= 3.3V ±5%, T_A= –40°C to +85°C

Parameter

V_IL

Description

Input Low Voltage

Conditions

Min.

Typ.

Max.

Unit

V

0.8

V_IH

Input High Voltage

2.0

V

I_IL

Input Low Current (@V_IL= V_SS

)

Note 6

–120

120

0.5

µA

V

I_IH

Input High Current (@V_IL=V_DD

Output Low Voltage

)

V_OL

V_OH

I_DDC

I_DD

I_OL= 40 mA, Note 7

I_OH= –40 mA, Note 7

All V_DDCand V_DD

V^DDonly

Output High Voltage

2.4

V

Quiescent Supply Current

PLL Supply Current

15

20

4

mA

pF

C_in

Input Capacitance

AC Parameters^[8]: V_DD= V_DDC= 3.3V ±5%, T_A= –40°C to +85°C

Parameter

Tr/Tf

Description

TCLK Input Rise/Fall

Conditions

Min.

Typ.

Max.

Unit

ns

3.0

Fref

Reference Input Frequency

Crystal Oscillator Frequency

Reference Input Duty Cycle

PLL VCO Lock Range

Note 9

10

Note 2

MHz

%

Fxtal

See Table 3 for details

25

FrefDC

Fvco

25

75

200

480

MHz

ms

Tlock

Tr/Tf

Maximum PLL lock Time

Output Clocks Rise/Fall Time^[10]

10

0.8V to 2.0V

QA = (÷2)

0.10

1.0

ns

Fout

Maximum Output Frequency

180

MHz

QA/QB = (÷4)

QB = (÷8)

120

60

FoutDC

Output Duty Cycle

TCYCLE/2 – 1

TCYCLE/2 + 1

ns

ps

tpZL, tpZH Output enable time (all outputs)

tpLZ, tpHZ Output disable time (all outputs)

6

7

TCCJ

Cycle to Cycle Jitter (peak to peak)^[10]

Any Output to Any Output Skew^[10]

±100

200

TSKEW0

350

Notes:

5. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

6. Inputs have internal pull-up/pull-down resistors that affect input current.

7. Driving series or parallel terminated 50Ω (or 50Ω to V_DD/2) transmission. Output buffers are dual staged to control drive strength in order to reduce over / under

shoot.

8. Parameters are guaranteed by design and characterization. Not 100% tested in production.

9. Maximum and minimum input reference is limited by the VCO lock range.

10. Outputs loaded with 30 pF each.

Document #: 38-07072 Rev. *C

Page 5 of 7

C9950

Package Drawing and Dimensions

32-Pin TQFP Outline Dimensions

Inches

Millimeters

Min. Nom. Max.

Symbol Min.

Nom.

Max.

A

A₁

D

1.000 1.100 1.200 0.039 0.043 0.047

0.950 1.000 1.050 0.037 0.039 0.041

8.950 9.000 9.050 0.352 0.354 0.356

D

D₁

b

6.95

0.30

7.000 7.050 0.274 0.276 0.278

0.37

0.80 BSC

0.600

0.45

0.75

0.012 0.015 0.018

0.031 BSC

e

L

0.45

0.018 0.024 0.030

D₁

12°

A₁

L

e

b

Ordering Information

Part Number^[11]

Package Type

Production Flow

Industrial, –40°C to +85°C

C9950AA

32-Pin TQFP

Note:

11. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below.

Marking: Example: Cypress

C9950AA

Date Code, Lot #

C9950AA

Package

A = TQFP

Revision

Device Number

Document #: 38-07072 Rev. *C

Page 6 of 7

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

C9950

Document Title: C9950 3.3V, 180-MHz, Multi-Output Clock Driver

Document Number: 38-07072

Issue

Date

Orig. of

Change

REV.

**

ECN NO.

107108

108125

Description of Change

06/11/01

07/03/01

IKA

Convert from IMI to Cypress

*A

NDP

Delete Pull Down in Pin 10, 30, & 32 and Pull Up in Pin 3, 4, 4, 5, 6, & 31(See

page 2)

*B

*C

109802

122757

02/08/02

12/22/02

DSG

RBI

Convert from Word to Frame

Add power up requirements to maximum ratings information

Document #: 38-07072 Rev. *C

Page 7 of 7


型号：	IMIC9950
厂家：	ETC
描述：	Clocks and Buffers 时钟和缓冲器\n 时钟
文件：	总7页 (文件大小：69K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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