CXA3537EN/TN [ETC]
Fan Motor Driver ; 风扇电机驱动器\n
| 型号： | CXA3537EN/TN |
| 厂家： | 
ETC |
| 描述： | Fan Motor Driver
|
| 文件： | 总14页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA3537EN/TN
Fan Motor Driver
Description
12 pin VSON (Plastic)
16 pin TSSOP (Plastic)
The CXA3537EN/TN is a single-phase full wave
drive type motor driver IC designed for the fan
motors of laptop computers.
Power saving drive is achieved with a newly
developed Drive Duty Control (DDC) system.
This DDC system also makes it possible to easily
change the motor rotational speed without changing
the motor components.
Absolute Maximum Ratings (Ta = 25°C)
Features
• Supply voltage
Vcc
Vs
14
14
300
4
V
V
• Supports single-phase full wave drive type fan
motors
1
• Motor drive voltage
• Output current
IO
mA
mA
• High efficiency driving with the DDC system
• Four kinds of drive duty can be selected by
changing the IC taps
• FG output current
IO (FG)
• Allowable power dissipation
PD
• Operating temperature
Topr
260
mW
• Low output stage saturation voltage
• Current slope control when cutting off the drive
current
–20 to +85
°C
°C
• Storage temperature Tstg
–65 to +150
• Wide operating voltage range
• FG output
1
CXA3537TN only. The VS pin voltage should not
exceed the VCC pin voltage.
• Thermal protection circuit
• Small package
Recommended Operating Conditions (Ta = 25°C)
• Supply voltage
Vcc
3.0 to 13.2
V
Applications
(5.0V Typ.)
Laptop PC fan motors
1
• Motor drive voltage
Vs
0 to Vcc
V
V
• Hole voltage in-phase input range
Structure
VIH
0.5 to Vcc – 1.3
Bipolar silicon monolithic IC
• Hole input minimum signal voltage
10 to
mVp-p
µF
• CEXT capacitor capacitance
Cext
• CHLD capacitor capacitance
Chld
0.01 to 0.022
0.01 to 0.047
8 to 100
µF
• REXT resistance value
Rext
kΩ
1
CXA3537TN only.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E00207D32
CXA3537EN/TN
Block Diagram
CXA3537EN
12
11
10
9
8
7
VCC
Hall Amp.
Drive Duty Controller
TSD
Drive Duty Selector
BIAS
1
2
3
4
5
6
Fig. 1
CXA3537TN
16
15
14
13
12
11
10
9
VCC
Hall Amp.
Drive Duty Controller
TSD
Drive Duty Selector
BIAS
1
2
3
4
5
6
7
8
Fig. 2
– 2 –
CXA3537EN/TN
1
Electrical Characteristics
(Ta = 25°C, VCC = 5V, Vs = 5V )
Item
Symbol
ICC
Min.
Typ.
1.6
Max. Unit
2.1 mA
V
Conditions and remarks
2
Supply current
VCC – 0.4 VCC – 0.2
IO = 120mA
Output voltage H
Output voltage L
Hole input dead voltage
Initial no-drive time
Drive time (1)
VOH
0.2
2
0.4
5
V
IO = –120mA
VOL
mV Zero peak value
3
25
21
31
41
51
60
32
28
38
48
58
65
0.2
39
36
46
56
66
75
0.4
30
%
T1
3
T2 (1)
T2 (2)
T2 (3)
T2 (4)
F3
%
%
%
%
%
V
SEL1 = L, SEL2 = L
SEL1 = H, SEL2 = L
SEL1 = L, SEL2 = H
3
Drive time (2)
3
Drive time (3)
3
Drive time (4)
SEL1 = H, SEL2 = H
4
Forced drive speed
FG voltage L
IO (FG) = –2mA
FG leak current
Thermal protection
µA Apply 5V during FG off
140
170
°C Design target value (reference value)
TSD
1
The VS pin is only on the CXA3537TN. VS and VCC are connected internally for the CXA3537EN.
Circuit current not including the output stage. The CEXT pin is connected to GND.
2
3
Time ratio with the half period of 1ms when R1 (REXT) = 15kΩ and C1 (CEXT) = C2 (CHLD) = 0.01µF,
during 40mVp-p 500Hz rectangular wave signal input. R1, C1 and C2 are the same values even for the F3
4
measurement ( ).
4
Speed ratio with the setting rated half period of 1 ms during 40mVp-p 1.75ms half period rectangular wave
signal input.
– 3 –
CXA3537EN/TN
Operating Waveforms
(1) Operating waveform at the rated speed
T
Hole signal (forward phase)
Hole signal (reversed phase)
T1
T2
Output current
(2) Operating waveform at low speed
T'
Hole signal (forward phase)
Hole signal (reversed phase)
T3
Output current
T: Specified rated rotational speed time (This is used as 100 [%].)
T': Hole polarity inversion time at low speed
T1: Initial drive wait time [%]
T2: Drive duty [%]
T3: Forced drive mode transition time
F3: Forced drive mode transition speed = T/T3 × 100 [%]
Fig. 3
Truth Table
Mode
HIN1
HIN2
OUT1
H
OUT2
L
FG
off
L
L
H
L
H
1
H
L
H
L
1
When rotating
(during drive)
L
H
off
off
off
off
off
off
off
L
When rotating
(during no-drive)
During thermal protection
off
1 Does not depend on the hole output conditions.
– 4 –
CXA3537EN/TN
Pin Description
(Ta = 25°C, Vcc = 5V)
Description
Pin voltage
(typ.)
Pin No.
Symbol
Equivalent circuit
No connected.
These pins are only on the
CXA3537TN.
1, 8, 9 NC
VCC
Sets the charging current to the
capacitor connected to the CEXT
pin.
Connect to GND via a resistor.
Set the resistor value according to
the motor rated rotational speed.
REXT
120
25k
100k
2 (1)
REXT
1.56V
FG
FG signal output.
This pin forms an open collector.
3 (2)
FG
VCC
VCC
Input for selecting the drive duty.
The duty is selected by switching
this pin between open or connected
to GND.
This pin has a built-in pull-up
resistor.
60k
SEL1
30k
60k
4 (3)
SEL1
2.1V
VCC
VCC
Input for selecting the drive duty.
The duty is selected by switching
this pin between open or connected
to GND.
This pin has a built-in pull-up
resistor.
60k
SEL2
30k
60k
5 (4)
6 (5)
SEL2
GND
2.1V
0V
GND.
VCC
VS
Output.
20k
(For the CXA3537EN, the VS pin in
the figure to the left is connected
internally to the VCC pin.)
7 (6)
OUT1
OUT1
20k
The numbers in the Pin No. column indicate the CXA3537TN pin numbers. The numbers in parentheses are
the CXA3537EN pin numbers.
"
" in the Pin voltage column indicates undetermined values.
– 5 –
CXA3537EN/TN
Pin voltage
(typ.)
Pin No.
Symbol
Equivalent circuit
Description
IC output stage drive block power
supply.
VS
≤ VCC
10
(See Pins 7 and 12.)
This pin is only on the CXA3537TN.
11 (7)
VCC
5V
Power supply.
VCC
VS
Output.
20k
(For the CXA3537EN, the VS pin in
the figure to the left is connected
internally to the VCC pin.)
12 (8) OUT2
OUT2
20k
VCC
VCC
13 (9) HIN1
14 (10) HIN2
Hole element signal input.
Hole element signal input.
HIN1
HIN2
5k
5k
VCC
CHLD
Holds the motor rotational speed
signal.
120
15 (11) CHLD
1.7V
Connect to GND via a capacitor.
5k
VCC
CEXT
120
5k
Controls the motor drive time.
Connect to GND via a capacitor.
16 (12)
CEXT
1.4V
The numbers in the Pin No. column indicate the CXA3537TN pin numbers. The numbers in parentheses are
the CXA3537EN pin numbers.
"
" in the Pin voltage column indicates undetermined values.
– 6 –
CXA3537EN/TN
Description of Operation
(1) Drive operating mode
The CXA3537EN/TN performs DDC mode operation near the rated rotational speed area set by the
external constant, and operates in forced drive mode which forcibly applies the drive current during startup
or when rotating at low speed.
The IC automatically switches between these two modes.
(2) DDC mode (Drive Duty Control mode)
The Drive Duty Control (DDC) system achieves high driving efficiency by applying the drive current
centering on rotational angles which have a high drive torque generation efficiency relative to the drive
current, and cutting the drive current at rotational angles which have a low drive torque generation
efficiency.
Fig. 4 shows the full wave drive operating waveforms for a general single-phase motor.
(a) shows the hole element output signal.
One cycle of this waveform represents an electrical angle of 360°, and the electrical angle is
determined as shown in Fig. 4.
(b) is the drive current applied to the motor coil.
This waveform assumes that an even current flows each time the hole polarity changes.
(Here, the effects of counter electromotive force on the coil are omitted to simplify the description.)
(c) represents the drive torque generated by the drive current.
The drive torque generally forms a curve with peak values around the electrical angles of 90° and 270°,
and bottom values around 0° and 180°.
In other words, this shows that even when the same amount of current is applied, there are rotational angle
ranges where large drive torque can be obtained, and rotational angle ranges where only small drive torque
can be obtained.
Fig. 5 shows the DDC system operating waveforms.
(a) is the hole element output signal.
(b) is the drive current. The drive current is applied centering on rotational angles which have a high drive
torque generation efficiency, and cut at angles of rotation which have a low drive torque generation
efficiency.
(c) is the drive torque generated by the drive current.
The power saving performance of the DDC system is examined below.
The drive torque generated by a constant drive current is assumed to form a sine wave relative to the
rotational angle.
If the drive duty is 50%, the input power is also 50% compared to the general single-phase full wave drive
system.
However, the average drive torque relative to the rotational angle is approximately 70% of that for the
general single-phase full wave drive system.
135° sinθ dθ / 180°sinθ dθ ≈ 0.7
∫
∫
45°
0°
In other words, even though the power consumption drops by 50%, the average drive torque only drops by
approximately 30%. This difference creates the power saving performance of the DDC system.
– 7 –
CXA3537EN/TN
(a) Hole signal
(b) Drive current
(c) Drive torque
0
90
180
270
360 Electrical angle [deg]
Fig. 4. Operating Waveforms of a General Single-phase Full Wave Drive Type Driver
(a) Hole signal
(b) Drive current
(c) Drive torque
0
90
180
270
360 Electrical angle [deg]
Fig. 5. Operating Waveforms of a DDC System Single-phase Full Wave Drive Type Driver
(3) Forced drive mode
This drive mode is used when starting up the motor or in the low speed transient status.
The operating waveforms during startup are the same as Fig. 4.
– 8 –
CXA3537EN/TN
Notes on Specifications
(1) Determining the external constants
1. Procedure for determining the external constants
The procedure for determining the CXA3537EN/TN peripheral constant values and the drive duty
selector pins SEL1 and SEL2 connection conditions is as follows.
1) Determine CHLD from the table below based on the number of motor poles and the target rated
rotational speed.
2) Determine CEXT and REXT from Fig. 6.
3) Drive the motor and determine the SEL1 and SEL2 connection conditions.
See the Application Circuit for the connection and wiring methods of each constant.
2. Selecting CHLD
Obtain the CHLD value from the following table based on the number of motor poles and the target rated
rotational speed.
Recommended CHLD pin external capacitor value by number of fan motor poles according to the rated
rotational speed
Recommended CHLD value
4-pole motor
6-pole motor
8-pole motor
0.01µF
0.022µF
0.033µF
0.047µF
7500 [rpm] or more 5000 [rpm] or more 3750 [rpm] or more
3400 [rpm] or more 2250 [rpm] or more 1700 [rpm] or more
2250 [rpm] or more 1500 [rpm] or more 1100 [rpm] or more
1600 [rpm] or more 1000 [rpm] or more 800 [rpm] or more
The capacitance value of the CHLD pin external capacitor is determined according to the number of
poles and rated rotational speed of the fan motor. The table above gives the recommended values.
Select a CHLD capacitance value that is the recommended value or one level larger than the
recommended value.
3. Selecting CEXT and REXT
Determine CEXT and REXT from Fig. 6 based on the number of motor poles and the target rated
rotational speed.
When the number of motor poles is 6 or 8 poles, convert the rotational speed to 1.5 times or 2 times the
actual motor rotational speed, respectively.
100
70
40
REXT range (when CEXT = 0.01µF is selected)
20
10
7
REXT range (when CEXT = 0.022µF is selected)
4
2
1
2000
3000
4000
5000
6000
7000
8000
9000
10000
Rated rotational speed (4-pole motor) [rpm]
Fig. 6. REXT Pin External Resistance Value According to the Motor Rated Rotational Speed
– 9 –
CXA3537EN/TN
4. SEL1 and SEL2 connection conditions
Finally, obtain the tap conditions for selecting the drive duty based on actual operation.
Set the three external constants, then connect and drive the motor.
Switch the two taps (SEL1 and SEL2 pins) between open and connected to GND to select the tap
conditions that most closely achieve the target rated rotational speed.
(2) External control of the SEL1 and SEL2 pins (taps)
The SEL1 and SEL2 pins have built-in pull-up resistors that are connected to the VCC pin.
When controlling SEL1 and SEL2 from external equipment, care should be taken for the pin current that
flows from the CXA3537EN/TN SEL1 and SEL2 pins to the external equipment.
Both the SEL1 and SEL2 pins are low at a voltage of 0.4V or less.
(3) DDC system motor rotational speed
For drive circuits with the same output stage loss characteristics, the average drive torque obtained by the
DDC system is less than the torque obtained by the general full interval drive system, so the motor
rotational speed also drops. The degree to which the speed drops depends on the motor characteristics.
For compact fan motors this drop in rotational speed is from several percent up to approximately 10%.
However, the CXA3537EN/TN has a low output saturation voltage, so the output stage loss is also small,
which works to suppress the drop in motor rotational speed due to the DDC system.
(4) Hole element signal level conditions
The input voltage signal from the hole element must be differential with a voltage amplitude of 10mVp-p or
more.
In addition, the signal must also be within the hole voltage in-phase input range. If the hole input voltage
signal is outside the hole voltage in-phase input range, take measures such as connecting a resistor in
series to the hole element power supply line or GND line to bring the hole signal within the range.
(5) Power supply pin capacitor
Adding a capacitor near the IC power supply pin is recommended.
When a capacitor cannot be added near the power supply pin, particular care should be taken for the
following points.
• There should not be surges which exceed the IC ratings.
• Anti-noise performance should be sufficient.
• There should be sufficient electrical characteristics margin on the side supplying power to the fan motor.
(6) Using the VS pin (CXA3537TN only)
When using the VS pin electrically separated from the VCC pin, take care that the VS pin voltage does not
exceed the VCC pin voltage.
(7) Current slope control when cutting off the output current
The CXA3537EN/TN has a function for gradually turning off the drive current when cutting off the drive current.
When the load is a resistor, the transition time when cutting off the drive current is fixed at 6µs (typ.). This is
in order to reduce the ringing noise produced around the load when cutting off the drive current. However,
this slope is not gradual enough to sufficiently suppress the surge current generated when cutting off the
drive current to the load.
Surge countermeasures should be taken as necessary.
– 10 –
CXA3537EN/TN
(8) FG output
The FG output forms an open collector. If the voltage applied to the FG pin is within the IC rated voltage, it
can exceed the Vcc pin voltage. The FG output outputs a frequency pulse that is proportional to the motor
rotational speed as shown in the Truth Table.
(9) Thermal shutdown
The CXA3537EN/TN has a built-in thermal shutdown circuit. When the IC chip temperature exceeds 170°C
(typ.), the output drive current is turned off. Then, the IC functions recover automatically when the IC chip
temperature falls to 140°C (typ.).
(10) Thermal loss reduction ratio
Allowable power consumption vs. Ambient temperature
The IC allowable power dissipation changes
according to the IC ambient temperature.
300
250
200
150
100
50
The IC power dissipation also changes according
to the load conditions, supply voltage conditions
and other factors, so check to make sure the
allowable power dissipation ratio is satisfied in
the actual operating condition.
0
–20
0
20
40
60
80
100
Ta – Ambient temperature [°C]
Fig. 7. Thermal Loss Reduction Ratio
– 11 –
CXA3537EN/TN
Measurement Circuit
CXA3537EN
CXA3537TN
I8
I8
WFG
EV1
I6
A
WFG
EV1
I6
A
R10
R10
V9
V9
V6
V6
C1
S10
C2
C1
S10
C2
I7
I7
S4-2
S7 S6
S7 S6
S4-2
V
V7
V
V7
S5
S5
12 11 10
9
8
5
7
6
16 15 14 13 12 11 10
CXA3537TN
9
8
R3
CXA3537EN
R3
1
2
3
4
1
2
3
4
5
6
7
S4-1
I5
S4-1
I5
V
V
V5
I1
V5 V
S2
I3
S3
R1
S2
S3
R1
I1
I2
I2
A
S1
I3
I4 S1
A
A
I4
A
A
V1
V1
V
A
R2
R2
V3
V3
V4
V4
V2
V2
Application Circuit
CXA3537EN
CXA3537TN
VCC
VCC
VS
R2
R2
C3
C3
C1
C2
C1
C2
12 11 10
9
8
5
7
6
16 15 14 13 12 11 10
CXA3537TN
9
8
CXA3537EN
1
2
3
4
1
2
3
4
5
6
7
FG
FG
R1
R1
OPEN/SHORT
OPEN/SHORT
Jumper Selector
Jumper Selector
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 12 –
CXA3537EN/TN
Package Outline
Unit: mm
12PIN VSON(PLASTIC)
CXA3537EN
+ 0.1
0.8 – 0.05
0.6
3.5
0.05
S
S
A
12
7
6
1
B
2x
0.35 ± 0.1
0.5
0.15
B
S
B
4x
A
S
0.15
1.25
0.05
M
S
AB
Solder Plating
0.23 ± 0.025
+ 0.09
0.24 - 0.03
TERMINAL SECTION
1) The dimensions of the terminal section apply to the
NOTE:
ranges of 0.1mm and 0.25mm from the end of a terminal.
PACKAGE STRUCTURE
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
0.02g
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
SONY CODE
VSON-12P-01
EIAJ CODE
JEDEC CODE
12PIN VSON(PLASTIC)
+ 0.1
0.8 – 0.05
0.6
3.5
0.05
S
S
A
12
7
1
6
B
2x
0.35 ± 0.1
0.5
0.15
B
S
B
4x
A
S
0.15
1.25
0.05
M
S
AB
Solder Plating
0.23 ± 0.025
+ 0.09
0.24 - 0.03
TERMINAL SECTION
1) The dimensions of the terminal section apply to the
NOTE:
ranges of 0.1mm and 0.25mm from the end of a terminal.
PACKAGE STRUCTURE
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
0.02g
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
SONY CODE
VSON-12P-01
EIAJ CODE
JEDEC CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
COPPER ALLOY
Sn-Bi Bi:1-4wt%
5-18µm
LEAD MATERIAL
SOLDER COMPOSITION
PLATING THICKNESS
– 13 –
CXA3537EN/TN
Package Outline
Unit: mm
CXA3537TN
16PIN TSSOP(PLASTIC)
1.2MAX
S
4.1
X
2.05
A
0.08
S
B
X2
16
9
0.2
S A B
0.1 ± 0.05
0.25
X
1
8
X4
0.1
M
S A B
0° to 8°
0.5
0.08
S A
B
0.2 ± 0.02
+ 0.036
0.22 – 0.03
DETAILB
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SOLDER PLATING
SONY CODE
EIAJ CODE
TSSOP-16P-L01
COPPER ALLOY
0.03g
JEDEC CODE
16PIN TSSOP(PLASTIC)
1.2MAX
S
4.1
X
2.05
A
0.08
S
B
X2
16
9
0.2
S A B
0.1 ± 0.05
0.25
X
1
8
X4
0.1
M
S A B
0° to 8°
0.5
0.08
S A
B
0.2 ± 0.02
+ 0.036
0.22 – 0.03
DETAILB
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
SONY CODE
EIAJ CODE
TSSOP-16P-L01
COPPER ALLOY
0.03g
JEDEC CODE
PACKAGE MASS
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
Sn-Bi Bi:1-4wt%
5-18µm
SOLDER COMPOSITION
PLATING THICKNESS
– 14 –
Sony Corporation
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