CXA3555N [SONY]
All Band Tuner IC with On-chip PLL; 全波段调谐器IC具有片上PLL
| 型号： | CXA3555N |
| 厂家： | 
SONY CORPORATION |
| 描述： | All Band Tuner IC with On-chip PLL |
| 文件： | 总28页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA3555N
All Band Tuner IC with On-chip PLL
Description
30 pin SSOP (Plastic)
The CXA3555N is a monolithic TV tuner IC which
integrates local oscillator and mixer circuits for VHF
band, local oscillator and mixer circuits for UHF
band, an IF amplifier and a tuning PLL onto a single
chip, enabling further miniaturization of the tuner.
Features
• Low power consumption (5V, 63mA typ.)
• Low noise figure, low distortion characteristics
• High gain/low gain selectable
Absolute Maximum Ratings
• Supply voltage
• Operating temperature Topr
• Storage temperature Tstg
VCC
–0.3 to +5.5
–25 to +75
V
• Supports IF double-tuned/adjacent channel trap
• Balanced oscillator circuits (3 sets) with excellent
oscillation stability
• On-chip PLL supports I2C bus
• On-chip high voltage drive transistor for charge
pump
°C
–55 to +150 °C
• Allowable power dissipation
PD
580
mW
V
Operating Conditions
• Frequency step selectable from 31.25, 50 or
62.5kHz (when using a 4MHz crystal)
• Low-phase noise synthesizer
Supply voltage
VCC
4.75 to 5.30
• On-chip 4-output band switch (output voltage: 5V,
current capacity: 5mA)
• 30-pin SSOP small package
Applications
• TV tuners
• VCR tuners
• CATV tuners
Structure
Bipolar silicon monolithic IC
Note: This IC has pins whose electrostatic discharge strength is weak as the operating frequency is high
and the high-frequency process is used for this IC. Take care of handling the IC.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01326-PS
CXA3555N
Block Diagram and Pin Configuration
30
IF AMP
IFOUT
ADSW
1
2
SCL
SDA
29
28 BS3
BS1
BS2
3
4
REF
OSC
REF
OSC
Divider
1/128, 160, 256
27
Shift
Register
I2C BUS
Interface
5
6
IFIN1
IFIN2
26
25
CPO
VT
Charge
Pump
Phase
Detector
Band SW
Driver
Programable
Divider
14/15 bit
7
Vcc
Prescaler
1/2
24 GND2
8
9
MIXOUT1
MIXOUT2
23
UOSCB2
22
21
20
UOSCE2
UOSCE1
UHFOSC
UOSCB1
VHOSC2
10
GND1
19
18
11
12
VHFIN
BYP
VLOSC2
VHOSC
13
BS4
14
15
UHFIN1
UHFIN2
UHF/VHF
MIX
17
16
VHOSC1
VLOSC1
VLOSC
– 2 –
CXA3555N
Pin Description
Pin
No.
Symbol
Description
1
SCL
SCL input
2
SDA
SDA I/O
3
BS1
Band switch output 1
Band switch output 2
IF amplifier input
IF amplifier input
Power supply
4
BS2
5
IFIN1
IFIN2
Vcc
6
7
8
MIXOUT1
MIXOUT2
MIX output (open collector)
MIX output (open collector)
Analog circuit GND
VHF input
9
10 GND1
11 VHFIN
12 BYP
VHF input GND and gain switching (low: GND, high: open)
Band switch output 4
13 BS4
14 UHFIN1
15 UHFIN2
16 VLOSC1
17 VHOSC1
18 VLOSC2
19 VHOSC2
20 UOSCB1
21 UOSCE1
22 UOSCE2
23 UOSCB2
24 GND2
25 VT
UHF input
UHF input
VHF Low-band oscillator
VHF High-band oscillator
VHF Low-band oscillator
VHF High-band oscillator
UHF oscillator (base pin)
UHF oscillator (emitter pin)
UHF oscillator (emitter pin)
UHF oscillator (base pin)
PLL circuit GND
Tuning voltage output (open collector)
Charge pump output (loop filter connection)
Crystal connection for PLL reference oscillator
Band switch output 3
26 CPO
27 REFOSC
28 BS3
29 ADSW
30 IFOUT
Address selection (I2C bus)
IF amplifier output
– 3 –
CXA3555N
Pin Description
Pin
Pin voltage
[V]
Symbol
No.
Equivalent circuit
Description
7
1
1
SCL
—
Clock input
40k
7
40k
2
SDA
—
Data input
2
5p
7
3
4
BS1
BS2
3
4
70k
Band switch outputs.
This pin corresponding to the
selected band goes High.
High: 4.9
Low: 0.0
7
13 BS4
28 BS3
13
28
– 4 –
CXA3555N
Pin
No.
Pin voltage
[V]
Symbol
Equivalent circuit
Description
7
5
6
1.6k
5
IFIN1
IF inputs.
These pins must be connected
to the mixer outputs via
coupling capacitance.
2.0
6
IFIN2
7
8
VCC
—
—
—
Power supply.
8
9
MIXOUT1
Mixer outputs.
These pins output the signal in
open collector format, and they
must be connected to the
power supply via a load.
9
MIXOUT2
10 GND1
11 VHFIN
Analog circuit GND.
2.4 during
7
VHF input.
The input format is unbalanced
input.
VHF reception
0.0 during
57k
UHF reception
150k
15p
3k
11
3k
VHF input GND and gain
switching.
GND: low gain
VCC
(when open)
12 BYP
Open: high gain
(However, when control byte
GC is "0")
12
7
14 UHFIN1
15 UHFIN2
UHF inputs.
14
15
Input a balanced signal to
Pins 14 and 15, or ground
either of Pin 14 or 15 with a
capacitor and input the signal
to the other pin.
0.0 during
VHF reception
2.3 during
3k
3k
UHF reception
– 5 –
CXA3555N
Pin
No.
Pin voltage
[V]
Symbol
Equivalent circuit
Description
16
18
7
16 VLOSC1
33
33
External resonance circuit
connection for VL oscillator.
0.0
50k
50k
18 VLOSC2
17
19
7
17 VHOSC1
20
20
External resonance circuit
connection for VH oscillator.
0.0
50k
50k
19 VHOSC2
2.4 during
VHF reception
2.2 during
7
20 UOSCB1
21 UOSCE1
22 UOSCE2
UHF reception
23
2.0 during
22
21
20
VHF reception
1.5 during
UHF reception
External resonance circuit
connection for UHF oscillator.
2.0 during
3k
VHF reception
1.5 during
3k
UHF reception
2.4 during
VHF reception
2.2 during
23 UOSCB2
24 GND2
UHF reception
—
PLL circuit GND.
Varicap drive voltage output.
This pin outputs the signal in
open collector format, and it
must be connected to the
7
25 VT
—
26
25
tuning power supply via a load.
70
Charge pump output.
Connects the loop filter.
26 CPO
2.0
– 6 –
CXA3555N
Pin
No.
Pin voltage
[V]
Symbol
Equivalent circuit
Description
7
30k
Crystal connection for
reference oscillator.
25p
27 REFOSC
4.4
27
38p
7
150k
29
Address selection.
Controls address bits 1 and 2.
1.25
(when open)
29 ADSW
50k
5p
7
30
30 IFOUT
2.8
IF output.
– 7 –
CXA3555N
Electrical Characteristics (See the Electrical Characteristics Measurement Circuit.)
(Vcc = 5V, IFVCC = 5V, Ta = 25°C)
Circuit Current
Item
Symbol
Iccv
Measurement conditions
VCC current
Min.
35
Typ.
56
Max.
78
Unit
mA
Band switch output open during VHF operation
Circuit current
VCC current
Band switch output open during UHF operation
Iccu
35
56
78
mA
OSC/MIX/IF Amplifier Block
Item
Symbol
CG1
CG2
CG3
CG4
CG5
CG6
CG7
CG8
NF1
NF2
NF3
NF4
NF5
NF6
NF7
NF8
Measurement conditions
Min.
19.0
19.5
23.0
23.0
17.0
17.5
21.0
21.0
Typ.
22.0
22.5
26.0
26.0
20.0
20.5
24.0
24.0
12
Max.
25.0
25.5
29.0
29.0
23.0
23.5
27.0
27.0
15
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
VHF operation fRF = 55MHz High gain mode
VHF operation fRF = 360MHz High gain mode
UHF operation fRF = 360MHz High gain mode
UHF operation fRF = 800MHz High gain mode
VHF operation fRF = 55MHz Low gain mode
VHF operation fRF = 360MHz Low gain mode
UHF operation fRF = 360MHz Low gain mode
UHF operation fRF = 800MHz Low gain mode
VHF operation fRF = 55MHz High gain mode
VHF operation fRF = 360MHz High gain mode
UHF operation fRF = 360MHz High gain mode
UHF operation fRF = 800MHz High gain mode
VHF operation fRF = 55MHz Low gain mode
VHF operation fRF = 360MHz Low gain mode
UHF operation fRF = 360MHz Low gain mode
UHF operation fRF = 800MHz Low gain mode
1
Conversion gain
15
12
13
10
14
11
1,
2
Noise figure
16
13
16
13
14
11
15
12
VHF operation fD = 55MHz
fUD = ±12MHz (30% AM) High gain mode
99
99
CM1
CM2
CM3
CM4
CM5
CM6
CM7
CM8
103
103
101
98
dBµ
dBµ
dBµ
dBµ
dBµ
dBµ
dBµ
VHF operation fD = 360MHz
fUD = ±12MHz (30% AM) High gain mode
UHF operation fD = 360MHz
fUD = ±12MHz (30% AM) High gain mode
97
UHF operation fD = 800MHz
fUD = ±12MHz (30% AM) High gain mode
94
1% cross
modulation 1
1,
3
VHF operation fD = 55MHz
fUD = ±12MHz (30% AM) Low gain mode
100
100
98
104
104
102
VHF operation fD = 360MHz
fUD = ±12MHz (30% AM) Low gain mode
UHF operation fD = 360MHz
fUD = ±12 MHz (30% AM) Low gain mode
UHF operation fD = 800MHz
fUD = ±12 MHz (30% AM) Low gain mode
94
8
98
11
dBµ
Maximum output power
Pomax 50Ω load, saturation output
– 8 –
dBm
CXA3555N
Item
Symbol
Measurement conditions
Min.
Typ.
Max.
±300
Unit
kHz
VHF operation fOSC = 100MHz
∆f from 3s to 3min after switch ON
∆fsw1
VHF operation fOSC = 405MHz
∆f from 3s to 3min after switch ON
∆fsw2
∆fsw3
∆fsw4
∆fst1
∆fst2
∆fst3
∆fst4
C/N1
C/N2
±600
±350
±400
±100
±450
±100
±100
kHz
kHz
Switch ON drift
(PLL not
operating)
4
UHF operation fOSC = 405MHz
∆f from 3s to 3min after switch ON
UHF operation fOSC = 845MHz
∆f from 3s to 3min after switch ON
kHz
VHF operation fOSC = 100MHz
∆f when VCC 5V changes ±5%
kHz
VHF operation fOSC = 405MHz
∆f when VCC 5V changes ±5%
kHz
Supply voltage drift
(PLL not
UHF operation fOSC = 405MHz
∆f when VCC 5V changes ±5%
4
operating)
kHz
UHF operation fOSC = 845MHz
∆f when VCC 5V changes ±5%
kHz
VHF operation 10kHz offset CP = 1
Phase comparison frequency = 31.25kHz
86
80
dBc/Hz
dBc/Hz
Oscillator phase
noise
UHF operation 10kHz offset CP = 1
Phase comparison frequency = 31.25kHz
1
Value measured with untuned input.
2
3
NF meter direct-reading value (DSB measurement).
Value with a desired reception signal input level of –30dBm, an interference signal of 100kHz/30% AM,
and an interference signal level where S/I = 46dB measured with a spectrum analyzer.
Value when the PLL is not operating.
4
– 9 –
CXA3555N
PLL Block
Item
Symbol
LUT1
Measurement conditions
Min.
Typ.
Max.
50
Unit
ms
VHF operation CP = 1
fOSC 100MHz →← fOSC 405MHz
Lock-up time
UHF operation CP = 1
fOSC 405MHz →← fOSC 845MHz
LUT2
REFL
50
ms
Phase comparison frequency
Reference leak
54
dBc
= 31.25kHz
CP = 1
CL and DA inputs
"H" level input voltage
"L" level input voltage
"H" level input current
"L" level input current
AD input
VIH
VIL
IIH
3
Vcc
1.5
V
V
GND
VIH = Vcc
0
–0.1
–4
µA
µA
IIL
VIL = GND
–0.2
"H" level input voltage
"L" level input voltage
"H" level input current
"L" level input current
SDA output
VIH
VIL
IIH
3
Vcc
1
V
V
GND
VIH = Vcc
100
200
–100
µA
µA
IIL
VIL = GND
–35
"H" output leak current
"L" output voltage
CPO (charge pump)
Output current 1
ISDALK
VSDAL
VIN = 5.5V
5
µA
V
Sink = –3mA
GND
±30
0.4
ICPO1
When CP = 0 is selected
±50
±80
30
µA
nA
µA
nA
Leak current 1
LeakCP1 When CP = 0 is selected
When CP = 1 is selected
Output current 2
ICPO2
±120 ±200 ±320
100
Leak current 2
LeakCP2 When CP = 1 is selected
VT (VC voltage output)
Maximum output voltage
Minimum output voltage
REFOSC
VTH
34
V
V
VTL
Sink current = 1mA
0.15
0.8
Oscillation frequency range
Input capacitance
FXTOSC
CXTOSC
3
12
26
MHz
pF
22
24
Crystal source impedance
fREF = 4MHz
Negative resistance
RNEG
–1
–3
kΩ
Band SW
Output current
Saturation voltage
Leak current
IBS
When ON
–5
300
3
mA
mV
µA
VSAT
When ON Source current = 5mA
100
0.5
LeakBS When OFF IFVCC = 5.5V
– 10 –
CXA3555N
Item
Bus timing (I2C bus)
SCL clock frequency
Start waiting time
Start hold time
Low hold time
Symbol
fSCL
Measurement conditions
Min.
Typ.
Max.
400
Unit
0
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
W;STA
H;STA
LOW
HIGH
S;STA
H;DAT
S;DAT
R
1300
600
1300
600
600
0
High hold time
Start setup time
Data hold time
Data setup time
Rise time
900
600
300
300
Fall time
F
Stop setup time
S;STO
600
– 11 –
CXA3555N
Electrical Characteristics Measurement Circuit
IF OUT
+30V
22k
4700p
240
220n
10k 0.056µ
10k
10k
10k
3.4φ
2.5T
3.4φ
8.5T
2.5φ
2.5T
10k
10k
56p
1T363
1T363
1T362
10k
0.5p 1T363
0.5p
56p
1n
0.5p
0.5p
10p
10k
7p
XTAL
4MHz
12p
12p
1.2k
10p
0
27
27
56p
7p
56p
7p
0
100p
28
2p
30
29
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1000p
51
51
1.2k
1.2k
1n
1n
1.2k 1n
1n
150p
150p
4.5T 4.5T
56p
56p
100
1000p
1000p
3.3µ
ADSW SCL SDA
+5V
VHF IN
UHF IN
– 12 –
CXA3555N
Application Circuit
IF OUT
+30V
22k
1000p
240
4700p
1.2µH
220n
10k 0.056µ
10k
10k
10k
2.0φ
1.5T
1T363
0.5p
1T362
56p
56p
10k
10k
0.5p
1T369
10k
0.5p
100p
22p
FMT
3.4φ
2.5T
3.4φ
8.5T
10p
12p
XTAL
4MHz
100p
6p
8p
51
20
100p
28
8p
8p
30
29
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1000p
33p
150p
3k
200
200
2k
3.2φ
7.5T
1n
1n
1n
1n
1n
3.8φ
14.5T
4.5T 4.5T
BVL BVH
BU
47p
47p
1n
1n
56p
56p
100
1000p
1000p
3.3µ
ADSW SCL SDA
+5V
VHF IN
UHF IN
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 13 –
CXA3555N
Description of Functions
The CXA3555N is an analog terrestrial TV broadcasting tuner IC which converts frequencies to IF in order to
tune and detect only the desired reception frequency of VHF and UHF band signals.
In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC
also integrates a PLL circuit for local oscillation frequency control onto a single chip.
The functions of the various circuits are described below.
1. Mixer circuit
This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local
oscillation signal.
2. Local oscillation circuit
A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance.
3. IF amplifier circuit
This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage.
4. PLL circuit
This PLL circuit fixes the local oscillation frequency to the desired frequency. It consists of a programmable
divider, reference divider, phase comparator, charge pump and reference oscillator. The control format
supports the I2C bus format.
The frequency steps of 31.25, 50 or 62.5kHz can be selected by the I2C bus data-based reference divider
frequency division setting value.
5. Band switch circuit
The CXA3555N has four sets of built-in PNP transistors for switching between the VL, VH and UHF bands
and for switching the FM trap, etc. These PNP transistors can be controlled by the bus data.
The emitters for these PNP transistors are connected to the power supply pin (VCC), and are ON and output
5V when the bus data is "1 (H)".
– 14 –
CXA3555N
Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.)
VHF-Low oscillator circuit
• This is a completely balanced oscillator circuit. The oscillation frequency is varied by connecting an LC parallel
resonance circuit including a varicap between Pins 16 and 18 via coupled capacitance and controlling the
voltage applied to the varicap.
VHF-High oscillator circuit
• This is a completely balanced oscillator circuit. The oscillation frequency is varied by connecting an LC parallel
resonance circuit including a varicap between Pins 17 and 19 via coupled capacitance and controlling the voltage
applied to the varicap.
VHF mixer circuit
• The mixer circuit employs a double balanced mixer with little local oscillation signal leakage.
The input format is base input type, with Pin 12 grounded either directly or via a capacitor and the RF signal
input to Pin 11.
(Pin 12 can also be used to switch the IC gain according to the applied DC voltage value. When switching the
gain with Pin 12, the GC bit of the PLL data must be set to "0".)
• The RF signal is fed from the oscillator, converted to IF frequency and output from Pins 8 and 9. Pins 8 and
9 are open collectors, so external power feed is necessary. Also, connect single-tuned filters to Pins 8 and 9.
UHF oscillator circuit
• The oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential
oscillation operation via an LC resonance circuit including a varicap.
• Resonance capacitance is connected between Pins 20 and 21, Pins 21 and 22, and Pins 22 and 23, and an
LC resonance circuit including a varicap is connected between Pins 20 and 23.
UHF mixer circuit
• This circuit employs a double balanced mixer like the VHF mixer circuit.
The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be
selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input consisting
of grounding Pin 14 via a capacitor and input to Pin 15.
• Pins 8 and 9 are the mixer outputs. Pins 8 and 9 are open collectors, so external power feed is necessary.
Also, connect single-tuned filters to Pins 8 and 9.
IF amplifier circuit
• Pins 5 and 6 are the IF amplifier inputs, and the input impedance is approximately 1.6kΩ.
• The signals frequency converted by the mixer are output from Pins 8 and 9, and Pins 8 and 9 are connected
to Pins 5 and 6 via capacitors. (An adjacent channel trap circuit can be formed by connecting LC parallel
circuits in place of capacitors.)
• The signal amplified by the IF amplifier is output from Pin 30. The output impedance is approximately 10Ω.
– 15 –
CXA3555N
Description of PLL Block
This IC is controlled by the I2C bus.
The PLL of this IC performs high-speed phase comparison, providing low reference leak and quick lock-up
time characteristics.
During power on, the power-on reset circuit operates to initialize the frequency data to all "0" and the band
data to all "OFF". Power-on reset is performed when VCC ≥ 3.2V at room temperature (Ta = 25°C).
1) Address setting
Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one
system.
The responding address can be set according to the ADSW pin voltage.
Address
1
1
0
0
0
MA1
MA0
R/W
Hardware bits
ADSW pin voltage
0 to 0.1Vcc
MA1
0
MA0
0
OPEN or
0.2Vcc to 0.3Vcc
0
1
0.4Vcc to 0.6Vcc
0.9Vcc to Vcc
1
1
0
1
2) Frequency data setting
The VCO lock frequency is obtained according to the following formula.
fosc = 2 × fref × (32M + S)
fosc: local oscillator frequency
fref: phase comparison frequency
M: main divider frequency division ratio
S:
swallow counter frequency division ratio
The variable frequency division ranges of M and S are as follows, and are set as binary.
S < M ≤ 1023
0 ≤ S ≤ 31
– 16 –
CXA3555N
3) Control format
When performing control for this IC, byte 1 contains the address data, bytes 2 and 3 contain the frequency
data, byte 4 contains the control data, and byte 5 contains the band switch data.
These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5.
When the correct address is received and acknowledged, the data is recognized as frequency data if the
first bit of the next byte is "0", and as control data and band switch data if this bit is "1".
Also, when data transmission is stopped part-way, the previously programmed data is valid.Therefore, once
the control and band switch data have been programmed, 3-byte commands consisting of the address and
frequency data are possible.
Further, even if the I2C bus stop conditions are not met, data can be input by sending the start conditions
and the new address.
The control format is as shown in the table below.
Slave Receiver
MSB
bit 7
1
LSB
bit 0
0
Mode
bit 6
1
bit 5
0
bit 4
0
bit 3
0
bit 2
MA1
M5
bit 1
MA0
M4
Address byte
Divider byte1
Divider byte2
Control byte
Band SW byte
A
A
A
A
A
0
M9
M1
CP
X
M8
M0
GC
X
M7
S4
CD
X
M6
S3
X
M3
S0
M2
1
S2
S1
R1
R0
OS
BS1
X
BS4
BS3
BS2
X: Don't care
A:
Acknowledge bit
MA0, MA1: address setting
M0 to:
S0 to:
CD:
main divider frequency division ratio setting
swallow counter frequency division ratio setting
charge pump OFF (when "1")
OS:
varicap output OFF (when "1")
CP:
charge pump current switching (200µA when "1", 50µA when "0")
1
GC:
gain switching (IC gain reduced by 2dB when "1")
BS1 to BS4: band switch control (output PNP transistor ON when "1")
R0, R1:
reference divider frequency division ratio setting (See the Reference Divider Frequency Division
Ratio Table.)
1
When switching the gain with the PLL data, ground Pin 12 (BYP) via a capacitor.
Reference Divider Frequency Division Ratio Table
R1
0
R0
1
Reference Divider
256
128
160
1
1
X
0
X: Don't care
– 17 –
CXA3555N
I2C Bus Timing Chart
tW;STA
SDA
tR
tF
tS;STO
tS;STA
SCL
tH;STA
tLOW
tHIGH
tS;DAT
tH;DAT
START
CLOCK
DATA CHANGE
STOP
tS;STA = Start setup time
tW;STA = Start waiting time
tH;STA = Start hold time
tS;DAT = Data setup time
tH;DAT = Data hold time
tS;STO = Stop setup time
tLOW = Low clock pulse width
tHIGH = High clock pulse width
tR
tF
= Rise time
= Fall time
– 18 –
CXA3555N
Example of Representative Characteristics
Band SW output voltage vs. Output current
(BS1, BS2, BS3, BS4)
Circuit current vs. Supply voltage
60
5.4
5.3
5.2
5.1
5.0
4.9
4.8
VHF
UHF
Vcc = 5V
58
56
54
52
50
48
46
44
42
40
4.7
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
0
1
2
3
4
5
6
7
Vcc – Supply voptage [V]
Output current [mA]
Conversion gain vs. Reception frequency
(Untuned input)
Noise figure vs. Reception frequency
(Untuned input, in DSB)
40
20
15
f
IF = 45MHz
f
IF = 45MHz
High gain mode
High gain mode
30
UHF
VHF (High)
VHF (Low)
VHF (High)
VHF (Low)
UHF
20
10
0
10
5
0
0
0
100 200 300 400 500 600 700 800 900
Reception frequency [MHz]
100 200 300 400 500 600 700 800 900
Reception frequency [MHz]
Next adjacent cross modulation vs. Reception frequency
Oscillation frequency power supply fluctuation
(Untuned input)
(PLL off)
120
400
Vcc + 5%
Vcc – 5%
(Vcc = 5V)
110
100
90
VHF (High)
VHF (Low)
UHF
300
200
100
0
VHF (High)
VHF (Low)
80
70
UHF
60
50
–100
–200
40
f
f
UD = f
UD = f
D
D
+ 12MHz
– 12MHz
30
(100kHz, 30% AM)
20
–300
–400
f
IF = 45MHz
10
0
0
High gain mode
100 200 300 400 500 600 700 800 900
Reception frequency [MHz]
0
100 200 300 400 500 600 700 800 900
Oscillation frequency [MHz]
– 19 –
CXA3555N
Oscillator phase noise vs. Reception frequency (untuned input)
130
120
f
IF = 45MHz
High gain mode
VHF (Low)
VHF (Low)
VHF (High)
UHF
110
100
90
VHF (High)
VHF (High)
UHF
UHF
80
70
VHF (Low)
60
1kHz offset
10kHz offset
100kHz offset
50
40
0
100
200
300
400
500
600
700
800
900
Reception frequency [MHz]
I/O characteristics (untuned input)
PCS beat characteristics (untuned input)
20
10
20
10
High gain mode
0
f
IF
0
–10
–20
–30
–40
–10
–20
–30
–40
f
Beat
f
f
Local = 495MHz
= 449.25MHz
–50
–60
–70
–80
P
fc = 452.83MHz
(f –12dB)
fs = 453.75MHz
(f –1.7dB)
P
f
RF = 45MHz
P
–50
–60
High gain mode
f
f
RF = 145MHz (VHF)
RF = 495MHz (UHF)
f
f
IF = 45.75MHz
Beat = fIF ± 950kHz
–60 –50 –40 –30 –20 –10
0
10
20
–40
–30
–20
–10
0
10
20
RF level [dBm]
RF level (SG Setting level) [dBm]
– 20 –
CXA3555N
Tuning Response Time
VHF (Low) 95MHz → VHF (High) 395MHz
CP = 0
T = 47.2ms
5.0V/div
Offset 10.0V
–75.0000ms
25.0000ms
20.0ms/div
125.0000ms
CP = 1
T = 15.0ms
5.0V/div
Offset 10.0V
–40.0000ms
10.0000ms
10.0ms/div
60.0000ms
– 21 –
CXA3555N
UHF 413MHz → UHF 847MHz
CP = 0
T = 63.6ms
5.0V/div
Offset 10.0V
–70.0000ms
30.0000ms
20.0ms/div
130.0000ms
CP = 1
T = 20.2ms
5.0V/div
Offset 10.0V
–40.0000ms
10.0000ms
10.0ms/div
60.0000ms
– 22 –
CXA3555N
VHF (High) 395MHz → VHF (Low) 95MHz
CP = 0
T = 27.0ms
5.0V/div
Offset 10.0V
–110.0000ms
–10.0000ms
90.0000ms
20.0ms/div
CP = 1
T = 7.2ms
5.0V/div
Offset 10.0V
–45.0000ms
5.0000ms
55.0000ms
10.0ms/div
– 23 –
CXA3555N
UHF 847MHz → UHF 413MHz
CP = 0
T = 35.6ms
5.0V/div
Offset 10.0V
–110.0000ms
–10.0000ms
90.0000ms
20.0ms/div
CP = 1
T = 14.4ms
5.0V/div
Offset 10.0V
–90.0000ms
10.0000ms
20.0ms/div
110.0000ms
– 24 –
CXA3555N
IF output spectrum
REF = –10.0dBm
10dB/div
VHF (Low)
f
f
RF = 55MHz
LO = 100MHz
RF input level: –40dBm
CENTER 45.00013MHz
RES BW 1.0kHz
SPAN 50.00kHz
SWP 30.0s
VBW 10Hz
REF = –10.0dBm
10dB/div
VHF (High)
f
f
RF = 350MHz
LO = 395MHz
RF input level: –40dBm
CENTER 45.00088MHz
RES BW 1.0kHz
SPAN 50.00kHz
SWP 30.0s
VBW 10Hz
REF = –0.0dBm
10dB/div
UHF
f
f
RF = 800MHz
LO = 845MHz
RF input level: –40dBm
CENTER 45.00188MHz
RES BW 1.0kHz
SPAN 50.00kHz
SWP 30.0s
VBW 10Hz
– 25 –
CXA3555N
VHF Input Impedance
j50
j25
j100
0
50
50MHz
11
12
1000p
S11
350MHz
–j25
–j100
–j50
UHF Input Impedance
j50
j25
j100
0
50
14
15
1000p
S11
350MHz
–j25
–j100
800MHz
–j50
– 26 –
CXA3555N
IF Output Impedance
j50
j25
j100
45MHz
38MHz
0
50
–j25
–j100
–j50
– 27 –
CXA3555N
Package Outline
Unit: mm
30PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
9.7 ± 0.1
0.10
30
16
A
1
15
0.65
b
0.13
M
b=0.22 ± 0.03
0.1 ± 0.1
DETAIL B : PALLADIUM
NOTE: Dimension " " does not include mold protrusion.
0˚ to 10˚
PACKAGE STRUCTURE
DETAIL A
PACKAGE MATERIAL
EPOXY RESIN
PALLADIUM PLATING
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
SSOP-30P-L01
P-SSOP30-5.6x9.7-0.65
COPPER ALLOY
0.1g
JEDEC CODE
Sony Corporation
– 28 –
相关型号：
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