CXA3562R [SONY]
LCD Driver; LCD驱动器
| 型号： | CXA3562R |
| 厂家： | 
SONY CORPORATION |
| 描述： | LCD Driver |
| 文件： | 总24页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA3562R
LCD Driver
Description
100 pin LQFP (Plastic)
The CXA3562R is a driver IC developed for use
with Sony polycrystalline silicon TFT LCD panels. It
supports digital 2-parallel and single input, and the
input data is analog demultiplexed into 12 phases and
output. The CXA3562R can directly drive an LCD
panel, and the VCOM setting circuit and precharge
pulse waveform generator are also on-chip.
Features
• Supports 10-bit 2-parallel and single input
• Supports signals up to UXGA
(1/2 clock when using UXGA signals)
• Low output deviation by on-chip output offset cancel circuit
• Supports both line inversion and dot and line inversion
• On-chip timing generator with ECL
• VCOM voltage generation circuit
• Precharge pulse waveform generation circuit
Applications
LCD projectors and other video equipment
Absolute Maximum Ratings (VSS = 0V)
• Supply voltage
VCC
VDD
Topr
16
5.5
V
V
• Operating temperature
• Storage temperature
–20 to +70
°C
Tstg –65 to +150 °C
• Allowable power dissipation PD
2300
mW
Recommended Operating Conditions
• Supply voltage
VCC
VDD
Topr
15.0 to 15.5
4.75 to 5.25
–20 to +70
V
V
• Operating temperature
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01115-PS
CXA3562R
Block Diagram and Pin Configuration
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D_A9
D_A8
D_A7
D_A6
D_A5
D_A4
76
77
78
79
80
81
50
49
48
PVCC
SID Gen.
VCOM Gen.
Line Inv.
SH_OUT2
NC
Vref Gen.
47 SH_OUT3
46 NC
Offset Cancel
Line Inv.
45 SH_OUT4
44 NC
Offset Cancel
Line Inv.
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
D_A3 82
Offset Cancel
Line Inv.
D_A2
D_A1
83
84
43 SH_OUT5
42 NC
D/A
Offset Cancel
Line Inv.
D_A0 85
GND 86
GND 87
GND 88
GND 89
GND 90
D_B9 91
D_B8 92
D_B7 93
D_B6 94
D_B5 95
D_B4 96
41 SH_OUT6
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
Offset Cancel
Line Inv.
GND
PGND
GND
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
GND
SH_OUT7
NC
Offset Cancel
Line Inv.
D/A
SH_OUT8
NC
Offset Cancel
Line Inv.
SH_OUT9
NC
Offset Cancel
Line Inv.
Offset Cancel
Line Inv.
97
98
99
100
D_B3
D_B2
D_B1
D_B0
SH_OUT10
NC
FRP_OD
FRP_EV
Offset Cancel
SH_OUT11
TG
PVCC
Offset Cancel Level Gen.
CAL_PLS
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
– 2 –
CXA3562R
Pin Description
Pin
Standard
voltage level
Symbol
No.
I/O
Equivalent circuit
Description
VDD
PECL
8k
140k
140k
differential
(amplitude
0.4V or more
between
Dot clock input.
1k
1k
PECL differential input or TTL
input. For TTL input, input to
MCLK and connect MCLKX to
GND through a capacitor.
2
3
2
3
MCLK
MCLKX
I
VDD to 2V)
or TTL input
60k
192
100µ 60k
GND
V
DD
50k
LCD panel AC drive inversion
timing input.
High: inverted
Low: non-inverted
See the Timing Chart.
High: ≥2.0V
Low: ≤0.8V
4
4
5
FRP
I
I
GND
Internal sample-and-hold timing
circuit reset pulse input.
This pin is also used as the
offset cancel level insertion
timing input.
V
DD
50k
192
High: ≥2.0V
Low: ≤0.8V
5
SHST
A reset is applied to the internal
timing generator at the falling
edge.
GND
VDD
Output phase adjustment.
The output phase is adjusted in
MCLK period units when
SL_DAT (Pin 72) is high, and in
1/2 MCLK period units when
SL_DAT is low.
50k
6
7
8
9
POSCTR0
POSCTR1
POSCTR2
POSCTR3
192
High: ≥2.0V
Low: ≤0.8V
I
6
7
8
9
GND
VDD
VCC
Signal center voltage (inversion
folded voltage) adjustment input.
The SH_OUT output center
voltage can be adjusted in the
range from 7.0 to 8.0V.
20µ
30k
16
SIG.C
I
1 to 5.0V
16
GND
V
DD
VCC
Output signal offset adjustment
from signal center voltage.
The SH_OUT output 100%
white level (at 3FF input) voltage
can be adjusted in the range
from 0 to 1V from the center
voltage.
10µ
30k
17
17
SIG_OFST
I
0 to 5.0V
GND
– 3 –
CXA3562R
Pin
No.
Standard
voltage level
Symbol
I/O
O
Equivalent circuit
Description
V
CC
40µ 1k
145
Level output for canceling the
offset between channels.
Connect directly to CAL_IL and
CAL_IH, respectively.
18
19
CAL_OL
CAL_OH
3.0 to 6.0V
9.0 to 12.0V
18
19
GND
Level input for canceling the
offset between channels.
VCC
20k
Connect directly to CAL_OL and
CAL_OH, respectively. When
using two CXA3562R, connect
the CAL_IL and CAL_IH of both
chips to the CAL_OL and
21
22
CAL_IH
CAL_IL
9.0 to 12.0V
3.0 to 6.0V
30k
O
21
22
20µ
CAL_OH of only one CXA3562R.
GND
VDD
Offset cancel function off.
Normally connect to GND to
use with the offset cancel
function on.
24k
24k
145
24
DCFBOFF
I
GND
24
High (offset cancel function off)
when open.
GND
PVCC
25 27
29 31
33 35
41 43
45 47
49 51
25, 27,
29, 31,
33, 35,
41, 43,
45, 47,
49, 51
300
300
Demultiplexed output of AC
inverse driven video signals.
Can be connected directly to
the LCD panel.
SH_OUT12
to
SH_OUT1
O
1.5 to 13.5V
GND
VCC
80µ
LCD panel common voltage
output.
Can be set in the range from
the SH_OUT center potential
Vsig.c to Vsig.c – 2V by
VCOM_OFST.
500
500
100k
145
53
53
VCOM_OUT
O
5.0 to 8.0V
GND
VDD
VCC
LCD panel common voltage
adjustment.
VCOM_OUT can be set in the
range from the SH_OUT center
potential Vsig.c to Vsig.c – 2V
by inputting 0 to 5V.
80µ
2k
54
54
VCOM_OFST
I
0 to 5.0V
100
GND
– 4 –
CXA3562R
Pin
No.
Standard
voltage level
Symbol
I/O
O
Equivalent circuit
Description
VCC
Precharge waveform output.
SID_OUTX outputs the inverse
of SID_OUT based on the
output center voltage. These
pins cannot directly drive the
LCD panel, so input to the LCD
panel with an external a buffer.
100k
0.2p
145
56
57
SID_OUTX
SID_OUT
56
57
1.5 to 13.5V
100k
0.2p
GND
VDD
VCC
Precharge level setting.
Adjusts the SID_OUT and
SID_OUTX output potential.
PRG_LV is reflected when the
PRG input pin (Pin 60) is high,
and SID_LV is reflected when
PRG is low.
29µ
50k
50k
58
59
PRG_LV
SID_LV
I
1.0 to 5.0V
58
59
GND
V
DD
V
CC
100k
10k
Timing pulse input for switching
the Pins 56 and 57 output levels.
(See PRG_LV (Pin 58) and
SID_LV (Pin 59).)
High: ≥2.0V
Low: ≤0.8V
60
60
PRG
I
50µ
GND
V
DD
70µ
10µ
Internal D/A converter reference
voltage input.
Normally connect directly to
VREF_O.
68
68
VREF_I
I
3.2V
1k
33.3k
280µ
GND
VDD
2k
Reference voltage output.
Normally connect directly to
VREF_I, and connect to GND
through a 0.5 to 1.0µF capacitor.
69
69
VREF_O
O
3.2V
20k
20µ
12.4k
GND
VDD
SH_OUT output timing selection.
High: SH_OUT1 to SH_OUT6
and SH_OUT7 to SH_OUT12
are output at different timing.
Low: SH_OUT1 to SH_OUT12
are output at the same timing.
50k
High: ≥2.0V
Low: ≤0.8V
Open: Low
192
70
70
F/H_CNT
I
200k
GND
– 5 –
CXA3562R
Standard
voltage level
Pin
No.
Symbol
I/O
Equivalent circuit
Description
V
DD
Power saving.
Power saving mode when set to
low level.
Low (power saving mode) when
open.
70k
66
66
38
PS
I
5V
180k
30µ
Normally connect to VDD.
GND
Power GND.
PGND
GND
15.5V
15.5V
5V
Power VCC.
26, 50 PVCC
15V power supply.
5V power supply.
55
67
VCC
VDD
11 to 15,
20, 36,
37, 39,
40,
GND
GND
GND.
61 to 65,
86 to 90
23, 28,
30, 32,
34, 42, NC
44, 46,
48, 52
VDD
2k
1µ
192
DAC output monitor test.
Normally connect to VDD.
1
75
1, 75 TEST
O
1.7 to 3.2V
20µ
GND
VDD
20k
20k
20k
250k
192
20k
10µ
Test.
Leave open.
10
SHTEST
I
2.5V
10
250k
10µ
GND
V
DD
Scan direction setting.
50k
High: output as a time series in
ascending order of output pin
symbol (in order from SH_OUT1
to SH_OUT12)
192
High: ≥2.0V
Low: ≤0.8V
71
DIRC
I
71
Low: output in descending order
GND
– 6 –
CXA3562R
Pin
No.
Standard
voltage level
Symbol
SL_DAT
I/O
Equivalent circuit
Description
V
DD
50k
Digital input mode switch setting.
High: single input from the A port
Low: parallel input from both the
A and B ports
High: ≥2.0V
Low: ≤0.8V
Open: Low
192
72
72
73
74
I
200k
200k
GND
V
DD
A and B port input switching
interlocked/non-interlocked
setting relative to scan direction
setting during parallel input.
High: A and B port switching
interlocked to DIRC
50k
High: ≥2.0V
Low: ≤0.8V
Open: High
192
73
SL_SCN
I
I
I
I
Low: fixed regardless of DIRC
GND
V
DD
SH_OUT odd-numbered and
even-numbered output polarity
inverted/non-inverted setting.
High: odd-numbered and even-
numbered outputs inverted
Low: non-inverted
50k
High: ≥2.0V
Low: ≤0.8V
Open: Low
192
74
SL_INV
200k
GND
VDD
50k
76
to
85
D_A9
to
D_A0
192
High: ≥2.0V
Low: ≤0.8V
A port digital data input.
76
85
to
GND
VDD
50k
91
to
D_B9
to
192
High: ≥2.0V
Low: ≤0.8V
B port digital data input.
91
100
to
100 D_B0
GND
– 7 –
CXA3562R
Electrical Characteristics Measurement Circuit
1µ
47p
47p
A
VCC
A
360p
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
PVCC
D_A9
D_A8
D_A7
D_A6
D_A5
D_A4
D_A3
D_A2
D_A1
D_A0
GND
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
SH_OUT2
NC
360p
360p
360p
360p
360p
SH_OUT3
NC
SH_OUT4
NC
SH_OUT5
NC
SH_OUT6
GND
GND
GND
PGND
GND
GND
GND
GND
GND
SH_OUT7
NC
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
360p
360p
360p
360p
360p
SH_OUT8
NC
SH_OUT9
NC
SH_OUT10
NC
SH_OUT11
PVCC
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VCC
360p
VCC
15.5V
VDD
5V
– 8 –
CXA3562R
Electrical Characteristics
Measurement
points
No.
1
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Digital input
resolution
n
—
2
10
—
—
—
—
—
bit
ns
ns
Digital input
setup time
SHST, D_A[9:0] and D_B[9:0] minimum
setup time relative to MCLK input. (PELL)
2
TS
Digital input
hold time
SHST, D_A[9:0] and D_B[9:0] minimum
hold time relative to MCLK input. (PECL)
3
TH
3
MCLK input
frequency
range 1
SL_DAT: 5V; maximum frequency at
which the internal timing generator
and D/A converter operate normally.
4
5
fMCLK1
30
60
—
—
80 MHz
100 MHz
MCLK input
frequency
range 2
SL_DAT: 0V; maximum frequency at
which the internal timing generator
and D/A converter operate normally.
fMCLK2
VREF_O output
voltage range
Measure the VREF_O (Pin 69)
voltage.
6
7
8
VVREF_O
3.10 3.20 3.32
4.44 4.50 4.83
4.44 4.50 4.83
V
V
V
SH_OUT
amplitude 1
Measure the SH_OUT1 voltage
difference at D_A[9:0]: 000h and 3FFh.
VSHOUT1p-p VOUT1
SH_OUT
amplitude 2
Measure the SH_OUT2 voltage
difference at D_B[9:0]: 000h and 3FFh.
VOUT2
VSHOUT2p-p
Lower the VREF_I voltage and adjust
the amplitude; minimum amplitude at
which SH_OUT1 can be output at
D_B[9:0]: 000h and 3FFh.
SH_OUT
minimum
amplitude
V
9
VOUT1
4
—
—
—
VOUTMINp-p
Load capacitance = 360pF; measure
slew rate at 10 to 90% of output
waveform rise and fall when D_A[9:0] 160 300
is varied from 000h to 3FFh and from
3FFh to 000h.
SH_OUT
slew rate
VOUT1 to
VOUT12
10
V/µs
SROUT
SH_OUT
11 minimum
output voltage
Minimum voltage at which sample-
and-hold outputs VOUT1 to VOUT12 can
be output.
VOUT1 to
VOUT12
1.5
—
—
—
V
V
VMIN
SH_OUT
12 maximum
Maximum voltage at which sample-
and-hold outputs VOUT1 to VOUT12 can
be output.
VOUT1 to
VOUT12
—
13.6
VMAX
output voltage
Value obtained by subtracting minimum
VOUT1 to VOUT12 value from maximum
VOUT1 to VOUT12 value at D_A[9:0]: 200h
and D_B[9:0]: 200h.
Output deviation
13 between
VOUT1 to
VOUT12
—
—
3
10 mVp-p
40 mVp-p
DOUT1
DOUT2
DIC1
channels 1
Value obtained by subtracting minimum
VOUT1 to VOUT12 value from maximum
VOUT1 to VOUT12 value at D_A[9:0]: 000h
or 3FFh and D_B[9:0]: 000h or 3FFh.
Output deviation
14 between
VOUT1 to
VOUT12
10
channels 2
Value obtained by subtracting minimum
VOUT1 to VOUT12 value from maximum
VOUT1 to VOUT12 value at D_A[9:0]: 200h
and D_B[9:0]: 200h. (when using two
CXA3562R)
Output deviation
between ICs 1
VOUT1 to
VOUT12
15
—
10
—
mVp-p
– 9 –
CXA3562R
Measurement
points
No.
16
Item
Symbol
DIC2
Measurement conditions
Min. Typ. Max. Unit
Value obtained by subtracting minimum
VOUT1 to VOUT12 value from maximum
VOUT1 to VOUT12 value at D_A[9:0]: 000h
or 3FFh and D_B[9:0]: 000h or 3FFh.
(when using two CXA3562R)
VOUT1 to
VOUT12
Output deviation
between ICs 2
20
mVp-p
—
—
PRG: 0V; measure VSID_LV and VSID at
FRP: 0V, and VSID_LV and VSIDX at
FRP: 5V.
VSID_LV
VSID
VSIDX
SID output
gain 1
17
18
ASID1
ASID2
2.0
2.0
times
times
1.9
1.9
2.1
2.1
Calculate as ASID1 = VSID(X)/VSID_LV.
PRG: 5V; measure VPRG_LV and VSID at
FRP: 0V, and VPRG_LV and VSIDX at
FRP: 5V.
VPRG_LV
VSID
VSIDX
SID output
gain 2
Calculate as ASID2 = VSID(X)/VPRG_LV.
Load capacitance = 47pF, PRG: 0V;
input a repeating high/low pulse to FRP
(Pin 4), and apply DC input voltage so
that VSID and VSIDX are 2.5V/11.5V.
Measure slew rate at 10 to 90% of
output waveform rise and fall.
VSID
VSIDX
SID output
slew rate
19
SRSID
VSIG
50
V/µs
15
—
VOUT1 center voltage when SIG.C
(Pin 16) is varied from 1 to 5V.
Signal center
adjustable range
20
21
VOUT1
—
—
V
V
7
0
8
1
D_A[9:0]: 3FFh, FRP: 0V, D_B[9:0]:
3FFh; value obtained by subtracting
VOUT1 from VOUT1 center voltage when
SIG_OFST (Pin 17) is varied from 1 to
5V.
SH_OUT offset
adjustable range
VSIGOFST VOUT1
VCOM_OUT voltage when VCOM_OFST
(Pin 54) is varied from 0 to 5V.
VCOM
adjustable range
Vc –
2.5
22
23
24
VCOM
IDD
VCOM
IVDD
—
85
40
V
Vc
112
59
VDD current
consumption
IDD = IVDD
mA
mA
59
21
ICC = IVCC1 + IVCC2
(no digital data input)
IVCC1
IVCC2
VCC current
consumption
ICC
Current
IVDD
IVCC1
IVCC2
GND (Pin 66),
ICC = IVDD + IVCC1 + IVCC2
consumption in
power saving
mode
25
IPS
8
mA
4
15
Differential
linearity error
VVREF_I = 3.2V
VVREF_I = 3.2V
26
27
DLE
ILE
—
—
—
LSB
LSB
–0.7
–1.2
0.7
1.2
Integral linearity
error
—
– 10 –
CXA3562R
Description of Operation
The flow of internal operations is described below.
The digital signals input to D_A9 to D_A0 and D_B9 to D_B0 are internally D/A converted into approximately
1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 12 phases is
amplified by a factor of three times, inverted at the signal center potential according to FRP, and output.
The output level relative to the digital input changes according to the following settings.
A: SIG_OFST voltage
B: VREF_I voltage
V
CC
C: SIG.C voltage
B
A
A
Signal Center
1023
C
B
512
0
GND
Digital IN
SH_OUT
1. Digital input block
The CXA3562R can be set to single input from only the A port or parallel input from both the A and B ports,
and port switching by right/left inversion is also possible in parallel input mode. This makes it possible to
support various systems.
In single input mode, the signal is internally demultiplexed to 2-parallel format and input to the D/A converter.
2. D/A converter block
The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input
from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a
maximum 1.5Vp-p with respect to input data of 000h to 3FFh.
3. Sample-and-hold (S/H) block
The odd-numbered and even-numbered D/A converter outputs are input to the odd-numbered and even-
numbered sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase
cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing
generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3
... SH_OUT12. For reverse scan, this order is inverted and the signals are output in descending order. Connect
the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown
on the following pages. These pulses are not output and are used only inside the IC.
– 11 –
CXA3562R
Single input mode
DAC
DAC
10bit
D_A1
D_A2
D_B2
DAC_O
D_A[9:0]
D
D
S/H
S/H
D
D
MCLK
MCLK/2
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
D_A[9:0]
MCLK
D_A1
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D_A2
0
10
D_B2
1
3
DAC_O
DIRC: H
SH1_1_2
SH1_3_4
SH1_5_6
SH1_7_8
SH1_9_10
SH1_11_12
SH2_1_6
SH2_7_12
CH1 to CH12 simultaneous output timing
F/H_CNT: L
SH3A_1_12
F/H_CNT: H
SH3B_1_6
CH1 to CH6 simultaneous output timing
CH7 to CH12 simultaneous output timing
SH3B_7_12
DIRC: L
SH1_1_2
SH1_3_4
SH1_5_6
SH1_7_8
SH1_9_10
SH1_11_12
SH2_1_6
SH2_7_12
F/H_CNT: L
SH3A_1_12
CH1 to CH12 simultaneous output timing
F/H_CNT: H
SH3B_1_6
CH1 to CH6 simultaneous output timing
CH7 to CH12 simultaneous output timing
SH3B_7_12
– 12 –
CXA3562R
2-parallel input mode
DAC
DAC
10bit
10bit
D_A2
D_B2
DAC_O
D_A[9:0]
D
D
D
S/H
S/H
D_B[9:0]
MCLK
D
–3
–2
–1
1
2
3
4
5
6
7
8
9
11
12
13
15
16
17
18
19
20
21
23
24
25
26
27
28
D_A[9:0]
D_B[9:0]
MCLK
0
10
14
22
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
D_A2
10
D_B2
DAC_O
–1
1
3
DIRC: H
SH1_1_2
SH1_3_4
SH1_5_6
SH1_7_8
SH1_9_10
SH1_11_12
SH2_1_6
SH2_7_12
CH1 to CH12 simultaneous output timing
F/H_CNT: L
SH3A_1_12
F/H_CNT : H
SH3B_1_6
CH1 to CH6 simultaneous output timing
CH7 to CH12 simultaneous output timing
SH3B_7_12
DIRC: L
SH1_1_2
SH1_3_4
SH1_5_6
SH1_7_8
SH1_9_10
SH1_11_12
SH2_1_6
SH2_7_12
F/H_CNT: L
SH3A_1_12
CH1 to CH12 simultaneous output timing
F/H_CNT: H
SH3B_1_6
CH1 to CH6 simultaneous output timing
CH7 to CH12 simultaneous output timing
SH3B_7_12
– 13 –
CXA3562R
4.Timing generator (TG) block
The internal timing generator operates by one pair of differential clock inputs (MCLK, MCLKX) and a horizontal sync
signal input (SHST), and generates the timing pulses needed by the demultiplexer block, dot inversion control pulse
and output deviation cancel circuit. The various operating modes can be designated by the pin settings.
The SHST and FRP inputs should satisfy the relationship shown in the figure below with the MCLK and
MCLKX input period as 1clk.
SHST
FRP
30clk or more
1µs or more
The CXA3562R can select various operating modes according to the timing generator block settings. These
settings are described below.
• SL_DAT (Pin 72)
Digital input selection. Single input from only the A port is selected when set to high level, and parallel input
from both the A and B ports is selected when set to low level. When inputting a 2-parallel processed digital
video signal in parallel input mode, input the earlier time series data to the A port and the later time series data
to the B port. Input a master clock having the same period as the input data rate to MCLK in both modes.
This pin is low level (2-parallel input mode) when left open.
• DIRC (Pin 71), SL_SCN (Pin 73)
Scan direction settings. Output is ascending order when DIRC is set to high level, and inverted to descending
order (SH_OUT1 to SH_OUT12) when set to low level. At this time if SL_SCN is set to high, the A and B port
data can be switched by switching DIRC between high and low. When SL_SCN is set to low, the A port data is
output from the odd-numbered SH_OUT and the B port data is output from the even-numbered SH_OUT
regardless of the DIRC setting.
Set SL_SCN to high when SL_DAT is high.
D_A[9:0]
D_B[9:0]
A3
B3
A4
B4
A5
B5
A6
B6
A1
B1
A2
B2
DIRC: L
DIRC: H
SH_OUT1: A6, SH_OUT2: B6,
SH_OUT3: A5, SH_OUT4: B5,
SH_OUT5: A4, SH_OUT6: B4,
SH_OUT7: A3, SH_OUT8: B3,
SH_OUT9: A2, SH_OUT10: B2,
SH_OUT11: A1, SH_OUT12: B1
SH_OUT1: A1, SH_OUT2: B1,
SH_OUT3: A2, SH_OUT4: B2,
SH_OUT5: A3, SH_OUT6: B3,
SH_OUT7: A4, SH_OUT8: B4,
SH_OUT9: A5, SH_OUT10: B5,
SH_OUT11: A6, SH_OUT12: B6
SL_SCN: L
SL_SCN: H
SH_OUT1: B6, SH_OUT2: A6,
SH_OUT3: B5, SH_OUT4: A5,
SH_OUT5: B4, SH_OUT6: A4,
SH_OUT7: B3, SH_OUT8: A3,
SH_OUT9: B2, SH_OUT10: A2,
SH_OUT11: B1, SH_OUT12: A1
SH_OUT1: A1, SH_OUT2: B1,
SH_OUT3: A2, SH_OUT4: B2,
SH_OUT5: A3, SH_OUT6: B3,
SH_OUT7: A4, SH_OUT8: B4,
SH_OUT9: A5, SH_OUT10: B5,
SH_OUT11: A6, SH_OUT12: B6
– 14 –
CXA3562R
• SL_INV (Pin 74)
Dot inversion and line inversion selection. When set to low level, all SH_OUT channels are output at the same
polarity as shown by the solid line in the figure below. When set to high level, the odd-numbered and even-
numbered SH_OUT outputs are output at inverse polarities. At this time the odd-numbered outputs are
inverted when the FRP pulse is high, and non-inverted when the FRP pulse is low. Conversely, the even-
numbered outputs are inverted when the FRP pulse is low, and non-inverted when the FRP pulse is high.
SH_OUT
GND
FRP
• F/H_CNT (Pin 70)
SH_OUT output timing phase setting. When set to low level, all SH_OUT outputs are output at the same
timing. When set to high level, SH_OUT1 to SH_OUT6 and SH_OUT7 to SH_OUT12 are output at phases
offset by 1/2 clock period from each other.
SH_OUT7 to 12
SH_OUT7 to 12
SH_OUT1 to 6
SH_OUT1 to 6
GND
GND
F/H_CNT: L
F/H_CNT: H
• Output phase setting
The phase of each SH_OUT output can be adjusted in MCLK period units when SL_DAT is high or in 1/2 MCLK
period units when SL_DAT is low by POSCTR[3:0] (Pins 6 to 9). The phase can be set in 16 ways by 4-bit digital
input. The output phase shifts backward by the above unit each time this setting is increased by one bit.
– 15 –
CXA3562R
5. Calibration level generator block
The CXA3562R generates the offset cancel circuit reference with a calibration level generator in order to
minimize the deviation between channels at the center level.
The 200h output level is generated at both the AC output high and low sides, and these levels are DC output
from CAL_OH and CAL_OL, respectively. At the same time, 200h data is forcibly inserted into the video signal
while the video blanking period SHST pulse is low level, and feedback is applied so that the output levels of all
SH_OUT channels conform to CAL_IH and CAL_IL during this period.
Video signal replacement period
SHST
FRP
200ns
CAL_PLS
(internal pulse)
Offset cancel operation
000h
200h
Signal center
SH_OUT
Delayed by sample-and-hold
000h
200h
6. SID signal generator block
This circuit generates the precharge signal waveform used by the LCD panel.
The voltage input from PRG_LV (Pin 58) and SID_LV (Pin 59) is switched by the PRG pulse (Pin 60). The
PRG_LV voltage is selected when PRG is high, and the SID_LV voltage is selected when PRG is low. This
signal is then further amplified by a factor of two times and folded by the FRP pulse. The folded center voltage
is the SH_OUT center voltage (voltage set by the SIG.C pin). SID_OUT (Pin 57) is inverted when FRP is high,
and non-inverted when FRP is low. Conversely, SID_OUTX (Pin 56) is inverted when FRP is low, and non-
inverted when FRP is high.
SID_OUT and SID_OUTX cannot directly drive the precharge signal input of the LCD panel, so they should be
connected via a buffer having sufficient current supply capability.
7. VCOM potential generator block
This block sets the DC common potential for the LCD panel.
VCOM_OFST (Pin 54) sets the deviation relative to the SH_OUT center potential, which is set by SIG.C.
– 16 –
CXA3562R
Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, Ta = 25°C)
VREF_I voltage vs. SH_OUT voltage white-black amplitude
Input data vs. SH_OUT voltage
4.8
14
12
10
8
4.7
<Measurement conditions>
SIG.C = 3.75V
SIG_OFST = 3.6V
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
FRP = High
6
FRP = Low
4
<Measurement conditions>
SIG.C = 3.75V
SIG_OFST = 3.6V
2
0
000h
2.7
2.8
2.9
3.0
3.1
3.2
3.3
100h
200h
300h
3FFh
VREF_I voltage [V]
Input data (10 bits)
SIG.C voltage vs. SH_OUT center voltage
SIG_OFST voltage vs. SH_OUT voltage
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
12
11
10
9
<Measurement conditions>
SIG_OFST = 3.6V
FRP = High
8
7
6
<Measurement conditions>
5
SIG.C = 3.75V
DATA = 200h
FRP = Low
4
3
2.5
3.0
3.5
4.0
4.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SIG_OFST voltage [V]
SIG.C voltage [V]
VCOM_OFST voltage vs. VCOM_OUT voltage
6.00
<Measurement conditions>
SIG.C = 3.75V
5.95
5.90
5.85
5.80
5.75
5.70
2.8
2.9
3.0
3.1
3.2
VCOM_OFST voltage [V]
– 17 –
CXA3562R
SID_LV voltage vs. SID_OUT voltage
PRG_LV voltage vs. SID_OUT voltage
16
14
12
10
8
16
14
12
10
8
<Measurement conditions>
SIG.C = 3.75V
<Measurement conditions>
SIG.C = 3.75V
FRP = High
FRP = High
6
6
FRP = Low
FRP = Low
4
4
2
2
0
0
0
1
2
3
4
0
1
2
3
4
SID_LV voltage [V]
PRG_LV voltage [V]
– 18 –
CXA3562R
Application Circuit 1 (to XGA Panel)
VDD
20kΩ
VDD
0.1µF
Buffer
20kΩ
1
Psig
DSD
CXD3511Q
VDD
10Ω
PRG 161
VDD
20kΩ
10Ω
RGT
136
0.1µF
47µF
VDD
VDD
1Ω
1Ω
1µF
31
3
COM
Vsig1
0.1µF
DD
VDD
V
10kΩ
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PVCC
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
D_A9
D_A8
D_A7
D_A6
D_A5
D_A4
D_A3
D_A2
D_A1
D_A0
GND
122
121
76
50
R1OUT9
R1OUT8
1Ω
1Ω
1Ω
1Ω
1Ω
SH_OUT2
NC
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
4
5
6
Vsig2
Vsig3
Vsig4
Vsig5
Vsig6
R1OUT7 120
R1OUT6 119
R1OUT5 118
R1OUT4 117
R1OUT3 116
R1OUT2 113
R1OUT1 112
R1OUT0 111
SH_OUT3
NC
SH_OUT4
NC
SH_OUT5
NC
7
8
SH_OUT6
GND
GND
GND
LCD Panel
LCX023
GND
PGND
GND
CXA3562R
GND
GND
GND
1Ω
1Ω
1Ω
1Ω
1Ω
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
SH_OUT7
NC
9
Vsig7
SH_OUT8
NC
10 Vsig8
11 Vsig9
SH_OUT9
NC
SH_OUT10
NC
12
Vsig10
SH_OUT11
13 Vsig11
PVCC
VCC
0.1µF
47µF
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
10kΩ
1Ω
14
Vsig12
VDD
OPEN
VDD
1µF
1µF
20kΩ
10Ω
10Ω
0.1µF
0.1µF
157
159
FRP
SHST
V
DD
V
CC
VDD
CXA3266Q
20kΩ
15.5V
5V
82Ω
82Ω
CLKH 32
31
CLKL
130Ω
130Ω
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 19 –
CXA3562R
Application Circuit 2 (to SXGA Panel)
VDD
20kΩ
VDD
0.1µF
Buffer
20kΩ
1
2
Psig
DSD
CXD3511Q
VDD
10Ω
PRG 161
COMR
VDD
20kΩ
10Ω
RGT
136
0.1µF
21 COML
47µF
VDD
VDD
1Ω
1Ω
1µF
32
3
COM
Vsig1
0.1µF
DD
V
10kΩ
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D_A9
D_A8
D_A7
D_A6
D_A5
D_A4
D_A3
D_A2
D_A1
D_A0
GND
PVCC
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
122
121
76
50
R1OUT9
R1OUT8
1Ω
1Ω
1Ω
1Ω
1Ω
SH_OUT2
NC
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
4
5
6
Vsig2
Vsig3
Vsig4
Vsig5
Vsig6
R1OUT7 120
R1OUT6 119
R1OUT5 118
R1OUT4 117
R1OUT3 116
R1OUT2 113
R1OUT1 112
R1OUT0 111
SH_OUT3
NC
SH_OUT4
NC
SH_OUT5
NC
7
8
SH_OUT6
GND
GND
GND
LCD Panel
LCX028
GND
PGND
GND
CXA3562R
GND
GND
GND
1Ω
1Ω
1Ω
1Ω
1Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
SH_OUT7
NC
R2OUT9
R2OUT8
110
109
9
Vsig7
SH_OUT8
NC
R2OUT7 108
R2OUT6 107
R2OUT5 106
10 Vsig8
11 Vsig9
SH_OUT9
NC
R2OUT4
R2OUT3
105
104
SH_OUT10
NC
12
Vsig10
R2OUT2 103
SH_OUT11
R2OUT1
R2OUT0
99
98
13 Vsig11
PVCC
VCC
0.1µF
47µF
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
10kΩ
1Ω
14
Vsig12
VDD
OPEN
VDD
1µF
1µF
20kΩ
10Ω
10Ω
0.1µF
0.1µF
157
159
FRP
SHST
V
DD
V
CC
VDD
CXA3266Q
20kΩ
15.5V
5V
82Ω
82Ω
30
29
CLK/2H
CLK/2L
130Ω
130Ω
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 20 –
CXA3562R
Application Circuit 3 (to WXGA Panel)
Another
CXA3562R
56 57
Buffer
2
3
4
Psig1
Psig2
Psig3
Psig4
5
6
DSD
CXD3511Q
VDD
V
DD
COMR
V
DD
20kΩ
10Ω
RGT
136
20kΩ
47µF
0.1µF
COML
COM
25
34
V
DD
VDD
1Ω
1Ω
1µF
0.1µF
DD
V
DD
VDD
V
Vsig-a1
7
10kΩ
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D_A9
D_A8
D_A7
D_A6
D_A5
D_A4
D_A3
D_A2
D_A1
D_A0
GND
PVCC
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
122
121
76
50
R1OUT9
R1OUT8
1Ω
1Ω
1Ω
1Ω
1Ω
SH_OUT2
NC
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
8
9
Vsig-a2
Vsig-a3
R1OUT7 120
R1OUT6 119
R1OUT5 118
R1OUT4 117
R1OUT3 116
R1OUT2 113
R1OUT1 112
R1OUT0 111
SH_OUT3
NC
SH_OUT4
NC
10 Vsig-a4
11 Vsig-a5
12 Vsig-a6
SH_OUT5
NC
SH_OUT6
GND
GND
GND
LCD Panel
LCX037
GND
PGND
GND
CXA3562R
GND
GND
GND
1Ω
1Ω
1Ω
1Ω
1Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
SH_OUT7
NC
R2OUT9
R2OUT8
110
109
Vsig-b1
13
SH_OUT8
NC
R2OUT7 108
R2OUT6 107
R2OUT5 106
14 Vsig-b2
15 Vsig-b3
16 Vsig-b4
SH_OUT9
NC
R2OUT4
R2OUT3
105
104
SH_OUT10
NC
R2OUT2 103
R2OUT1 99
SH_OUT11
Vsig-b5
17
PVCC
98
R2OUT0
VCC
0.1µF
47µF
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
10kΩ
1Ω
18 Vsig-b6
VDD
OPEN
VDD
1µF
1µF
20kΩ
10Ω
10Ω
0.1µF
0.1µF
157
159
FRP
SHST
V
DD
V
CC
VDD
CXA3266Q
20kΩ
15.5V
5V
82Ω
82Ω
30
29
CLK/2H
CLK/2L
130Ω
130Ω
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 21 –
CXA3562R
V
DD
Application Circuit 4 (to UXGA Panel)
0.1µF
20kΩ
V
DD
0.1µF
DSD
20kΩ
CXD3511Q
10Ω
PRG 161
Buffer
0.47µF
V
DD
1
2
Psig1
Psig2
10Ω
RGT
136
47µF
V
DD
VDD
V
DD
0.1µF
DD
V
DD
V
1Ω
11 Vsig1
10kΩ
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
D_A9
D_A8
D_A7
D_A6
D_A5
D_A4
D_A3
D_A2
D_A1
D_A0
GND
PVCC
R1OUT9 122
R1OUT8 121
R1OUT7 120
R1OUT6 119
R1OUT5 118
R1OUT4 117
R1OUT3 116
R1OUT2 113
R1OUT1 112
R1OUT0 111
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1Ω
1Ω
1Ω
1Ω
1Ω
SH_OUT2
NC
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
13
15
Vsig3
Vsig5
SH_OUT3
NC
SH_OUT4
NC
17 Vsig7
SH_OUT5
NC
19
Vsig9
SH_OUT6
GND
21 Vsig11
GND
GND
LCD Panel
LCX036
GND
PGND
GND
CXA3562R
GND
GND
GND
1Ω
1Ω
1Ω
1Ω
1Ω
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
SH_OUT7
NC
23
Vsig13
SH_OUT8
NC
25 Vsig15
SH_OUT9
NC
27
29
Vsig17
Vsig19
SH_OUT10
NC
SH_OUT11
31 Vsig21
PVCC
V
CC
0.1µF
47µF
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
10kΩ
1Ω
33
Vsig23
OPEN
V
DD
0.47µF
0.47µF
V
DD
10Ω
10Ω
157
159
FRP
SHST
20kΩ
Buffer
0.1µF
4
3
Psig4
Psig3
82Ω
82Ω
V
DD
V
DD
20kΩ
130Ω
130Ω
0.1µF
V
DD
0.1µF
20kΩ
47µF
56 COM1
57 COM2
0.47µF
V
DD
V
DD
1Ω
1Ω
0.1µF
DD
V
DD
V
12 VSig2
10kΩ
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
10Ω
D_A9
D_A8
D_A7
D_A6
D_A5
D_A4
D_A3
D_A2
D_A1
D_A0
GND
PVCC
R2OUT9 110
R2OUT8 109
R2OUT7 108
R2OUT6 107
R2OUT5 106
R2OUT4 105
R2OUT3 104
R2OUT2 103
R2OUT1 99
R2OUT0 98
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1Ω
1Ω
1Ω
1Ω
1Ω
SH_OUT2
NC
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
10Ω
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
14
Sig4
SH_OUT3
NC
16 Sig6
18 Sig8
20 Sig10
22 Sig12
SH_OUT4
NC
SH_OUT5
NC
SH_OUT6
GND
GND
GND
GND
PGND
GND
CXA3562R
GND
GND
GND
1Ω
1Ω
1Ω
1Ω
1Ω
D_B9
D_B8
D_B7
D_B6
D_B5
D_B4
D_B3
D_B2
D_B1
D_B0
SH_OUT7
NC
24 Sig14
SH_OUT8
NC
26
28
30
Sig16
Sig18
Sig20
SH_OUT9
NC
SH_OUT10
NC
SH_OUT11
32 Sig22
PVCC
V
CC
0.1µF
47µF
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
10Ω
XFRP 158
10kΩ
1Ω
34
Sig24
V
CC
VDD
CXA3266Q
OPEN
0.47µF
0.47µF
V
DD
V
DD
15.5V
5V
CLK/2H
CLK/2L
30
29
20kΩ
0.1µF
0.1µF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 22 –
CXA3562R
Notes on Operation
The CXA3562R has high power consumption, so be sure to take the following radiation measures.
• Use four-layer substrate.
• GND lines connected between Pins 11 to 15, Pins 36 to 40, Pins 61 to 65 and Pins 86 to 90 should be as
thick as possible.
– 23 –
CXA3562R
Package Outline
Unit: mm
100PIN LQFP (PLASTIC)
16.0 ± 0.2
14.0 ± 0.1
75
51
76
50
B
A
26
M
100
(0.22)
1
25
0.13
0.5
b
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
b = 0.18 ± 0.03
DETAIL B : PALLADIUM
0˚ to 10˚
NOTE: Dimension " " does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
PALLADIUM PLATING
LQFP-100P-L01
LEAD TREATMENT
LEAD MATERIAL
SONY CODE
EIAJ CODE
P-LQFP100-14x14-0.5
COPPER ALLOY
0.7g
JEDEC CODE
PACKAGE MASS
Sony Corporation
– 24 –
相关型号：
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