CXA3572R [SONY]
Driver/Timing Generator for Color LCD Panels; 驱动器/时序发生器彩色LCD面板
| 型号： | CXA3572R |
| 厂家： | 
SONY CORPORATION |
| 描述： | Driver/Timing Generator for Color LCD Panels |
| 文件： | 总40页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA3572R
Driver/Timing Generator for Color LCD Panels
Description
48 pin LQFP (Plastic)
The CXA3572R is an IC designed to drive the color
LCD panel ACX306/312.
This IC greatly reduces the number of peripheral
circuits and parts by incorporating a RGB driver and
timing generator for video signals and a VCO onto a
single chip. This chip has a built-in serial interface
circuit and electronic attenuators which allow various
settings to be performed by microcomputer control,
etc.
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VCC1
VCC2
VDD
5.5
15
V
V
V
Features
• Color LCD panel ACX306/312 driver
• Supports NTSC and PAL systems
• Supports Y/color difference and RGB inputs
• Supports OSD input
4.6
• Analog input pin voltage
VINA1 (Pins 18, 19, 20, 22, 23, 24 and 25)
GND – 0.3 to VCC1 + 0.3 V
GND – 0.3 to VCC2 + 0.3 V
• Power saving function (clock stopped)
• Various setting control using a serial interface
circuit (asynchronous type)
VINA2 (Pin 16)
• Digital input pin voltage
VIND (Pins 34 and 35) VSS – 0.3 to +5.5
V
• Electronic attenuators (D/A converter)
• VCO (no external oscillator circuit)
• LPF (fc variable)
• Common input pin voltage
VINAD (Pins 31, 32 and 33)
GND, VSS – 0.3 to +5.5 V
• Operating temperature Topr –15 to +75 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation (Ta ≤ 25°C)
600
• COMMON and PSIG output circuits
• Sharpness function
• 2-point γ correction circuit
• R, G, B signal delay time adjustment circuit
• Sync separation circuit
PD
mW
• D/A output pin (0 to 3V, 8 level output)
• Output polarity inversion circuit
• Supports AC drive for LCD panel during no signal
Operating Conditions
• Supply voltage VCC1 – GND1 2.7 to 3.6
V
V
V
VCC2 – GND2 11.0 to 14.0
VDD – VSS
2.7 to 3.6
Applications
Compact LCD monitors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E00Y05A11-PS
CXA3572R
Block Diagram
+12V
+3V
24 23 22
21
PICTURE Gain PICTURE f0
20
19
18
17
16
15
14 13
MODE
PICTURE
PSIG-
BRIGHT
ATT
ATT
DL
DL
MATRIX
25
SYNC IN
HUE
COLOR
ATT
DA
26
27
DA
DA OUT
REF
HUE COLOR
G OUT
12
11
REF
R, G, B
LPF
TRAP
SUB-
CONTRAST
USER-
BRIGHT
SUB-
BRIGHT
GAMMA1
GAMMA2
G DC DET
CONTRAST
CONTRAST
OSD
BLIM
COM
28
FILTER
10 R OUT
USER-
BRIGHT
9
8
R DC DET
SYNC SEL
SYNC SEP
S/H
B OUT
PHASE
COMPARATOR
CLOCK
GENERATOR
29
30
RPD
BLIM
7
B DC DET
GND1
FRP
Analog block 3V
31
32
SEN
SCK
COM
6
5
COM
Analog block 12V
GND2
XSTBY2
33
SDAT
Digital block 3V
4
3
2
1
TEST
VST
VCK
EN
SERIAL I/F
H. FILTER
34
35
36
VD
XCLR
POF
TIMING GENERATOR
PLL
COUNTER
0V
48
0V
41
+3V
45
+3V
37
38
39
40
42
43
44
46
47
– 2 –
CXA3572R
Pin Description
Pin
Input pin for
open status
Symbol
No.
I/O
Description
1
2
3
4
5
6
7
8
9
EN
O
O
O
—
—
O
O
O
O
O
O
O
—
O
O
I
EN pulse output
VCK
V clock pulse output
V start pulse output
Test (Leave this pin open.)
Analog 12.0V GND
VST
TEST
GND2
COM
Common pad voltage output for LCD panel
B signal DC voltage feedback circuit capacitor connection
B signal output
B DC DET
B OUT
R DC DET
R signal DC voltage feedback circuit capacitor connection
R signal output
10 R OUT
11 G DC DET
12 G OUT
13 VCC2
G signal DC voltage feedback circuit capacitor connection
G signal output
Analog 12.0V power supply
14 PSIG OUT
15 PSIG DC DET
16 SIG.C
17 NC
PSIG output
PSIG signal DC voltage feedback circuit capacitor connection
R, G, B and PSIG output DC voltage adjustment
—
I
18 OSD B
19 OSD R
20 OSD G
21 VCC1
OSD B input
I
OSD R input
I
OSD G input
—
I
Analog 3.0V power supply
G/Y signal input
22 G/Y
23 R/R-Y
24 B/B-Y
25 SYNC IN
26 DA OUT
27 REF
I
R/R-Y signal input
I
B/B-Y signal input
I
Sync separation circuit input/sync signal input
DAC output
O
O
O
O
—
I
Level shifter circuit REF voltage output for LCD panel
Internal filter circuit f0 adjusting resistor connection
Phase comparator output
Analog 3.0V GND
28 FILTER
29 RPD
30 GND1
31 SEN
Serial load input
32 SCK
I
Serial clock input
33 SDAT
34 VD
I
Serial data input
L
I
Vertical sync signal input
Power-on reset capacitor connection (timing output block)
35 XCLR
I
LCD panel power supply on/off
(Leave this pin open when not using this function.)
36 POF
O
– 3 –
CXA3572R
Pin
No.
Input pin for
open status
Symbol
I/O
Description
37 VDD
—
O
O
O
—
O
O
O
—
O
O
—
Digital 3.0V power supply
HDO pulse output
38 HDO
39 VDO
40 RGT
41 VSS
VDO pulse output
Right/left inversion switching signal output
Digital 3.0V GND
42 HCK1
43 HCK2
44 HST
45 VDD
H clock pulse 1 output
H clock pulse 2 output
H start pulse output
Digital 3.0V power supply
WIDE pulse output
46 WIDE
47 DWN
48 VSS
Up/down inversion switching signal output
Digital 3.0V GND
– 4 –
CXA3572R
Analog Block Pin Description
Pin
voltage
Pin
No.
Symbol
GND2
Equivalent circuit
Description
Analog 12.0V GND.
5
—
Vcc2
6
125k
5k
COMMON voltage output.
The output voltage is controlled by serial
communication.
6
COM
—
100k
GND2
Vcc2
7
9
B DC DET
R DC DET
Smoothing capacitor connection for the
feedback circuit of R, G, B and PSIG
output signal DC level control.
7
9
4K
5k
3.0V
11 G DC DET
15
10k
11
PSIG DC DET
Connect a low-leakage capacitor.
15
GND2
Vcc2
8
B OUT
R OUT
G OUT
PSIG OUT
R, G, B and PSIG signal outputs.
The DC level is controlled to match the
SIG.C pin voltage.
8
10
10
10
500
5k
10
12
14
—
12
Low output in power saving mode.
100k
14
GND2
13
16
17
VCC2
SIG.C
NC
12.0V
Analog 12.0V power supply.
Vcc2
16
R, G, B and PSIG output DC voltage
setting.
Connect a 0.01µF capacitor between
this pin and GND1.
When using a SIG.C of other than
Vcc2/2, input the SIG.C voltage from an
external source.
200k
200k
VCC/2
10p
GND2
—
No connection.
– 5 –
CXA3572R
Pin
No.
Pin
voltage
Symbol
Equivalent circuit
Description
OSD pulse inputs.
Vcc1
When one of these input pins exceeds
the Vth1 level, all of the outputs go to
black limiter level; when an input pin
exceeds the Vth2 level, only the
corresponding output goes to white
limiter level.
Vth1 =
VCC1 ×
1/3
18
19
20
18
19
20
OSD B
OSD R
OSD G
20k
Vth2 =
VCC1 ×
2/3
Connect these pins to GND when not
used.
GND1
21
VCC1
3.0V
Analog 3.0V power supply.
G/Y:
1.8V
Vcc1
In Y/color difference input mode, input
the Y signal to Pin 22, the R-Y signal to
Pin 23 and the B-Y signal to Pin 24.
In RGB input mode, input the G signal
to Pin 22, the R signal to Pin 23 and the
B signal to Pin 24.
R/R-Y,
B/B-Y,
RGB:
1.8V
22
23
24
22
23
24
G/Y
R/R-Y
B/B-Y
1k
Y/color
difference:
2.0V
Pedestal clamp these pins with external
coupling capacitors.
GND1
Vcc1
10k
1k
Sync separation circuit input, or composite
sync/horizontal sync signal input.
During input to the sync separation
circuit, input via a capacitor.
25
26
27
SYNC IN
DA OUT
REF
0.9V
25
GND1
Vcc1
DA output.
80k
15p
Outputs the serial data converted to DC
voltage. The current driving capacity is
±1.0mA (max.).
26
—
GND1
Vcc1
25k
REF output.
The current driving capacity (sink) is
1.6mA (max.).
27
VCC1/2
100k
GND1
– 6 –
CXA3572R
Pin
No.
Pin
voltage
Symbol
Equivalent circuit
Description
Connect a resistor between this pin and
GND1 to control the internal LPF and
trap frequencies.
Vcc1
Connect a 43kΩ resistor (tolerance ±2%,
temperature characteristics ±200ppm or
less).
This pin is easily affected by external
noise, so make the connection between
the pin and external resistor, and
between the GND side of the external
resistor and the GND1 pin as close as
possible.
28
FILTER
1.2V
500
28
GND1
Vcc1
1k
100k
29
30
RPD
1.8V
Phase comparator output.
Analog 3.0V GND.
29
GND1
GND1
—
Vcc1
1
31
32
33
20k
31
32
33
SEN
SCK
SDAT
Serial clock, serial load and serial data
inputs for serial communication.
—
GND1
Vss
– 7 –
CXA3572R
Digital Block Pin Description
Pin
No.
Pin
voltage
Symbol
EN
Equivalent circuit
Description
1
2
VCK
3
VST
36
38
39
40
42
43
44
46
47
POF
HDO
VDO
RGT
HCK1
HCK2
HST
1
2
3
36 40 44
38 42 46
39 43 47
—
Digital block outputs.
Vss
WIDE
DWN
35 32
31 33
35
31
32
33
XCLR
SEN
SCK
Digital block system reset, and serial
clock, serial load and serial data inputs
for serial communication.
—
—
SDAT
Vss
34
34
VD
Vertical sync signal input.
Vss
37
45
VDD
—
—
—
Digital 3.0V power supply.
Digital 3.0V GND.
41
48
VSS
Test.
4
TEST
Leave this pin open.
– 8 –
CXA3572R
Setting Conditions for Measuring Electrical Characteristics
Use the Electrical Characteristics Measurement Circuit on page 21 when measuring electrical characteristics.
For measurement, the digital block must be initialized and power saving must be canceled by performing
Settings 1, 2 and 3 below. In addition, the serial data must be set to the initial settings shown in the table below.
Setting 1. System reset
After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low.
The serial bus is set to the default values.
VDD
XCLR (Pin 35)
T
R
TR > 10µs
System reset
Setting 2. Horizontal AFC adjustment
In the condition without sync input, adjust so that the HDO pulse output frequency is
NTSC: 15.734 ± 0.1kHz and PAL: 15.625 ± 0.1kHz.
Setting 3. Canceling power saving mode
The power-on default is power saving mode, so clear (set all “1”) serial data PS0 and SYNC GEN.
– 9 –
CXA3572R
Serial data initial settings
MSB ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
LSB MSB
DATA
LSB
D0
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
USER-BRIGHT
SUB-BRIGHT R
SUB-BRIGHT B
CONTRAST
SUB-CONTRAST R
SUB-CONTRAST B
γ-1
(10000000/LSB)
(1000000/LSB)
(1000000/LSB)
(10000000/LSB)
(1000000/LSB)
(1000000/LSB)
(0000000/LSB)
(0000000/LSB)
0
0
0
0
0
0
γ-2
PSIGSW
(0)
0
0
0
0
1
0
0
0
PSIG-BRIGHT
(1000000/LSB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
COM-DC
COLOR
(1000000/LSB)
(1000000/LSB)
(1000000/LSB)
(10000000/LSB)
(100000/LSB)
HUE
VCO Fine
BLACK-LIMITER
0
0
PICTURE-GAIN (00000/LSB)
PICTURE-F0 (000/LSB)
LPFSW
TRAP
(0)
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
1
0
0
1
0
1
LPF (000/LSB)
DA (000/LSB)
(0)
0
INPUT SYNC MODE
SEL (0) SEL (1)
0
0
VCO Coarse (000/LSB)
(0)
SLPOF SYNC
(0) GEN (1)
PS0
(1)
TEST1
(0)
TEST2 PONF
(1) (1)
0
SLWD SLNTPL
(0) (0)
SLSYP
(1)
SLDWN SLRGT
SLEXVD
(1)
TEST3
(0, 0)
(0)
(0)
SLCLP0 SLVDO SLHDO
(0) (0) (0)
SYST
(0)
SLFR SL4096 SLCLP1
SLFL
(0)
(0)
(0) (0)
SLMBK
(0)
0
H POSITION (100000/LSB)
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
S/H POSITION (000/LSB)
SB POSITION (100/LSB)
HDO POSITION (00000/LSB)
V POSITION (01000/LSB)
TEST4 (00000000/LSB)
Note: If there is the possibility that data may be set at other than the above-noted addresses, set these data to “0”.
– 10 –
CXA3572R
Electrical Characteristics — DC Characteristics
Analog Block
(Ta = 25°C, VCC1 = VDD = 3.0V, VCC2 = 12.0V, see page 10 for the DAC)
Item
Symbol
I1
Measurement conditions
Min.
16
Typ.
34
Max.
50
Unit
Current consumption 1
(Y/color difference input)
Measure the inflow current
to Pin 21.
Current consumption 2
(Y/color difference input)
Measure the inflow current
to Pin 13.
1.0
12
1.0
—
3.4
28
3.4
7
10
42
10
11
1.0
27
1.0
I2
Current consumption 1
(RGB input)
Measure the inflow current
to Pin 21.
IRGB1
IRGB2
IPS01
IPS02
ISG1
ISG2
Current consumption 2
(RGB input)
Measure the inflow current
to Pin 13.
mA
Current consumption 1
(PS0 = 0)
Measure the inflow current
to Pin 21.
Current consumption 2
(PS0 = 0)
Measure the inflow current
to Pin 13.
—
0.3
14
0.3
Current consumption 1
(SYNC GEN = 0)
Measure the inflow current
to Pin 21.
—
Current consumption 2
(SYNC GEN = 0)
Measure the inflow current
to Pin 13.
—
3.0
3.0
3.0
3.0
6.0
1.8
B DC DET pin voltage
R DC DET pin voltage
G DC DET pin voltage
PSIG DC DET pin voltage
SIG.C pin voltage
V7
V9
V11
V15
V16
V22
G/Y pin voltage
During Y/color difference
input
2.0
1.8
2.0
R/R-Y pin voltage 1
R/R-Y pin voltage 2
B/B-Y pin voltage 1
V23
V23
V24
During RGB input
V
During Y/color difference
input
1.8
1.1
B/B-Y pin voltage 2
SYNC IN pin voltage
V24
V25
During RGB input
During no input
REF pin voltage
(power saving mode)
0.2
1.2
V27
V28
FILTER pin voltage
GND
5.0
VCC1
OSD R, G, B input voltage
SIG. C input voltage
6.5
VSIG.C
– 11 –
CXA3572R
Item
Symbol
Measurement conditions
Min.
Typ.
0.35
Max.
0.4
Unit
1
Y
SYNC
(Y on SYNC)
Y/Color difference mode
Y, R-Y, B-Y signal input
level 1
0.15
0.2
2
INPUT SEL = 0
(–6dB Attenuate OFF)
0.245
0.311
R-Y
B-Y
1
0.7
0.3
Y
SYNC
(Y on SYNC)
Y/Color difference mode
Y, R-Y, B-Y signal input
level 2
INPUT SEL = 1
(–6dB Attenuate ON)
2
Vp-p
0.490
0.622
0.5
R-Y
B-Y
1
0.35
0.15
R, G, B
RGB mode
R, G, B signal input
level 1
INPUT SEL = 0
(–6dB Attenuate OFF)
SYNC
(G on SYNC)
0.2
0.7
0.3
2
1
R, G, B
RGB mode
R, G, B signal input
level 2
INPUT SEL = 1
(–6dB Attenuate ON)
SYNC
(G on SYNC)
2
1
Y signal level (SYNC level is not included.)
SYNC level of Y (G) on SYNC signal.
2
– 12 –
CXA3572R
Control Signal Block (Sync signal, serial-serial signal, XCLR, digital output)
(Ta = –15 to +75°C, VCC1 = VDD = 2.7 to 3.6V)
Item
Symbol Measurement conditions Min.
Typ.
Max. Unit Applicable pins
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input current
Low level input current
High level input current
Low level input current
High level input current
Low level input current
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
VIH1
VCC1 – 0.7
VCC1
1
VIL1
0
2.0
0
0.7
V
VIH2
VDD (VCC1)
2, 3,
4
VIL2
0.7
20
| IIH1 |
| IIL1 |
| IIH2 |
| IIL2 |
| IIH3 |
| IIL3 |
VOH1
VOL1
VOH2
VOL2
VIN = VDD
1,
2
VIN = 0V
20
VIN = VDD
20
150
1.0
1.0
1.0
3
µA
(pull-down)
VIN = 0V
VIN = VDD
4
VIN = 0V
IOH = –1.2mA
IOL = 4.0mA
IOH = –0.6mA
IOL = 2.0mA
2.6
2.6
5
6
0.3
0.3
V
1
SYNC IN (Pin 25)
2
SEN (Pin 31), SCK (Pin 32), SDAT (Pin 33)
VD (Pin 34)
3
4
5
6
XCLR (Pin 35)
HCK1 (Pin 42), HCK2 (Pin 43), HST (Pin 44)
EN (Pin 1), VCK (Pin 2), VST (Pin 3), POF (Pin 36), HDO (Pin 38), VDO (Pin 39), RGT (Pin 40),
WIDE (Pin 46), DWN (Pin 47)
– 13 –
CXA3572R
Electrical Characteristics
AC Characteristics
Unless otherwise specified, Settings 1 and 2, the serial data initial settings, and the following setting conditions
are required.
Ta = 25°C, VCC1 = 3.0V, VCC2 = 12V, GND1 = GND2 = 0V, VSS = 0V, SW8/10/12/14 = OFF, no video input,
SG1 input to TP25
Note: Serial data values in the table are HEX notation.
Serial data
setting (HEX)
Item
Symbol
Measurement conditions
Min.
19
Typ.
22
Max. Unit
Maximum gain
between input and GMAX
output
Input SG2 (0.2Vp-p) to TP22 and
measure the output amplitude at
TP12.
CONT FFh
MODE 00h
dB
25
Minimum gain
between input and GMIN
output
Input SG2 (0.2Vp-p) to TP22 and
measure the output amplitude at
TP12.
CONT 00h
MODE 00h
–6
–3
dB
0
Input SG2 (0.2Vp-p) to TP22 and
measure the inverted output
amplitude Vinv and the non-inverted
output amplitude Vninv at TP12.
∆Ginv = 20 log (Vninv/Vinv)
Inverted and
non-inverted gain
difference
∆GINV
CONT 2Fh
—
—
dB
±0.4
Input SG2 (0.2Vp-p) to TP22 (TP23,
TP24), measure the non-inverted
output amplitude at TP8, TP10 and
TP12, and obtain the maximum and
minimum difference between these
values.
Gain difference
between R, G and ∆GRGB
B
MODE 00h
CONT 2Fh
—
—
dB
dB
0.6
Set CONT = 26h, input SG2 (0.2Vp-p)
to TP22, and assume the non-inverted
output amplitude at TP8 and TP10
when SUB-CONT R, B = 40h, 00h
and 7Fh as V1, V2 and V3, respectively.
∆Gsc1 = 20 log (V3/V1)
SUB-CONT
00h
∆GSC1
–1.0
–4
–2.0
Sub-contrast
variable amount
SUB-CONT
7Fh
∆GSC2
4.0
1.0
2.0
∆Gsc2 = 20 log (V2/V1)
Set U-BRT = 1Ah and measure the
non-inverted level at TP8 and TP10
relative to the non-inverted black
level at TP12 when SUB-BRT R, B =
7Fh and 00h.
SUB-BRT
R, B 00h
–0.9
–2.0 –1.4
∆VSB1
Sub-bright variable
amount
V
SUB-BRT
R, B 7Fh
∆VSB2
2.0
0.9
1.4
R, G, B, PSIG and
COM output
voltage in power
saving mode
Measure the R, G, B, PSIG and
COM output voltages in power
saving mode.
100
VPSO
—
—
mV
Set U-BRT = 00h, measure the
non-inverted black limit level at TP12
when BLK-LIM = 00h and 3Fh, and
assume the difference from the
output DC voltage as VBL1 and VBL2,
respectively.
BLK-LIM
00h
3.0
—
2.5
5.0
VBL1
Black limiter
variable amount
V
BLK-LIM
3Fh
—
4.5
VBL2
– 14 –
CXA3572R
Serial data
setting (HEX)
Item
Symbol
VWL
Measurement conditions
Min.
0.3
Typ.
0.6
Max. Unit
Set CONT = FFh, input SG2 (0.2Vp-p)
to TP22, measure the non-inverted
white limit level, and obtain the
White limiter
variable amount
1.0
V
difference from the output DC voltage.
Measure the non-inverted black level
at TP8, TP10 and TP12, and obtain
the maximum and minimum
Black level
difference between ∆VB
R, G and B
—
5.8
—
—
6.0
—
300 mV
difference between these values.
Measure the output DC level
(average voltage) at TP8, TP10,
TP12 and TP14.
RGB and PSIG
Vc
6.2
V
output DC voltage
Measure the output average voltage
difference at TP8, TP10 and TP14
relative to the output average
voltage at TP12.
DC voltage
difference between ∆Vc
RGB and PSIG
300 mV
PSIG-BRT
00h
VPB1
8.5
1.0
4.5
10.0
2.0
—
Assume the PSIG output amplitude
when PSIG-BRT = 00h and 7Fh as
VPB1 and VPB2, respectively.
PSIG-BRT variable
amount
Vp-p
—
PSIG-BRT
7Fh
VPB2
U-BRT
00h
Measure the non-inverted black level
at TP12 when U-BRT = 00h and FFh
and assume the difference from the
average voltage as ∆UB1 and ∆UB2,
respectively.
∆UB1
4.8
—
USER-BRT
variable amount
V
U-BRT
FFh
1.4
2.0
2.5
∆UB2
∆VBB
Set BLK-LIM = 00h and measure
the difference between the inverted
and non-inverted black level at TP12
and TP14.
Level difference
between PSIG-BLK
and BLK-LIM
SLWD
1
—
—
300
mV
Set U-BRT = 80h, CONT = 80h,
COLOR = 40h, input SG4 (56mVp-p)
to TP23, input SG4 (100mVp-p) to
TP24, and assume the amplitude at
TP8 when HUE = 80h, 00h and 3Fh
as VB1, VB2 and VB3.
Similarly, assume the amplitude at
TP10 as VR1, VR2 and VR3.
∆HUR1 = 20 log (VR2/VR1)
∆HUR2 = 20 log (VR2/VR1)
∆HUB1 = 20 log (VB2/VB1)
1.5
—
3
—
–2
–2
HUE 00h
∆HUR1
HUE variable
amount R
–5
–5
HUE 3Fh
HUE 00h
∆HUR2
∆HUB1
dB
—
HUE variable
amount B
HUE 3Fh
∆HUB2
1.5
–2.5
9
3
0
—
2.5
—
∆HUB2 = 20 log (VB2/VB1)
Set CONT = 80h, input SG3 to
TP22, and measure the TP12
amplitude at f0 relative to the TP12
amplitude at 100kHz when PIC-G =
00h and 1Fh, respectively.
PIC-G
00h
GP1
GP2
Picture variable
amount
dB
dB
PIC-G
1Fh
12
Input SG4 (160mVp-p) to TP23 and
TP24, and assume the output
amplitude at TP8 and TP10 when
COLOR = 00h, 40h and 50h as V1,
V2 and V3, respectively.
COLOR
00h
—
—
—
–20
GC1
GC2
Color variable
amount
COLOR
50h
GC1 = 20 log (V1/V2)
GC2 = 20 log (V3/V2)
0.5
—
– 15 –
CXA3572R
Serial data
setting (HEX)
Item
Symbol
Measurement conditions
Min.
Typ.
Max. Unit
1.15
Assume the TP10 output when SG4
(0.1Vp-p) is input to TP23 as RR,
the TP8 amplitude when SG4
(0.1Vp-p) is input to TP24 as BB,
the TP10 amplitude when SG5
(0.1Vp-p) is input to TP23 as RG,
and the TP8 amplitude when SG5
(0.1Vp-p) is input to TP24 as BG.
B-Y/R-Y = RR/BB
B-Y/
R-Y
0.85 1.00
0.41 0.51
0.15 0.19
G-Y/
R-Y
CONT 80h
COLOR 40h
Matrix amplitude
ratio
0.61
0.23
G-Y/
B-Y
G-Y/R-Y = RG/RR
G-Y/B-Y = BG/BB
LPF 01h
MODE 00h
Input SG3 to TP22 and measure the
frequency which results in –3dB
relative to the TP12 amplitude at
100kHz when LPF = 01h and 07h.
fc1
fc2
—
—
1.5
5.2
—
LPF characteristics
Trap characteristics
MHz
—
LPF 07h
MODE 00h
Set U-BRT = 30h, CONT = DFh,
input SG7 (13.5MHz) to TP22, TP23
and TP24, and measure the amount
by which each output is attenuated
relative to SG7 (100kHz).
MODE 00h
TRAP 1
fo
dB
—
–27
–18
Set SW8, SW10 and SW12 = ON,
input SG3 to TP22, TP23 and TP24,
MODE 00h and measure the frequency which
results in –3dB relative to the TP8,
Frequency
response
fRGB
MHz
5.5
—
—
TP10 and TP12 amplitude at 100kHz.
Measure the REF pin output voltage
at the output current 1.5mA sink.
V
V
REF output voltage
1.3
—
1.5
—
1.7
0.3
—
VREF
VDA1
VDA2
Output current
DA 00h Measure the DA
1.0mA
DA adjustment
range
output voltage when
DA = 00h and 07h.
Output current
–1.0mA
2.6
—
DA 07h
Input SG2 (0.35mVp-p) to TP22 and
measure the amplitude at TP8, TP10
and TP12.
Assume the output amplitude when
GAMMA1 = 7Fh as V1, when
GAMMA1 = 3Fh as V2, and when
GAMMA1 = GAMMA2 = 3Fh as V3.
∆γ1 = 20 log (V1/V2)
12
12
14
14
16
16
∆γ1
∆γ2
γ gain
CONT 41h
dB
∆γ2 = 20 log (V3/V2)
Input SG2 (0.35mVp-p) to TP22 and
read the gain transition points of the
non-inverted output at TP12 when
γ1 = 00h and γ1 = 7Fh from the IRE
level of the input signal.
Vγ1MN
—
—
—
0
γ1 adjustment
variable range
CONT 41h
IRE
100
—
γ1 = 00h: Vγ1MN
γ1 = 7Fh: Vγ1MX
Vγ1MX
– 16 –
CXA3572R
Serial data
setting (HEX)
Item
Symbol
Measurement conditions
Min.
100
Typ.
Max. Unit
Input SG2 (0.35mVp-p) to TP22 and
read the gain transition points of the
non-inverted output at TP12 when
γ2 = 00h and γ2 = 7Fh from the IRE
level of the input signal.
—
—
Vγ2MN
γ2 adjustment
variable range
IRE
CONT 41h
Vγ2MX
γ2 = 00h: Vγ2MN
γ2 = 7Fh: Vγ2MX
—
—
50
Measure the COM output DC voltage
when COM-DC = 00h and 7Fh, and
measure the difference from the
COM output DC voltage when
COM-DC = 40h.
COM-DC
00h
COMMIN
COMMX
–1.3 –1.0
–0.8
COMMON control
range
V
COM-DC
7Fh
0.8
0.8
1.0
1.0
1.3
Input SG4 to TP18, TP19 and TP20,
gradually raise the high level from
0V, and assume the high level
voltage at which the output level
goes to BLK-LIM level as Vth1OSD,
and the high level voltage at which
the output goes to WHITE-LIM level
as Vth2OSD.
Vth1
OSD
1.2
OSD threshold
value
V
Vth2
OSD
1.8
2.0
2.2
SEN setup time, activated by the
rising edge of SCK. (See Fig. 3.)
ts0
ts1
th0
th1
150
150
150
150
—
—
—
—
—
ns
Data setup time
Data hold time
SDAT setup time, activated by the
rising edge of SCK. (See Fig. 3.)
—
SEN hold time, activated by the
rising edge of SCK. (See Fig. 3.)
—
ns
SDAT hold time, activated by the
rising edge of SCK. (See Fig. 3.)
—
ns
SCK pulse width. (See Fig. 3.)
SCK pulse width. (See Fig. 3.)
SEN pulse width. (See Fig. 3.)
tw1L
tw1H
tw2
210
210
1
—
—
—
—
Minimum pulse
width
ns
—
µs
—
Measure the transition time of each
output.
90pF load: HST output pin
120pF load: HCK1 and HCK2 output
pins
tTHL
tTLH
—
—
—
—
30
ns
30
(See Fig. 1.)
Output transition
time
Measure the transition time of each
output.
50pF load: DWN, WIDE, VCK, VST,
TEST, EN, VDO, HDO,
POF and RGT output
pins
tTHL
tTLH
—
—
40
ns
—
—
48
—
—
50
40
(See Fig. 1.)
Measure HCK1/HCK2.
120pF load
(See Fig. 2.)
Cross-point time
difference
—
∆T
ns
Measure the HCK1/HCK2 duty.
120pF load
HCK duty
DTYHC
%
52
– 17 –
CXA3572R
Electrical Characteristic Measurement Method Diagrams
∆T
90%
10%
50%
∆T
tTLH
tTHL
Fig. 1. Output transition time measurement
conditions
Fig. 2. Cross-point time difference
measurement conditions
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ts1 th1
D15
SDAT
50%
SCK
SEN
tw1H
tw1L
50%
ts0
th0
tw2
Fig. 3. Serial transfer block measurement conditions
– 18 –
CXA3572R
SG No.
SG1
Waveform
Horizontal sync signal
(CSYNC)
4.7µs
3.0Vp-p
1H
Amplitude variable
SG2
1H
Horizontal sync signal
Sine wave video signal; frequency and amplitude variable
0.1Vp-p
SG3
0.1Vp-p
1H
High level variable
0V
25µs
10µs
SG4
Horizontal sync signal
3V
10µs
Low level variable
SG5
25µs
Horizontal sync signal
– 19 –
CXA3572R
SG No.
SG6
Waveform
Horizontal sync signal
(CSYNC)
50mVp-p
4.7µs
1H
Sine wave video signal
0.1Vp-p
SG7
1H
Horizontal sync signal
(CSYNC)
4.7ns
0.15Vp-p
SG8
1H
– 20 –
CXA3572R
Electrical Characteristics Measurement Circuit
TP29
6800p
10k
3.3µ
+3V
TP36
36
TP33 TP32 TP31
TP27 TP26 TP25
A
100k
1µ
43k
29
0.1µ
35 34
0.01µ
47µ
33
32
31
30
28
27
26
25
0.01µ
0.01µ
0.01µ
TP24
TP23
TP22
24
23
22
21
20
19
18
17
16
15
14
13
37 VDD
B/B-Y
R/R-Y
+3V
A
38
39
40
41
42
43
44
45
46
47
48
HDO
VDO
RGT
Vss1
HCK1
HCK2
HST
TP38
G/Y
Vcc1
TP39
TP40
0.01µ
47µ
TP20
OSD G
OSD R
OSD B
NC
TP42
TP43
TP44
TP19
TP18
V
DD
TP16
SIG.C
0.1µ
10
TP46
TP47
WIDE
DWN
Vss2
0.01µ
PSIG DC DET
Buffer
PSIG
OUT
TP14
SW14
60n
V
CC2
+12V
1
2
3
4
5
6
7
8
9
10
10
11
12
10
10
A
0.01µ
47µ
TP1 TP2 TP3
TP6
TP10
TP12
TP8
Resistance value tolerance: ±2%, temperature coefficient: ±200ppm/°C or less
Locate this resistor as close to the IC pin as possible to reduce the effects of external signals.
– 21 –
CXA3572R
Description of Operation
1) RGB andY/color difference signal processing block
Signal processing is comprised of picture, HUE, matrix, LPF/trap, contrast, OSD, sample-and-hold, γ correction,
bright, sub-bright, sub-contrast and output circuits.
• Input signal mode switching
The input mode (RGB input, Y/color difference input) can be switched by the serial communication settings.
(During internal sync separation signal input)
During RGB input:
The G signal is input to Pins 22 and 25, the B signal to Pin 24, and the
R signal to Pin 23.
During Y/color difference input: The Y signal is input to Pins 22 and 25, the B-Y signal to Pin 24, and
the R-Y signal to Pin 23.
(During external sync signal input)
During RGB input:
The G signal is input to Pin 22, the B signal to Pin 24, the R signal to
Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34.
During Y/color difference input: The Y signal is input to Pin 22, the B-Y signal to Pin 24, the R-Y signal
to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34.
• NTSC/PAL switching
The input system (NTSC/PAL) can be switched by the serial communication settings.
• Picture circuit
This performs aperture correction for the Y signal. The center frequency to be corrected and the correction
amount are controlled by serial communication.
• HUE circuit
This is the hue adjustment circuit for the color difference signal. It is controlled by serial communication.
• Matrix circuit
This circuit converts Y, R-Y and B-Y signals into RGB signals.
• LPF circuit
This is the band limitation filter for the RGB signal. It is used to eliminate the noise component generated at
the front end of this IC. The cut-off frequency can be controlled by serial communication. In addition, when
not using the LPF, it can be turned off by serial communication.
• Trap circuit
This is used to eliminate the DSP clock and RGB decoder carrier leak generated at the front end of this IC.
In addition, when not using the trap, it can be turned off by serial communication.
• Contrast adjustment circuit
This adjusts the amplitude to set the input RGB signal to the appropriate output level.
• OSD
This inputs the OSD pulses. There are two input threshold values: Vth1 (Vcc1 × 1/3) and Vth2 (Vcc1 × 2/3).
When an input exceeds Vth1, the corresponding output falls to the level specified by BLACK-LIMITER. When
an input exceeds Vth2, the corresponding output rises to the level specified by WHITE-LIMITER. Also, when
one of the RGB inputs exceeds Vth1, any signal outputs not exceeding Vth1 also fall to the level specified by
BLACK-LIMITER.
– 22 –
CXA3572R
• Sample-and-hold circuit
This circuit performs time axis correction for the RGB output signals in order to support the RGB simultaneous
sampling systems of LCD panels.
HCK1
R
G
B
S/H1
S/H4
S/H4
S/H4
R
G
B
A
S/H2
SH2
A'
B
S/H3
SH3
SH1
SH4
B'
C
C'
RGT = H (Normal)
SHS1
SHS2
A'
SHS3
A
SHS4
C'
SHS5
C
SHS6
B'
B
SH1
SH2
SH3
SH4
Through Through Through Through Through Through
A
C
C'
B'
C
B
B'
A'
B
A
A'
C'
SH1: R signal SH pulse
SH2: G signal SH pulse
SH3: B signal SH pulse
SH4: RGB signal SH pulse
RGT = L (right/left inversion)
SHS1
SHS2
A'
SHS3
SHS4
C'
SHS5
SHS6
B'
B
A
A
C
C
B
SH1
SH2
SH3
SH4
SHS1, 2, 3, 4, 5, 6:
C'
B'
A'
Serial data settings
Through Through Through Through Through Through
B' A' C'
C
B
A
The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG
block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be
compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation and
other timing is also generated by the digital block. The sample-and-hold timing changes according to the
phase relationship with the HCK pulse, so the timing should be set to the SHS1 to SHS6 position in
accordance with the actual board.
• γ correction
In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The γ1
gain transition point A voltage changes as shown in Fig. 2 by adjusting the serial bus register γ1, and the γ2
gain transition point B voltage changes as shown in Fig. 3 by adjusting γ2.
Output
Output
Output
B'
A'
B
A
A
B
B'
A
B
Input
Input
Input
Fig. 1
Fig. 2
Fig. 3
– 23 –
CXA3572R
• Bright circuit
This is used to adjust the black-black amplitude of polarity-inverted RGB output signals. It is not interlinked
with the γ transition points.
• White balance adjustment circuit
This is used to adjust the white balance. The black level is adjusted by SUB-BRIGHT, and the black-white
amplitude is adjusted by SUB-CONTRAST.
• Output circuit
RGB output (Pins 8, 10, and 12) signals are inverted each horizontal line by the FRP pulse (internal pulse)
supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage
(SIG.C) of the output signal matches the reference voltage (Vcc2 + GND2)/2 (or the voltage input to SIG.C
(Pin 16)). In addition, the white level output is clipped at the limiter operation point that is set by the serial
communication WHITE-LIMITER, and the black level output is clipped at the limiter operation point that is set
by the serial communication BLACK-LIMITER.
The output PSIG signal level is normally adjusted by PSIG-BRIGHT, but during black frame display the level
is specified by the BLACK-LIMITER level at some timings. In addition, the RGB output also simultaneously
goes to BLACK-LIMITER level output.
RGB IN
1H inverted signal
(internal)
Black frame display signal
(internal)
BLACK-LIMITER
Set by BLACK-LIMITER
PSIG OUT
SIG.C
Set by PSIG-BRIGHT
BLACK-LIMITER
BLACK-LIMITER
WHITE-LIMITER
SIG.C
RGB OUT
WHITE-LIMITER
BLACK-LIMITER
Set by BLACK-LIMITER
– 24 –
CXA3572R
2) Common voltage generation circuit block
The common voltage circuit generates and supplies the common pad voltage to the LCD panel. The voltage is
offset by serial communication using the SIG.C voltage as the reference and then output.
3) DA OUT output circuit
The DA OUT output circuit outputs DC 3.0V at equal divisions.
4) REF output circuit
The REF output circuit generates and supplies the panel level shifter circuit reference voltage to the LCD
panel.
5) Sync system
• Internal sync separation circuit
Sync separation is performed from the signal input from SYNC IN (Pin 25). An external sync signal can also
be input from the same pin (SYNC IN) according to the serial communication setting.
Serial communication setting
SYNC SEL = 0: Internal sync separation.
SYNC SEL = 1: External sync signal input. (The internal sync separation circuit is set to power
saving mode.)
Input pin (Pin 25) processing
During internal sync separation: Input through an external capacitor (0.1µF)
During external sync signal input: Directly coupled, input level 3Vp-p positive or negative polarity
• PLL and AFC circuits (VCO setting method)
A PLL circuit can be comprised by connecting a PLL circuit phase comparator and frequency division
counter and a VCO circuit and external LPF circuit. The PLL error detection signal is generated using the
phase comparison output of the entire bottom of the horizontal sync signal and the internal frequency
division counter as the RPD output. RPD output is converted to DC error voltage with the lag-lead filter, and
then it controls the internal VCO circuit to stabilize the oscillation frequency.
The internal clock oscillation frequency is set as follows by adjusting VCO-Coarse/Fine.
Adjust the VCO-Coarse/Fine settings so that the HDO pulse output frequency in the condition without sync
input is NTSC: 15.734 ± 0.1kHz and PAL: 15.625 ± 0.1kHz.
Min: 25MHz
Max: 30MHz
5MHz
Clock oscillation
frequency
VCO-Coarse setting
(7 steps)
VCO-Coarse: f0 coarse setting (7 steps) from 5 to 25MHz
VCO-Fine: Variable by approximately 4MHz using the f0 coarse setting made by
VCO-Fine setting range (255 steps)
VCO-Coarse as the reference
6) Power saving circuit (PS circuit)
A power saving system can be realized together with the LCD panel by independently controlling (serial
communication) the operation of each output block. This system is also effective for improving picture quality
during power-on/off.
The serial data PS0 and SYNC GEN must be set in order to use this IC.
For details of the setting methods, see the “Description of Serial Control Operation” and “Power supply
and power saving sequence” items.
– 25 –
CXA3572R
7) Power supply and power saving sequence
Power-on for the CXA3572R and the LCD panel should be performed in the following order.
Power-on
Power-off
LCD VDD
(LCD panel 12V)
D1
D2
VCC2
(analog 12V block)
B1
C1
C2
B2
VCC1
(analog 3V block)
A1
A2
VDD
(digital 3V block)
Power saving set
E2
Power saving canceled
E1
1
Power saving setting
(serial control)
Power saving
PS0 = 0, SLSG = 0
Normal operation
PS0 → 1, SLSG → 1
Power saving
PS0 → 0, SLSG → 0
Normal video display
12 fields
4 fields
Picture cancel period
(no video display)
Display setting period
(no video display)
DA OUT (Pin 26) operation
When power saving is set to on or off, video display is
automatically turned on or off at the above timings.
Power-on
Power-off
min.
max.
—
min.
max.
—
A1
B1
C1
D1
E1
A2
B2
C2
D2
E2
0
0
0
0
0
0
—
—
ms
—
—
ms
2
3
100
0
—
—
100
150
300
3
1
2
After the panel 12V VDD has completely
fallen.
After the digital 3V VDD has completely risen
and XCLR (Pin 35) is completely high level.
After the 3V VDD/VCC1 has completely risen.
• POF (Pin 36) is output as the panel VDD control signal. The POF output can be switched by the serial
communication setting, and the POF setting can be made regardless of the power saving setting.
3V power supply
Power supply
SLPOF
POF (Pin 36) output
Low level
High Level (VDD)
V
CC2
0
1
V
V
DD
CC
1
POF
V
DD
CXA3572R
ACX306
Panel power supply configuration using POF output
– 26 –
CXA3572R
8) TG block
• H-Position
This adjusts the horizontal display position. Set this function so that the picture center matches the center of
the LCD panel.
• V-Position
This adjusts the vertical display position. Set this function so that the picture center matches the center of the
LCD panel.
• Right/left (RGT) and/or up/down (DWN) inversion
The video display direction can be switched. The horizontal direction can be switched between right scan and
left scan, and the vertical direction between down scan and up scan. Set the display direction in accordance
with the LCD panel mounting position.
• Overscan display mode (SLWD)
Displaying black in the up/down 6 lines and right/left 18 (19) dots of the display area generates an overscan
area (black frame) in the display area. Fine adjustment of the black frame display position is performed by
SB-Position.
Black display
453 dots
490 dots
6 lines
240 lines
Display area
Display area
228 lines
6 lines
Black frame display
Normal display
• AC driving of LCD panels during no signal
The output signal runs freely so that the LCD panel is AC driven even when there is no sync signal from the
SYNC IN (Pin 25) and VD (Pin 34) pins.
– 27 –
CXA3572R
Description of Serial Control Operation
1) System reset
After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low. (See Fig. )
The serial bus is set to the default values.
VDD
XCLR (Pin 35)
T
R
TR > 10µs
System reset
2) Control method
Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCK. This loading
operation starts from the falling edge of SEN and is completed at the next rising edge.
Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for
the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator)
block control data becomes valid each time the SEN signal is input.
In addition, if 16 bits or more of SCK are not input while SEN is low, the transferred data is not loaded to the
inside of the IC and is ignored. If 16 bits or more of SCK are input, the 16 bits of data before the rising edge of
the SEN pulse are valid data.
SDAT
SCK
SEN
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A: ADDRESS D: DATA
Serial transfer timing
– 28 –
CXA3572R
2) Serial data map
The serial data map is as follows. Values inside parentheses are the default values.
MSB
ADDRESS
LSB MSB
DATA
LSB
D0
A7 A6 A5 A4 A3 A2 A1 A0
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
USER-BRIGHT
SUB-BRIGHT R
SUB-BRIGHT B
CONTRAST
SUB-CONTRAST R
SUB-CONTRAST B
γ-1
(10000000/LSB)
(1000000/LSB)
(1000000/LSB)
(10000000/LSB)
(1000000/LSB)
(1000000/LSB)
(0000000/LSB)
(0000000/LSB)
(0)
(0)
(0)
(0)
(0)
(0)
γ-2
PSIGSW
(0)
0
0
0
0
1
0
0
0
PSIG-BRIGHT
(1000000/LSB)
(0)
(0)
(0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
COM-DC
COLOR
(1000000/LSB)
(1000000/LSB)
(1000000/LSB)
(10000000/LSB)
(100000/LSB)
HUE
VCO Fine
BLACK-LIMITER
(0)
(0)
PICTURE-GAIN (00000/LSB)
LPFSW
PICTURE-F0 (000/LSB)
DA (000/LSB)
TRAP
(0)
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
1
0
0
1
0
1
LPF (000/LSB)
(0)
INPUT SYNC MODE
(0)
(0)
(0)
VCO Coarse (000/LSB)
SEL (0) SEL (0)
(0)
SLPOF SYNC
(0) GEN (0)
PS0
(0)
TEST1
(0)
TEST2 PONF
(1) (0)
(0)
SLEXVD
(0)
SLWD SLNTPL
(0) (0)
SLSYP
(0)
SLDWN SLRGT
(0) (0)
TEST3
(00)
SLFL
(0)
SLCLP0 SLVDO SLHDO
(0) (0) (0)
SYST
(0)
SLFR SL4096 SLCLP1
(0)
(0) (0)
SLMBK
(0)
(0)
H POSITION (100000/LSB)
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
S/H POSITION (000/LSB)
SB POSITION (100/LSB)
HDO POSITION (00000/LSB)
V POSITION (01000/LSB)
TEST4 (00000000/LSB)
Note: If there is the possibility that data may be set at other than the above-noted addresses, set these data to “0”.
– 29 –
CXA3572R
3) Description of control data
• USER-BRIGHT
This adjusts the brightness of the RGB output signals. Adjustment from LSB → MSB decreases the
amplitude (black – black).
• SUB-BRIGHT R/B
This adjusts the brightness of the R and B output signals using the G output signal as the reference.
Adjustment from LSB → MSB decreases the amplitude (black – black).
• CONTRAST
This adjusts the contrast of the RGB output signals. Adjustment from LSB → MSB increases the amplitude
(black – white).
• SUB-CONTRAST R/B
This adjusts the contrast of the R and B output signals using the G output signal as the reference.
Adjustment from LSB → MSB increases the amplitude (black – white).
• γ-1
This sets the black side γ point level of the RGB output signals. Adjustment from MSB → LSB lowers the
γ point. When not adjusting γ-1, set γ-1: 0000000 (LSB). Set the γ-1 point to the black side (lower side) of
the γ-2 point.
• γ-2
This sets the white side γ point level of the RGB output signals. Adjustment from LSB → MSB lowers the
γ point. When not adjusting γ-2, set γ-2: 0000000 (LSB). Set the γ-2 point to the white side (upper side) of
the γ-1 point.
• PSIG-BRIGHT
This adjusts the brightness of the PSIG output signal. Adjustment from LSB → MSB decreases the amplitude
(peak to peak).
• PSIG-SW
This switches the PSIG circuit on and off.
D7
0
Mode
PSIG OFF
PSIG ON
1
• COM-DC
This adjusts the COMMON output voltage. Adjustment from LSB → MSB increases the output voltage.
• COLOR
This adjusts the color gain during Y/color difference input. Adjustment from LSB → MSB increases the gain.
• HUE
This adjusts the phase during Y/color difference input. Adjustment from LSB → MSB advances the phase.
– 30 –
CXA3572R
• VCO-Fine
This finely adjusts the VCO oscillation center frequency. Adjustment from LSB → MSB increases the
frequency.
Perform this adjustment after adjusting VCO-Coarse.
• VCO-Coarse
This roughly adjusts the VCO oscillation center frequency. Adjustment from LSB → MSB increases the
frequency.
Adjust with VCO-Fine set to 10000000 (LSB).
• BLACK-LIMITER
This adjusts the black side limiter level of the RGB output signals. Adjustment from LSB → MSB lowers the
limiter level.
• PICTURE-GAIN
This adjusts the picture gain during Y/color difference input. Adjustment from LSB → MSB raises the gain.
When not using the picture function, set PICTURE-GAIN: 00000 (LSB).
• PICTURE-F0
This sets the picture center frequency (f0) during Y/color difference input. See the AC Characteristics for the
output level.
D2 D1 D0
Center frequency (f0) typ.
1.0MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.3MHz
1.6MHz
1.9MHz
2.2MHz
2.5MHz
2.8MHz
3.1MHz
• LPF
This switches the frequency response of the low-pass filter. Set the fc/–3dB frequency relative to the
amplitude 100kHz reference. See the AC Characteristics for the output level.
D6 D5 D4
fc (RGB input/no load/typ.)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
—
1.5MHz
2.1MHz
2.7MHz
3.5MHz
4.1MHz
4.6MHz
5.2MHz
– 31 –
CXA3572R
• LPF-SW
This switches the LPF circuit on and off.
D7
0
Mode
LPF off
LPF on
1
• TRAP
This switches the trap circuit on and off.
D3
0
Mode
TRAP off
TRAP on
1
• DA
This adjusts the DA output voltage. Adjustment from LSB → MSB raises the output voltage level.
• INPUT-SEL
Set this according to the input signal level.
D2
0
Mode
Input signal level
Normal input
Internally attenuated by –6dB
0.35Vp-p or less, 0.5Vp-p or less with sync
0.35Vp-p or more, 0.5Vp-p or more with sync
1
• SYNC SEL
This switches between internal sync separation and external sync signal input.
D1
0
Mode
Internal sync separation
Input connection method
Input via a coupling capacitor
External sync signal input
(internal sync separation circuit power saving)
1
Input level 3Vp-p positive or negative polarity
• MODE
This switches the input signal.
D0
0
Input signal
RGB input
Y/color difference input
1
• PS0 (Default: 0)
This performs the power saving setting. Be sure to use this setting as described in “Power supply and power
saving sequence”. The power-on default for this IC is power saving mode, so the settings should be canceled by
serial communication after power-on. The LCD panel power supply must be turned off in power saving mode.
PS0
0
Mode
Power saving
Normal operation
1
– 32 –
CXA3572R
• SYNC GEN (Default: 0)
This sets the sync generator mode. In sync generator mode, only the HDO and VDO pulses are output
normally, and all other pulses are low. The LCD panel power supply must be turned off in sync generator
mode. Normally set to “1”.
SYNC GEN
Mode
Sync generator mode
Normal operation
0
1
• SLPOF (Default: 0)
This sets the POF (Pin 36) output. The POF output setting can be made regardless of the power saving
mode.
SLPOF
Mode
POF = Low output
POF = High output
0
1
• TEST1 (Default: 0)
This is the test mode. Set to “0”.
TEST0
Mode
0
1
Normal operation
Test mode
• PONF (Default: 0)
This switches the time until the picture is displayed after power saving is canceled.
PONF
Mode
0
1
12 fields
4 fields
• TEST2 (Default: 0)
This is the test mode. Set to “1”.
TEST2
Mode
0
1
Test mode
Normal operation
• SLNTPL (Default: 0)
This switches between NTSC and PAL mode.
SLNTPL
Mode
0
1
NTSC
PAL
– 33 –
CXA3572R
• SLWD (Default: 0)
This sets the up/down and/or right/left black frame display.
SLWD
Display
0
1
100% viewing field display
Black frame display (95% display)
• TEST3 (Default: 0, 0)
This is the test mode. Set to “0, 0”.
TEST3
0, 0
Mode
Normal operation
0, 1
1, 0
1, 1
Test mode
• SLRGT (Default: 0)
This switches between normal and right/left inverted display.
SLRGT
Setting
0
1
Normal display (right scan)
Right/left inverted display (left scan)
• SLDWN (Default: 0)
This switches between normal and up/down inverted display.
SLDWN
Setting
0
1
Normal display (down scan)
Up/down inverted display (up scan)
• SLEXVD (Default: 0)
This sets the external VD input. The external VD signal is input via VD (Pin 34). When using internal vertical
sync separation, vertical sync separation is performed using the CSYNC input from SYNC IN (Pin 25).
SLEXVD
Setting
0
1
Internal vertical sync separation
External VSYNC input
• SLSYP (Default: 0)
This switches the input sync signal polarity. When performing sync separation with the internal sync
separation circuit from YonSYNC or GonSYNC, set this to “0”.
SLSYP
HD/CSYNC, VSYNC polarity
Positive polarity
0
1
Negative polarity
– 34 –
CXA3572R
• SLHDO (Default: 0)
This switches the HDO pulse output polarity.
SLHDO
HDO polarity
Positive polarity
Negative polarity
0
1
• SLVDO (Default: 0)
This switches the VDO pulse output polarity.
SLVDO
VDO polarity
Positive polarity
Negative polarity
0
1
• SLCLP0, SLCLP1 (Default: 0, 0)
These switch the clamp position.
SLCLP1
SLCLP0
Position
0
0
1
1
0
1
0
1
A: Back porch position (during internal sync separation)
B: Sync position (during internal sync separation)
C: Back porch position (during external sync signal input)
D: Sync position (during external sync signal input)
HSYNC
2.0µs
00: A
01: B
2.9µs
2.0µs
1.3µs
1.0µs
XCLP
2.0µs
10: C
11: D
3.6µs
2.0µs
• SL4096 (Default: 0)
This function inverts the R, G, B and PSIG output signal polarities every 4096 fields. This further inverts the
output polarities that are inverted every 1H for 4096 fields.
SL4096
Polarity inversion cycle
1H inversion
1H inversion + 4096-field inversion
0
1
• SLFR (Default: 0)
This function inverts the R, G, B and PSIG output signal polarities every field. Normally set to 1H inversion.
SLFR
Polarity inversion cycle
1H inversion
1-field inversion
0
1
– 35 –
CXA3572R
• SLFL (Default: 0)
This function is used to stop R, G, B and PSIG output signal polarity inversion.
SLFL
Polarity inversion cycle
Polarity inversion
Polarity inversion stopped
0
1
• SYST (Default: 0)
This invalidates the input horizontal sync (CSYNC, HD) and forcibly sets the free-running status.
SYST
Mode
Normal operation
Forced free-running
0
1
• H POSITION (Default: 100000/LSB)
These set the horizontal display position. The HST pulse position is adjusted using the horizontal sync signal
as the reference.
Adjustment is possible in 1 bit = 1fH increments.
HSYNC
HP: 100000 (LSB) Default
HP: 000000 (LSB)
HST
HP: 111111 (LSB)
30 steps (fH)
31 steps (fH)
• SLMBK (Default: 0)
This sets the decimation cycle in PAL mode.
SLMBK
Decimation cycle
1/6, 1/6 decimation
1/6, 1/8 decimation
0
1
• HDO POSITION (Default: 00000/LSB)
These set the HDO pulse output position. The HDO pulse output position is adjusted using the horizontal
sync signal as the reference.
Adjustment is possible in 1 bit = 4fH increments.
HSYNC
HP: 00000 (LSB) Default
HDO
HP: 11111 (LSB)
31 steps (124fH)
– 36 –
CXA3572R
• V POSITION (Default: 01000/LSB)
These set the vertical display position. The VST pulse position is adjusted using the input vertical sync signal
as the reference.
Adjustment is possible in 1 bit = 1H (1 line) increments.
Vertical sync signal
VP: 01000 (LSB) Default
VP: 00000 (LSB)
VST
VP: 11111 (LSB)
8 steps (8H)
23 steps (23H)
• S/H POSITION (Default: 000/LSB)
These set the sample-and-hold pulse output phase.
D7 D6 D5
Sample-and-hold position
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SHS1
SHS2
SHS3
SHS4
SHS5
SHS6
Through (sample-and-hold off)
Through (sample-and-hold off)
• SB POSITION (Default: 100/LSB)
In overscan display mode, fine adjustment of the right/left overscan area (black frame) position is possible in
1 bit = 1fH increments.
HST
SBP: 000 (LSB)
SBP: 100 (LSB)
SBP: 111 (LSB)
(BLK)
4 steps 3 steps
(4fH) (3fH)
4 steps 3 steps
(4fH) (3fH)
• TEST4 (Default: 00000000/LSB)
This is the test mode. Set to 00000000/LSB (8 bits).
– 37 –
CXA3572R
Application Circuit
0.1µ
1
0.1µ
36
35
34
33
32
31
30
29
28
27
26
25
100k
0.1µ
0.1µ
0.1µ
37 VDD
B/B-Y
R/R-Y
G/Y
24
B/B-Y
38
39
40
41
42
43
44
45
46
47
48
HDO
VDO
RGT
Vss1
HCK1
HCK2
HST
23
22
21
20
19
18
17
16
15
14
13
R/R-Y
G/Y
+3V
(Analog)
Vcc1
0.1µ
33µ
OSD G
OSD R
OSD B
NC
To LCD
Panel
2
0.01µ
0.68µ
V
DD
SIG.C
WIDE
DWN
Vss2
PSIG DC DET
Buffer
To LCD
Panel
PSIG
OUT
10
V
CC2
0.1µ
33µ
0.1µ
33µ
1
2
3
4
5
6
7
8
9
10
11
12
+12V
(Analog)
+3V
(Digital)
+12V
To LCD Panel
(Analog)
10
10
10
10
22k
33µ
10
10
IN
OUT
To LCD Panel
22k
PSIG Buffer Circuit
1 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm/°C or less
2 When using a signal center voltage other than Vcc2/2, input an external signal center voltage.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 38 –
CXA3572R
Notes on Operation
(1) This IC contains digital circuits, so the set board pattern must be designed in consideration of undesired
radiation, interference to analog circuits, etc. Care should also be taken for the following items when
designing the pattern.
• The digital and analog IC power supplies should be separated, but the GND and VSS should not be
separated and should use a plain GND (VSS) pattern in order to reduce impedance as much as
possible. The power supplies should also use a plain pattern.
• Use ceramic capacitors for the by-pass capacitors between the power supplies and GND, and connect
these capacitors as close to the pins as possible.
• The resistor connected to Pin 28 should be connected as close to the pin as possible, and the wiring
from the pin to GND should be as short as possible. Also, do not pass other signal lines close to this pin
or the connected resistor.
(2) The G/Y (Pin 22), R/R-Y (Pin 23), B/B-Y (Pin 24) and SYNC IN (Pin 25) pin input signals are clamped at
the inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low
impedance.
(Input at an impedance of 1kΩ (max.) or less.)
(3) The smoothing capacitor of the DC level control feedback circuit in the capacitor block connected to the
RGB output pins should have a leak current with a small absolute value and variance. Also, when using
the pulse elimination (PAL display) function, the picture quality should be thoroughly evaluated before
deciding the capacitance value of the capacitor.
(4) A thorough study of whether the capacitor connected to the COM output pin satisfies the LCD panel
specifications should be made before deciding the capacitance value.
(5) If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction
depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of
using this IC with other circuits before deciding on its use.
(6) Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater
than the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or
due to the order in which power is supplied to circuits. Be sure to take measures against the possibility of
latch up.
(7) Be sure to observe the power supply and power saving sequence specifications specified for this IC.
(8) Do not apply a voltage higher than VDD or lower than VSS to I/O pins.
(9) Do not use this IC under operating conditions other than those given.
(10) Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may
damage the device, leading to eventual breakdown.
(11) This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should
be taken to prevent electrostatic discharge.
(12) Always connect the VSS, GND1 and GND2 pins to the lowest potential applied to this IC; do not leave
these pins open. The voltages applied to the power supply pins should be as follows.
VSS = GND1 = GND2 ≤ VDD = VCC1 ≤ VCC2.
(13) Be sure to connect the damping resistor of 10Ω to ROUT, GOUT, BOUT, PSIGOUT and COM output.
– 39 –
CXA3572R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
7.0 ± 0.1
S
36
25
24
13
37
48
B
A
(0.22)
0.13
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.2
1.5 – 0.1
+ 0.08
0.18 – 0.03
M
0.1
S
0.1 ± 0.1
0.18 ± 0.03
0˚ to 10˚
DETAIL B: PALLADIUM
DETAIL A
NOTE: Dimension “ ” does not include mold protrusion.
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PALLADIUM PLATING
COPPER ALLOY
0.2g
LQFP-48P-L01
P-LQFP48-7x7-0.5
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MASS
Sony Corporation
– 40 –
相关型号：
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