CXA3541N [SONY]
2-channel Read/Write Amplifier for GMR-Ind Head Hard Disk Drive; 2通道的读/写放大器GMR -IND头硬盘驱动器
| 型号： | CXA3541N |
| 厂家： | 
SONY CORPORATION |
| 描述： | 2-channel Read/Write Amplifier for GMR-Ind Head Hard Disk Drive |
| 文件： | 总17页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA3541N
2-channel Read/Write Amplifier for GMR-Ind Head Hard Disk Drive
Description
24 pin SSOP (Plastic)
The CXA3541N is a read/write amplifier for GMR-Ind
(Giant Magneto Resistive-Inductive) heads used in
hard disk drives, and is capable of supporting up to
two channels.
Features
• +5V and –3V power supply
• Current bias voltage sense type
• Low power 180mW at read
• Differential read amplifier gain; ×100/135 (RMR = 50Ω)
• Input noise of 0.77nV/√ Hz (typ.), RMR = 50Ω,
IB = 5.9mA
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Supply voltage
• Digital input voltage
VCC
VEE
Vdi
–0.3 to +5.8
–3.7 to +0.3
V
V
–0.3 to VCC + 0.3 V
0 to +70 °C
–55 to +150 °C
• Recovery time write to read; 300ns (typ.)
• Write data is triggered by differential P-ECL signal
• Servo bank write
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
• Write unsafe detection circuit
• Serial port
PD
800
mW
(on board)
Head selection
MR bias
Operating Conditions
Write current
• Supply voltage
VCC
VEE
VMR
IB
4.4 to 5.5
–3.5 to –2.6
V
V
Applications
• MR bias voltage
• Bias current
–300 to +300 mV
3 to 8 mA
19.5 to 49.5 mA
Hard disk drives with GMR-Ind heads
• Write current
IW
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E00205-PS
CXA3541N
Block Diagram and Pin Configuration
Bias
Current
Source
SCLK
SDATA
WDX
1
2
RS
24
23
22
Serial Interface
NC
Write
Current
Source
3
R1Y
WD BUF
AMP
4
WDY
21 R1X
5
VCC
20
W1Y
DRIVER
6
GND
19 W1X
18 W0X
17 W0Y
16 R0X
15 R0Y
14 NC
7
RDY
AMP
DRIVER
AMP
8
RDX
9
FLT/SE/BHV
R/XW
10
11
12
SDEN
VEE
13 CAP
– 2 –
CXA3541N
Pin Description
Pin
No.
Symbol
Equivalent circuit
Description
VCC
1
2
7.5k
1
2
SCLK
SDATA
Serial control signal input.
11
11 SDEN
14k
VEE
2Vf
GND
VCC
100
100
3
4
WDX
WDY
3
4
Differential P-ECL write data input.
GND
VEE
5V power supply.
Ground.
5
6
VCC
GND
VCC
100
Read amplifier output with coupling
capacitors.
High impedance in the write mode.
7
8
7
8
RDY
RDX
1.8mA
GND
VEE
VCC
Head unsafe detection output.
Servo bank write enable input.
Buffered head voltage output.
9
FLT/SE/BHV
9
GND
VEE
– 3 –
CXA3541N
Pin
No.
Symbol
Equivalent circuit
Description
VCC
Read/write control signal input.
Read when high, write when low.
10 R/XW
10
3Vf
GND
VEE
12
VEE
–3V power supply.
VCC
Connect an external capacitor of read
amplifier between this pin and VEE.
13 CAP
13
VEE
14
NC
23
Non connection.
VCC
R0X
R0Y
R1X
R1Y
16
15
21
22
16 21
15 22
MR heads for read.
Two channels are provided.
VEE
VCC
18 W0X
17 W0Y
19 W1X
20 W1Y
18 19
17 20
Inductive heads for write.
Two channels are provided.
GND
VEE
– 4 –
CXA3541N
Pin
No.
Symbol
Equivalent circuit
Description
VCC
Bias current setting register is connected
between this pin and GND.
250
24 RS
24
VBGR
= 1.3V
GND
VEE
– 5 –
CXA3541N
Electrical Characteristics
(Unless otherwise specified; VCC = 5V, VEE = –3V, Ta = 25°C, CAP = 0.1µF, RS = 7.5kΩ)
No.
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Power Dissipation IW = 29.5mA, IB = 5.9mA
1-1
1-2
1-3
1-4
1-5
1-7
1-8
Sleep mode
2.15 2.85
mA
mA
mA
mA
mA
mA
mA
ISP1
IID1
Idle mode
22
37
98
10
10
10
29
48
VCC power supply current
Read mode
Write mode
Idle mode
IRE1
IWR1
IID2
130
13
VEE power supply current
Bank write mode
Read mode
Write mode
13
IRE2
IWR2
13
ICCBW = 17 + 17 × N + IW × N
IW = 29.5mA
1-9
111
mA
ICCBW
Digital Inputs
TTL input
2-1
0
0.8
V
V
VIL
low input voltage
TTL input; R/XW
Internal pull-up resistor
TTL input
VCC
+ 0.3
2-2
2-3
2-4
2-5
2.0
VIH
high input voltage
TTL input
High voltage: 5V
Low voltage: 0V
–200
200
0.8
µA
V
ITTL
VSIL
VSIH
input current
Serial interface input
low input voltage
Serial input;
SDATA, SCLK, SDEN
Serial interface input
high input voltage
2.35
V
High voltage: 3.3V
Low voltage: 0V
Pull-down resistor: 14kΩ
Serial interface input
input current
2-6
–500
500
µA
VST
P-ECL common voltage
P-ECL differential voltage
P-ECL high voltage
(VH + VL)/2
(VH – VL)
3-1
3-2
3-3
3-4
1.55
0.2
VCC
1.5
VCC
20
V
V
VPC
VPD
VPH
IWD
V
P-ECL input current
Input voltage: 4V
–20
µA
Power Dissipation IW = 29.5mA, IB = 5.9mA
VCC
+ 1.2
VCC
+ 1.4
Bank write enable voltage
Bank write enable current
FLT output low voltage
4-1
4-2
5-1
V
mA
V
VSEH
ISEH
6
14
Open collector output
External resistance = 2.4kΩ
0.8
VFLTL
Open collector output
External resistance = 2.4kΩ
FLT output high voltage
BHV gain accuracy
5-2
6
4.5
–8
V
VFLTH
EBHV
VBHV = VCC – 4 × IB × (RMR + 5.5Ω)
IB = "111", RMR = 50Ω
8
%
– 6 –
CXA3541N
No.
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Read Characteristics RMR = 50Ω, IB = 5.9mA
Gain = 0
RMR = 50Ω, IB = 5.9mA
R1 Low gain
R2 High gain
AVL
AVH
FCL
FCH
ENi
82
100
135
350
200
118
160
550
V/V
V/V
kHz
Gain = 1
RMR = 50Ω, IB = 5.9mA
110
Low frequency cut-off
(–3dB)
R3
R4
High frequency cut-off
(–3dB)
140
MHz
nV
Exclusive of head noise
RMR = 50Ω, IB = 5.9mA
R5 Input reflected noise
0.77 0.95
Hz
√
R6 MR bias current range 1
R7 MR bias accuracy
R8 MR bias resolution
IBR1
EIB
RIB
3
8
+7
mA
%
–7
0.714
mA
3-bit DAC
VCC power supply
R9-1
Ripple voltage: 100mVp-p
100kHz to 50MHz
PSRR1
PSRR2
CMRR1
CMRR2
CLRR
38
45
37
27
40
dB
dB
dB
dB
dB
mV
Ω
rejection ratio
VEE power supply
R9-2
Ripple voltage: 100mVp-p
100kHz to 10MHz
rejection ratio
Common mode
R10-1
Ripple voltage: 100mVp-p
100kHz to 50MHz
rejection ratio 1
Common mode
R10-2
Ripple voltage: 100mVp-p
51MHz to 80MHz
rejection ratio 2
Control line input noise
rejection
Ripple voltage: 100mVp-p
4MHz to 80MHz
R11
RDX/RDY offset
R12
VOFF1
50
Write to read
difference magnitude
RDX/RDY output
R13
RDro
30
100
Differential, read mode
impedance
Read Safety Characteristics
P1 MR head open threshold MRop
P2 MR head short threshold MRsh
Write Characteristics
600
15
750
50
900
90
mV
mV
Head X – Head Y
Head X – Head Y
IB = "000" to "011"
W1 Write current range
W2 Write current accuracy
W3 Write current resolution
W4 Leakage current
IWR
EIW
RIW
ILEAK
RD
19.5
–7
49.5
+7
mA
%
DAC code = x "0000" to x "1111"
RH = 0Ω
2
mA
µA
Ω
4-bit DAC
200
Unselected head
W6 Damping resistor
800 1000 1200
Write current propagation
delay time
LH = 0, RH = 0
Write data to 50% of write current
W7
Tpd
10
ns
ns
%
W8 Write current rise/fall time TR/TF
1.9
RH = 15Ω, LH = 150nH, IW = 25mA
VCC = 3.5V
DAC code = x "0101"
W9 Erase current accuracy
EIE
–18
–9
0
Bank write current
accuracy
W10
Refer to Fig.
– 7 –
CXA3541N
No.
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Write Safety Characteristics
U1 Write head open threshold
Detect open head
1.2
1.4
0.1
V
V
Rop
Head voltage when short to
U2
Detect short to GND
VG
GND
U3 WD frequency too low
U4 Write safety detect time
0.5
1.8 MHz
fWDL
Tws
300
ns
T1: 2 transitions on WDX/WDY
+ T1
U5 Low VCC threshold
Fault detected
Fault removed
3.7
3.9
3.9
4.1
200
4.1
4.3
V
V
VWthL
VWthH
Vhys
U6 Low VCC threshold
U7 Low VCC threshold hysteresis
mV
Switching Characteristics Iw = 29.5mA, IB = 5.9mA
Signal on WDX/WDY
90% RD signal or 10% IW
S1 Write to Read
300
50
500
ns
TWR
S2 Read to Write
S3 Idle to Read
90% IW
70
ns
µs
TRW
TIR
90% RD signal
1.0
1
90% RD signal, 90% IB
S4 Sleep to Read
600 2000
µs
TSR1
IB = "011"
Bank Write Characteristics Iw = 29.5mA, IB = 5.9mA
S5 Read to Bank write
S6 Bank write to Read
90% IW
10% IW
100
100
ns
ns
TRB
TBR
Idle to Bank write
Idle to Write
S7
90% IW
300
µs
TIW
Serial Port Timing
B1 Setup time
SDEN to first SCLK
30
15
ns
ns
TSU (sden)
Th (sden)
f (sclk)
B2 Hold time
Last SCLK to deassert SDEN
B4 SCLK frequency
B5 SCLK pulse width
B6 SCLK – SDATA setup time
B7 SCLK – SDATA hold time
B8 SDEN low time
30
MHz
ns
10
10
Tw (sclk)
TSU (d)
Th (d)
ns
10
ns
100
ns
TSL
1
TSR is proportional to IB and external CAP value.
– 8 –
CXA3541N
Serial Port Characteristics
ADR1
ADR0
DATA5
XSLP
DATA4
XIDL
DATA3
N/A
DATA2
N/A
DATA1
N/A
DATA0
HS
0
0
1
0
1
0
GAIN
BHV
N/A
IB2
IB1
IB0
MROPN
MRSHT
IW3
IW2
IW1
IW0
IB[2:0] bits are initialized by "0" at power on.
Code Description
Bit
Function
XSLP
XIDL
0 = Set the pre-amplifier into low power "sleep" mode.
0 = Set pre-amplifier to idle mode.
Head select bit.
HS
GAIN
BHV
Set the pre-amplifier to high or low gain mode. 1 = Set pre-amplifier to high gain mode.
Active the BHV test point pin. "1" active.
MR bias current set.
IB[2:0]
MROPN
MRSHT
IW[3:0]
1 = Set MR head open detector active.
1 = Set MR head short detector active.
Set write current.
– 9 –
CXA3541N
Mode Control
SLEEP
XSLP = 0
READ
IDLE
WRITE
XSLP = 1
XIDL = 1
R/XW = H
XSLP = 1
XIDL = 0
R/XW = X
XSLP = 1
XIDL = 1
R/XW = L
Serial Port Timing Detail
TSL
SDEN
f (sclk)
Th (sden)
Tsu (sden)
Tw (sclk)
SCLK
Th (d)
Tsu (d)
SDATA
A1
A0
D5
D4
D3
D2
D1
D0
Serial Port Timing
After the SDEN goes high, the last eight bits are transferred into the register. The SCLK will shift the data
presented at SDATA into an internal shift register on the rising edge of each clock.
As SCLK initial condition, both of low and high signal is acceptable.
– 10 –
CXA3541N
Unsafe Condition
1. Write fault condition
FLT is a high level in write fault condition.
• Open write head leads. fWD < 15MHz
• Write head leads shorted to ground.
• WD frequency is too low.
• Power supply is out of tolerance.
2. Read fault condition
FLT is a low level in read fault condition.
• Open short MR head. (This function is set by serial resister.)
Bank Write Control (Refer to Bank "Write current vs. Current accuracy" characteristic curve)
1. Set the read mode.
2. Force a certain voltage (min. VCC + 1.2V) to FLT/SE pin by using the pull-up register. (RSE = 820Ω)
#This operation disables all fault detection.
3. Set VCC at 3.5V (in case of the erase mode only)
4. Start the write operation by setting R/XW = L.
5. Terminate the write operation by setting R/XW = H.
i) Allow 50% write duty or less.
ii) Low voltage detector is disabled in the bank write mode and erase mode.
iii) Don't change the serial register data bits in following conditions:
• VCC = 3.5V
• On entering write data.
BHV (Buffered Head Voltage)
1. Applicable within VCC = 5V ± 5%.
2. Turn BHV on, but turn off MROPN and MRSHT.
3. VBHV is determined by basis of VCC. VBHV = VCC – (4 × IB × (RMR + 5.5Ω))
Head Condition
1. Short X-Y terminal on un-used write head.
2. Recommended X-Y terminal on un-used read head short.
Polarity
1. Read output signal on RDX is negative, when MRX is positive by increasing RMR.
2. Write current flows into X side, when WDX is high and WDY is low.
Head Select Table
(2ch)
HS
0
Normal operation
0
1
1
– 11 –
CXA3541N
MR Bias
IB2
0
IB1
0
IB0
0
IB [mA]
3.0
0
0
1
3.714
4.429
5.143
5.857
6.571
7.286
8.0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Write Current
Write current
[mA0-P]
IW3
IW2
IW1
IW0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
19.5
21.5
23.5
25.5
27.5
29.5
31.5
33.5
35.5
37.5
39.5
41.5
43.5
45.5
47.5
49.5
Actual head current is defined by the following equation:
IHEAD = IW/(1 + RH/RD)
RH: Head resistance
RD: Damping resistance
– 12 –
CXA3541N
Electrical Characteristics Measurement Circuit
7.5kΩ
1
2
3
4
5
6
7
8
9
RS
SCLK
SDATA
WDX
24
NC 23
25Ω
25Ω
R1Y
22
V WDX
V WDY
3300µH
R1X 21
WDY
1µF
S7
VCC
20
19
W1Y
W1X
1000pF
S6
VPSRR
150nH
GND
10µF
R13
1.5k
Amp1 Gain = ×1
RDY
W0X 18
W0Y 17
R0X 16
R0Y 15
NC 14
1000pF
1000pF
150nH
RDX
VCC
2.4k
V
VM1
R14
1.5k
25Ω
25Ω
FLT/SE/BHV
V SE
10 R/XW
Amp2 Gain = ×100
V R/XW
SDEN
VEE
11
12
VEE
CAP 13
BPF
100kHz
to 50MHz
S6'
S7'
1kΩ
VPSRR'
1µF
S/I
V
VM2
0.1µF
0.1µF
3300µH
– 13 –
CXA3541N
Application Circuit
7.5kΩ
SCLK
SDATA
WDX
1
2
3
4
5
6
7
8
9
RS
NC
24
23
22
R1Y
R1X 21
WDY
5V
0.1µF
VCC
20
19
18
W1Y
W1X
W0X
GND
RDY
RDX
W0Y 17
R0X 16
R0Y 15
NC 14
FLT/SE/BHV
10 R/XW
SDEN
VEE
11
12
–3V
0.1µF
CAP 13
0.1µF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 14 –
CXA3541N
Normalized bias current
vs. Ambient temperature
Normalized bias current
vs. Power supply voltage
1.04
1.02
1.00
0.98
0.96
1.04
1.02
1.00
0.98
0.96
VCC = 5V
VEE = –3V
VEE = –3V
RMR = 50Ω
IBn = "100"
RMR = 50Ω
IBn = "100"
Ta = 25°C
–25.0
0.0
25.0
50.0
75.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Ta – Ambient temperature [°C]
VCC [V]
Normalized read amplifier voltage gain
vs. Ambient temperature
Normalized read amplifier voltage gain
vs. Power supply voltage
1.06
1.04
1.02
1.00
1.04
1.02
1.00
0.98
0.96
VCC = 5V
VEE = –3V
RMR = 50Ω
IBn = "100"
High gain
VEE = –3V
RMR = 50Ω
IBn = "100"
High gain
Ta = 25°C
0.98
0.96
0.94
–25.0
0.0
25.0
50.0
75.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Ta – Ambient temperature [°C]
VCC [V]
Bank write current vs. Current accuracy
0
–2
VCC = 5V
Ta = 25°C
RH = 0Ω
–4
Read 170µs
Write 30µs
with Write Data
–6
–8
–10
–12
–14
–16
15
20
25
30
35
40
45
50
55
Bank write current [mA]
Deviation of bank write current is within ± 7% at basis of the chart.
– 15 –
CXA3541N
Input refered noise voltage
vs. Ambient temperature
Normalized write current
vs. Ambient temperature
0.82
0.80
0.78
0.76
0.74
0.72
0.70
1.04
1.02
1.00
0.98
VCC = 5V
VCC = 5V
VEE = –3V
IWn = "0101"
VEE = –3V
RMR = 50Ω
IBn = "100"
0.96
0.94
–25.0
0.0
25.0
50.0
75.0
–25.0
0.0
25.0
50.0
75.0
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
Power supply ON/OFF detector
threshold voltage
vs. Ambient temperature
Normalized write current
vs. Power supply voltage
1.04
1.02
1.00
0.98
0.96
4.15
4.10
4.05
4.00
3.95
3.90
3.85
ON → OFF
OFF → ON
VEE = –3V
IWn = "0101"
Ta = 25°C
3.5
4.0
4.5
5.0
5.5
6.0
6.5
–25.0
0.0
25.0
50.0
75.0
VCC [V]
Ta – Ambient temperature [°C]
– 16 –
CXA3541N
Package Outline
Unit: mm
24PIN SSOP(PLASTIC)
+ 0.2
1.25 – 0.1
7.8 ± 0.1
0.1
24
13
A
1
12
b
0.13
M
0.65
B
+ 0.1
b=0.22 – 0.05
(0.22)
b=0.22 ± 0.03
0.1 ± 0.1
DETAIL B : SOLDER
DETAIL B : PALLADIUM
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
A
DETAIL
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER/PALLADIUM
SONY CODE
EIAJ CODE
SSOP-24P-L01
PLATING
SSOP024-P-0056
42/COPPER ALLOY
0.1g
JEDEC CODE
PACKAGE MASS
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 17 –
Sony Corporation
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