IMIC9835CT [CYPRESS]
Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems; 低EMI时钟发生器，用于Intel移动133兆赫/ 3 SO -DIMM芯片组的系统
| 型号： | IMIC9835CT |
| 厂家： | 
CYPRESS |
| 描述： | Low-EMI Clock Generator for Intel Mobile 133-MHz/3 SO-DIMM Chipset Systems |
| 文件： | 总18页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C9835
Low-EMI Clock Generator for Intel®
Mobile 133-MHz/3 SO-DIMM Chipset Systems
• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
AGP memory
Features
• Meets Intel’s Mobile 133.3MHz Chipset
• One selectable frequency for VCH video channel clock
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
• Power management using power-down, CPU stop, and
PCI stop pins
• Three function select pins (include test-mode select)
• Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
• Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)
• Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)
• Seven PCI Clocks (33MHz, 3.3V), one free running
• Two IOAPIC clocks, synchronous to CPU clock (33.3
MHz, 2.5V)
• One REF Clock
• Two 48-MHz fixed non-SSCG clocks (USB and DOT)
• SMBUS support with readback
• 56-pin SSOP and TSSOP packages
Table 1. Function Table[1]
SDRAM(0:5)
TEST#
SEL1
SEL0
CPU(0:2)
3V66(0:2)
PCIF(1:6) 48M(0:1)
REF
IOAPIC(0:10)
DCLK
0
0
1
1
1
1
X
X
0
0
1
1
0
1
0
1
0
1
Hi-Z
TCLK/2
66.6
Hi-Z
Hi-Z
TCLK/3
66.6
Hi-Z
TCLK/6
33.3
Hi-Z
TCLK/2
48
Hi-Z
Hi-Z
TCLK/6
33.3
TCLK/2
100.0[2]
100.0[2]
133.3
TCLK
14.318
14.318
14.318
14.318
100.0
133.3
133.3
66.6
33.3
48
33.3
66.6
33.3
48
33.3
100.0[2]
66.6
33.3
48
33.3
Note:
1. These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
2. Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
Pin Configuration
Block Diagram
56
REF
VDD
XIN
XOUT
VSS
VSS
1
2
3
4
5
6
7
8
VSS
X IN
IOAPIC0
IOAPIC1
VDDI
CPU0
VDDC
CPU1
CPU2
VSS
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
DCLK
VDDS
VCH_CLK
VDD
CPU_STP#
TEST#
PD#
55
54
53
52
51
50
49
3 6 p F
3 6 p F
X O U T
V D D
R E F
1
1
V D D
3V66_0
3V66_1
3V66_2(AGP)
VDD
V C H _ C L K
V D D I
9
48
47
46
45
IO A P IC (0 ,1 )
C P U (0 :2 )
IO A P IC
C P U
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PCI_STP#
PCI_F
PCI1
V D D C
V D D S
C
9
8
3
5
3
44
43
42
41
R in
VSS
PCI2
PCI3
VDDP
PCI4
PCI5
PCI6
VSS
AVDD
AVSS
T E S T #
S E L 0 ,1
S D R A M ( 0 :5 )
tris ta te
s 0
S D R A M
3 V 6 6
6
3
V D D
40
39
38
37
36
35
34
33
P D #
3 V 6 6 (0 :2 )
P C I_ F
V D D P
V D D P
V D D
P C I_ S T P #
C P U _ S T P #
i2 c -c lk
i2 c -d a ta
P C I(1 :6 )
P C I
6
2
1
P L L 1
R in
4 8 M (0 ,1 )
D C L K
4 8
VSS
48M0(USB)
48M1(DOT)
VDD
24
25
26
27
V D D S
P D #
S C L K
32
31
30
P D #
SCLK
SDATA
i2 c -c lk
i2 c -d a ta
S D A T A
SEL0
28
SEL1
29
P L L 2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07303 Rev. **
Revised April 5, 2002
C9835
Pin Description[3]
Pin
Name
PWR
Description
1
3
REF
XIN
VDD 3.3V 14.318 MHz clock output
VDD Oscillator buffer input. Connect to a crystal or to an external clock.
Oscillator buffer output. Connect to a crystal. Do not connect when an external
clock is applied at XIN.
4
XOUT
VDD
49, 50, 52
7, 8, 9
CPU(0:2)
3V66(0:2)
VDDC 2.5V Host bus clock outputs
VDD 3.3V Fixed 66.6 MHz clock outputs
3.3V PCI clock output. This clock continues to run when PCI_STP# is at a logic
low level.
12
PCI_F
VDDP
3.3V PCI clock outputs. These clocks synchronously stop in a low state when
VDDP PCI_STP# is brought to a logic low level. They synchronously resume running
when PCI_STP# is brought to a logic high state.
13, 15, 16, 18,
19, 20
PCI (1:6)
25, 26
36
48M(0,1)
VDD 3.3V Fixed 48 MHz clock outputs
3.3V selectable 66.6 MHz or 48 MHz clock output to VCH. Spread spectrum
VCH_CLK
VDD
applies only when 66.6 MHz is selected. Select via SMBUS, byte 4 bit7.
CPU0 stop clock control input. Stops only CPU0 in a low state when asserted
VDD low. Using this pin to start and stop CPU0 clock insures synchronous (no short or
long clocks) transitioning of this clock.
34
CPU_STP#
PCI stop clock control input. When this signal is at a logic low level (0), all PCI
clocks (except PCI_F) stop at a logic low level. Using this pin to start and stop PCI
clocks insures synchronous (no short or long clocks) transitioning of these clocks.
This pin has no effect on the PCI_F clock.
11
PCI_STP#
SEL(0,1)
SDATA
VDD
3.3V LVTTL inputs for logic selection. These pins have Internal pull-ups,
typically 250k (range 200k to 800k).
28, 29
30
VDD
Serial data input pin. Conforms to the SMBUS specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See 2-Wire SMBUS
VDD
Control Interface on page 7.
Serial clock input pin. Conforms to the SMBUS specification. See 2-Wire
SMBUS Control Interface on page 7.
31
32
SCLK
PD#
VDD
3.3V LVTTL-compatible input. When held LOW, the device enters a power down
VDD mode. This pin has an Internal Pull-Up. See Power Management Functions on
page 3.
33
38
TEST#
DCLK
VDD 3.3V LVTTL compatible input for selecting test mode. See Table 1.
3.3V SDRAM feedback clock output. See Table 1 for frequency selection. See
VDDS
Figure 4 for timing relationship.
39, 40, 42, 43,
45, 46
SDRAM(0:5)
VDDS 3.3V SDRAM clock outputs
54, 55
37, 44
17
IOAPIC(0,1)
VDDS
VDDI 2.5V IOAPIC clock outputs. See Figure 4 for timing relationships.
3.3V Power for SDRAM and DCLK clock output buffers
3.3V Power for PCI clock output buffers
2.5V Power for IOAPIC clock output buffers
2.5V Power for CPU clock output buffers
3.3V Common power supply
VDDP
53
VDDI
51
VDDC
2, 10, 27, 35 VDD
22
23
AVDD
AVSS
Analog power
Analog ground
5,6,14,21,24,
41, 47, 48, 56
VSS
Common ground pins
Note:
3. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Document #: 38-07303 Rev. **
Page 2 of 18
C9835
Table 2. Expanded Frequency Selection (MHz)[4, 5, 6]
SDRAM(0:5),
DCLK
PCI_F,
3V66(0:2) PCI(1:6)
TEST# ESEL ESEL
SEL
SEL CPU(0:2)
Notes
0% extension
(Default)
1
0
0
0
0
66.7
100[6]
66.6
33
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100
133.3
133.3
70
100[6]
133.3
100[6]
105[6]
105[6]
140
105[6]
110[6]
110[6]
146.7
110[6]
120[6]
120[6]
160
66.6
66.6
66.6
70
33
33
33
35
5% extension
10% extension
20% extension
105
70
35
140
70
35
140
70
35
73.3
110
73.3
73.3
73.3
73.3
80
36.6
36.6
36.6
36.6
40
146.7
146.7
80
120
80
40
160
80
40
160
120[6]
80
40
Power Management Functions
Power management on this device is controlled by the PD#,
CPU_STP# and PCI_STP# pins. When PD# is high (default)
the device is in normal running mode and all signals are active.
in a low state on their next high-to-low transition. The REF and
USB clocks are stopped in a low state as soon as possible.
When in power down (and before power is removed), all
outputs are synchronously stopped in a low state (see
Figure 1), all PLLs are shut off, and the crystal oscillator is
disabled. When the device is shutdown, the I²C function is
also disabled.
The PD# signal is used to bring all clocks to a low level in an
orderly fashion prior to power (all except AVDD) being
removed from the part. When PD# is asserted (forced) low, the
device transitions to a shutdown (power down) mode and all
power supplies (3.3V and 2.5V except for AVDD) may then be
removed. When PD# is sampled low by two consecutive rising
edges of the CPU clock, then all affected clocks are stopped
At power-up, using the PD# select pin, all clocks are started in
such a manner as to guarantee a glitch-free operation, no
partial clock pulses.
Notes:
4. Extended frequencies are only available via SMBUS interface. They are accessable via SMBUS Byte 5 bits 0,1.
5. 48M(0,1) clocks are constant at 48 MHz and REF is constant at 14.31818 MHz for all table selections.
6. Will be set to 133 MHz and boosted accordingly, when Byte3,Bit 0 is set to logic 1.
Document #: 38-07303 Rev. **
Page 3 of 18
C9835
Power Management Timing
0ns
10ns
20ns
30ns
40ns
50ns
60ns
CPU 100 MHz
3V66 66 MHz
PCI 33 MHz
IOAPIC 33 MHz
PD#
SDRAM 100 MHz
REF 14.3 MHz
VCH_CLK , 48M (0,1)
Figure 1.
Table 3. Power Management Current
Maximum 2.5V Current Consumption
(VDDC = VDDI = 2.625)
Maximum 3.3V Current Consumption
(VDD = AVDD = VDDS = 3.465V)
Conditions
Power-down (PD# = LOW)
CPU = 66 MHz @ max loads
CPU = 100 MHz @ max loads
CPU = 133 MHz @ max loads
≤ 1mA
60 mA
75 mA
90 mA
≤ 1mA
295 mA
295 mA
295 mA
When exiting the power-down mode, the application must
supply power to the VDD pins a minimum of 200 ms before
releasing the PD# pin high to insure that an orderly startup will
occur and that the initial clocks that the device produces are
full and correctly compliant with data sheet specified phase
relationships.
started in such a manner as to guarantee that the high pulse
width is a full pulse. Only one rising edge of PCI_F occurs after
the clock control logic is switched for the CPU0 output to
become enabled/disabled.
PCI_STP# Timing
PCI_STP# is an input to the clock generator and is made
synchronous to the clock driver PCI_F output. It is used to turn
off the PCI clocks for low power operation. PCI clocks are
stopped in a low state and started such that a full high pulse
width is guaranteed. ONLY one rising edge of PCI_F occurs
after the clock control logic switched for the PCI outputs to
become enabled/disabled.
CPU_STP# Timing
CPU_STP# is an input to the clock generator. CPU_STP# is
asserted asynchronously by the external clock control logic
and is internally synchronized to the external PCI_F output. All
other clocks will continue to run while the CPU0 clock is
disabled. The CPU0 is always stopped in a low state and
Note:
7. All internal timing is referenced to the CPU clock.
8. CPU_STP# signal is an input signal that is made synchronous to free-running PCI_F.
9. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz.
Document #: 38-07303 Rev. **
Page 4 of 18
C9835
CPU(1,2)
PCI_F
Tsu
Tsu
CPU_STP#
CPU0
PCI_STP#
(High)
(High)
PWR_DWN#
Figure 2. CPU_STP Timing Diagram
PCI_F
Tsu
Tsu
PCI_STP#
PCI(1:6)
CPU_STP#
PD#
(High)
(High)
Figure 3. PCI_STP# Timing Diagram[[10,11,12,13,14]
Note:
10. All the internal timing is referenced to the CPU clock
11. PCI_STP# signal is an input signal that must be made synchronous to PCI_F output.
12. All other clocks continue to run undisturbed.
13. PD# is understood to in a high state.
14. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz
Document #: 38-07303 Rev. **
Page 5 of 18
C9835
Clock Phase
0ns
10ns
20ns
30ns
40ns
Sync
CPU CLOCK 66MHz
100MHz
133MHz
CPU CLOCK
CPU CLOCK
2.5ns
5ns
0ns
5ns
7.5ns
3.75ns
DCLK/SDRAM CLOCK 100MHz
DCLK/SDRAM CLOCK 133MHz
0ns
0ns
0nS
3V66 CLOCK
PCI CLOCK
66MHz
33MHz
3.75ns
1.5ns~3.5
IOAPIC CLOCK
33MHz
Figure 4.
Table 4. Group Timing Relationships and Tolerances
CPU = 66.6 MHz, SDRAM = 100 MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
2.5
7.5
500
500
500
500
1000
N/A
180 degrees phase shift
When rising edges line up
3V66 leads
SDRAM/DCLK to 3V66
3V66 to PCI
0
1.5–3.5
0
PCI to IOAPIC
48M (0,1)
Async
CPU = 100 MHz, SDRAM = 100 MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
5
500
500
500
500
1000
N/A
180 degrees phase shift
CPU leads
5
0
SDRAM/DCLK to 3V66
3V66 to PCI
When rising edges line up
3V66 leads
1.5–3.5
0
PCI to IOAPIC
48M (0,1)
Async
CPU = 133.3 MHz, SDRAM = 100 MHz
Offset(ns)
Tolerance(ps)
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
0
500
500
500
500
1000
N/A
When rising edges line up
0
0
SDRAM/DCLK to 3V66
3V66 to PCI
When rising edges line up
3V66 leads
1.5–3.5
0
PCI to IOAPIC
48M (0,1)
Async
Document #: 38-07303 Rev. **
Page 6 of 18
C9835
Table 4. Group Timing Relationships and Tolerances (continued)
CPU = 66.6 MHz, SDRAM = 100 MHz
CPU = 133.3MHz, SDRAM = 133.3MHz
Offset(ns)
3.75
Tolerance(ps)
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
500
500
500
500
1000
N/A
180 degrees phase shift
0
SDRAM/DCLK to 3V66
3V66 to PCI
3.75
1.5–3.5
0
3V66 leads
PCI to IOAPIC
48M (0,1)
Async
is high indicates the end of a data transfer cycle. Data is
always sent as complete 8-bit bytes, after which an
acknowledge is generated. The first byte of a transfer cycle is
an 8-bit address. The LSB address Byte = 0 in write mode.
2-Wire SMBUS Control Interface
The 2-wire control interface implements a read/write slave
only interface according to SMBus specification. (SeeFigure 5
below). The device can be read back by using standard
SMBUS command bytes. Sub addressing is not supported,
thus all preceding bytes must be sent in order to change one
of the control bytes. The 2-wire control interface allows each
clock output to be individually enabled or disabled. 100 Kbits/s
(standard mode) data transfer is supported.
The device will respond to transfers of 10 bytes (max) of data.
The device will generate an acknowledge (low) signal on
SDATA following reception of each byte. Data is transferred
MSB first at a max rate of 100kbits/s. This device will also
respond to a D3 address which sets it in a read mode. It will
not respond to any other control interface conditions, and
previously set control registers are retained.
During normal data transfer, the SDATA signal only changes
when the SCLK signal is low, and is stable when SCLK is high.
There are two exceptions to this. A high to low transition on
SDATA while SCLK is high is used to indicate the start of a data
transfer cycle. A low to high transition on SDATA while SCLK
When a clock driver is placed in power down mode, the
SMBUS signals SDATA and SCLK must be tri-stated. In power
down, the device retains all SMBUS programming information.
Transmit
ACK
ACK
ACK
ACK
ACK
Receive
COMMAND BYTE
BYTE COUNT
BYTE 0
(Valid)
BYTE N
(Valid)
1
1
0
1
0
0
1
0
(Don’t Care)
(Don’t Care)
DATA
MSB
LSB
8
8
8
8
CLK
START CONDITION
STOP CONDITION
Figure 5a (WRITE Cycle)
Transmit
ACK BYTE COUNT
BYTE 0
BYTE1
(Valid)
BYTE N
(Valid)
Receiv
ACK
ACK
ACK
ACK
1
1
0
1
0
1
0
1
(Valid)
(Valid)
DATA
MSB
LSB
8
8
8
8
CLK
START CONDITION
STOP CONDITION
Figure 5b (READ Cycle)
Figure 5. SMBus Communications Waveforms
Document #: 38-07303 Rev. **
Page 7 of 18
C9835
Although the data (bits) in these two bytes are considered
“don’t care,” they must be sent and will be acknowledged. After
the Command Code and the Byte Count have been acknowl-
edged, the sequence (Byte 0, Byte 1, and Byte 2) described
below will be valid and acknowledged.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
1) “Command Code “ byte
2) “Byte Count” byte.
Byte 0: CPU Clock Register (1 = Enable, 0 = Disable)
Bit
7
@Pup[15]
Pin#[16]
Description
Description
Description
1
1
1
1
0
1
1
0
36
49
50
52
–
VCH_CLK
6
CPU2
5
CPU1
4
CPU0
3
Spread Spectrum ( 1 = enabled)
48M1(DOT)
48M0(USB)
Reserved. Set to 0
2
26
25
–
1
0
Byte 1: SDRAM Clock Register (1 = Enable, 0 = Disable)
Bit
7
@Pup[15]
Pin#[16]
0
–
Reserved. Set to 0
Reserved. Set to 0
SDRAM5
0
1
1
–
6
39
40
5
SDRAM4
4
3
1
1
42
43
SDRAM3
SDRAM2
2
1
1
45
46
SDRAM1
SDRAM0
1
0
Byte 2: 3C66 Clock Register (1 = Enable, 0 = Disable)
Bit
7
@Pup[15]
Pin#[16]
1
9
3V66_2 (AGP)
3V66_1
1
1
8
7
6
3V66_0
5
4
0
0
–
–
Reserved. Set to 0
Reserved. Set to 0
3
0
0
0
–
–
–
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
2
1
0
Byte 3: PCI Register (1 = Enable, 0 = Disable)
Bit
7
@Pup[17]
Pin#[18]
Description
0
–
Reserved. Set to 0
1
1
1
1
20
19
18
16
PCI6
PCI5
PCI4
PCI3
6
5
4
3
2
1
1
15
13
PCI2
PCI1
1
0
–
SDRAM 133- MHz Mode Enable. Default is disabled = “0,” enabled = “1”
0
Notes:
15. The @Pup column gives the default state at power-up.
16. The Pin# column lists the relevant pin number where applicable.
Document #: 38-07303 Rev. **
Page 8 of 18
C9835
Byte 4: VCH Clock Register (1 = Enable, 0 = Disable)
Bit
@Pup[17]
Pin#[18]
Description
VCH_CLK SSC Mode Enable
“0” = 48 MHZ (non-SSCG)
7
0
36
“1” = 66.6 MHz (SSCG applicable when Byte 0,Bit3 = 1)
6
5
4
3
2
1
0
0
0
0
0
0
0
0
–
–
–
–
–
–
–
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Byte 5: SSCG Control Register (1 = Enable, 0 = Disable)
Bit
7
@Pup[17]
Pin#[18]
Description
0
0
Spread Mode (0 = down, 1 = center)
–
–
–
–
–
–
–
–
Selects spread bandwidth. See Table 5.
6
5
0
0
Selects spread bandwidth. See Table 5.
Reserved. Set to 0
4
0
0
0
0
Reserved. Set to 0
Reserved. Set to 0
3
2
ESEL1 Expanded Freq. Selection MSB, See Table 2.
ESEL0 Expanded Freq. Selection LSB, See Table 2.
1
0
SMBus Test Circuitry
+ 5V
2.2 K
Device under
DATAIN
SDATA
SCLK
+ 5V
2.2 K
+ 5V
DATAOU
2.2 K
CLOCK
Figure 6. SMBUS Test Circuitry[19]
power up keeps the Spread Spectrum disabled, it is therefore,
important to have SMBUS accessibility to turn-on the Spread
Spectrum function. Once the Spread Spectrum is enabled, the
spread bandwidth option is selected by SST(0:2) in SMBUS
Byte 5, bits 5, 6, and 7 . See Table 7 below.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique applied here for
maximum efficiency in minimizing EMI radiation generated by
repetitive digital signals, mainly clocks. A clock accumulates
EM energy at the center frequency it is generating. Spread
Spectrum distributes this energy over a small frequency
bandwidth therefore distributing an even amount of energy
over a wider spectrum. This technique is achieved by
modulating the clock either down or around the center (see
Figure 7 below) of its resting frequency by a certain
percentage (which also determines the energy distribution
bandwidth). In this device, Spread Spectrum is enabled by
In Down Spread mode the center frequency is shifted down
from its rested (non-spread) value by ½ of the total spread %
(e.g., assuming the center frequency is 100 MHz in
non-spread mode; when down spread of –0.5% is enabled,
the center frequency shifts to 99.75 MHz.). In Center Spread
Mode, the center frequency remains the same as in
non-spread mode.
setting SMBUS Byte0,Bit3 = 1. The default of the device at
Notes:
17. The @Pup column gives the default state at power-up
18. The Pin# column lists the relevant pin number where applicable.
Document #: 38-07303 Rev. **
Page 9 of 18
C9835
Downspread
Center Spread
Figure 7. Spread Spectrum
Spread Spectrum Selection Tables
Table 5. (I²C BYTE 5 Bit 7=0), Down Spread
I²C Byte 5
Table 6. (I²C BYTE 5 Bit 7=0), Center Spread
I²C Byte 5
Bit
Bit
Spread %
Spread %
6
0
0
1
1
5
0
1
0
1
6
0
0
1
1
5
0
1
0
1
–0.5
–0.7
–1.0
–1.5
±0.25
±0.35
±0.5
±0.75
Note:
19. Buffer is 7407 with VCC@ 5.0V.
Document #: 38-07303 Rev. **
Page 10 of 18
C9835
Maximum Ratings
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:....................................0°C to +85°C
Maximum ESD Protection.............................................. 2 KV
Maximum Power Supply: ................................................5.5V
This device contains circuitry that protects the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
VSS < (VIN or VOUT) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDD = VDDS = 3.3V ± 5%, VDDC = VDDI = 2.5V ± 5%, TA = 0°C to +70°C[20]
Parameter
VIL1
Description
Input Low Voltage
Conditions
Min.
Typ.
Max.
Units
V
Note 21
1.0
VIH1
Input High Voltage
2.0
V
VIL2
Input Low Voltage
Note 22
1.0
V
VIH2
Input High Voltage
2.2
V
IIL1
Input Low Current (@VIL = VSS
)
For internal pull-up resistors[23]
–20
20
10
295
60
75
90
1
µA
µA
µA
mA
mA
mA
mA
mA
mA
pF
pF
nH
pF
V
IIH1
Input High Current (@VIH =VDD
Three-state leakage Current
Dynamic Supply Current
)
Ioz
Idd3.3V
Idd2.5V
CPU @ 66 MHz
CPU @ 100 MHz
CPU @ 133 MHz
PD# = “0”
Dynamic Supply Current
Ipd3.3V
Ipd2.5V
Cin
Power Down Supply Current
Power Down Supply Current
Input pin capacitance
Output pin capacitance
Pin inductance
PD# = “0”
1
5
Cout
6
Lpin
7
Cxtal
VBIAS
Txs
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Measured from Pin to Ground[24]
From stable 3.3V power supply.
34
36
38
0.7VDD
40
0.3VDD
VDD/2
µs
Table 7. Maximum Output Load
Clock Name
Max Load (in pF)
CPU(0:2), IOAPIC(0:1), REF, 48M0 (USB), VCH_CLK
PCI(0:6), SDRAM(0:5), DCLK, 3V66(0:2)
48M1 (DOT)
20
30
15
Notes:
20. All outputs loaded per Table 7.
21. Applicable to input signals : SEL(0:1), PD# (pull-up).
22. Applicable to SDATA and SCLK.
23. Internal pull-up and pull-down resistors affect this current.
24. See Applications data that is presented later in this datasheet on crystal interfacing.
Document #: 38-07303 Rev. **
Page 11 of 18
C9835
AC Parameters
133 MHz Host
100 MHz Host
66 MHz Host
Parameter
Description
Units
Min.
Max.
Min.
Max.
Min.
Max.
CPU
TPeriod
THIGH
TLOW
Tr / Tf
CPU(0:2) period[25,26]
CPU(0:2) high time[30]
CPU(0:2) low time[31]
CPU(0:2) rise and fall times[27]
CPU0 to any CPU Skew[26,29]
CPU(0:2) Cycle to Cycle Jitter[26,29]
7.5
1.87
1.67
0.4
8.0
10.0
3.0
10.5
15.0
5.2
15.5
ns
ns
ns
ns
ps
ps
2.8
5.0
1.6
150
250
0.4
1.6
150
250
0.4
1.6
150
250
TSKEW
TCCJ
SDRAM
TPeriod
SDRAM(0:5) 100 MHz and DCLK
period[25,26]
10.0
3.0
10.5
10.0
3.0
10.5
10.0
3.0
10.5
ns
ns
ns
ns
ps
ps
THIGH
TLOW
Tr / Tf
SDRAM(0:5) 100 MHz and DCLK high
time[30]
SDRAM(0:5) 100 MHz and DCLK low
time[31]
2.8
2.8
2.8
SDRAM(0:5) 100 MHz and DCLK rise and
fall times[27]
0.4
1.6
250
250
0.4
1.6
250
250
0.4
1.6
250
250
TSKEW
TCCJ
SDRAM(0:5) 100 MHzand DCLK
Skew[26,29]
SDRAM(0:5) 100 MHz, DCLK Cycle to
Cycle Jitter[26,29]
IOAPIC
TPeriod
IOAPIC(0,1) period[25,26]
30.0
12.0
12.0
0.4
30.0
12.0
12.0
0.4
30.0
12.0
12.0
0.4
ns
ns
ns
ns
ps
ps
THIGH
TLOW
Tr / Tf
IOAPIC(0,1) high time[30]
IOAPIC(0,1) low time[31]
IOAPIC(0,1) rise and fall times[27]
IOAPIC(0,1) Skew[26,29]
IOAPIC(0,1) Cycle to Cycle Jitter[26,29]
N/S
1.6
1.6
250
500
1.6
250
500
TSKEW
TCCJ
250
500
3V66
TPeriod
3V66-(0:2) period[25,26]
15.0
5.25
5.05
0.5
16.0
15.0
5.25
5.05
0.5
16.0
15.0
5.25
5.05
0.5
16.0
ns
ns
ns
ns
ps
ps
THIGH
TLOW
Tr / Tf
3V66-(0:2) high time[30]
3V66-(0:2) low time[31]
3V66-(0:2) rise and fall times[28]
(Any 3V66) to (any 3V66) Skew[26,29]
3V66-(0:2) Cycle to Cycle Jitter[26,29]
2.0
175
500
2.0
175
500
2.0
175
500
TSKEW
TCCJ
PCI_F
TPeriod
PCI(_F,1:6) period[25,26]
PCI(_F, 1:6) high time[30]
30.0
12.0
30.0
12.0
30.0
12.0
ns
ns
THIGH
Notes:
25. This parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818 MHz.
26. All outputs loaded per Table 6. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for 2.5V signals (see Figure 8).
27. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals (see
Figure 8).
28. Measured from when both SEL1 and SEL0 are switched to high (enable).
29. This measurement is applicable with Spread ON or Spread OFF.
30. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals (see Figure 8).
31. Probes are placed on the pins, and measurements are acquired at 0.4V.
Document #: 38-07303 Rev. **
Page 12 of 18
C9835
AC Parameters (continued)
133 MHz Host
100 MHz Host
66 MHz Host
Parameter
Description
Units
Min.
12.0
0.5
Max.
Min.
12.0
0.5
Max.
Min.
12.0
0.5
Max.
TLOW
Tr / Tf
PCI(_F, 1:6) low time[31]
ns
ns
ps
ps
PCI(_F, 1:6) rise and fall times[27]
(Any PCI) to (Any PCI) Skew[26,29]
PCI(_F, 1:6) Cycle to Cycle Jitter[26,29]
2.0
500
500
2.0
500
500
2.0
500
500
TSKEW
TCCJ
DOT and USB
TPeriod
DOT and USB (48M[0,1]) period
20.8299 20.8333 20.8299 20.8333 20.829 20.833
ns
(conforms to +167 ppm max) [25,26]
DOT and USB rise and fall times[27]
DOT and USB Cycle to Cycle Jitter[26,29]
VCH_CLK Cycle to Cycle Jitter[26]
Tr / Tf
TCCJ
TCCJ
1.0
4.0
500
250
1.0
4.0
500
250
1.0
4.0
500
250
ns
ps
ps
REF
TPeriod
REF period[25,26]
69.8413
1.0
71.0
4.0
69.8413
1.0
71.0
4.0
69.8413
1.0
71.0
4.0
ns
ns
ps
Tr / Tf
TCCJ
REF rise and fall times[27]
REF Cycle to Cycle Jitter[26]
1000
1000
1000
tpZL, tpZH Output enable delay (all outputs)[28]
tpLZ, tpHZ Output disable delay (all outputs)[33]
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
ns
ns
ms
%
tstable
Tduty
All clock stabilization from power-up[32]
Duty cycle for all outputs[34]
45
55
45
55
45
55
Notes:
32. The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the
specifications.
33. Measured from when both SEL1 and SEL0 are switched to low (disable).
34. Device designed for Typical Duty Cycle of 50%.
Document #: 38-07303 Rev. **
Page 13 of 18
C9835
Output Buffer Characteristics
Table 8. CPU, IOAPIC
Parameter
IOH1
IOH2
IOL1
Description
Pull-up Current
Conditions
Vout =VDDC - 0.5V (or VDDI –0.5V)
Vout = 1.2V
Min.
–15
–26
12
Typ.
–31
–58
24
Max.
–51
–101
40
Units
mA
mA
mA
mA
Ω
Pull-up Current
Pull-down Current
Pull-down Current
Output Impedance
Vout = 0.4V
IOL2
Vout = 1.2V
27
56
93
Z0
13.5
45
Table 9. PCI, 3V66, VCH
Parameter
Description
Conditions
Vout =VDD – 0.5V
Vout = 1. 5V
Min.
–20
–30
9.4
28
Typ.
–25
–54
18
Max.
–33
–184
38
Units
mA
mA
mA
mA
Ω
IOH1
IOH2
IOL1
IOL2
Z0
Pull-up Current
Pull-up Current
Pull-down Current
Pull-down Current
Output Impedance
Vout = 0.4V
Vout = 1.5V
55
148
55
12
Table 10. 48M0(USB), 481(DOT), REF
Parameter
IOH1
IOH2
IOL1
Description
Pull-up Current
Conditions
Vout =VDD – 0.5V
Vout = 1. 5V
Min.
–12
–27
9
Typ.
–16
–43
13
Max.
–28
–92
27
Units
mA
mA
mA
mA
Ω
Pull-up Current
Pull-down Current
Pull-down Current
Output Impedance
Vout = 0.4V
IOL2
Vout = 1.5V
26
39
79
Z0
20
60
Table 11. SDRAM (VDD = VDDS = 3.3V ± 5%, VDDC = VDDI = 2.5V ± 5%, TA = 0°C to 70°C)
Parameter
IOH1
IOH2
IOL1
Description
Pull-up Current
Conditions
Vout =VDD – 0.5V
Min.
–28
–67
23
Typ.
–40
–107
34
Max.
–60
–184
53
Units
mA
mA
mA
mA
Ω
Pull-up Current
Vout = 1. 5V
Vout = 0.4V
Vout = 1.5V
Pull-down Current
Pull-down Current
Output Impedance
IOL2
64
98
159
24
Z0
10
Document #: 38-07303 Rev. **
Page 14 of 18
C9835
Test Measurement Condition
Output under Test
Probe
Load Cap
3.3V signals
2.5V signals
tDC
tDC
-
-
-
-
3.3V
2.5V
2.4V
1.5V
2.0V
1.25V
0.4V
0.4V
0V
0V
Tr
Tf
Tr
Tf
Figure 8.
Table 12. Suggested Oscillator Crystal Parameters
Parameter Description
Fo
Conditions
Min.
Typ.
Max.
Units
Frequency
Tolerance
14.17
14.31818
14.46
MHz
TC
TS
Note 35
±100
±100
PPM
PPM
Frequency Stability
Stability (TA – 10 to +60C)[35]
Parallel Resonant[35]
The crystal’s rated load[35]
Note 36
Operating Mode
CXTAL
RESR
Load Capacitance
20
40
pF
Effective Series Resistance (ESR)
Ohms
To obtain the maximum accuracy, the total circuit loading
capacitance should be equal to CXTAL. This loading capaci-
tance is the effective capacitance across the crystal pins and
includes the clock generating device pin capacitance (CFTG),
any circuit trace capacitance (CPCB) and any onboard discrete
load capacitance (CDISC).
Where:
CXTAL = the load rating of the crystal.
CXOUTFTG ....= the clock generators XIN pin effective device
internal capacitance to ground.
CXOUTFTG = the clock generators XOUT pin effective device
internal capacitance to ground.
The following formula and schematic illustrates the application
of the loading specification of a crystal (CXTAL) for a design.
CXINPCB = the effective capacitance to ground of the crystal
to device PCB trace.
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC
)
CXOUTPCB = the effective capacitance to ground of the crystal
to device PCB trace.
As an example and using a formula for this datasheet’s device,
a design that has no disrete loading capacitors (CDISC) and
each of the crystal to device PCB traces has a capacitance
(CPCB) to ground of 4pF (typical value) would calculate as:
CXINDISC = any discrete capacitance that is placed between
the XIN pin and ground.
CXOUTDISC= any discrete capacitance that is placed between
the XOUT pin and ground.
Notes:
35. For best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these
specifications.
36. Larger values may cause this device to to exhibit oscillator startup problems.
Document #: 38-07303 Rev. **
Page 15 of 18
C9835
XIN
CXINPCB
CXINDISC
CXINFTG
CXOUTPCB
CXOUTDISC
CXOUTFTG
XOUT
Clock Generator
Figure 9.
Therefore, to obtain output frequencies that are as close to this
datasheets specified values as possible, in this design
Ordering Information
example, you should specify a parallel cut crystal that is
designed to work into a load of 20pF.
Part Number
IMIC9835CY
Package Type
56-pin Shrunk Small Outlie package (SSOP)
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
IMIC9835CYT
IMIC9835CT
IMIC9835CTT
56-pin Shrunk Small Outlie package (SSOP)–Tape and Reel
56-pin Thin Shrunk Small Outlie package (TSSOP)
56-pin Thin Shrunk Small Outlie package (TSSOP)–Tape and Reel Commercial, 0° to 70°C
Package Diagrams
56-lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
51-85060-B
Document #: 38-07303 Rev. **
Page 16 of 18
C9835
Package Diagrams (continued)
56-lead Shrunk Small Outline Package O56
51-85062-C
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips.
Intelis aregistered trademark of Intel Corporation. All product and company names mentioned in this document are thetrademarks
of their respective holders.
Document #: 38-07303 Rev. **
Page 17 of 18
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
C9835
Document Title: C9835 Low-EMI Clock Generator for Intel® Mobile 133-MHz/3 SO-DIMM Chipset Systems
Document Number: 38-07373
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
113556
05/28/02
DMG
New Data Sheet (converted from IMI format)
Document #: 38-07303 Rev. **
Page 18 of 18
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