CEP630N [CET]
N-Channel Enhancement Mode Field Effect Transistor; N沟道增强型网络场效晶体管型号: | CEP630N |
厂家: | CHINO-EXCEL TECHNOLOGY |
描述: | N-Channel Enhancement Mode Field Effect Transistor |
文件: | 总4页 (文件大小:371K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CEP630N/CEB630N
CEF630N
N-Channel Enhancement Mode Field Effect Transistor
FEATURES
Type
VDSS
200V
200V
200V
RDS(ON)
0.36Ω
0.36Ω
0.36Ω
ID
@VGS
10V
CEP630N
CEB630N
CEF630N
9A
9A
9A d
10V
10V
D
Super high dense cell design for extremely low RDS(ON)
High power and current handing capability.
Lead free product is acquired.
.
G
S
CEB SERIES
CEP SERIES
TO-263(DD-PAK)
TO-220
CEF SERIES
TO-220F
ABSOLUTE MAXIMUM RATINGS T = 25 C unless otherwise noted
c
Limit
Parameter
Symbol
Units
TO-220/263
TO-220F
Drain-Source Voltage
VDS
VGS
ID
200
V
V
Gate-Source Voltage
±20
9
36
9 d
36 d
33
Drain Current-Continuous
Drain Current-Pulsed a
A
e
IDM
A
Maximum Power Dissipation @ TC = 25 C
- Derate above 25 C
78
W
PD
0.63
0.27
W/ C
C
Operating and Store Temperature Range
TJ,Tstg
-55 to 150
Thermal Characteristics
Parameter
Symbol
RθJC
Limit
Units
C/W
C/W
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
1.6
62.5
3.7
65
RθJA
Rev 3. 2008.Oct.
Details are subject to change without notice .
http://www.cetsemi.com
1
CEP630N/CEB630N
CEF630N
Electrical Characteristics T = 25 C unless otherwise noted
c
4
Parameter
Off Characteristics
Symbol
Test Condition
Min
Typ
Max
Units
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics b
BVDSS
IDSS
VGS = 0V, ID = 250µA
VDS = 160V, VGS = 0V
VGS = 20V, VDS = 0V
VGS = -20V, VDS = 0V
200
V
25
µA
nA
nA
IGSSF
IGSSR
100
-100
Gate Threshold Voltage
Static Drain-Source
VGS(th)
RDS(on)
VGS = VDS, ID = 250µA
VGS = 10V, ID = 5A
2
4
V
0.30
0.36
Ω
On-Resistance
Dynamic Characteristics c
Forward Transconductance
Input Capacitance
gFS
Ciss
Coss
Crss
VDS = 10V, ID = 5A
4
S
930
130
25
pF
pF
pF
VDS = 25V, VGS = 0V,
f = 1.0 MHz
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics c
Turn-On Delay Time
td(on)
tr
td(off)
tf
24
15
116
25
19
3
ns
ns
48
30
VDD = 100V, ID = 5A,
VGS = 10V, RGEN = 50Ω
Turn-On Rise Time
Turn-Off Delay Time
ns
232
50
Turn-Off Fall Time
ns
24.7
Total Gate Charge
Qg
nC
nC
nC
VDS = 160V, ID = 5.9A,
VGS = 10V
Gate-Source Charge
Qgs
Qgd
Gate-Drain Charge
5
Drain-Source Diode Characteristics and Maximun Ratings
f
IS
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage b
9
A
V
VGS = 0V, IS = 9A g
1.5
VSD
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature .
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% .
c.Guaranteed by design, not subject to production testing.
d.Limited only by maximum temperature allowed .
e.Pulse width limited by safe operating area .
f.Full package I
= 5.9A .
S(max)
g.Full package V test condition I = 5.9A .
SD
S
2
CEP630N/CEB630N
CEF630N
12
10
8
15
12.5
10
VGS=10,9,8,7,6V
V
GS=6V
6
7.5
4
5
25 C
2
2.5
TJ=125C
-55 C
V
GS=4V
0
0
0
2
4
6
8
10
12
0
1.5
3.0
4.5
6.0
7.5
VDS, Drain-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1800
1500
1200
900
600
300
0
ID=5A
VGS=10V
C
iss
C
oss
C
rss
-100
-50
0
50
100
150
200
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature( C)
Figure 3. Capacitance
Figure 4. On-Resistance Variation
with Temperature
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
VDS=VGS
ID=250µA
V
GS=0V
101
100
10-1
-50 -25
0
25 50 75 100 125 150
0.4
0.7
1.0
1.3
1.6
1.9
TJ, Junction Temperature( C)
VSD, Body Diode Forward Voltage (V)
Figure 5. Gate Threshold Variation
with Temperature
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CEP630N/CEB630N
CEF630N
10
8
102
VDS=160V
ID=5.9A
RDS(ON)Limit
100µs
101
1ms
6
10ms
100ms
DC
4
100
2
TC=25 C
TJ=175 C
Single Pulse
0
10-1
100
101
102
103
0
5
10
15
20
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
on
t
toff
d(off)
t
r
t
d(on)
OUT
RL
t
f
t
VIN
90%
10%
90%
D
OUT
V
V
VGS
10%
INVERTED
RGEN
G
90%
50%
50%
S
IN
V
10%
PULSE WIDTH
Figure 10. Switching Waveforms
Figure 9. Switching Test Circuit
100
D=0.5
0.2
0.1
10-1
PDM
0.05
t1
t2
0.02
0.01
1. Rθ JC (t)=r (t) * Rθ JC
2. Rθ JC=See Datasheet
3. TJM-TC = P* Rθ JC (t)
4. Duty Cycle, D=t1/t2
Single Pulse
10-2
10-5
10-4
10-3
10-2
10-1
100
101
Square Wave Pulse Duration (sec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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