ACPL-P456-560E [AVAGO]
ACPL-P456 and ACPL-W456 Intelligent Power Module and Gate Drive Interface Optocouplers; ACPL- P456和ACPL- W456智能功率模块和门驱动接口光电耦合器
| 型号： | ACPL-P456-560E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | ACPL-P456 and ACPL-W456 Intelligent Power Module and Gate Drive Interface Optocouplers |
| 文件： | 总12页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-P456 and ACPL-W456
Intelligent Power Module and Gate Drive Interface Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-P456 and ACPL-W456 contain a GaAsP LED ꢀ Performance Specified for Common IPM Applications
optically coupled to an integrated high gain photo
detector. Minimized propagation delay difference
between devices make these optocouplers excellent
solutions for improving inverter efficiency through
reduced switching dead time. Specifications and perfor-
mance plots are given for typical IPM applications.
Over Industrial Temperature Range.
ꢀ Short Maximum Propagation Delays
ꢀ Minimized Pulse Width Distortion (PWD)
ꢀ Very High Common Mode Rejection (CMR)
ꢀ High CTR.
ꢀ Available in Stretched SO-6 package with 8 mm
Functional Diagram
creepage and clearance.
ꢀ Safety Approval:
ANODE
N.C.
1
2
3
6
5
4
VCC
UL Recognized with 3750 V
Vrms for 1 minute for ACPL-W456 devices) per
UL1577.
for 1 minute (5000
rms
VO
CATHODE
Ground
SHIELD
CSA Approved.
IEC/EN/DIN EN 60747-5-5 Approved with V
=
IORM
= 891 Vpeak
Note: A 0.1 μF bypass capacitor must be connected between pins 4 and 6.
1140 Vpeak (ACPL-W456) and V
(ACPL-P456) for Option 060.
IORM
Truth Table
Specifications
ꢀ Wide operating temperature range: –40°C to 100°C.
ꢀ Maximum propagation delay t = 400 ns, t = 490 ns
LED
ON
V
O
LOW
OFF
HIGH
PHL
PLH
ꢀ Maximum Pulse Width Distortion (PWD) = 450 ns.
ꢀ 15 kV/μs minimum common mode rejection (CMR) at
V
CM
= 1500 V.
ꢀ CTR > 44% at I = 10 mA
F
Applications
ꢀ IPM Isolation
ꢀ Isolated IGBT/MOSFET Gate Drive
ꢀ AC and Brushless DC Motor Drives
ꢀ Industrial Inverters
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-P456 and ACPL-W456 are UL Recognized with 3750 Vrms (5000 Vrms for ACPL-W456) for 1 minute per UL1577
and are approved under CSA Component Acceptance Notice #5, File CA 88324.
Option
Surface
Mount
Tape
& Reel
IEC/EN/DIN EN
60747-5-5
Part number
RoHS Compliant
-000E
Package
Quantity
X
X
X
X
100 per tube
1000 per reel
100 per tube
1000 per reel
-500E
X
X
ACPL-P456
ACPL-W456
Stretched
SO-6
-060E
X
X
-560E
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P456-560E to order product of Stretched SO-6 package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-P456-000E to order product of Stretched SO-6 package in tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
ACPL-P456 Stretched SO-6 Package, 7 mm clearance
+
0.254
4.580
0.180
0
10.7
0.421
0.381 0.127
0.015 0.005
1.27 BSG
0.050
+0.010
0.000
0.76
0.030
-
1.27
0.050
2.16
0.085
7.62
0.300
3.180 0.127
0.125 0.005
6.81
0.45
0.268
1.590 0.127
0.063 0.005
0.018
45°
7°
7°
7°
7°
NOM.
0.20 0.10
0.008 0.004
0.254 0.050
0.010 0.002
Floating Lead Protusions max. 0.25 [0.01]
5
1
0.250
Dimensions in Millimeters [ Inches ]
Lead Coplanarity= 0.1mm [0.004 Inches ]
0.040 0.010
9.7 0.250
0.382 0.010
2
ACPL-W456 Stretched SO-6 Package, 8 mm clearance
+
0.254
4.580
1.27 BSG
0.050
0
0.760
0.030
0.381 0.127
0.015 0.005
12.650
0.498
+
0.010
0.180
-
0.000
1
6
4
2
3
5
7.62
[0.300]
1.905
0.075
1.270
0.050
+
0
0.127
6.807
+
0.005
0.268
-
0.000
1.590 0.127
0.063 0.005
3.180 0.127
0.125 0.005
45°
0.45
0.018
0.20 0.10
0.008 0.004
0.254 0.050
0.010 0.002
0.750 0.250
[0.0295 0.010]
35° NOM.
Floating Lead protusion max. 0.25[0.01]
11.500 0.25
0.453 0.010
Dimensions in millimeters [Inches]
Lead Coplanarity=0.1mm [0.004 Inches]
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-P456 and ACPL-W456 are approved by the following organizations:
IEC/EN/DIN EN 60747-5-5 (Option 060 only)
Approved with Maximum Working Insulation Voltage
UL
Approval under UL 1577, component recognition
program up to V = 3750 V
W456). File E55361.
V
= 1140 Vpeak (ACPL-W456) and V
= 891 Vpeak
(or 5000 V
for ACPL-
IORM
(ACPL-P456).
IORM
ISO
RMS
RMS
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
3
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (ACPL-P456/W456 Option 060)
Description
Symbol
ACPL-W456
ACPL-P456
Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
I – IV
I – IV
I – III
I – III
I – II
I – IV
I – IV
I – III
I – III
for rated mains voltage ≤ 1000 Vrms
Climatic Classification
55/100/21
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
2
2
VIORM
VPR
1140
891
Vpeak
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
2138
1671
Input to Output Test Voltage, Method a*
VIORM x 1.5=VPR, Type and Sample Test, tm=10 sec,
Partial discharge < 5 pC
VPR
1824
8000
1425
6000
Vpeak
Vpeak
Highest Allowable Overvoltage
VIOTM
(Transient Overvoltage tini = 60 sec)
Safety-limiting values – maximum values
allowed in the event of a failure.
Case Temperature
Input Current
Output Power
TS
175
230
600
175
230
600
°C
mA
mW
IS, INPUT
PS, OUTPUT
Insulation Resistance at TS, VIO = 500 V
RS
>109
>109
ꢁ
*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol ACPL-P456 ACPL-W456
Units Conditions
Minimum External Air Gap
(External Clearance)
L(101)
7.0
8.0
mm
mm
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
(External Creepage)
L(102)
8.0
8.0
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
0.08
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Minimum Internal Tracking
(Internal Creepage)
NA
>175
IIIa
NA
>175
IIIa
mm
V
Measured from input terminals to output
terminals, along internal cavity.
Tracking Resistance
(Comparative Tracking Index)
CTI
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
4
Table 3. Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
-55
-40
Max.
125
100
25
Units
°C
Note
Storage Temperature
Operating Temperature
Average Input Current
TA
°C
IF(avg)
IF(peak)
mA
mA
1
2
Peak Input Current
50
(50% duty cycle, <1 ms pulse width)
Peak Transient Input Current
(<1 ꢀs pulse width, 300 pps)
IF(tran)
1.0
A
Reverse Input Voltage (Pin 3-1)
Average Output Current (Pin 5)
Output Voltage (Pin 5-4)
Supply Voltage (Pin 6-4)
VR
5
V
IO(avg)
VO
15
30
30
100
145
mA
-0.5
-0.5
VCC
PO
Output Power Dissipation
Total Power Dissipation
mW
mW
3
4
PT
Infrared and Vapor Phase Reflow Tem-
perature
See Reflow Thermal Profile.
Table 4. Recommended Operating Conditions
Parameter
Symbol
Min.
4.5
0
Max.
30
Units
Note
Power Supply Voltage
Output Voltage
VCC
VO
V
30
V
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
IF(on)
VF(off)
TA
10
-5
20
mA
V
0.8
100
-40
°C
Table 5. Electrical Specifications
Over recommended operating conditions unless otherwise specified: T = -40°C to +100°C, V = +4.5 V to 30 V, I
=
A
CC
F(on)
10 mA to 20 mA, V
) = -5 V to 0.8 V
F(off
Parameter
Symbol
CTR
IOL
Min.
44
Typ.* Max. Units
Test Conditions
Fig.
Note
Current Transfer Ratio
90
%
IF = 10 mA, VO = 0.6 V
IF = 10 mA, VO = 0.6 V
IO = 2.4 mA
5
Low Level Output Current
Low Level Output Voltage
Input Threshold Current
High Level Output Current
High Level Supply Current
Low Level Supply Current
Input Forward Voltage
4.4
9.0
0.3
1.5
5
mA
V
1, 2
VOL
0.6
5.0
50
ITH
mA
ꢀA
mA
mA
V
VO = 0.8 V, IO = 0.75 mA
VF = 0.8 V
1
3
9
IOH
ICCH
ICCL
0.6
0.6
1.5
-1.6
1.3
1.3
1.8
VF = 0.8 V, VO = Open
IF = 10 mA, VO = Open
IF = 10 mA
9
9
VF
4
Temperature Coefficient
of Forward Voltage
ΔVF/ΔTA
mV/°C IF = 10 mA
Input Reverse Breakdown Voltage
Input Capacitance
BVR
CIN
5
V
IR = 10 ꢀA
60
pF
f = 1 MHz, VF = 0 V
*All typical values at 25°C, V = 15 V.
CC
5
Table 6. Switching Specifications (R = 20 kΩ)
L
Over recommended operating conditions unless otherwise specified. T = -40°C to +100°C, V = +4.5 V to 30 V, I
=
A
CC
F(on)
10 mA to 20 mA, V
= -5 V to 0.8 V
F(off)
Parameter
Symbol
Min.
Typ.
Max. Units Test Conditions
Fig.
Note
Propagation Delay Time
to Low Output Level
tPHL
30
200
400
ns
CL = 100
pF
IF(on) = 10 mA,
F(off) = 0.8 V,
VCC = 15.0 V,
THLH = 2.0 V,
VTHHL = 1.5 V
5, 7 -11
8, 9
V
100
400
ns
ns
CL = 10 pF
V
Propagation Delay Time
to High Output Level
tPLH
270
550
CL = 100
pF
130
200
ns
ns
CL = 10 pF
Pulse Width Distortion
PWD
450
450
CL = 100
pF
13
10
11
12
Propagation Delay Difference
Between Any 2 Parts
tPLH-tPHL -150
200
30
ns
Output High Level Common
Mode Transient Immunity
|CMH|
|CML|
15
15
kV/ꢀs IF = 0 mA, VCC = 15.0 V,
VO > 3.0 V CL = 100 pF,
6
V
CM = 1500 VP-P
,
Output Low Level Common
Mode Transient Immunity
30
kV/ꢀs IF = 10 mA,
O < 1.0 V
TA = 25°C
V
*All typical values at 25°C, V = 15 V.
CC
Table 7. Package Characteristics
Parameter
Symbol Min.
Typ.
Max. Units Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage
VISO
3750
Vrms RH < 50%, t = 1 min,
TA = 25°C
6, 7
5000 (For ACPL-W456)
Input-Output Resistance
Input-Output Capacitance
RI-O
CI-O
1012
0.6
ꢁ
VI-O = 500 Vdc
Freq=1 MHz
6
6
pF
Notes:
1. Derate linearly above 90°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90°C free-air temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90°C free-air temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90°C free-air temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (I ) to the forward LED input current (I ) times 100.
O
F
6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
for 1 second (leakage detection
RMS
current limit, I ≤ 5 ꢀA) ; each optocoupler under ACPL-W456 is proof tested by applying an insulation test voltage ≥ 6000 V
for 1 second
I-O
RMS
(leakage detection current limit, I ≤ 5 μA).
I-O
8. Pulse: f = 20 kHz, Duty Cycle = 10%.
9. Use of a 0.1 ꢀF bypass capacitor connected between pins 4 and 6 can improve performance by filtering power supply line noise.
10. The difference between t
Specifications section.)
and t
between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay
PLH
PHL
11. Common mode transient immunity in a Logic High level is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in a Logic High state (i.e., V > 3.0 V).
O
12. Common mode transient immunity in a Logic Low level is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in a Logic Low state (i.e., V < 1.0 V).
O
13. Pulse Width Distortion (PWD) is defined as |t - t | for any given device.
PHL PLH
6
10
8
1.05
1.00
0.95
0.90
0.85
0.80
6
4
IF = 10 mA
VO = 0.6 V
VO = 0.6 V
2
0
100 C
25 C
-40 C
0
5
10
15
20
20
TA – TEMPERATURE – C
-40
-20
0
40
60
80
100
IF – FORWARD CURRENT – mA
Figure 1. Typical Transfer Characteristics.
Figure 2. Normalized Output Current vs. Temperature.
1000
2.0
TA = 25 C
VF = 0.8 V
IF
V
CC = VO = 4.5 V OR 30 V
100
10
+
1.5
1.0
0.5
0
VF
-
4.5 V
30 V
1.0
0.1
0.01
0.001
20
TA – TEMPERATURE – C
-40
-20
0
40
60
80
100
1.10
1.20
1.30
1.40
1.50
1.60
VF – FORWARD VOLTAGE – VOLTS
Figure 3. High Level Output Current vs. Temperature.
Figure 4. Input Current vs. Forward Voltage.
IF(ON) = 10 mA
1
2
3
6
I
f
20 kΩ
VOUT
0.1μF
+
-
t
t
r
f
+
-
VCC = 15
V
5
O
CL*
90%
10%
90%
10%
4
SHIELD
* TOTAL LOAD
CAPACITANCE
V
V
THHL
THLH
t
t
PLH
PHL
Figure 5. Propagation Delay Test Circuit.
7
IF
V
CM
1
2
3
6
20 kΩ
VOUT
V
δV
δt
CM
Δt
0.1 μF
5
=
+
-
VCC = 15
B
A
100 pF *
OV
4
+
SHIELD
Δt
* 100 pF TOTAL
CAPACITANCE
VFF
-
V
O
V
V
CC
SWITCH AT A: I = 0 mA
F
VCM = 1500V
V
O
OL
SWITCH AT B: I = 10 mA
F
Figure 6. CMR Test Circuit and Waveforms.
500
800
IF = 10 mA
VCC = 15 V
IF = 10 mA
VCC = 15 V
CL = 100 pF
TA = 25 C
CL = 100 pF
RL = 20 kΩ (EXTERNAL)
400
300
200
100
600
400
200
tPLH
tPHL
tPLH
tPHL
20
TA – TEMPERATURE – C
20
RL – LOAD RESISTANCE – kΩ
-40
-20
0
40
60
80
100
0
10
30
40
50
Figure 7. Propagation Delay with External 20 kΩ RL vs. Temperature.
Figure 8. Propagation Delay vs. Load Resistance.
1400
1200
1400
IF = 10 mA
CL = 100 pF
RL = 20 kΩ
TA = 25 C
IF = 10 mA
VCC = 15 V
1200
RL = 20 KΩ
TA = 25 C
1000
800
600
400
200
0
1000
tPLH
tPHL
800
600
400
tPLH
tPHL
200
0
5
10
15
20
25
30
0
100
200
300
400
500
V
CC – SUPPLY VOLTAGE – V
CL – LOAD CAPACITANCE – pF
Figure 9. Propagation Delay vs. Load Capacitance.
Figure 10. Propagation Delay vs. Supply Voltage.
8
Another cause of CMR failure for a shielded optocoupler
is direct coupling to the optocoupler output pins through
LEDO1
500
VCC = 15 V
CL = 100 pF
RL = 20 kΩ
TA = 25 C
tPLH
tPHL
C
in Figure 14. Many factors influence the effect and
400
300
200
100
magnitude of the direct coupling including: the position
of the LED current setting resistor and the value of the
capacitor at the optocoupler output (C ).
L
CLEDP
1
2
3
6
5
4
CLED01
CLEDN
SHIELD
0
5
10
15
20
IF – FORWARD LED CURRENT – mA
Figure 14. Optocoupler Input to Output Capacitance Model for Shielded
Optocouplers.
Figure 11. Propagation Delay vs. Input Current.
CMR With The LED On (CMR )
L
Applications Information
A high CMR LED drive circuit must keep the LED on
during common mode transients. This is achieved by
overdriving the LED current beyond the input threshold
so that it is not pulled below the threshold during a
transient. The recommended minimum LED current of 10
LED Drive Circuit Considerations For Ultra High CMR
Performance
Without a detector shield, the dominant cause of opto-
coupler CMR failure is capacitive coupling from the input
side of the optocoupler, through the package, to the
detector IC as shown in Figure 13. The ACPL-P456/W456
improve CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the ca-
pacitive coupling between the LED and the optocoupler
output pin and output ground as shown in Figure 14.
This capacitive coupling causes perturbations in the LED
current during common mode transients and becomes
the major source of CMR failures for a shielded optocou-
pler. The main design objective of a high CMR LED drive
circuit becomes keeping the LED in the proper state (on
or off) during common mode transients. For example,
the recommended application circuit (Figure 12), can
achieve 15 kV/μs CMR while minimizing component
complexity. Note that a CMOS gate is recommended in
Figure 12 to keep the LED off when the gate is in the high
state.
mA provides adequate margin over the maximum I of
TH
4.0 mA (see Figure 1) to achieve 15 kV/μs CMR.
The placement of the LED current setting resistor effects
the ability of the drive circuit to keep the LED on during
transients and interacts with the direct coupling to the
optocoupler output. For example, the LED resistor in
Figure 15 is connected to the anode. Figure 16 shows
the AC equivalent circuit for Figure 15 during common
mode transients. During a +dV /dt in Figure 16, the
CM
current available at the LED anode (Itotal) is limited by
the series resistor. The LED current (I ) is reduced from its
F
DC value by an amount equal to the current that flows
through C
and C
. The situation is made worse
LEDO1
LEDP
because the current through C
has the effect of
LEDO1
trying to pull the output high (toward a CMR failure) at
the same time the LED current is being reduced. For this
reason, the recommended LED drive circuit (Figure 12)
places the current setting resistor in series with the LED
cathode. Figure 17 is the AC equivalent circuit for Figure
12 during common mode transients. In this case, the
LED current is not reduced during a +dV /dt transient
CM
+5 V
1
2
3
6
because the current flowing through the package capaci-
20 kΩ
VOUT
0.1 μF
tance is supplied by the power supply. During a -dV
/
CM
+
-
VCC = 15 V
5
dt transient, however, the LED current is reduced by the
amount of current flowing through C . But, better
CL*
310 Ω
LEDN
4
SHIELD
CMR performance is achieved since the current flowing
CMOS
* 100 pF TOTAL
CAPACITANCE
in C
during a negative transient acts to keep the
LEDO1
output low.
Figure 12. Recommended LED Drive Circuit.
+5 V
1
2
3
6
310 Ω
20 kΩ
VOUT
0.1 μF
CLEDP
1
6
+
-
VCC = 15 V
5
CL*
2
5
4
4
SHIELD
CMOS
* 100 pF TOTAL
CAPACITANCE
3
CLEDN
Figure 15. LED Drive Circuit with Resistor Connected to LED Anode (Not
Recommended).
Figure 13. Optocoupler Input to Output Capacitance Model for Unshielded
Optocouplers.
9
ITOTAL
*
Since the open collector drive circuit, shown in Figure 18,
cannot keep the LED off during a +dV /dt transient, it is
ICLEDP
ICLED01
1
2
3
6
5
4
CM
IF
300 Ω
CLED01
20 kΩ
not desirable for applications requiring ultra high CMR
H
VOUT
performance. Figure 19 is the AC equivalent circuit for
Figure 18 during common mode transients. Essentially
100pF
all the current flowing through C
during a +dV /dt
LEDN
CM
CLEDN
SHIELD
transient must be supplied by the LED. CMR failures can
H
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING + dVCM /dt
occur at dv/dt rates where the current through the LED
and C
exceeds the input threshold. Figure 20 is an al-
LEDN
ternative drive circuit which does achieve ultra high CMR
performance by shunting the LED in the off state.
VCM
Figure 16. AC Equivalent Circuit for Figure 15 during Common Mode Tran-
sients.
+5 V
1
2
3
6
5
4
CLEDP
1
2
3
6
5
4
CLED01
20 kΩ
VOUT
+ V **-
SHIELD
R
Q1
100pF
CLEDN
*
SHIELD
ICLEDN
300 Ω
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR + dVCM /dt TRANSIENTS.
Figure 18. Not Recommended Open Collector LED Drive Circuit.
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE. VR < VF (OFF)DURING + dVCM/dt
CLEDP
1
2
3
6
5
4
CLED01
20kΩ
VOUT
VCM
100pF
Figure 17. AC Equivalent Circuit for Figure 12 during Common Mode Tran-
sients.
Q1
CLEDN
*
SHIELD
ICLEDN
300 Ω
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
TRANSIENTS.
FLOW FOR + dVCM /dt
CMR With The LED Off (CMR )
H
A high CMR LED drive circuit must keep the LED off (V
F
VCM
≤ V
) during common mode transients. For example,
F(OFF)
during a +dV /dt transient in Figure 17, the current
CM
Figure 19. AC Equivalent Circuit for Figure 18 during Common Mode Tran-
flowing through C
is supplied by the parallel com-
LEDN
sients.
bination of the LED and series resistor. As long as the
voltage developed across the resistor is less than V
+5 V
F(OFF)
the LED will remain off and no common mode failure
will occur. Even if the LED momentarily turns on, the
100 pF capacitor from pins 5-4 will keep the output from
dipping below the threshold. The recommended LED
drive circuit (Figure 12) provides about 10 V of margin
between the lowest optocoupler output voltage and a
1
2
3
6
5
4
SHIELD
3 V IPM threshold during a 15kV/μs transient with V
CM
= 1500 V. Additional margin can be obtained by adding
a diode in parallel with the resistor, as shown by the
dashed line connection in Figure 17, to clamp the voltage
Figure 20. Recommended LED Drive Circuit for Ultra High CMR.
across the LED below V
.
F(OFF)
10
IPM Dead Time and Propagation Delay Specifications
off. Note that the propagation delays used to calculate
PDD are taken at equal temperatures since the optocou-
plers under consideration are typically mounted in close
proximity to each other. (Specifically, previous equation
The ACPL-P456/W456 includes a Propagation Delay
Difference specification intended to help designers
minimize “dead time” in their power inverter designs.
Dead time is the time period during which both the high
and low side power transistors (Q1 and Q2 in Figure 21)
are off. Any overlap in Q1 and Q2 conduction will result
in large currents flowing through the power devices
between the high and low voltage motor rails.
are not the same as the t
max and t
min, over the
PLH
PHL
full operating temperature range, specified in the data
sheet.) This delay is the maximum value for the propaga-
tion delay difference specification which is specified at
450 ns for the ACPL-P456/W456 over an operating tem-
perature range of -40°C to 100°C.
To minimize dead time the designer must consider
the propagation delay characteristics of the optocou-
pler as well as the characteristics of the IPM IGBT gate
drive circuit. Considering only the delay characteristics
of the optocoupler (the characteristics of the IPM IGBT
gate drive circuit can be analyzed in the same way) it is
important to know the minimum and maximum turn on
(t ) and turn-off (t ) propagation delay specifications,
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time occurs in
the highly unlikely case where one optocoupler with
the fastest t
and another with the slowest t
are in
PLH
PHL
PHL
PLH
the same inverter leg. The maximum dead time in this
case becomes the sum of the spread in the t and t
preferably over the desired operating temperature range.
PLH
PHL
The limiting case of zero dead time occurs when the input
to Q1 turns off at the same time that the input to Q2 turns
on. This case determines the minimum delay between
LED1 turn-off and LED2 turn-on, which is related to the
worst case optocoupler propagation delay waveforms,
as shown in Figure 22. A minimum dead time of zero is
achieved in Figure 22 when the signal to turn on LED2
propagation delays as shown in Figure 23. The maximum
dead time is also equivalent to the difference between
the maximum and minimum propagation delay differ-
ence specifications. The maximum dead time (due to the
optocouplers) for the ACPL-P456/W456 are 600 ns (= 450
ns - (-150 ns)) over an operating temperature range of -
40°C to 100°C.
is delayed by (t
max - t
min) from the LED1 turn
PHL
PLH
IPM
ILED1
+HV
+5 V
VCC1
1
6
0.1 μF
20 kΩ
VOUT1
2
5
4
310 Ω
3
SHIELD
SHIELD
CMOS
ILED2
M
+5 V
VCC2
1
6
0.1 μF
20 kΩ
VOUT2
2
5
310 Ω
ACPL-P/W456
ACPL-P/W456
ACPL-P/W456
ACPL-P/W456
ACPL-P/W456
3
4
CMOS
-HV
Figure 21. Typical Application Circuit.
11
I
I
LED1
LED1
Q1 OFF
Q2 ON
Q1 OFF
Q2 ON
Q1 ON
V
V
OUT1
OUT2
Q1 ON
V
V
OUT1
OUT2
Q2 OFF
Q2 OFF
I
LED2
t
PLH
I
LED2
MIN.
t
PLH MAX.
t
PLH
MAX.
t
PHL
MIN.
t
PHL
MIN.
PDD*
MAX.
t
PDD* MAX. =
(t
PHL
MAX.
t
)
t
t
PLH- PHL MAX. = PLH MAX. - PHL MIN.
MAX.
DEAD TIME
*PDD = PROPAGATION DELAY DIFFERENCE
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
= (t
= (t
t
) + (t
t
)
PLH MAX. - PLH MIN.
PLH MAX. - PHL MIN.
PHL MAX. - PHL MIN.
PLH MIN. - PHL MAX.
t
) - (t
t
)
= PDD* MAX. - PDD* MIN.
Figure 22. Minimum LED Skew for Zero Dead Time.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
Figure 23. Waveforms for Deadtime Calculation.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0647EN
AV02-1306EN - July 31, 2010
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