ACPL-P481 [AVAGO]
Inverted Logic, High CMR Optocoupler for Intelligent Power Modules and IGBT/MOSFET Gate Drive;
| 型号： | ACPL-P481 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Inverted Logic, High CMR Optocoupler for Intelligent Power Modules and IGBT/MOSFET Gate Drive 栅 双极性晶体管 |
| 文件： | 总9页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-P481 and ACPL-W481
Inverted Logic, High CMR Optocoupler for Intelligent
Power Modules and IGBT/MOSFET Gate Drive
Data Sheet
Description
Features
The high-speed ACPL-P481/W481 optocoupler contains • Inverted output type (totem pole output)
a GaAsP LED, photo detector and a Schmitt trigger that
eliminates the need for external waveform conditioning
circuits.
• Performance Specified for Common IPM Applications
Over Industrial Temperature Range.
• Short Maximum Propagation Delays
• Minimized Pulse Width Distortion (PWD)
• Very High Common Mode Rejection (CMR)
• Hysteresis
The totem pole output eliminates the need for a pull-up
resistor. An Intelligent Power Module, Power MOSFET or
IGBT can be driven directly.
Propagation delay difference between devices has been
minimized to maximize inverter efficiency through
reduced switching dead time.
• Available in Stretched SO-6 Package.
• Package Clearance/Creepage at 8 mm (ACPL-W481)
• Safety Approval: (pending)
Applications
– UL Recognized with 3750 V
(5000 Vrms for
rms
ACPL-W481) for 1 minute per UL1577.
– CSA Approved.
– IEC/EN/DIN EN 60747-5-5 Approved with V
• IPM Interface Isolation
• Isolated IGBT/MOSFET Gate Drive
• AC and Brushless DC Motor Drives
• Industrial Inverters
=
for
IORM
891 V
for ACPL-P481 and V
= 1140 V
peak
IORM
peak
ACPL-W481, under option 060.
• General Digital Isolation
Specifications
Functional Diagram
• Wide Operating Temperature Range: –40°C to 100°C.
• Maximum Propagation Delay t / t = 350 ns
PHL PLH
Anode 1
N.C. 2
6 VCC
• Maximum Pulse Width Distortion (PWD) = 250 ns.
• Propagation Delay Difference: Min. –100 ns, Max. 250 ns
5 VO
• Wide Operating V Range: 4.5 V to 20 V
CC
Cathode 3
4 Ground
SHIELD
• 20 kV/µs Minimum Common Mode Rejection (CMR) at
Note: A 0.1 µF bypass capacitor must be connected between pins 4 and 6.
V
CM
= 1000 V.
Truth Table (Positive Logic)
LED
ON
V
O
LOW
OFF
HIGH
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-P481/W481 is UL recognized with 3750/5000 Vrms for 1 minute respectively per UL 1577. Both are approved under
CSA Component Acceptance Notice #5, File CA 88324.
Option
Surface
Mount
Tape
& Reel
IEC/EN/DIN EN
60747-5-5
Part number
RoHS Compliant
-000E
Package
Quantity
X
X
X
X
100 per tube
1000 per reel
100 per tube
1000 per reel
-500E
X
X
ACPL-P481
ACPL-W481
Stretched
SO-6
-060E
X
X
-560E
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an ordering part number.
Example 1:
ACPL-P481-560E: Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5
Safety Approval and RoHS compliant.
Example 2:
ACPL-P481-000E: Stretched SO-6 Surface Mount package in tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
ACPL-P481 Stretched SO-6 Package, 7 mm clearance
+
0.ꢀ54
1.ꢀ2 BSG
0.050
4.580
0.180
10.2
0.4ꢀ1
0
0.26
0.030
0.381 0.1ꢀ2
0.015 0.005
+0.010
0.000
-
1.ꢀ2
0.050
ꢀ.16
0.085
2.6ꢀ
0.300
6.81
1.590 0.1ꢀ2
0.063 0.005
3.180 0.1ꢀ2
0.1ꢀ5 0.005
0.45
0.018
0.ꢀ68
45°
2°
2°
2°
2°
NOM.
0.ꢀ0 0.10
0.008 0.004
0.ꢀ54 0.050
0.010 0.00ꢀ
5
Floating Lead Protusions max. 0.ꢀ5 [0.01]
1
0.ꢀ50
0.040 0.010
Dimensions in Millimeters [ Inches ]
Lead Coplanarity= 0.1mm [0.004 Inches ]
9.2 0.ꢀ50
0.38ꢀ 0.010
2
ACPL-W481 Stretched SO-6 Package, 8 mm clearance
+
0
0.254
4.580
1.27 BSG
0.050
+
0.010
12.650
0.498
0.760
0.030
0.381 0.127
0.015 0.005
0.180
-
0.000
1
6
4
2
3
5
7.62
[0.300]
1.905
0.075
1.270
0.050
+
0.127
6.807
-0.000
0.005
0.000
+
-
0.268
1.590 0.127
0.063 0.005
3.180 0.127
0.125 0.005
45°
0.45
0.018
7°
7°
0.20 0.10
0.008 0.004
0.254 0.050
0.010 0.002
0.750 0.250
[0.0295 0.010]
35° NOM.
Floating Lead protusion max. 0.25[0.01]
11.500 0.25
0.453 0.010
Dimensions in millimeters [inches]
Lead Coplanarity=0.1mm [0.004 inches]
Recommended Pb-Free IR Profile
The recommended reflow profile is per JEDEC Standard, J-STD-020 (latest revision). Non-halide flux should be used.
Regulatory Information
The ACPL-P481/W481 is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5 (Option 060 only)
UL
Approved with Maximum Working Insulation Voltage Approval under UL 1577, component recognition
= 891 V for ACPL-P481 and V = 1140 V program up to
= 3750 V (5000 Vrms for ACPL-W481). File E55361.
RMS
V
IORM
peak
IORM
peak
for ACPL-W481
V
ISO
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
3
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (ACPL-P481/W481 Option 060)
Description
Symbol
ACPL-P481
ACPL-W481 Unit
Installation Classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
I – IV
I – IV
I – III
I – IV
I – IV
I – IV
for rated mains voltage ≤ 600 Vrms
Climatic Classification
55/100/21
55/100/21
2
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
2
VIORM
VPR
891
1670
1140
2137
Vpeak
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.6=VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
VPR
1426
6000
1824
8000
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
Vpeak
Safety-limiting Values – maximum values allowed in the event of a failure.
Case Temperature
TS
175
230
600
>109
175
230
600
>109
°C
Input Current
IS, INPUT
PS, OUTPUT
RS
mA
mW
Ω
Output Power
Insulation Resistance at TS, VIO = 500 V
*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under the Product Safety Regulations section,
(IEC/EN/DIN EN 60747-5-5), for a detailed description of Method a and Method b partial discharge test profiles.
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-P481 ACPL-W481 Units
Conditions
Minimum External Air Gap
(External Clearance)
L(101)
7.0
8.0
mm
mm
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (External Creepage)
L(102)
CTI
8.0
8.0
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
0.08
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
>175
IIIa
>175
IIIa
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
4
Table 3. Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
-55
-40
Max.
125
100
10
Units
°C
Note
Storage Temperature
Operating Temperature
Average Input Current
TA
°C
IF(avg)
mA
Peak Transient Input Current
(< 1 µs pulse width, 300 pps)
(< 200 µs pulse width, < 1% duty cycle)
IF(tran)
1.0
40
A
mA
Reverse Input Voltage
Average Output Current
Supply Voltage
VR
IO
5
V
25
25
25
210
mA
V
VCC
VO
PT
0
Output Voltage
-0.5
V
Total Package Power Dissipation
mW
1
Table 4. Recommended Operating Conditions
Parameter
Symbol
VCC
Min.
4.5
6
Max.
20
Units
V
Note
Power Supply Voltage
Forward Input Current (OFF)
Forward Input Voltage (ON)
Operating Temperature
2
IF(OFF)
VF(ON)
TA
10
mA
V
–
0.8
100
-40
°C
5
Table 5. Electrical Specifications
Over recommended operating conditions T = -40 °C to 100 °C, V = +4.5 V to 20 V, I
= 6 mA to 10 mA, V
= 0 V
F(OFF)
A
CC
F(ON)
to 0.8 V, unless otherwise specified. All typicals at T = 25 °C.
A
Parameter
Symbol
Min.
Typ.
Max.
0.3
Units
Test Conditions
Fig. Note
Logic Low Output Voltage VOL
V
IOL = 3.5 mA
1, 3
0.5
IOL = 6.5 mA
Logic High Output Voltage VOH
VCC-1.8 VCC - 0.9
VCC-2.5 VCC - 1.2
V
IOH = -3.5 mA
2, 3, 7
IOH = -6.5 mA
Output Leakage Current
(VO = VCC + 0.5 V)
IOHH
100
500
3.0
3.0
2.5
2.5
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
V
VCC = 5 V, VF = 0 V
VCC = 20 V, VF = 0 V
Logic Low Supply Current ICCL
1.9
VCC = 5.5 V, IF = 10 mA, IO = 0mA
VCC = 20 V, IF = 10 mA, IO = 0mA
VCC = 5.5 V, VF = 0 V, IO = 0mA
VCC = 20 V, VF = 0 V, IO = 0mA
VO = VCC = 5.5 V, IF = 10 mA
VO = VCC = 20 V, IF = 10 mA
VCC = 5.5 V, VF = 0 V, VO = GND
VCC = 20 V, VF = 0 V, VO = GND
TA = 25°C, IF = 6 mA
IF = 6 mA
2.0
Logic High Supply Current ICCH
1.5
1.6
Logic Low Short Circuit
Output Current
IOSL
IOSH
VF
25
50
3
Logic High Short Circuit
Output Current
-25
-50
1.7
3
Input Forward Voltage
1.5
4
1.85
V
Input Reverse
Breakdown Voltage
BVR
5
V
IR = 10 µA
Input Diode
Temperature Coefficient
∆VF/∆TA
CIN
1.7
60
mV/°C
pF
IF = 6 mA
Input Capacitance
f = 1 MHz, VF = 0 V
4
Table 6. Switching Specifications
Over recommended operating conditions T = -40 °C to 100 °C, V = +4.5 V to 20 V, I
= 6 mA to 10 mA, V
= 0 V
F(OFF)
A
CC
F(ON)
to 0.8 V, unless otherwise specified. All typicals at T = 25 °C.
A
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig. Note
Propagation Delay Time to
Logic Low Output Level
tPHL
110
350
ns
With Peaking Capacitor
5, 6
6
Propagation Delay Time to
Logic High Output Level
tPLH
140
350
250
250
ns
ns
ns
With Peaking Capacitor
5, 6
6
Pulse Width Distortion
|tPHL - tPLH
= PWD
|
9
Propagation Delay
Difference Between
Any Two Parts
PDD
-100
11
Output Rise Time (10-90%)
Output Fall Time (90-10%)
tr
16
20
ns
5, 8
5, 8
9
tf
ns
Logic High Common Mode
Transient Immunity
|CMH|
20
20
kV/µs
|VCM| = 1000 V, VF = 0 V,
VCC = 5 V, TA = 25°C
7
7
Logic Low Common Mode
Transient Immunity
|CML|
kV/µs
|VCM| = 1000 V, IF = 6.0 mA,
VCC = 5 V, TA = 25°C
9
6
Table 7. Package Characteristics
Parameter
Symbol Min.
Typ.
Max. Units
Test Conditions
Fig. Note
Input-Output Momentary
Withstand Voltage*
VISO
3750
(ACPL-P481)
5000
Vrms
RH < 50%, t = 1 min.
TA = 25°C
5, 8
(ACPL-W481)
Input-Output Resistance
Input-Output Capacitance
RI-O
CI-O
1012
0.6
VI-O = 500 Vdc
5
5
f = 1 MHz, VI-O = 0 Vdc
*
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable).
Notes:
1. Derate total package power dissipation, P , linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.
T
2. Detector requires a VCC of 4.5V or higher for stable operation as output might be unstable if VCC is lower than 4.5V. Be sure to check the power
ON/OFF operation other than the supply current.
3. Duration of output short circuit time should not exceed 10 ms.
4. Input capacitance is measured between pin 1 and pin 3.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. The t
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the trailing edge of the
PLH
output pulse. The t
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the leading
PHL
edge of the output pulse.
7. CM is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V > 2.0 V. CM
L
H
O
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V < 0.8 V.
O
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
(6000 V
for ACPL-W481) for
RMS
RMS
one second (leakage detection current limit, I <= 5 µA). This test is performed before the 100% production test for partial discharge (Method b)
I-O
shown in the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table, if applicable.
9. Pulse Width Distortion (PWD) is defined as |t
- t
| for any given device.
PHL PLH
10. Use of a 0.1 µF bypass capacitor connected between pins 4 and 6 is recommended.
11. The difference between t and t between any two devices under the same test condition.
PLH
PHL
7
0.15
0.14
0.13
0.12
0.11
0.1
0
-5
VCC = 4.5V
VF = 0V
IF = 6mA
-10
-15
-20
-25
Vcc = 4.5V
Vo = 2.7V
Vo = 2.4V
Vcc = 20V
-50
0
50
TA - TEMPERATURE - °C
100
150
-50
0
50
TA - TEMPERATURE - °C
100
150
Figure 1. Typical Logic Low Output Voltage vs. Temperature
Figure 2. Typical Logic High Output Current vs. Temperature
4.5
1000
Io = -2.6mA
4
TA = 25°C
IF
TA = 25°C
Vcc=4.5V
100
10
+
-
3.5
3
VF
2.5
2
1.0
1.5
1
0.1
0.01
0.5
Io = 6.4mA
0.001
0
0
1
2
3
4
5
1.1
1.2
1.3
1.4
1.5
VF - FORWARD VOLTAGE - V
IF - INPUT CURRENT - mA
Figure 3. Typical Output Voltage vs. Forward Input Current
Figure 4. Typical Input Diode Forward Characteristic
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C1 AND C2.
PULSE GEN.
tr = tf = 5ns
f = 100 kHz
10% DUTY
CYCLE
R1
660 Ω
330 Ω
VCC
IF(ON)
6 mA
10 mA
VO = 5 V
ZO = 50
5 V
ALL DIODES ARE EITHER 1N916 OR 1N3064
OUTPUT VO
MONITORING
NODE
1
2
6
5
4
619 Ω
*
D1
IF(ON)
50% IF(ON)
INPUT IF
INPUT
D2
D3
D4
0 mA
MONITORING
tPLH
tPHL
NODE
3
C2
15 pF
=
5 kΩ
SHIELD
R1
C1
=
120 pF
OUTPUT V
VOH
1.3 V
* 0.1 µF BYPASS - SEE NOTE 10
VOL (OV)
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf
8
230
210
190
170
150
130
110
90
25
20
15
10
5
TA = 25°C
VF = 0V
Vcc = 20V
IF = 10mA
TPLH
Vcc = 10V
IF = 6mA
TPHL
70
50
0
0
5
10
15
20
25
-50
0
50
TA - TEMPERATURE - C
100
150
Vcc-SUPPLY VOLTAGE-V
Figure 6. Typical Propagation Delays vs. Temperature.
Figure 7. Typical Logic High Output Voltage vs. Supply Voltage
200
TA = 25°C
180
IF (mA)
10
6
160
TPLH
140
120
100
IF (mA)
6
80
10
TPHL
60
40
20
0
0
5
10
15
20
25
Vcc-SUPPLY VOLTAGE-V
Figure 8. Typical Propagation Delay vs. Supply Voltage
VCC
CMH
CML
RIN
A
VCM (PEAK)
1
6
5
4
|VCM|
0V
B
0.1 µF
+
VFF
2
OUTPUT VO
MONITORING
NODE
SWITCH AT B:VF = 0V
3
VOH
SHIELD
VO (MIN.)*
OUTPUT VO
VOL
VCM
SWITCH AT A:IF = 6 mA
+
VO (MAX.)*
* SEE NOTE 6
Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms
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Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-2122EN - December 21, 2012
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