ACPL-P480 [AVAGO]
Available in Stretched SO-6 package;
| 型号： | ACPL-P480 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Available in Stretched SO-6 package |
| 文件： | 总10页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-P480 and ACPL-W480
High CMR Intelligent Power Module and Gate Drive Interface Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-P480 and ACPL-W480 fast speed optocou- • Performance Specified for Common IPM Applications
plers contain a GaAsP LED and photo detector with
built-in Schmitt trigger to provide logic-compatible
waveforms, eliminating the need for additional wave
shaping. The totem pole output eliminates the need for
a pull up resistor and allows for direct drive Intelligent
Power Module or gate drive. Minimized propagation
delay difference between devices make these optocou-
plers excellent solutions for improving inverter efficiency
through reduced switching dead time.
Over Industrial Temperature Range.
• Short Maximum Propagation Delays
• Minimized Pulse Width Distortion (PWD)
• Very High Common Mode Rejection (CMR)
• Hysteresis
• Totem Pole Output (No Pull-up Resistor Required)
• Available in Stretched SO-6 package.
• Safety Approval:
Functional Diagrams
ACPL-P480
UL Recognized with 3750 V
for 1 minute (5000
rms
Vrms for 1 minute for all ACPL-W480 devices and
Option 020 device for ACPL-P480) per UL1577.
ANODE
1
2
3
6
5
4
VCC
CSA Approved.
N.C.
VO
IEC/EN/DIN EN 60747-5-5 Approved:
V
IORM
V
peak
= 891 V
for ACPL-P480, and V
= 1140
IORM
peak
for ACPL-W480.
CATHODE
Ground
SHIELD
Specifications
ACPL-W480
• Wide operating temperature range: –40°C to 100°C.
• Maximum propagation delay t / t = 350 ns
• Maximum Pulse Width Distortion (PWD) = 250 ns.
• Propagation Delay Difference: Min. –100 ns, Max. 250 ns
ANODE
N.C.
1
2
3
6
5
4
VCC
PHL PLH
VO
CATHODE
Ground
SHIELD
• Wide Operating V Range: 4.5 to 20 Volts
CC
Note: A 0.1 µF bypass capacitor must be connected between pins 4 and 6.
• 20 kV/µs minimum common mode rejection (CMR) at
V
= 1000 V.
CM
Truth Table (Positive Logic)
Applications
LED
ON
VO
• IPM Interface Isolation
HIGH
LOW
• Isolated IGBT/MOSFET Gate Drive
• AC and Brushless DC Motor Drives
• Industrial Inverters
OFF
• General Digital Isolation
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-P480 is UL Recognized with 3750 Vrms for 1 minute and ACPL-W480 is UL Recognized with 5000 Vrms for 1
minute per UL1577. Both are approved under CSA Component Acceptance Notice #5, File CA 88324.
Option
UL 1577
RoHS
Compliant
Surface
Mount
5000VRMS / 1 IEC/EN/DIN EN
Part number
Package
Tape & Reel Minute Rating
60747-5-5
Quantity
-000E
-500E
-020E
-520E
-060E
-560E
-000E
-500E
-060E
-560E
X
X
X
X
X
X
X
X
X
X
100 per tube
1000 per reel
100 per reel
1000 per reel
100 per tube
1000 per reel
100 per tube
1000 per reel
100 per tube
1000 per reel
X
X
X
X
X
7mm
Stretched
SO-6
X
X
ACPL-P480
X
X
X
X
X
X
8mm
Stretched
SO-6
ACPL-W480
X
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P480-560E to order product of Stretched SO-6 package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-P480-000E to order product of Stretched SO-6 package in tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
ACPL-P480 Stretched SO-6 Package, 7 mm clearance
+
0.ꢀ54
1.ꢀ2 BSG
0.050
4.580
0.180
10.2
0.4ꢀ1
0
0.26
0.030
0.381 0.1ꢀ2
0.015 0.005
+0.010
0.000
-
1.ꢀ2
0.050
ꢀ.16
0.085
2.6ꢀ
0.300
6.81
1.590 0.1ꢀ2
0.063 0.005
3.180 0.1ꢀ2
0.1ꢀ5 0.005
0.45
0.018
0.ꢀ68
45°
2°
2°
2°
2°
NOM.
0.ꢀ0 0.10
0.008 0.004
0.ꢀ54 0.050
0.010 0.00ꢀ
5
Floating Lead Protusions max. 0.ꢀ5 [0.01]
1
0.ꢀ50
0.040 0.010
Dimensions in Millimeters [ Inches ]
Lead Coplanarity= 0.1mm [0.004 Inches ]
9.2 0.ꢀ50
0.38ꢀ 0.010
ACPL-W480 Stretched SO-6 Package, 8 mm clearance
+
0
0.254
4.580
1.27 BSG
0.050
+
0.010
12.650
0.498
0.760
0.030
0.381 0.127
0.015 0.005
0.180
-
0.000
1
6
4
2
3
5
7.62
[0.300]
1.905
0.075
1.270
0.050
+
0.127
6.807
0.268
- 0.000
+
0.005
-
0.000
1.590 0.127
0.063 0.005
3.180 0.127
0.125 0.005
45°
0.45
0.018
7°
7°
0.20 0.10
0.008 0.004
0.254 0.050
0.010 0.002
0.750 0.250
[0.0295 0.010]
35° NOM.
Floating Lead protusion max. 0.25[0.01]
11.500 0.25
0.453 0.010
Dimensions in millimeters [inches]
Lead Coplanarity=0.1 mm [0.004 inches]
3
Solder Reflow Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-P480 and ACPL-W480 are approved by the following organizations:
IEC/EN/DIN EN 60747-5-5 (Option 60 only)
UL
Approval under:
ACPL-P480: Approval under UL 1577, component recog-
nition program up to V = 3750 V . File E55361.
ISO RMS
IEC 60747-5-5 : 2007
EN 60747-5-5 : 2011
ACPL-W480 and ACPL-P480 (option 020): Approval under
DIN EN 60747-5-5 (VDE 0884-5) : 2011-11
UL 1577, component recognition program up to V
=
ISO
CSA
5000 V . File E55361.
RMS
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060)
Description
Characteristic
Symbol
ACPL-P480
ACPL-W480 Unit
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 300 Vrms
I - IV
I - III
I - III
I - IV
I - IV
I - IV
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
Climatic Classification
55/100/21
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
2
VIORM
VPR
891
1140
2137
Vpeak
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge < 5 pC
1670
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test with tm = 10 sec,
Partial discharge < 5 pC
VPR
1426
6000
1824
8000
Vpeak
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
Safety-limiting values - maximum values allowed in the event of a failure.
Case Temperature
Input Current
Output Power
TS
175
230
600
°C
mA
mW
IS,INPUT
PS,OUTPUT
Insulation Pesistance at TS, VIO = 500 V
RS
>109
W
*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
4
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol ACPL-P480 ACPL-W480
Units Conditions
Minimum External Air Gap
(External Clearance)
L(101)
7.0
8.0
mm
mm
mm
Measured from input terminals to output
terminals shortest distance through air.
Minimum External Tracking
(External Creepage)
L(102)
8.0
8.0
Measured from input terminals to output
terminals shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Minimum Internal Tracking
(Internal Creepage)
NA
>175
IIIa
mm
V
Measured from input terminals to output
tereminals, along internal cavity.
Tracking Resistance
(Comparative Tracking Index)
CTI
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
Table 3. Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
Max.
Units
°C
Note
Storage Temperature
Operating Temperature
Average Input Current
-55
-40
125
100
10
TA
°C
IF(avg)
IF(tran)
mA
Peak Transient Input Current
(<1 µs pulse width, 300 pps)
(<200 µs pulse width, < 1% duty cycle)
1.0
40
A
mA
Reverse Input Voltage
VR
IO
5
V
Average Output Current
Supply Voltage
25
25
25
210
mA
VCC
VO
PT
0
Output Voltage
-0.5
Total Package Power Dissipation
mW
1
Table 4. Recommended Operating Conditions
Parameter
Symbol
VCC
Min.
4.5
6
Max.
20
Units
V
Note
Power Supply Voltage
Forward Input Current (ON)
Forward Input Voltage (OFF)
Operating Temperature
IF(ON)
VF(OFF)
TA
10
mA
V
-
0.8
100
-40
°C
Notes:
1. Derate total package power dissipation, P , linearly above 70°C free-air temperature at a rate of 4.5 mW/°C.
T
5
Table 5. Electrical Specifications
Over recommended operating conditions T = -40 °C to 100 °C, V = +4.5 V to 20 V, I
= 6 mA to 10 mA, V
= 0
A
CC
F(ON)
F(OFF)
V to 0.8 V, unless otherwise specified. All typicals at T = 25 °C.
A
Parameter
Symbol
Min. Typ.
Max. Units
Test Conditions
Fig.
Note
Logic Low Output Voltage
VOL
0.5
V
IOL = 6.4 mA
1, 3, 9,
10
Logic High Output Voltage
ACPL-P480
VOH
2.4
2.7
2.7
VCC - 1.1
V
IOH = -2.6 mA
IOH = -0.4 mA
IOH = -1.6 mA
2, 3, 7,
9, 10
ACPL-W480
Threshold Input Current
Low to High
IFLH
2.2
5.5
mA
Output Leakage Current
(VO = VCC+0.5V)
IOHH
100
500
3.0
3.0
2.5
µA
VCC = 5 V, IF = 10mA
VCC = 20 V, IF = 10mA
µA
Logic Low Supply Current
ICCL
1.9
2.0
1.5
mA
mA
mA
VCC = 5.5 V, VF = 0 V, IO = Open
VCC = 20 V, VF = 0 V, IO = Open
Logic High Supply Current
ICCH
VCC = 5.5 V, IF = 10 mA,
IO = Open
1.6
2.5
mA
VCC = 20 V, IF = 10 mA
IO = Open
Logic Low Short Circuit
Output Current
IOSL
IOSH
VF
25
50
mA
mA
mA
mA
V
VO = VCC = 5.5 V, VF=0V
VO = VCC = 20 V, VF=0V
VCC = 5.5 V, IF=6mA, VO=GND
VCC = 20 V, IF=6mA, VO=GND
TA = 25˚C, IF=6mA
1
1
Logic High Short Circuit
Output Current
-25
-50
1.7
Input Forward Voltage
1.5
4
1.85
V
IF=6mA
Input Reverse
BVR
5
V
IR = 10 µA
Breakdown Voltage
Input Diode Temperature
Coefficient
DVF/DTA
CIN
1.7
60
mV/°C IF = 6 mA
pF f = 1 MHz, VF = 0 V
Input Capacitance
2
Notes:
1. Duration of output short circuit time should not exceed 10 ms.
2. Input capacitance is measured between pin 1 and pin 3.
6
Table 6. Switching Specifications
Over recommended operating conditions T = -40 °C to 100 °C, V = +4.5 V to 20 V, I
= 6 mA to 10 mA, V
= 0
A
CC
F(ON)
F(OFF)
V to 0.8 V, unless otherwise specified. All typicals at T = 25 °C.
A
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay Time to
Logic Low Output Level
tPHL
150
350
ns
With Peaking
Capacitor
5, 6
1
1
2
3
Propagation Delay Time to
Logic High Output Level
tPLH
110
350
250
250
ns
ns
ns
With Peaking
Capacitor
5, 6
Pulse Width Distortion
|tPHL - tPLH
= PWD
|
Propagation Delay Difference
Between Any 2 Parts
PDD
-100
Output Rise Time (10-90%)
Output Fall Time (90-10%)
tr
16
20
ns
5, 8
5, 8
tf
ns
Logic High Common Mode
Transient Immunity
|CMH|
20
20
kV/µs
|VCM| = 1000 V, IF = 6.0 11
mA, VCC = 5 V, TA = 25˚C
4
4
Logic Low Common Mode
Transient Immunity
|CML|
kV/µs
|VCM| = 1000 V, VF = 0 V, 11
VCC = 5 V, TA = 25˚C
Table 7. Package Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage*
VISO
3750**
5000***
Vrms
RH < 50%, t = 1 min.
TA = 25°C
5, 6
Input-Output Resistance
Input-Output Capacitance
RI-O
CI-O
1012
0.6
VI-O = 500 Vdc
5
5
f = 1 MHz, VI-O = 0 Vdc
*
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable).
** For all ACPL-P480 devices except Option 020
*** For ACPL-W480 and Option 020 of ACPL-P480)
Notes:
1. The t
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
PLH
output pulse. The t
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing
PHL
edge of the output pulse.
2. Pulse Width Distortion (PWD) is defined as |t
- t
| for any given device.
PHL PLH
3. The difference between t
and t
between any two devices under the same test condition.
PLH
PHL
4. CM is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V > 2.0 V.
H
O
CM is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V < 0.8 V.
L
O
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
for one second (leakage
RMS
detection current limit, I ≤ 5 µA). ; each optocoupler with option 020 is proof tested by applying an insulation test voltage ≥ 6000 V
for
I-O
RMS
1 second (leakage detection current limit, I ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b)
I-O
shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
7. Use of a 0.1 μF bypass capacitor connected between pins 4 and 6 is recommended.
7
0.15
0.14
0.13
0.12
0.11
0.1
0
VCC = 4.5V
IF = 6mA
VCC = 4.5/20V
VF = 0V
-5
IO = 6.4mA
-10
VCC = 4.5V
VO = 2.7V
VCC = 20V
-15
-20
-25
VO = 2.4V
-50
0
50
TA - TEMPERATURE - °C
100
150
-50
0
50
TA - TEMPERATURE - °C
100
150
Figure 1. Typical Logic Low Output Voltage vs. Temperature
Figure 2. Typical Logic High Output Current vs. Temperature
4.5
1000
TA = 25 °C
4
IF
IO = -2.6mA
100
10
3.5
3
+
VF
-
2.5
2
1.0
1.5
0.1
0.01
TA = 25C
1
VCC = 4.5V
0.5
IO = 6.4mA
0
0.001
0
1
2
3
4
5
1.1
1.2
1.3
1.4
1.5
IF - INPUT CURRENT - mA
VF - FORWARD VOLTAGE - V
Figure 3. Typical Output Voltage vs. Forward Input Current
Figure 4. Typical Input Diode Forward Characteristic
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C1AND C2 .
PULSE GEN.
tr =tf = 5 ns
f = 100 kHz
10% DUTY
CYCLE
VCC
R
580 W
6 mA
330 W
10 mA
1
VO = 5 V
ZO = 50
IF(ON)
5 V
OUTPUT V
O
MONITORING
NODE
ALL DIODES ARE 1N916 OR 1N3064.
1
2
6
5
4
619W
*
D1
IF (ON)
50 % IF (ON)
0 mA
INPUT I F
INPUT
MONITORING
NODE
D2
D3
D4
3
5 kW
SHIELD
t PLH
tPHL
C2 =
15pF
C1 =
120pF
VOH
R1
1.3 V
OUTPUT VO
VOL
* 0.1 µF BYPASS - SEE NOTE 7
Figure 5. Circuit for tPLH, tPHL, tr, tf
8
230
210
190
170
150
130
110
90
25
20
15
10
5
o
TA = 25 C
tPHL
IO = -2.6mA
VCC = 20V
IF = 10mA
tPLH
70
0
50
-60
-40
-20
0
20
40
60
80
100 120
0
5
10
15
20
25
TA - TEMPERATURE - C
VCC - SUPPLY VOLTAGE - V
Figure 6. Typical Propagation Delays vs. Temperature.
Figure 7. Typical Logic High Output Voltage vs. Supply Voltage
200
180
IF (mA)
10
6
160
tPHL
140
120
100
IF (mA)
6
80
10
tPLH
60
40
TA = 25oC
20
0
0
5
10
15
20
25
VCC - SUPPLY VOLTAGE - V
Figure 8. Typical Propagation Delay vs. Supply Voltage
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
4.5
Vcc=4.5V
IF=6mA
4.0
100 °C
25 °C
100 °C
-40 °C
3.5
25 °C
-40 °C
3.0
2.5
2.0
0.5
1.5
2.5
3.5
4.5
5.5
6.5
-6
-5
-4
-3
-2
-1
0
Iol - LOW OUTPUT CURRENT - mA
Ioh - HIGH OUTPUT CURRENT - mA
Figure 10. Vol vs Iol Across Temperatures
Figure 9. Voh vs Ioh Across Temperatures
9
RIN
VCC
A
1
2
3
6
5
4
0.1 µF
B
+
-
VFF
OUTPUT V
MONITORING
NODE
O
SHIELD
VCM
+
-
VCM (PEAK)
|VCM
|
0 V
SWITCH AT A: I F = 6 mA
VO (MIN.)
VOH
OUTPUT VO SWITCH AT B: V F = 0 V
VO (MAX.)
VOL
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0646EN
AV02-1305EN - December 21, 2012
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