ACPL-P454-500E [AVAGO]
High CMR High Speed Optocoupler Surface Mountable in 6-pin stretched SO6; 高CMR高速光电耦合器可表面安装的6针绷SO6
| 型号： | ACPL-P454-500E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | High CMR High Speed Optocoupler Surface Mountable in 6-pin stretched SO6 |
| 文件： | 总9页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-P454 and ACPL-W454
High CMR High Speed Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
ꢀ Package Clearance/Creepage at 8mm (ACPL-W454)
ꢀ Function Compatible with HCPL-4504
ꢀ Surface Mountable in 6-pin stretched SO6
ꢀ Short Propagation Delays for TTL and IPM Applications
ꢀ Very High Common Mode Transient Immunity: Guaran-
The ACPL-W454/P454 is similar to Avago Technologies
other high speed transistor output optocouplers, but with
shorter propagation delays and higher CTR. The ACPL-
W454/P454 also has a guaranteed propagation delay
difference (t
- t ). These features make the ACPL-
PLH
PHL
W454/P454 an excellent solution to IPM inverter dead time
and other switching problems.
teed 15 kV/ꢁs at V = 1500 V
CM
The ACPL-W454/P454 CTR, propagation delays, and CMR ꢀ High CTR: >25% at 25°C
are specified both for TTL load and drive conditions and for
ꢀ Guaranteed Specifications for Common IPM Applica-
IPM (Intelligent Power Module) load and drive conditions.
Specifications and typical performance plots for both TTL
and IPM conditions are provided for ease of application.
tions
ꢀ TTL Compatible
ꢀ Guaranteed AC and DC Performance Over Temperature:
This diode-transistor optocoupler uses an insulating layer
between the light emitting diode and an integrated photo
detector to provide electrical insulation between input
and output. Separate connections for the photodiode bias
and output transistor collector increase the speed up to a
hundred times over that of a conventional phototransistor
coupler by reducing the base-collector capacitance.
0°C to 70°C
ꢀ Open Collector Output
ꢀ Safety approval
UL Recognized 3750 Vrms for 1 minute (5000 Vrms for
1 minute under ACPL-W454 devices) per UL1577
CSA Approved
IEC/EN/DIN EN 60747-5-2 Approved with V
= 1140
IORM
Functional Diagram
Vpeak (ACPL-W454) and V
for Option 060.
= 891 Vpeak (ACPL-P454)
IORM
ANODE
1
2
3
6
5
4
VCC
VO
TRUTH TABLE
LED
VO
Applications
ON
OFF
LOW
HIGH
NC
ꢀ Inverter Circuits and Intelligent Power Module (IPM) In-
terfacing – Shorter propagation delays and guaranteed
CATHODE
GND
(t
- t ) specifications.
PLH PHL
ꢀ High Speed Logic Ground Isolation
- TTL/TTL, TTL/LTTL, TTL/CMOS, TTL/LSTTL
A 0.1 μF bypass capacitor between pins 4 and 6 is recommended.
ꢀ Line Receivers
Schematic
- High common mode transient immunity (>15 kV/ꢁs
for a TTL load/drive) and low input-output capacitance
(0.6 pF).
I
CC
6
V
V
CC
I
F
+
1
ANODE
ꢀ Replace Pulse Transformers
V
F
I
O
5
4
- Save board space and weight
Ð
3
O
CATHODE
ꢀ Analog Signal Ground Isolation
- Integrated photo detector provides improved linearity
over phototransistors
SHIELD
GND
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-P454 and ACPL-W454 are UL Recognized with 3750 Vrms (5000 Vrms under ACPL-W454) for 1 minute per UL1577
and are approved under CSA Component Acceptance Notice #5, File CA 88324.
Option
RoHS
Compliant
Tape
& Reel
IEC/EN/DIN EN
60747-5-2
Part number
Package
Surface Mount
Quantity
-000E
-500E
-060E
-560E
X
X
X
X
100 per tube
1000 per reel
100 per tube
1000 per reel
X
X
ACPL-P454
ACPL-W454
Stretched
SO-6
X
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P454-560E to order product of Stretched SO-6 package in Tape and Reel packaging with IEC/EN/DIN EN 60747-
5-2 Safety Approval in RoHS compliant.
Example 2:
ACPL-P454-000E to order product of Stretched SO-6 package in tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
ACPL-W454 (Stretched SO6, 8mm Clearance)
+0.254
0
4.580
+.010
- .000
1.27 [.050ꢀ BSG
Land Pattern Recommendation
12.65 [.498ꢀ
.180
0.38 0.127
[.015 .005ꢀ
1
2
6
5
4
3
0.76
[.030ꢀ
+0.127
0
6.807
.268
1.590 0.127
[.063 .005ꢀ
+.005
- .000
1.91 [.075ꢀ
7°
7°
3.180 0.127
[.125 .005ꢀ
0.45
[.018ꢀ
45°
0.20 0.10
[.008 .004ꢀ
0.750 0.250
[0.0295 0.010ꢀ
Dimensions in Millimeters [Inchesꢀ
Coplanarity = 0.1mm [0.004 inchesꢀ
11.50 0.250
[.453 .010ꢀ
2
ACPL-P454 (Stretched SO6, 7mm Clearance)
+0.254
0
4.580
.180
Land Pattern Recommendation
10.7 [.421ꢀ
+.010
0.38 0.127
1.27 [.050ꢀ BSG
[.015 .005ꢀ
- .000
2.16 [.085ꢀ
7.62 [.300ꢀ
1.590 0.127
[.063 .005ꢀ
6.81 [.268ꢀ
0.45 [.018ꢀ
0.20 [.008ꢀ
7.00°
7.00°
45.00°
7.00°
A
7.00°
3.180 0.127
[.125 .005ꢀ
1
.0.250
[.040 .010ꢀ
Dimensions in Millimeters [Inchesꢀ
Coplanarity = 0.1mm [0.004 inchesꢀ
9.7 0.250
[.382 .010ꢀ
0.20 0.10
[.008 .004ꢀ
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-W454/P454 are approved by the following organizations:
IEC/EN/DIN EN 60747-5-2 (Option 060 only)
Approval under:
IEC 60747-5-2 :1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
UL - Approval under UL 1577, component recognition pro-
gram up to V = 3750 V
(5000VRMS for ACPL-W454).
ISO
RMS
File E55361.
CSA - Approval under CSA Component Acceptance Notice
#5, File CA 88324.
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
3
Insulation Related Specifications
W454
P454
Parameter
Symbol
Value
Value
Units Conditions
Min External Air Gap
(Clearance)
L(IO1)
8
7
mm
mm
mm
V
Measured from input terminals to output terminals
Min. External Tracking Path
(Creepage)
L(IO2)
8
8
Measured from input terminals to output terminals
Through insulation distance conductor to conductor
Min. Internal Plastic Gap
(Clearance)
0.08
0.08
175
Tracking Resistance
CTI
175
IIIa
DIN IEC 112/VDE 0303 Part 1
Material Group DIN VDE 0109
Isolation Group
(per DIN VDE 0109)
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060 only)
Description
Symbol
ACPL-W454
ACPL-P454
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ꢂ 150 Vrms
I-IV
I-IV
I-III
I-III
I-II
I-IV
I-IV
I-III
I-III
for rated mains voltage ꢂ 300 Vrms
for rated mains voltage ꢂ 450 Vrms
for rated mains voltage ꢂ 600 Vrms
for rated mains voltage ꢂ 1000 Vrms
Climatic Classification
55/100/21
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
2
2
VIORM
VPR
1140
891
V peak
V peak
V
IORM x 1.875 = VPR, 100% Production Test with tm = 1 sec
2137
1670
Partial Discharge < 5 pC,
Input to Output Test Voltage, Method a*
V
IORM x 1.5 = VPR, Type and sample test, tm = 60 sec,
VPR
1710
8000
1336
8000
V peak
Partial Discharge < 5 pC
Highest Allowable Overvoltage*
VIOTM
V peak
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure)
Case Temperature
Input Current
Output Power
TS
175
230
600
175
230
600
°C
mA
mW
IS,INPUT
PS,OUTPUT
Insulation Resistance at TS, VIO = 500 V
RS
ꢂ109
ꢂ109
ꢃ
*
Refer to the optocoupler section of the Designer’s Catalog, under regulatory information (IEC/EN/DIN EN 60747-5-2) for a detailed description of
Method a and Method b partial discharge test profiles.
4
Absolute Maximum Ratings
Storage Temperature
-55°C to +125°C
-55°C to +100°C
Operating Temperature
Average Input Current - IF
25 mA[1]
Peak Input Current - IF
50 mA[2] (50% duty cycle, 1 ms pulse width)
1.0 A (ꢂ1 ms pulse width, 300 pps)
5 V
Peak Transient Input Current - IF
Reverse Input Voltage - VR (Pin3-1)
Input Power Dissipation
45 mW[3]
Average Output Current - IO (Pin 5)
Peak Output Current
8 mA
16 mA
Output Voltage - VO (Pin 5-4)
Supply Voltage - VCC (Pin 6-4)
Output Power Dissipation
Solder Reflow Temperature Profile
-0.5 V to 20 V
-0.5 V to 30 V
100 mW[4]
see Package Outline Drawings section
DC Electrical Specifications
Over recommended temperature (T = 0°C to 70°C) unless otherwise specified.
A
Parameter
Symbol Min Typ.*
Max. Units
Test Conditions
Fig.
Note
Current
Transfer Ratio
CTR
CTR
VOL
IOH
25
21
26
22
32
60
65
%
%
V
TA = 25°C
VO = 0.4 V
IF = 16 mA 1, 2,
5
V
CC = 4.5 V
4
34
VO = 0.5 V
Current
Transfer Ratio
35
TA = 25°C
TA = 25°C
VO = 0.4 V
IF = 12 mA
5
V
CC = 4.5 V
37
VO = 0.5 V
Logic Low
Output Voltage
0.2
0.2
0.003
0.01
0.4
0.5
0.5
1
IO = 3.0 mA
IO = 2.4 mA
VO = VCC= 5.5 V
VO = VCC = 15.0 V
IF = 16 mA
VCC = 4.5 V
1
5
Logic High
Output Current
ꢁA
TA = 25°C
TA = 25°C
IF = 0 mA
50
Logic Low
Supply Current
ICCL
ICCH
50
200
ꢁA
ꢁA
IF = 16 mA, VCC = 15 V
VO = open,
VCC = 15 V
11
11
Logic High
Supply Current
0.02
0.02
1.5
1
TA = 25°C
TA = 25°C
IR = 10 ꢁA
IF = 16 mA, VO =
Open,
2
Input Forward
Voltage
VF
1.7
1.8
V
V
IF = 16 mA
3
1.5
Input Reverse
Breakdown
Voltage
BVR
5
Temperature
Coefficient of For-
ward Voltage
ꢄVF/ꢄTA
-1.6
60
mV/°C IF = 16 mA
Input
CIN
pF
f = 1 MHz, VF = 0
Capacitance
*All typicals at T = 25°C.
A
5
Switching Specifications
Over recommended temperature (T = 0°C to 70°C) unless otherwise specified
A
Parameter
Symbol Min. Typ.* Max. Units Test Conditions
Fig.
Note
Propagation
Delay Time to
Logic Low at
Output
tPHL
0.2
0.2
0.5
0.3
0.5
0.7
ꢁs
TA = 25°C
Pulse: f = 20 kHz, Duty Cycle = 10%
IF = 16 mA, VCC = 5.0 V
6,8,9
9
RL = 1.9 kꢃ, CL = 15 pF
V
THHL = 1.5 V
0.2
0.1
TA = 25°C
Pulse: f = 10 kHz, Duty Cycle = 50%
IF = 12 mA, VCC = 15.0 V
6,
10-14
10
RL = 20 kꢃ, CL = 100 pF
0.5
1.0
V
THHL = 1.5 V
Propagation
Delay Time to
Logic High at
Output
tPLH
0.3
0.3
0.5
0.7
ꢁs
TA = 25°C
TA = 25°C
Pulse: f = 20 kHz, Duty Cycle = 10%
IF = 16 mA, VCC = 5.0 V
6,8,9
9
RL = 1.9 kꢃ, CL = 15 pF
V
THHL = 1.5 V
0.3
0.2
0.8
0.8
1.1
1.4
Pulse: f = 10 kHz, Duty Cycle = 50%
IF = 12 mA, VCC = 15.0 V
6,
10-14
10
RL = 20 kꢃ, CL = 100 pF
V
THHL = 2.0 V
Propagation
Delay Difference
Between Any 2
Parts
tPLH
- tPHL
-0.4 0.3
-0.7 0.3
0.9
1.3
ꢁs
ꢁs
TA = 25°C
Pulse: f = 10 kHz, Duty Cycle = 50%
IF = 12 mA, VCC = 15.0 V
6,
10-14
13
RL = 20 kꢃ, CL = 100 pF
V
THHL = 1.5 V VTHLH = 2.0V
Common Mode
Transient Immu-
nity at Logic High
Level Output
|CMH|
|CML|
15
15
15
15
15
30
30
30
30
30
kV/ꢁs TA = 25°C
TA = 25°C
VCC = 5.0 V, RL = 1.9 kꢃ
7
7
7
7
7
7,9
CL = 15 pF, IF = 0 mA
VCM = 1500 VP-P
VCC = 15.0 V, RL = 20 kꢃ
CL = 100 pF, IF = 0 mA
8,10
7,9
V
CM = 1500 VP-P
Common Mode
Transient Immu-
nity at Logic Low
Level Output
kV/ꢁs TA = 25°C
TA = 25°C
VCC = 5.0 V, RL = 1.9 kꢃ
CL = 15 pF, IF = 16 mA
V
CM = 1500 VP-P
VCC = 15.0 V, RL = 20 kꢃ
CL = 100 pF, IF = 12 mA
8,10
8,10
VCM = 1500 VP-P
TA = 25°C
VCC = 15.0 V, RL = 20 kꢃ
CL = 100 pF, IF = 16 mA
V
CM = 1500 VP-P
*All typicals at T = 25°C.
A
6
Package Characteristics
Over recommended temperature (T = 0°C to 70°C) unless otherwise specified. All typicals at T = 25°C.
A
A
Parameter
Symbol Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage*
VISO
3750
Vrms
RH ꢂ 50%, t = 1 min, TA = 25°C
6,12
5000 (For “ACPL-W454)
1012
Input-Output Resistance
Input-Output Capacitance
RI-O
CI-O
ꢃ
V
I-O = 500 Vdc
6
6
0.6
pF
f = 1 MHz; VI-O = 0 Vdc
*
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable).
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 1.6mA/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C.
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (I ), to the forward LED input current (I ), times 100.
O
F
6. Device considered a two-terminal device: Pins 1 and 3 shorted together and Pins 4, 5 and 6 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dV /dt on the
CM
leading edge of the common mode pulse, V , to assure that the output will remain in a Logic High state (i.e., V > 2.0 V). Common mode transient
CM
O
immunity in a Logic Low level is the maximum tolerable (negative) dV /dt on the trailing edge of the common mode pulse signal, V to assure
CM
CM,
that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum
tolerable dV /dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., V > 3.0
CM
O
V). Common mode transient immunity in a Logic Low level is the maximum tolerable dV /dt on the trailing edge of the common mode pulse
CM
signal,V , to assure that the output will remain in a Logic Low state (i.e., V < 1.0 V).
CM
O
9. The 1.9 kꢃ load represents 1 TTL unit load of 1.6 mA and the 5.6 kꢃ pull-up resistor.
10. The R = 20 kꢃ, C = 100 pF load represents an IPM (Intelligent Power Mode) load.
L
L
11. Use of a 0.1 ꢁF bypass capacitor connected between pins 4 and 6 is recommended.
12. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ꢅꢆ4500 V
for 1 second (leakage detection
RMS
current limit, I ꢂ 5 ꢁA); each optocoupler under ACPL-W454 is proof tested by applying an insulation test voltage ≥ 6000 V
for 1 second (leak-
I-O
RMS
age detection current limit, I ≤ 5 μA).
I-O
13. The difference between t and t , between any two ACPL-W454/P454 parts under the same test condition. (See Power Inverter Dead Time and
PLH
PHL
Propagation Delay Specifications section).
1000
100
10
1.5
1.0
40 mA
35 mA
T
V
= 25 ˚C
A
10
= 5.0 V
CC
I
F
T
A
= 25˚C
30 mA
25 mA
20 mA
+
V
F
-
1.0
5
0.1
NORMALIZED
= 16 mA
0.5
0.0
15 mA
10 mA
I
F
V
V
T
= 0.4 V
= 5.0 V
= 25 ˚C
O
0.01
0.001
CC
I
= 5 mA
F
A
0
0
20
10
- OUTPUT VOLTAGE - V
0
2
4
6
8 10 12 14 16 18 20 22 24 26
IF - INPUT CURRENT - mA
1.1
1.2
1.3
1.4
1.5
1.6
V
O
VF - FORWARD VOLTAGE - VOLTS
Figure 1. DC and Pulsed Transfer Characteristics.
Figure 2. Current Transfer Ratio vs. Input Current.
Figure 3. Input Current vs. Forward Voltage.
7
4
3
2
1.1
1.0
10
10
10
I
V
= 0 mA
F
= V
= 5.0 V
CC
O
0.9
0.8
0.7
0.6
NORMALIZED
1
0
10
10
I
= 16 mA
F
V
V
T
= 0.4 V
O
= 5.0 V
CC
= 25 ˚C
A
-1
10
10
-2
-60 -40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100 120
TA - TEMPERATURE - ˚C
TA - TEMPERATURE - ˚C
Figure 4. Current Transfer Ratio vs. Temperature.
Figure 5. Logic High Output Current vs. Tempera-
ture.
ACPL-W454/P454
I
F
PULSE
GEN.
I
V
F
CC
O
0
1
2
6
Z
= 50Ω
= 5 ns
O
r
R
L
t
V
CC
OL
V
O
5
4
V
L
0.1μF
V
V
THLH
THHL
3
I
MONITOR
F
V
C
100 Ω
t
t
PHL
PLH
Figure 6. Switching Test Circuit.
ACPL-W454/P454
10 V
I
90%
90%
V
F
CM
0 V
V
V
1
2
3
6
5
4
10%
10%
CC
O
R
L
A
t
r
t
f
B
0.1μF
V
V
V
O
O
CC
SWITCH AT A: I = 0 mA
F
V
FF
C
L
V
OL
V
CM
SWITCH AT B: I = 12 mA, 16 mA
F
+
-
PULSE GEN.
Figure 7. Test Circuit for Transient Immunity and Typical Waveforms.
8
0.50
0.45
1.4
1.2
1.0
0.8
2.6
2.4
V
T
C
V
= 5.0 V
V
R
C
V
= 5.0 V
= 1.9 k
= 15 pF
V
T
C
V
V
= 5.0 V
= 25 ˚C
= 100 pF
CC
CC
CC
= 25 ˚C
= 15 pF
= V
A
L
A
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
L
L
L
0.40
= 1.5 V
THLH
= V
= 1.5 V
THLH
= 1.5 V
= 2.0 V
THHL
THHL
THHL
THLH
t
PLH
10% DUTY CYCLE
10% DUTY CYCLE
t
0.35
0.30
0.25
PLH
50% DUTY CYCLE
t
PHL
t
PLH
0.6
0.4
0.2
0.0
I
I
= 10 mA
= 16 mA
F
F
I
I
= 10 mA
= 16 mA
F
F
t
PHL
t
0.20
PHL
8
I
I
= 10 mA
= 16 mA
F
F
0.15
0.10
0.2
0.0
-60 -40 -20
0
20 40 60 80 100 120
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
10 12 14 16 18 20
RL - LOAD RESISTANCE - k
TA - TEMPERATURE - ˚C
RL - LOAD RESISTANCE - k
Figure 8. Propagation Delay Time vs. Tempera-
ture.
Figure 9. Propagation Delay Time vs. Load Resis-
tance.
Figure 10. Propagation Delay Time vs. Load
Resistance.
1.8
1.1
3.5
V
T
C
V
V
= 15.0 V
= 25 ˚C
V
R
C
V
V
= 15.0 V
= 20 k
= 100 pF
I
I
= 10 mA
= 16 mA
V
T
R
V
V
= 15.0 V
CC
CC
F
F
CC
= 25 ˚C
t
PLH
PHL
1.6
1.4
1.0
0.9
A
L
A
3.0
2.5
2.0
1.5
1.0
0.5
= 100 pF
= 1.5 V
= 20 k
L
L
L
= 1.5 V
= 2.0 V
= 1.5 V
= 2.0 V
THHL
THHL
THLH
THHL
t
PLH
= 2.0 V
1.2
1.0
0.8
0.6
0.4
THLH
THLH
t
0.8
0.7
0.6
PLH
50% DUTY CYCLE
50% DUTY CYCLE
50% DUTY CYCLE
t
t
PHL
0.5
t
PHL
I
I
= 10 mA
= 16 mA
F
F
I
I
= 10 mA
= 16 mA
F
0.4
0.3
0.2
0.0
F
0.0
-60 -40 -20
0
20 40
60 80 100 120
0
200
400
600
800
1000
0
5
10 15 20 25 30 35 40 45 50
C - LOAD CAPACITANCE - pF
R - LOAD RESISTANCE - k
L
TA - TEMPERATURE - ˚C
L
Figure 11. Propagation Delay Time vs. Tempera-
ture.
Figure 12. Propagation Delay Time vs. Load Re-
sistance.
Figure 13. Propagation Delay Time vs. Load
Capacitance.
1.2
T
= 25 ˚C
= 20 k
= 100 pF
A
1.1
1.0
R
C
V
V
L
L
= 1.5 V
= 2.0 V
THHL
THLH
0.9
0.8
0.7
50% DUTY CYCLE
t
PLH
0.6
0.5
0.4
0.3
0.2
t
PHL
I
I
= 10 mA
= 16 mA
F
F
10 11 12 13 14 15 16 17 18 19 20
- SUPPLY VOLTAGE - V
V
CC
Figure 14. Propagation Delay Time vs. Supply
Voltage.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0253EN
AV02-1307EN - August 4, 2010
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