EVAL-ADV7189BEB_技术文档

Multiformat SDTV Video Decoder

ADV7189B

FEATURES

Multiformat video decoder supports NTSC-(J, M, 4.43),

PAL-(B/D/G/H/I/M/N), SECAM

0.5 V to 1.6 V analog signal input range

Differential gain: 0.4% typ

Integrates three 54 MHz, Noise Shaped Video®, 12-bit ADCs

Clocked from a single 28 MHz crystal

Differential phase: 0.4° typ

Programmable video controls

Peak white/hue/brightness/saturation/contrast

Integrated on-chip video timing generator

Free-run mode (generates stable video output with no I/P)

VBI decode support for close captioning, WSS, CGMS, EDTV,

Gemstar® 1×/2×

Line-locked clock-compatible (LLC)

Adaptive-Digital-Line-Length-Tracking (ADLLT™), signal

processing, and enhanced FIFO management gives mini-

TBC functionality

5-line adaptive comb filters

Proprietary architecture for locking to weak, noisy, and

unstable video sources such as VCRs and tuners

Power-down mode

2-wire serial MPU interface (I²C®-compatible)

3.3 V analog, 1.8 V digital core; 3.3 V IO supply

2 temperature grades: 0°C to +70°C and –40°C to +85°C

80-lead LQFP Pb-free package

Subcarrier frequency lock and status information output

Integrated AGC with adaptive peak white mode

Macrovision® copy protection detection

CTI (chroma transient improvement)

DNR (digital noise reduction)

Multiple programmable analog input formats

CVBS (composite video)

S-Video (Y/C)

YPrPb component (VESA, MII, SMPTE, and BetaCam)

12 analog video input channels

Automatic NTSC/PAL/SECAM identification

Digital output formats (8-bit/10-bit/16-bit/20-bit)

ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD

APPLICATIONS

High-end DVD recorders

Video projectors

HDD-based PVRs/DVDRs

LCD TVs

Set-top boxes

Professional video products

AVR receivers

GENERAL DESCRIPTION

The ADV7189B integrated video decoder automatically detects

and converts a standard analog baseband television signal, com-

patible with worldwide standards NTSC, PAL, and SECAM into

4:2:2 component video data-compatible with 20-, 16-, 10-, and

8-bit CCIR601/CCIR656.

The 12 analog input channels accept standard composite,

S-Video, YPrPb video signals in an extensive number of

combinations. AGC and clamp restore circuitry allow an

input video signal peak-to-peak range of 0.5 V to 1.6 V.

Alternatively, these can be bypassed for manual settings.

The advanced and highly flexible digital output interface

enables performance video decoding and conversion in line-

locked, clock-based systems. This makes the device ideally

suited for a broad range of applications with diverse analog

video characteristics, including tape-based sources, broadcast

sources, security/surveillance cameras, and professional

systems.

The fixed 54 MHz clocking of the ADCs and datapath for

all modes allows very precise, accurate sampling and digital

filtering. The line-locked clock output allows the output data

rate, timing signals, and output clock signals to be synchronous,

asynchronous, or line locked even with 5% line length variation.

The output control signals allow glueless interface connections

in almost any application. The ADV7189B modes are set up

over a 2-wire, serial, bidirectional port (I²C-compatible).

The 12-bit accurate A/D conversion provides professional

quality video performance and is unmatched. This allows

true 10-bit resolution in the 10-bit output mode.

The ADV7189B is fabricated in a 3.3 V CMOS process. Its

monolithic CMOS construction ensures greater functionality

with lower power dissipation. The ADV7189B is packaged in a

small, 80-lead LQFP Pb-free package.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADV7189B

TABLE OF CONTENTS

Introduction ...................................................................................... 4

General Setup.............................................................................. 21

SD Color Controls...................................................................... 23

Clamp Operation........................................................................ 25

Luma Filter.................................................................................. 26

Chroma Filter.............................................................................. 29

Gain Operation........................................................................... 30

Chroma Transient Improvement (CTI) .................................. 34

Digital Noise Reduction (DNR)............................................... 34

Comb Filters................................................................................ 35

AV Code Insertion and Controls ............................................. 38

Synchronization Output Signals............................................... 40

Sync Processing .......................................................................... 48

VBI Data Decode ....................................................................... 48

Pixel Port Configuration ............................................................... 60

MPU Port Description................................................................... 61

Register Accesses........................................................................ 62

Register Programming............................................................... 62

I²C Sequencer.............................................................................. 62

I²C Register Maps ........................................................................... 63

I²C Register Map Details ........................................................... 67

I²C Interrupt Register Map ....................................................... 68

I²C Programming Examples.......................................................... 90

Examples Using 28 MHz Clock................................................ 90

Examples Using 27 MHz Clock................................................ 94

PCB Layout Recommendations.................................................... 97

Analog Interface Inputs............................................................. 97

Power Supply Decoupling ......................................................... 97

PLL ............................................................................................... 97

Digital Outputs (Both Data and Clocks) ................................ 97

Digital Inputs .............................................................................. 98

Antialiasing Filters ..................................................................... 98

Analog Front End......................................................................... 4

Standard Definition Processor ................................................... 4

Functional Block Diagram .............................................................. 5

Specifications..................................................................................... 6

Electrical Characteristics............................................................. 6

Video Specifications..................................................................... 7

Timing Specifications .................................................................. 8

Analog Specifications................................................................... 8

Thermal Specifications ................................................................ 9

Timing Diagrams.......................................................................... 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Analog Front End ........................................................................... 13

Analog Input Muxing ................................................................ 13

Global Control Registers ............................................................... 16

Power-Save Modes...................................................................... 16

Reset Control .............................................................................. 16

Global Pin Control..................................................................... 17

Global Status Registers................................................................... 19

Identification............................................................................... 19

Status 1 ......................................................................................... 19

SD Autodetection Result ........................................................... 19

Status 2 ......................................................................................... 19

Status 3 ......................................................................................... 19

Standard Definition Processor (SDP).......................................... 20

SD Luma Path ............................................................................. 20

SD Chroma Path......................................................................... 20

Sync Processing........................................................................... 21

VBI Data Recovery..................................................................... 21

Rev. B | Page 2 of 104

ADV7189B

Crystal Load Capacitor Value Selection...................................98

Outline Dimensions......................................................................101

Ordering Guide .........................................................................101

Typical Circuit Connection ...........................................................99

REVISION HISTORY

9/05—Rev. A to Rev. B

7/05—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................6

Changes to Table 2 ............................................................................7

Changes to Table 3 and Table 4 .......................................................8

Changes to Table 5 ............................................................................9

Changes to Figure 6.........................................................................13

Changes to Table 8 ..........................................................................14

Update Table Formatting................................................................19

Update Page Layout ........................................................................29

Change to Table 34..........................................................................31

Update Table Formatting................................................................39

Change to Table 55..........................................................................40

Changes to Figure 21 ......................................................................42

Update Page Formatting.................................................................49

Change Footnote Numbering in Table 84....................................67

Change to Table 85..........................................................................68

Change to Table 87..........................................................................90

Change to Table 88..........................................................................91

Change to Table Numbering..........................................................94

Updated Format ................................................................. Universal

Changes to Features..........................................................................1

Changes to Analog Specifications...................................................6

Changes to Table 7 ..........................................................................11

Changes to Clamp Operation Section..........................................26

Changes to Table 30 ........................................................................29

Changes to Figure 12, Figure 13, Figure 14, and Figure 15 .......30

Added CSFM[2:0] C-Shaping Filter Mode, Address 0x17[7]

Section and Changes to Figure 16.................................................31

Changes to Luma Gain Section.....................................................32

Changes to Table 54 ........................................................................41

Changes to VSEHO VS End Horizontal Position Odd,

Address 0x33[7] Section.................................................................42

Changes to Table 55 ........................................................................44

Changes to Table 84 ........................................................................69

Changes to Table 85 .......................................................................73

Changes to Table 86 ........................................................................91

Changes to Table 87 ........................................................................92

Changes to Table 88 ........................................................................93

Changes to Table 89 ........................................................................94

Added XTAL Load Capacitor Value Section...............................99

Inserted Figure 44; Renumbered Sequentially ............................99

Changes to Figure 46 ....................................................................101

Updated Outline Dimensions......................................................102

Changes to Ordering Guide.........................................................102

9/04—Revision 0: Initial Version

Rev. B | Page 3 of 104

ADV7189B

INTRODUCTION

The ADV7189B is a high quality, single chip, multiformat video

decoder that automatically detects and converts PAL, NTSC,

and SECAM standards in the form of composite, S-Video, and

component video into a digital ITU-R BT.656 format.

STANDARD DEFINITION PROCESSOR

The ADV7189B is capable of decoding a large selection of base-

band video signals in composite, S-Video, and component

formats. The video standards supported by the ADV7189B

include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc,

NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7189B

can automatically detect the video standard and process it

accordingly. The ADV7189B has a 5-line, super-adaptive, 2D

comb filter that gives superior chrominance and luminance

separation when decoding a composite video signal. This highly

adaptive filter automatically adjusts its processing mode

according to video standard and signal quality with no user

intervention required. Video user controls such as brightness,

contrast, saturation, and hue are also available within the

ADV7189B.

The advanced and highly flexible digital output interface enables

performance video decoding and conversion in line-locked,

clock-based systems. This makes the device ideally suited for a

broad range of applications with diverse analog video charac-

teristics, including tape-based sources, broadcast sources,

security/ surveillance cameras, and professional systems.

ANALOG FRONT END

The ADV7189B analog front end comprises three 12-bit noise

shaped video ADCs that digitize the analog video signal before

applying it to the standard definition processor. The analog front

end employs differential channels to each ADC to ensure high

performance in mixed-signal applications.

The ADV7189B implements a patented adaptive-digital-line-

length-tracking (ADLLT) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7189B to track and decode poor quality video sources

such as VCRs, noisy sources from tuner outputs, VCD players,

and camcorders. The ADV7189B contains a chroma transient

improvement (CTI) processor that sharpens the edge rate of

chroma transitions, resulting in sharper vertical transitions.

The front end also includes a 12-channel input mux that

enables multiple video signals to be applied to the ADV7189B.

Current and voltage clamps are positioned in front of each

ADC to ensure the video signal remains within the range of

the converter. Fine clamping of the video signals is performed

downstream by digital fine clamping within the ADV7189B.

The ADCs are configured to run in 4× oversampling mode.

The ADV7189B can process a variety of VBI data services,

such as closed captioning (CC), wide screen signaling (WSS),

copy generation management system (CGMS), EDTV, Gemstar

1×/2×, and extended data service (XDS). The ADV7189B

is fully Macrovision certified; detection circuitry enables

Type I, Type II, and Type III protection levels to be identified

and reported to the user. The decoder is also fully robust to all

Macrovision signal inputs.

Rev. B | Page 4 of 104

ADV7189B

FUNCTIONAL BLOCK DIAGRAM

OUTPUT FORMATTER

Figure 1.

Rev. B | Page 5 of 104

ADV7189B

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

At A_VDD= 3.15 V to 3.45 V, D_VDD= 1.65 V to 2.0 V, D_VDDIO= 3.0 V to 3.6 V, P_VDD= 1.65 V to 2.0 V, operating temperature range,

unless otherwise specified.

Table 1.

Parameter^{1, 2}

F

Symbol

Test Conditions

Min

Typ

Max

Unit

F

STATIC PERFORMANCE

Resolution (Each ADC)

Integral Nonlinearity

Differential Nonlinearity

DIGITAL INPUTS

N

INL

DNL

12

±±

–0.95/+2

Bits

LSB

BSL at 54 MHz

–1.5/+2.5

–0.7/+0.7

Input High Voltage

Input Low Voltage

V_IH

V_IL

I_IN

2

V

μA

pF

0.±

Input Current³

F

–50

–10

+50

+10

10

All other pins

Input Capacitance

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

C_IN

V_OH

V_OL

I_LEAK

I_SOURCE= 0.4 mA

I_SINK= 3.2 mA

2.4

V

μA

pF

0.4

50

10

20

High Impedance Leakage Current⁴

F

All other pins

Output Capacitance

C_OUT

POWER REQUIREMENTS⁵

F

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

Analog Power Supply

Digital Core Supply Current

Digital I/O Supply Current

PLL Supply Current

D_VDD

D_VDDIO

P_VDD

A_VDD

I_DVDD

I_DVDDIO

I_PVDD

1.65

3.0

1.65

3.15

1.±

3.3

1.±

3.3

±2

2

10.5

±5

2

V

mA

ms

3.6

2.0

3.45

Analog Supply Current

I_AVDD

CVBS input⁶

YPrPb input⁷

F

1±0

1.5

20

Power-Down Current

Power-Up Time

I_PWRDN

t_PWRUP

¹Temperature range: T_MINto T_MAX, –40°C to +±5°C. (0°C to 70°C for ADV71±9BKSTZ)

²The min/max specifications are guaranteed over this range.

³Pin 36 and Pin 79.

⁴Pin 1, Pin 2, Pin 5 to Pin ±, Pin 12, Pin 17 to Pin 24, Pin 32 to Pin 35, Pin 73 to Pin 76, and Pin ±0.

⁵Guaranteed by characterization.

⁶ADC1 powered on.

⁷All three ADCs powered on.

Rev. B | Page 6 of 104

ADV7189B

VIDEO SPECIFICATIONS

Guaranteed by characterization. At A_VDD= 3.15 V to 3.45 V, D_VDD= 1.65 V to 2.0 V, D_VDDIO= 3.0 V to 3.6 V, P_VDD= 1.65 V to 2.0 V;

operating temperature range, unless otherwise specified.

Table 2.

Parameter^{1, 2}

F

Symbol

Test Conditions

Min

Typ

Max

Unit

F

NONLINEAR SPECIFICATIONS

Differential Phase

Differential Gain

Luma Nonlinearity

NOISE SPECIFICATIONS

SNR Unweighted

DP

DG

LNL

CVBS I/P, modulate 5-step

CVBS I/P, 5-step

0.4

0.6

0.7

Degrees

%

Luma ramp

61

63

65

60

dB

Luma flat field

Analog Front End Crosstalk

LOCK TIME SPECIFICATIONS

Horizontal Lock Range

Vertical Lock Range

–5

40

+5

70

%

Hz

F_SCSubcarrier Lock Range

Color Lock In Time

Sync Depth Range

±1.3

60

Hz

Lines

%

20

5

200

Color Burst Range

%

Vertical Lock Time

2

100

Fields

Lines

Autodetection Switch Speed

CHROMA SPECIFICATIONS

Hue Accuracy

Color Saturation Accuracy

Color AGC Range

HUE

CL_AC

1

Degrees

%

5

400

Chroma Amplitude Error

Chroma Phase Error

Chroma Luma Intermodulation

LUMA SPECIFICATIONS

Luma Brightness Accuracy

Luma Contrast Accuracy

0.4

0.3

0.1

%

Degrees

%

CVBS, 1 V I/P

1

%

¹Temperature range: T_MINto T_MAX, –40°C to +±5°C. (0°C to 70°C for ADV71±9BKSTZ).

²The min/max specifications are guaranteed over this range.

Rev. B | Page 7 of 104

ADV7189B

TIMING SPECIFICATIONS

Guaranteed by characterization. A_VDD= 3.15 V to 3.45 V, D_VDD= 1.65 V to 2.0 V, D_VDDIO= 3.0 V to 3.6 V, P_VDD= 1.65 V to 2.0 V; operating

temperature range, unless otherwise specified.

Table 3.

Parameter^{1, 2}

F

Symbol

Test Conditions

Min

Typ

Max

Unit

F

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency

Frequency Stability

I²C PORT

SCLK Frequency

2±.6363

MHz

ppm

±50

400

kHz

μs

ns

μs

SCLK Min Pulse Width High

SCLK Min Pulse Width Low

Hold Time (Start Condition)

Setup Time (Start Condition)

SDA Setup Time

SCLK and SDA Rise Time

SCLK and SDA Fall Time

Setup Time for Stop Condition

RESET FEATURE

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t_±

0.6

1.3

0.6

100

300

0.6

Reset Pulse Width

5

ms

CLOCK OUTPUTS

LLC1 Mark Space Ratio

t₉:t₁₀

45:55

55:45

% duty

cycle

LLC1 Rising to LLC2 Rising

LLC1 Rising to LLC2 Falling

DATA AND CONTROL OUTPUTS

Data Output Transitional Time

t₁₁

t₁₂

0.5

ns

t₁₃

t₁₄

Negative clock edge to start of

valid data (t_ACCESS= t₁₀– t₁₃)

End of valid data to negative

clock edge (t_HOLD= t₉+ t₁₄)

3.4

2.4

ns

Data Output Transitional Time

Propagation Delay to Hi Z

Max Output Enable Access Time

Min Output Enable Access Time

t₁₅

t₁₆

t₁₇

6

7

4

ns

¹Temperature range: T_MINto T_MAX, –40°C to +±5°C. (0°C to 70°C for ADV71±9BKSTZ).

²The min/max specifications are guaranteed over this range.

ANALOG SPECIFICATIONS

Guaranteed by characterization. A_VDD= 3.15 V to 3.45 V, D_VDD= 1.65 V to 2.0 V, D_VDDIO= 3.0 V to 3.6 V, P_VDD= 1.65 V to 2.0 V; operating

temperature range, unless otherwise specified. Recommended Analog input video signal range 0.5 V to 1.5 V, typically 1 V p-p.

Table 4.

Parameter^{1, 2}

F

Symbol

Test Condition

Min

Typ

Max

Unit

F

CLAMP CIRCUITRY

External Clamp Capacitor

Input Impedance

Large Clamp Source Current

Large Clamp Sink Current

Fine Clamp Source Current

Fine Clamp Sink Current

0.1

10

0.75

60

μF

Clamps switched off

MΩ

mA

μA

60

μA

¹Temperature range: T_MINto T_MAX, –40°C to +±5°C. (0°C to 70°C for ADV71±9BKSTZ).

²The min/max specifications are guaranteed over this range.

Rev. B | Page ± of 104

ADV7189B

THERMAL SPECIFICATIONS

Table 5.

Parameter^{1, 2}

F

Symbol

Test Conditions

Min Typ

Max Unit

F

THERMAL CHARACTERISTICS

Junction-to-Case Thermal Resistance

Junction-to-Ambient Thermal Resistance (Still Air)

θ_JC

θ_JA

4-layer PCB with solid ground plane

7.6

3±.1

°C/W

¹Temperature range: T_MINto T_MAX, –40°C to +±5°C. (0°C to 70°C for ADV71±9BKSTZ)

²The min/max specifications are guaranteed over this range.

TIMING DIAGRAMS

t₅

t₃

SDA

t₁

t₆

SCLK

t₄

t₇

t₈

t₂

Figure 2. I²C Timing

t₉

t₁₀

OUTPUT LLC 1

OUTPUT LLC 2

t₁₁

t₁₂

t₁₃

t₁₄

OUTPUTS P0–P19, VS,

HS, FIELD,

SFL

Figure 3. Pixel Port and Control Output Timing

OE

t₁₅

t₁₇

P0–P19, HS,

VS, FIELD,

SFL

t₁₆

OE

Figure 4.

Timing

Rev. B | Page 9 of 104

ADV7189B

ABSOLUTE MAXIMUM RATINGS

Table 6.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to abso-

lute maximum rating conditions for extended periods may

affect device reliability.

Parameter

Rating

A_VDDto GND

4 V

A_VDDto AGND

4 V

D_VDDto DGND

2.2 V

P_VDDto AGND

2.2 V

D_VDDIOto DGND

D_VDDIOto AVDD

P_VDDto D_VDD

D_VDDIO– P_VDD

D_VDDIO– D_VDD

4 V

–0.3 V to +0.3 V

–0.3 V to +2 V

–0.3 V to D_VDDIO+ 0.3 V

AGND – 0.3 V to A_VDD+ 0.3 V

150°C

A_VDD– P_VDD

A_VDD– D_VDD

Digital Inputs Voltage to DGND

Digital Output Voltage to DGND

Analog Inputs to AGND

Maximum Junction Temperature

(T_JMax)

Storage Temperature Range

–65°C to +150°C

Infrared Reflow Soldering (20 sec) 260°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page 10 of 104

ADV7189B

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

VS

HS

1

2

3

4

5

6

7

8

9

60 AIN5

59 AIN11

58 AIN4

DGND

DVDDIO

P15

57 AIN10

56 AGND

55 CAPC2

54 CAPC1

53 AGND

52 CML

P14

P13

P12

DGND

ADV7189B

TOP VIEW

(Not to Scale)

DVDD 10

11

51 REFOUT

50 AVDD

49 CAPY2

48 CAPY1

47 AGND

46 AIN3

INTRQ

SFL 12

NC 13

DGND 14

DVDDIO 15

NC 16

45 AIN9

P11 17

44 AIN2

P10 18

43 AIN8

P9 19

42 AIN1

P8 20

41 AIN7

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

NC = NO CONNECT

Figure 5. 80-Lead LQFP Pin Configuration

Rev. B | Page 11 of 104

ADV7189B

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type Function

3, 9, 14, 31, 71 DGND

G

Digital Ground.

Analog Ground.

39, 40, 47, 53,

56

AGND

4, 15

10, 30, 72

50

DVDDIO

DVDD

AVDD

PVDD

AIN1toAIN12

P

I

Digital I/O Supply Voltage (3.3 V).

Digital Core Supply Voltage (1.± V).

Analog Supply Voltage (3.3 V).

PLL Supply Voltage (1.± V).

3±

42, 44, 46, 5±,

60, 62, 41, 43,

45, 57, 59, 61

Analog Video Input Channels.

11

INTRQ

NC

O

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input

video. See the interrupt register map in Table ±6.

No Connect Pins.

13, 16, 25, 63,

65, 69, 70, 77,

7±

35 to32, 24 to P0–P19

17, ± to 5,

O

Video Pixel Output Port.

76 to 73

2

1

±0

67

6±

66

HS

VS

FIELD

SDA

SCLK

ALSB

O

I/O

I

Horizontal Synchronization Output Signal.

Vertical Synchronization Output Signal.

Field Synchronization Output Signal.

I²C Port Serial Data Input/Output Pin.

I²C Port Serial Clock Input (Max Clock Rate of 400 kHz).

This pin selects the I²C address for the ADV71±9B. ALSB set to a Logic 0 sets the address for a

write as 0x40; for ALSB set to a logic high, the address selected is 0x42.

I

64

27

26

29

2±

RESET

LLC1

I

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset

the ADV71±9B circuitry.

This is a line-locked output clock for the pixel data output by the ADV71±9B. Nominally 27 MHz,

but varies up or down according to video line length.

This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV71±9B.

Nominally 13.5 MHz, but varies up or down according to video line length.

This is the input pin for the 2±.6363 MHz crystal, or can be overdriven by an external 3.3 V,

27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

O

I

LLC2

XTAL

XTAL1

O

This pin should be connected to the 2±.6363 MHz crystal or left as a no connect if an external

3.3 V, 27 MHz clock oscillator source is used to clock the ADV71±9B. In crystal mode, the crystal

must be a fundamental crystal.

36

79

PWRDN

OE

I

A logic low on this pin places the ADV71±9B in a power-down mode. Refer to Power

Management Register in the I2C Register Maps section for more options on power-down

modes for the ADV71±9B.

When set to a logic low, OE enables the pixel output bus, P19 toP0 of the ADV71±9B. A logic

high on the OE pin places Pins P19 to P0, HS, VS, SFL into a high impedance state.

37

12

ELPF

SFL

I

The recommended external loop filter must be connected to this ELPF pin, as shown in

Figure 46.

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the

subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video

encoder.

O

51

52

REFOUT

CML

O

Internal Voltage Reference Output. Refer to Figure 46 for a recommended capacitor network for

this pin.

The CML pin is a common-mode level for the internal ADCs. Refer to Figure 46 for a

recommended capacitor network for this pin.

4±, 49

54, 55

CAPY1, CAPY2

CAPC1, CAPC2

I

ADC’s Capacitor Network. Refer to Figure 46 for a recommended capacitor network for this pin.

Rev. B | Page 12 of 104

ADV7189B

ANALOG FRONT END

ANALOG INPUT MUXING

ADC_SW_MAN_EN

INSEL[3:0]

INTERNAL

MAPPING

FUNCTIONS

AIN1

AIN7

AIN2

AIN8

AIN3

AIN9

AIN4

AIN10

AIN5

AIN11

AIN6

AIN12

ADC0_SW[3:0]

1

0

ADC0

AIN3

AIN9

AIN4

AIN10

AIN5

AIN11

AIN6

AIN12

ADC1_SW[3:0]

1

0

ADC1

ADC2_SW[3:0]

ADC2

AIN2

AIN8

AIN5

AIN11

AIN6

AIN12

1

0

Figure 6. Internal Pin Connections

ADI Recommended Input Muxing

The ADV7189B has an integrated analog muxing section that

allows more than one source of video signal to be connected to

the decoder. Figure 6 outlines the overall structure of the input

muxing provided in the ADV7189B.

A maximum of 12 CVBS inputs can be connected and decoded

by the ADV7189B. As seen in Figure 5, this means the sources

have to be connected to adjacent pins on the IC. This calls for a

careful design of the PCB layout, for example, ground shielding

between all signals routed through tracks that are physically

close together.

As can be seen in Figure 6, there are two different ways in which

the analog input muxes can be controlled:

•

Control via functional registers (INSEL). Using INSEL[3:0]

simplifies the setup of the muxes, and minimizes crosstalk

between channels by pre-assigning the input channels.

This is referred to as ADI recommended input muxing.

INSEL[3:0] Input Selection, Address 0x00[3:0]

The INSEL bits allow the user to select an input channel as well

as the input format. Depending on the PCB connections, only

a subset of the INSEL modes are valid. The INSEL[3:0] does

not only switch the analog input muxing, it also configures the

standard definition processor core to process CVBS (Comp),

S-Video (Y/C), or component (YPbPr) format.

Control via an I²C manual override (ADC_sw_man_en,

ADC0_sw, ADC1_sw, ADC2_sw). This is provided for

applications with special requirements, for example,

number/combinations of signals that would not be

served by the pre-assigned input connections. This is

referred to as manual input muxing.

Refer to Figure 7 for an overview of the two methods of

controlling the ADV7189B’s input muxing.

Rev. B | Page 13 of 104

ADV7189B

CONNECTING

ANALOG SIGNALS

TO ADV7189

ADI-RECOMMENDED

INPUT MUXING; SEE TABLE 9

YES

NO

SET INSEL[3:0] FOR REQUIRED

MUXING CONFIGURATION

SET INSEL[3:0] TO

CONFIGURE ADV7189B TO

DECODE VIDEO FORMAT:

CVBS: 0000

YC: 0110

YPrPb: 1001

USE MANUAL INPUT MUXING

(ADC_SW_MAN_EN, ADC0_SW,

ADC1_SW, ADC2_SW)

Figure 7. Input Muxing Overview

Table 8. Input Channel Switching Using INSEL[3:0]

Table 9. Input Channel Assignments

Description

Input

Channel No.

ADI Recommended Input Muxing Control

INSEL[3:0]

0000

0001

0010

0011

0100

0101

0110

Analog Input Pins

CVBS1 = AIN1 (default)

CVBS2 = AIN2

CVBS3 = AIN3

CVBS4 = AIN4

CVBS5 = AIN5

CVBS6 = AIN6

Y1 = AIN1

Video Format

Composite

YC

AIN7

AIN1

AIN±

AIN2

AIN9

AIN3

AIN10

AIN4

AIN11

AIN5

AIN12

AIN6

41

42

43

44

45

46

57

5±

59

60

61

62

CVBS7

CVBS1

CVBS±

CVBS2

CVBS9

CVBS3

CVBS10

CVBS4

CVBS11

CVBS5

Not Available

CVBS6

YC1-Y

YC2-Y

YC3-Y

YC1-C

YC2-C

YC3-C

YPrPb1-Y

YPrPb2-Y

YPrPb2-Pb

YPrPb1-Pb

YPrPb1-Pr

YPrPb2-Pr

C1 = AIN4

Y2 = AIN2

C2 = AIN5

Y3 = AIN3

YC

0111

1000

1001

C3 = AIN6

YC

Y1 = AIN1

PB1 = AIN4

PR1 = AIN5

Y2 = AIN2

YPrPb

ADI-recommended input muxing is designed to minimize

crosstalk between signal channels and to obtain the highest

level of signal integrity. Table 9 summarizes how the PCB lay-

out should connect analog video signals to the ADV7189B.

1010

PB2 = AIN3

YPrPb

It is strongly recommended to connect any unused analog input

pins to AGND to act as a shield.

PR2 = AIN6

YPrPb

1011

1100

1101

1110

1111

CVBS7 = AIN7

CVBS± = AIN±

CVBS9 = AIN9

CVBS10 = AIN10

CVBS11 = AIN11

Composite

Inputs AIN7 to AIN11 should be connected to AGND when

only six input channels are used. This improves the quality

of the sampling due to better isolation between channels.

AIN12 is not under the control of INSEL[3:0]. It can only be

routed to ADC0/ADC1/ADC2 by manual muxing. See Table 10

for further details.

Rev. B | Page 14 of 104

ADV7189B

This means INSEL must be used to tell the ADV7189B whether

the input signal is of component, YC, or CVBS format.

Manual Input Muxing

By accessing a set of manual override muxing registers, the

analog input muxes of the ADV7189B can be controlled

directly. This is referred to as manual input muxing.

Restrictions in the channel routing are imposed by the analog

signal routing inside the IC; every input pin cannot be routed

to each ADC. Refer to Figure 6 for an overview on the routing

capabilities inside the chip. The three mux sections can be

controlled by the reserved control signal buses ADC0/ADC1/

ADC2_sw[3:0]. Table 10 explains the control words used.

Manual input muxing overrides other input muxing control

bits, for example, INSEL. The manual muxing is activated by

setting the ADC_SW_MAN_EN bit. It only affects the analog

switches in front of the ADCs.

SETADC_sw_man_en, Manual Input Muxing Enable,

Address C4[7]

This means if the settings of INSEL and the manual input

muxing registers (ADC0/1/2_sw) contradict each other, the

ADC0/ADC1/ADC2_sw settings apply and INSEL is ignored.

ADC0_sw[3:0], ADC0 Mux Configuration, Address 0xC3[3:0]

ADC1_sw[3:0], ADC1 Mux Configuration, Address 0xC3[7:4]

ADC2_sw[3:0], ADC2 Mux Configuration, Address 0xC4[3:0]

Manual input muxing controls only the analog input muxes.

INSEL[3:0] still has to be set so the follow-on blocks process

the video data in the correct format.

Table 10. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1)

ADC0_sw[3:0]

ADC0 Connected To:

No Connection

AIN1

AIN2

AIN3

ADC1_sw[3:0]

ADC1 Connected To:

No Connection

AIN3

ADC2_sw[3:0]

0000

0001

0010

0011

ADC2 Connected To:

No Connection

AIN2

No Connection

AIN5

0000

0001

0010

0011

0100

0101

0000

0001

0010

0011

0100

0101

AIN4

AIN5

AIN4

AIN5

0100

0101

0110

AIN6

0110

AIN6

0110

AIN6

0111

1000

1001

1010

1011

1100

1101

No Connection

AIN7

AIN±

AIN9

0111

1000

1001

1010

1011

1100

1101

No Connection

AIN9

0111

1000

1001

1010

1011

1100

1101

No Connection

AIN±

No Connection

AIN11

AIN10

AIN11

AIN10

AIN11

1110

AIN12

1110

AIN12

1110

AIN12

1111

No Connection

1111

No Connection

1111

No Connection

Rev. B | Page 15 of 104

ADV7189B

GLOBAL CONTROL REGISTERS

PWRDN_ADC_0, Address 0x3A[3]

Register control bits listed in this section affect the whole chip.

When PWRDN_ADC_0 is 0 (default), the ADC is in normal

operation.

POWER-SAVE MODES

Power-Down

When PWRDN_ADC_0 is 1, ADC 0 is powered down.

PDBP, Address 0x0F[2]

The digital core of the ADV7189B can be shut down by using a

PWRDN_ADC_1, Address 0x3A[2]

pin (

) and a bit (

, see below). The PDBP con-

PWRDN

trols which of the two has the higher priority. The default is to

give the pin ( ) priority. This allows the user to have the

PWRDN

When PWRDN_ADC_1 is 0 (default), the ADC is in normal

operation.

PWRDN

When PWRDN_ADC_1 is 1, ADC 1 is powered down.

ADV7189B powered down by default.

PWRDN_ADC_2, Address 0x3A[1]

When PDBD is 0 (default), the digital core power is controlled

by the

pin (the bit is disregarded).

PWRDN

When PWRDN_ADC_2 is 0 (default), the ADC is in normal

operation.

When PDBD is 1, the bit has priority (the pin is disregarded).

When PWRDN_ADC_2 is 1, ADC 2 is powered down.

PWRDN, Address 0x0F[5]

RESET CONTROL

Chip Reset (RES), Address 0x0F[7]

Setting the PWRDN bit switches the ADV7189B into a chip-

wide power-down mode. The power down stops the clock

from entering the digital section of the chip, thereby freezing

its operation. No I²C bits are lost during power down. The

PWRDN bit also affects the analog blocks and switches them

into low current modes. The I²C interface itself is unaffected,

and remains operational in power-down mode.

Setting this bit, equivalent to controlling the

pin on the

RESET

ADV7189B, issues a full chip reset. All I²C registers get reset to

their default values. Note: Some register bits do not have a reset

value specified. They keep their last written value. These bits are

marked as having a reset value of x in the register table. After

the reset sequence, the part immediately starts to acquire the

incoming video signal.

The ADV7189B leaves the power-down state if the PWRDN bit

is set to 0 (via I²C), or if the overall part is reset using the

pin.

RESET

After setting the RES bit, or initiating a reset via the pin, the

part returns to the default mode of operation with respect to

its primary mode of operation. All I²C bits are loaded with

their default values, making this bit self-clearing.

Note: PDBP must be set to 1 for the PWRDN bit to power down

the ADV7189B.

When PWRDN is 0 (default), the chip is operational.

When PWRDN is 1, the ADV7189B is in chip-wide power down.

ADC Power-Down Control

Executing a software reset takes approximately 2 ms. However,

it is recommended to wait 5 ms before any further I²C writes are

performed.

The I²C master controller receives a no-acknowledge condi-

tion on the ninth clock cycle when chip reset is implemented.

See the MPU Port Description section for a full description.

The ADV7189B contains three 12-bit ADCs (ADC 0, ADC 1,

and ADC 2). If required, it is possible to power down each ADC

individually.

When RES is 0 (default), operation is normal.

When RES is 1, the reset sequence starts.

The ADCs should be powered down when in:

•

CVBS mode. ADC 1 and ADC 2 should be powered down

to save on power consumption.

•

S-Video mode. ADC 2 should be powered down to save on

power consumption.

Rev. B | Page 16 of 104

ADV7189B

Individual drive strength controls are provided via the

DR_STR_XX bits.

GLOBAL PIN CONTROL

Three-State Output Drivers

TOD, Address 0x03[6]

When TIM_OE is 0 (default), HS, VS, and FIELD are three-

stated according to the TOD bit.

This bit allows the user to three-state the output drivers of the

ADV7189B.

When TIM_OE is 1, HS, VS, and FIELD are forced active all

the time.

Upon setting the TOD bit, the P[19:0], HS, VS, FIELD, and SFL

pins are three-stated.

Drive Strength Selection (Data)

DR_STR[1:0] Address 0xF4[5:4]

The timing pins (HS/VS/FIELD) can be forced active via the

TIM_OE bit. For more information on three-state control, refer

to the Three-State LLC Drivers and the Timing Signals Output

Enable sections.

For EMC and crosstalk reasons, it can be desirable to strengthen

or weaken the drive strength of the output drivers. The

DR_STR[1:0] bits affect the P[19:0] output drivers.

Individual drive strength controls are provided via the

DR_STR_XX bits.

For more information on three-state control, refer to the Drive

Strength Selection (Clock) and the Drive Strength Selection

(Sync) sections.

The ADV7189B supports three-stating via a dedicated pin.

Table 11. DR_STR_C Function

When set high, the

pin three-states the output drivers for

OE

P[19:0], HS, VS, FIELD, and SFL. The output drivers are three-

stated if the TOD bit or the pin is set high.

DR_STR_C[1:0]

Description

00

Low drive strength (1×).

Medium low drive strength (2×).

Medium high drive strength (3×).

High drive strength (4×).

OE

01 (default)

10

11

When TOD is 0 (default), the output drivers are enabled.

When TOD is 1, the output drivers are three-stated.

Three-State LLC Drivers

Drive Strength Selection (Clock)

TRI_LLC, Address 0x1D[7]

DR_STR_C[1:0] Address 0xF4[3:2]

This bit allows the output drivers for the LLC1 pin and LLC2

pin of the ADV7189B to be three-stated. For more information

on three-state control, refer to the Three-State Output Drivers

and the Timing Signals Output Enable sections.

The DR_STR_C[1:0] bits can be used to select the strength of

the clock signal output driver (LLC pin). For more information,

refer to the Drive Strength Selection (Sync) and the Drive

Strength Selection (Data) sections.

Table 12. DR_STR_C Function

Individual drive strength controls are provided via the

DR_STR_XX bits.

DR_STR_C[1:0]

Description

00

Low drive strength (1×).

Medium low drive strength (2×).

Medium high drive strength (3×).

High drive strength (4×).

When TRI_LLC is 0 (default), the LLC pin drivers work

according to the DR_STR_C[1:0] setting (pin enabled).

01 (default)

10

11

When TRI_LLC is 1, the LLC pin drivers are three-stated.

Timing Signals Output Enable

Drive Strength Selection (Sync)

TIM_OE, Address 0x04[3]

DR_STR_S[1:0] Address 0xF4[1:0]

The TIM_OE bit should be regarded as an addition to the

TOD bit. Setting it high forces the output drivers for HS, VS,

and FIELD into the active (that is, driving) state even if the

TOD bit is set. If set to low, the HS, VS, and FIELD pins are

three-stated dependent on the TOD bit. This functionality is

useful if the decoder is to be used as a timing generator only.

This may be the case if only the timing signals are to be

extracted from an incoming signal, or if the part is in free-

run mode where a separate chip can output, for instance, a

company logo.

The DR_STR_S[1:0] bits allow the user to select the strength of

the synchronization signals with which HS, VS, and F are driven.

For more information, refer to the Drive Strength Selection

(Clock) and the Drive Strength Selection (Data) sections.

Table 13. DR_STR_S Function

DR_STR_S[1:0]

Description

00

Low drive strength (1×).

Medium low drive strength (2×).

Medium high drive strength (3×).

High drive strength (4×).

01 (default)

10

11

For more information on three-state control, refer to the Three-

State Output Drivers and the Three-State LLC Drivers sections.

Rev. B | Page 17 of 104

ADV7189B

Enable Subcarrier Frequency Lock Pin

Polarity LLC Pin

EN_SFL_PIN Address 0x04[1]

PCLK Address 0x37[0]

The EN_SFL_PIN bit enables the output of subcarrier lock

information (also known as GenLock) from the ADV7189B

core to an encoder in a decoder-encoder back-to-back

arrangement.

The polarity of the clock that leaves the ADV7189B via the

LLC1 and LLC2 pins can be inverted using the PCLK bit.

Changing the polarity of the LLC clock output can be necessary

to meet the setup-and-hold time expectations of follow-on

chips.

When EN_SFL_PIN is 0 (default), the subcarrier frequency

lock output is disabled.

Note: This bit also inverts the polarity of the LLC2 clock.

When PCLK is 0, the LLC output polarity is inverted.

When EN_SFL_PIN is 1, the subcarrier frequency lock

information is presented on the SFL pin.

When PCLK is 1 (default), the LLC output polarity is normal

(as per the Timing Diagrams).

Rev. B | Page 1± of 104

ADV7189B

GLOBAL STATUS REGISTERS

Table 15. STATUS 1 Function

Four registers provide summary information about the video

decoder. The IDENT register allows the user to identify the

revision code of the ADV7189B. The other three registers

contain status bits from the ADV7189B.

STATUS 1[7:0]

Bit Name

Description

0

1

IN_LOCK

LOST_LOCK

In lock (right now).

Lost lock (since last read of

this register).

2

3

FSC_LOCK

FOLLOW_PW AGC follows peak white

algorithm.

F_SClocked (right now).

IDENTIFICATION

IDENT[7:0] Address 0x11[7:0]

This register provides identification of the revision of

the ADV7189B.

4

5

6

7

AD_RESULT.0 Result of autodetection.

AD_RESULT.1 Result of autodetection.

AD_RESULT.2 Result of autodetection.

An identification value of 0x11 indicates the ADV7189,

released silicon.

COL_KILL

Color kill active.

STATUS 2

STATUS_2[7:0], Address 0x12[7:0]

Table 16. STATUS 2 Function

An identification value of 0x13 indicates the ADV7189B silicon.

STATUS 1

STATUS_1[7:0] Address 0x10[7:0]

STATUS 2[7:0] Bit Name

Description

0

MVCS DET

Detected Macrovision color

striping.

Macrovision color striping

protection. Conforms to

Type 3 if high, to Type 2 if

low.

Detected Macrovision

pseudo sync pulses.

Detected Macrovision AGC

pulses.

This read-only register provides information about the internal

status of the ADV7189B. These bits are used to set VS free run

(coast) frequency. See the VS_Coast[1:0], Address

0xF9[3:2]section and COL[2:0] Count Out-of-Lock, Address

0x51[5:3] for information on the timing.

1

MVCS T3

2

3

MV_PS DET

Depending on the setting of the FSCLE bit, the Status[0] and

Status[1] are based solely on horizontal timing information or

on the horizontal timing and lock status of the color subcarrier.

See the FSCLE FSC Lock Enable, Address 0x51[7] section.

MV_AGC DET

4

5

LL_NSTD

FSC_NSTD

Line length is nonstandard.

F_SCfrequency is

nonstandard.

SD AUTODETECTION RESULT

6

7

Reserved

AD_RESULT[2:0] Address 0x10[6:4]

The AD_RESULT[2:0] bits report back on the findings from

the autodetection block. For more information on enabling

the autodetection block, see the General Setup section. For

information on configuring it, see the Autodetection of SD

Modes section.

STATUS 3

STATUS_3[7:0], Address 0x13[7:0]

Table 17. STATUS 3 Function

STATUS 3[7:0] Bit Name

Description

0

INST_HLOCK

Horizontal lock indicator

(instantaneous).

Gemstar Detect.

Flags whether 50 Hz or

60 Hz is present at output.

Table 14. AD_RESULT Function

AD_RESULT[2:0]

Description

1

2

GEMD

SD_OP_50HZ

000

001

010

011

100

101

110

111

NTSM-MJ

NTSC-443

PAL-M

PAL-60

PAL-BGHID

SECAM

3

4

Reserved for future use.

FREE_RUN_ACT ADV71±9B outputs a blue

screen (see the DEF_VAL_EN

Default Value Enable,

PAL-Combination N

SECAM 525

Address 0x0C[0] section).

5

STD_FLD_LEN

Field length is correct for

currently selected video

standard.

6

7

INTERLACED

Interlaced video detected

(field sequence found).

Reliable sequence of

PAL_SW_LOCK

swinging bursts detected.

Rev. B | Page 19 of 104

ADV7189B

STANDARD DEFINITION PROCESSOR (SDP)

STANDARD DEFINITION PROCESSOR

MACROVISION

DETECTION

STANDARD

AUTODETECTION

SLLC

CONTROL

VBI DATA

RECOVERY

LUMA

DIGITAL

FINE

DIGITIZED CVBS

DIGITIZED Y (YC)

LUMA

2D COMB

LUMA

FILTER

GAIN

CONTROL

LUMA

RESAMPLE

CLAMP

LINE

AV

SYNC

EXTRACT

RESAMPLE

CONTROL

VIDEO DATA

OUTPUT

LENGTH

CODE

PREDICTOR

INSERTION

CHROMA

DIGITAL

FINE

MEASUREMENT

BLOCK (= >I C)

DIGITIZED CVBS

DIGITIZED C (YC)

CHROMA

DEMOD

CHROMA

FILTER

GAIN

CONTROL

CHROMA

RESAMPLE

CHROMA

2D COMB

2

CLAMP

VIDEO DATA

PROCESSING

BLOCK

F

SC

RECOVERY

Figure 8. Block Diagram of the Standard Definition Processor

A block diagram of the ADV7189B’s standard definition

processor (SDP) is shown in Figure 8.

SD CHROMA PATH

The input signal is processed by the following blocks:

The ADV7189B block can handle standard definition video in

CVBS, YC, and YPrPb formats. It can be divided into a lumi-

nance and chrominance path. If the input video is of a composite

type (CVBS), both processing paths are fed with the CVBS input.

•

Digital Fine Clamp. This block uses a high precision

algorithm to clamp the video signal.

•

Chroma Demodulation. This block employs a color sub-

carrier (F_SC) recovery unit to regenerate the color subcarrier

for any modulated chroma scheme. The demodulation

block then performs an AM demodulation for PAL and

NTSC and an FM demodulation for SECAM.

SD LUMA PATH

The input signal is processed by the following blocks:

•

Digital Fine Clamp. This block uses a high precision

algorithm to clamp the video signal.

•

Chroma Filter Block. This block contains a chroma

decimation filter (CAA) with a fixed response, and some

shaping filters (CSH) that have selectable responses.

•

Luma Filter Block. This block contains a luma decimation

filter (YAA) with a fixed response, and some shaping filters

(YSH) that have selectable responses.

Gain Control. Automatic gain control (AGC) can operate

on several different modes, including gain based on the

color subcarrier’s amplitude, gain based on the depth of

the horizontal sync pulse on the luma channel, or fixed

manual gain.

•

Luma Gain Control. The automatic gain control (AGC)

can operate on a variety of different modes, including gain

based on the depth of the horizontal sync pulse, peak white

mode, and fixed manual gain.

•

Chroma Resample. The chroma data is digitally resampled

to keep it perfectly aligned with the luma data. The

resampling is done to correct for static and dynamic line-

length errors of the incoming video signal.

•

Luma Resample. To correct for line-length errors and

dynamic line-length changes, the data is digitally resampled.

Luma 2D Comb. The two-dimensional comb filter

provides YC separation.

•

Chroma 2D Comb. The two-dimensional, 5-line,

superadaptive comb filter provides high quality YC

separation in case the input signal is CVBS.

AV Code Insertion. At this point, the decoded luma (Y)

signal is merged with the retrieved chroma values. AV

codes (as per ITU-R. BT-656) can be inserted.

AV Code Insertion. At this point, the demodulated chroma

(Cr and Cb) signal is merged with the retrieved luma

values. AV codes (as per ITU-R. BT-656) can be inserted.

Rev. B | Page 20 of 104

ADV7189B

SYNC PROCESSING

GENERAL SETUP

Video Standard Selection

The ADV7189B extracts syncs embedded in the video data

stream. There is currently no support for external HS/VS

inputs. The sync extraction has been optimized to support

imperfect video sources such as VCRs with head switches. The

actual algorithm used employs a coarse detection based on a

threshold crossing followed by a more detailed detection using

an adaptive interpolation algorithm. The raw sync information

is sent to a line-length measurement and prediction block. The

output of this is then used to drive the digital resampling

section to ensure that the ADV7189B outputs 720 active pixels

per line.

The VID_SEL[3:0] register allows the user to force the digital

core into a specific video standard. Under normal circumstances,

this should not be necessary. The VID_SEL[3:0] bits default to

an autodetection mode that supports PAL, NTSC, SECAM, and

variants thereof. The following section provides more informa-

tion on the autodetection system.

Autodetection of SD Modes

To guide the autodetect system of the ADV7189B, individ-

ual enable bits are provided for each of the supported video

standards. Setting the relevant bit to 0 inhibits the standard

from being detected automatically. Instead, the system picks

the closest of the remaining enabled standards. The results of

the autodetection can be read back via the status registers. See

the Global Status Registers section for more information.

The sync processing on the ADV7189B also includes the

following specialized postprocessing blocks that filter and

condition the raw sync information retrieved from the

digitized analog video.

•

Vsync Processor. This block provides extra filtering of

the detected Vsyncs to give improved vertical lock.

VID_SEL[3:0] Address 0x00[7:4]

Table 18. VID_SEL Function

VID_SEL[3:0]

Description

•

Hsync Processor. The Hsync processor is designed to filter

incoming Hsyncs that are corrupted by noise, providing

much improved performance for video signals with stable

time base but poor SNR.

0000 (default)

Autodetect (PAL BGHID) <–> NTSC J (no

pedestal), SECAM.

Autodetect (PAL BGHID) <–> NTSC M

(pedestal), SECAM.

Autodetect (PAL N) (pedestal) <–> NTSC J (no

pedestal), SECAM.

Autodetect (PAL N) (pedestal) <–> NTSC M

(pedestal), SECAM.

0001

0010

0011

VBI DATA RECOVERY

The ADV7189B can retrieve the following information from

the input video:

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

NTSC J (1).

NTSC M (1).

PAL 60.

NTSC 4.43 (1).

•

Wide-screen signaling (WSS)

Copy generation management system (CGMS)

Closed captioning (CC)

PAL BGHID.

PAL N[= PAL BGHID (with pedestal)].

PAL M (without pedestal).

PAL M.

PAL Combination N.

PAL Combination N (with pedestal).

SECAM.

Macrovision protection presence

EDTV data

Gemstar-compatible data slicing

The ADV7189B is also capable of automatically detecting

the incoming video standard with respect to

SECAM (with pedestal).

AD_SEC525_EN Enable Autodetection of SECAM 525

Line Video, Address 0x07[7]

•

Color subcarrier frequency

Field rate

Setting AD_SEC525_EN to 0 (default), disables the

autodetection of a 525-line system with a SECAM style,

FM-modulated color component.

Line rate

Setting AD_SEC525_EN to 1 enables the detection.

The ADV7189B can configure itself to support PAL-BGHID,

PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM

50 Hz/60 Hz, NTSC4.43, and PAL60.

AD_SECAM_EN Enable Autodetection of SECAM,

Address 0x07[6]

Setting AD_SECAM_EN to 0 disables the autodetection of

SECAM.

Setting AD_SECAM_EN to 1 (default) enables the detection.

Rev. B | Page 21 of 104

ADV7189B

AD_N443_EN Enable Autodetection of NTSC 443,

Address 0x07[5]

SFL_INV Subcarrier Frequency Lock Inversion

This bit controls the behavior of the PAL switch bit in the SFL

(GenLock Telegram) data stream. It was implemented to solve

some compatibility issues with video encoders. It solves two

problems as follows:

Setting AD_N443_EN to 0 disables the autodetection of NTSC

style systems with a 4.43 MHz color subcarrier.

Setting AD_N443_EN to 1 (default) enables the detection.

First, the PAL switch bit is only meaningful in PAL. Some

encoders (including Analog Devices encoders) also look at the

state of this bit in NTSC.

AD_P60_EN Enable Autodetection of PAL60,

Address 0x07[4]

Setting AD_P60_EN to 0 disables the autodetection of PAL

systems with a 60 Hz field rate.

Second, there was a design change in Analog Devices encoders

from ADV717x to ADV719x. The older versions used the SFL

(GenLock Telegram) bit directly, while the later ones invert the

bit prior to using it. The reason for this is the inversion

compensated for the 1-line delay of an SFL (GenLock Telegram)

transmission.

Setting AD_P60_EN to 1 (default) enables the detection.

AD_PALN_EN Enable Autodetection of PAL N,

Address 0x07[3]

Setting AD_PALN_EN to 0 disables the detection of the

PAL N standard.

As a result, ADV717x encoders need the PAL switch bit in the

SFL (GenLock Telegram) to be 1 for NTSC to work. Also,

ADV7190/ADV7191/ADV7194 encoders need the PAL switch

bit in the SFL to be 0 to work in NTSC. If the state of the PAL

switch bit is wrong, a 180° phase shift occurs.

Setting AD_PALN_EN to 1 (default) enables the detection.

AD_PALM_EN Enable Autodetection of PAL M,

Address 0x07[2]

Setting AD_PALM_EN to 0 disables the autodetection of PAL M.

Setting AD_PALM_EN to 1 (default), enables the detection.

In a decoder/encoder back-to-back system in which SFL is used,

this bit must be set up properly for the specific encoder used.

SFL_INV Address 0x41[6]

AD_NTSC_EN Enable Autodetection of NTSC,

Address 0x07[1]

Setting SFL_INV[6] to 0 makes the part SFL-compatible with

ADV7190/ADV7191/ADV7194 encoders.

Setting AD_NTSC_EN to 0 disables the detection of standard

NTSC.

Setting SFL_INV to 1 (default) makes the part SFL-compatible

with ADV717x/ADV7173x encoders.

Setting AD_NTSC_EN to 1 (default) enables the detection.

Lock-Related Controls

AD_PAL_EN Enable Autodetection of PAL,

Address 0x07[0]

Lock information is presented to the user through Bits[1:0] of

the Status 1 register. See the STATUS_1[7:0] Address 0x10[7:0]

section. Figure 9 outlines the signal flow and the controls avail-

able to influence the way the lock status information is generated.

Setting AD_PAL_EN to 0 disables the detection of standard PAL.

Setting AD_PAL_EN to 1 (default) enables the detection.

SELECT THE RAW LOCK SIGNAL

SRLS

FILTER THE RAW LOCK SIGNAL

CIL[2:0], COL[2:0]

TIME_WIN

1

0

1

FREE_RUN

COUNTER INTO LOCK

COUNTER OUT OF LOCK

STATUS 1 [0]

STATUS 1 [1]

F

LOCK

SC

MEMORY

TAKE F LOCK INTO ACCOUNT

SC

FSCLE

Figure 9. Lock-Related Signal Path

Rev. B | Page 22 of 104

ADV7189B

Table 20. CIL Function

SRLS Select Raw Lock Signal, Address 0x51[6]

CIL[2:0]

Description

Using the SRLS bit, the user can choose between two sources for

determining the lock status (per Bits[1:0] in the Status 1 register).

000

1

001

2

010

011

100 (default)

101

110

5

10

100

500

1000

100000

•

The time_win signal is based on a line-to-line evaluation of

the horizontal synchronization pulse of the incoming video.

It reacts quickly.

•

The free_run signal evaluates the properties of the

incoming video over several fields, and takes vertical

synchronization information into account.

111

COL[2:0] Count Out-of-Lock, Address 0x51[5:3]

Setting SRLS to 0 (default) selects the free_run signal.

Setting SRLS to 1 selects the time_win signal.

FSCLE F_SCLock Enable, Address 0x51[7]

COL[2:0] determines the number of consecutive lines for which

the out-of-lock condition must be true before the system switches

into unlocked state, and reports this via Status 0[1:0]. It counts

the value in lines of video.

The FSCLE bit allows the user to choose whether the status

of the color subcarrier loop is taken into account when the

overall lock status is determined and presented via Bits[1:0]

in Status Register 1. This bit must be set to 0 when operating

the ADV7189B in YPrPb component mode in order to generate

a reliable HLOCK status bit.

Table 21. COL Function

COL[2:0]

Description

000

1

001

2

010

5

011

10

100 (default)

101

110

100

500

1000

100000

Setting FSCLE to 0 (default) makes the overall lock status

dependent on only the horizontal sync lock.

Setting FSCLE to 1 makes the overall lock status dependent on

the horizontal sync lock and F_SClock.

111

SD COLOR CONTROLS

VS_Coast[1:0], Address 0xF9[3:2]

These registers allow the user to control picture appearance

including control of the active data in the event of video being

lost. These controls are independent of any other controls. For

instance, brightness control is independent from picture clamp-

ing, although both controls affect the signal’s dc level.

These bits are used to set VS free-run (coast) frequency.

Table 19. VS_COAST[1:0] Function

VS_COAST[1:0]

Description

00 (default)

Auto coast mode—follows VS

frequency from last video input

CON[7:0] Contrast Adjust, Address 0x08[7:0]

This register allows the user to adjust the contrast of the picture.

Table 22. CON Function

01

10

11

Forces 50 Hz coast mode

Forces 60 Hz coast mode

Reserved

CON[7:0]

0x±0 (default)

0x00

Description

Gain on luma channel = 1

Gain on luma channel = 0

Gain on luma channel = 2

CIL[2:0] Count Into Lock, Address 0x51[2:0]

CIL[2:0] determines the number of consecutive lines for which

the into lock condition must be true before the system switches

into the locked state and reports this via Status 0[1:0]. It counts

the value in lines of video.

0xFF

SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address

0xE3[7:0]

This register allows the user to control the gain of the Cb channel

only. The user can adjust the saturation of the picture.

Table 23. SD_SAT_Cb Function

SD_SAT_Cb[7:0] Description

0x±0 (default)

0x00

0xFF

Chroma gain = 0 dB

Gain on Cb channel = −42 dB

Gain on Cb channel = +6 dB

Rev. B | Page 23 of 104

ADV7189B

The hue adjustment value is fed into the AM color demodulation

block. Therefore, it only applies to video signals that contain

chroma information in the form of an AM modulated carrier

(CVBS or Y/C in PAL or NTSC). It does not affect SECAM

and does not work on component video inputs (YPrPb).

SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address

0xE4[7:0]

This register allows the user to control the gain of the Cr

channel only.

Table 24. SD_SAT_Cr Function

SD_SAT_Cr[7:0] Description

Table 28. HUE Function

HUE[7:0]

0x00 (default)

0x7F

Description

0x±0 (default)

0x00

0xFF

Chroma gain = 0 dB

Gain on Cb channel = −42 dB

Gain on Cb channel = +6 dB

Phase of the chroma signal = 0°

Phase of the chroma signal = –90°

Phase of the chroma signal = +90°

0x±0

SD_OFF_Cb[7:0] SD Offset Cb Channel, Address

0xE1[7:0]

DEF_Y[5:0] Default Value Y, Address 0x0C[7:2]

When the ADV7189B loses lock on the incoming video signal

or when there is no input signal, the DEF_Y[5:0] register allows

the user to specify a default luma value to be output. This value

is used under the following conditions:

This register allows the user to select an offset for data on the

Cr channel only and adjust the hue of the picture. There is a

functional overlap with the Hue[7:0] register.

Table 25. SD_OFF_Cb Function

SD_OFF_Cb[7:0] Description

•

If DEF_VAL_AUTO_EN bit is set to high, and the

ADV7189B lost lock to the input video signal. This is

the intended mode of operation (automatic mode).

0x±0 (default)

0x00

0xFF

0 offset applied to the Cb channel

−312 mV offset applied to the Cb channel

+312 mV offset applied to the Cb channel

•

The DEF_VAL_EN bit is set, regardless of the lock status of

the video decoder. This is a forced mode that can be useful

during configuration.

SD_OFF_Cr[7:0] SD Offset Cr Channel, Address

0xE2[7:0]

The DEF_Y[5:0] values define the 6 MSBs of the output video.

The remaining LSBs are padded with 0s. For example, in 10-bit

mode, the output is Y[9:0] = {DEF_Y[5:0], 0, 0, 0, 0}.

This register allows the user to select an offset for data on the

Cr channel only and adjust the hue of the picture. There is a

functional overlap with the Hue[7:0] register.

DEF_Y[5:0] is 0x0D (Blue) is the default value for Y.

Register 0x0C has a default value of 0x36.

Table 26. SD_OFF_Cr Function

SD_OFF_Cr[7:0] Description

0x±0 (default)

0x00

0xFF

0 offset applied to the Cr channel

−312 mV offset applied to the Cr channel

+312 mV offset applied to the Cr channel

DEF_C[7:0] Default Value C, Address 0x0D[7:0]

The DEF_C[7:0] register complements the DEF_Y[5:0] value.

It defines the 4 MSBs of Cr and Cb values to be output if

BRI[7:0] Brightness Adjust, Address 0x0A[7:0]

•

The DEF_VAL_AUTO_EN bit is set to high and the

ADV7189B can’t lock to the input video (automatic mode).

This register controls the brightness of the video signal through

the ADV7189B. It allows the user to adjust the brightness of the

picture.

•

DEF_VAL_EN bit is set to high (forced output).

Table 27. BRI Function

The data that is finally output from the ADV7189B for the

chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =

{DEF_C[3:0], 0, 0, 0, 0}.

BRI[7:0]

0x00 (default)

0x7F

Description

Offset of the luma channel = 0IRE

Offset of the luma channel = +100IRE

Offset of the luma channel = –100IRE

In full 10-bit output mode, two extra LSBs of value 00 are

appended.

0xFF

HUE[7:0] Hue Adjust, Address 0x0B[7:0]

DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb.

This register contains the value for the color hue adjustment.

It allows the user to adjust the hue of the picture.

HUE[7:0] has a range of 90°, with 0x00 equivalent to an

adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.

Rev. B | Page 24 of 104

ADV7189B

The clamping can be divided into two sections:

DEF_VAL_EN Default Value Enable, Address 0x0C[0]

This bit forces the use of the default values for Y, Cr, and Cb.

Refer to the descriptions for DEF_Y and DEF_C for additional

information. In this mode, the decoder also outputs a stable

27 MHz clock, HS, and VS.

•

Clamping before the ADC (analog domain): current sources.

Clamping after the ADC (digital domain): digital

processing block.

The ADCs can digitize an input signal only if it resides within

the ADC’s 1.6 V input voltage range. An input signal with a dc

level that is too large or too small is clipped at the top or bottom

of the ADC range.

Setting DEF_VAL_EN to 0 (default) outputs a colored screen

determined by user-programmable Y, Cr, and Cb values when

the decoder free-runs. Free-run mode is turned on and off by the

DEF_VAL_AUTO_EN bit.

The primary task of the analog clamping circuits is to ensure

the video signal stays within the valid ADC input window, so

the analog-to-digital conversion can take place. It is not neces-

sary to clamp the input signal with a very high accuracy in the

analog domain as long as the video signal fits the ADC range.

Setting DEF_VAL_EN to 1 forces a colored screen output

determined by user-programmable Y, Cr, and Cb values.

This overrides picture data even if the decoder is locked.

DEF_VAL_AUTO_EN Default Value Automatic Enable,

Address 0x0C[1]

After digitization, the digital fine clamp block corrects for any

remaining variations in dc level. Since the dc level of an input

video signal refers directly to the brightness of the picture

transmitted, it is important to perform a fine clamp with high

accuracy; otherwise, brightness variations can occur. Dynamic

changes in the dc level lead to visually objectionable artifacts so

it is recommended not to use dynamic changes.

This bit enables the automatic use of the default values for Y, Cr,

and Cb when the ADV7189B cannot lock to the video signal.

Setting DEF_VAL_AUTO_EN to 0 disables free-run mode.

If the decoder is unlocked, it outputs noise.

Setting DEF_VAL_EN to 1 (default) enables free-run mode.

A colored screen set by the user-programmable Y, Cr, and Cb

values is displayed when the decoder loses lock.

The clamping scheme has to complete two tasks. It must be

able to acquire a newly connected video signal with a com-

pletely unknown dc level, and it must maintain the dc level

during normal operation.

CLAMP OPERATION

The input video is ac-coupled into the ADV7189B through a

0.1 μF capacitor. The recommended range of the input video

signal range be 0.5 V to 1.6 V (typically 1 V p-p). If the signal

exceeds the range, it cannot be processed correctly in the decoder.

Because the input is ac-coupled into the decoder, its dc value

needs to be restored. This process is referred to as clamping the

video. This section explains the general process of clamping on

the ADV7189B and shows the different ways in which a user can

configure its behavior.

For quickly acquiring an unknown video signal, the large current

clamps can be activated. It is assumed the amplitude of the

video signal is of a nominal value at this point. Control of the

coarse and fine current clamp parameters is performed auto-

matically by the decoder.

Standard definition video signals may have excessive noise

on them. In particular, CVBS signals transmitted by terrestrial

broadcast and demodulated using a tuner usually show very

large levels of noise (>100 mV). A voltage clamp is unsuitable

for this type of video signal. Instead, the ADV7189B employs a

set of four current sources that cause coarse (>0.5 mA) and fine

(<0.1 mA) currents to flow into and away from the high imped-

ance node that carries the video signal (see Figure 10).

The ADV7189B uses a combination of current sources and a

digital processing block for clamping, as shown in Figure 10.

The analog processing channel shown is replicated three times

inside the IC. While only one single channel (and only one

ADC) is needed for a CVBS signal, two independent channels

are needed for YC (S-VHS) type signals, and three independent

channels are needed to allow component signals (YPrPb) to

be processed.

FINE

CURRENT

SOURCES

COARSE

CURRENT

SOURCES

DATA

SDP

WITH DIGITAL

PROCESSOR

FINE CLAMP

(DPP)

ANALOG

VIDEO

INPUT

PRE-

ADC

CLAMP CONTROL

Figure 10. Clamping Overview

Rev. B | Page 25 of 104

ADV7189B

The following sections describe the I²C signals that can be

used to influence the behavior of the clamping block on the

ADV7189B.

The luma antialias filter decimates the oversampled video

using a high quality, linear phase, low-pass filter that pre-

serves the luma signal while at the same time attenuating

out-of-band components. The luma antialias filter (YAA)

has a fixed response.

CCLEN Current Clamp Enable, Address 0x14[4]

The current clamp enable bit allows the user to switch off the

current sources in the analog front end altogether. This can be

useful if the incoming analog video signal is clamped externally.

•

Luma shaping filters (YSH). The shaping filter block is

a programmable low-pass filter with a wide variety of

responses. It can be used to selectively reduce the luma

video signal bandwidth (needed prior to scaling, for

example). For some video sources that contain high

frequency noise, reducing the bandwidth of the luma

signal improves visual picture quality. A follow-on video

compression stage can work more efficiently if the video

is low-pass filtered.

When CCLEN is 0, the current sources are switched off.

When CCLEN is 1 (default), the current sources are enabled.

DCT[1:0] Digital Clamp Timing, Address 0x15[6:5]

The clamp timing register determines the time constant of the

digital fine clamp circuitry. It is important to realize that the

digital fine clamp reacts very quickly because it is supposed to

immediately correct any residual dc level error for the active

line. The time constant of the digital fine clamp must be much

quicker than the one from the analog blocks.

The ADV7189B has two responses for the shaping filter:

one that is used for good quality CVBS, component, and

S-VHS type sources, and a second for nonstandard CVBS

signals.

By default, the time constant of the digital fine clamp is adjusted

dynamically to suit the currently connected input signal.

The YSH filter responses also include a set of notches for

PAL and NTSC. However, it is recommended to use the

comb filters for YC separation.

Table 29. DCT Function

DCT[1:0]

Description

•

Digital resampling filter. This block is used to allow dynamic

resampling of the video signal to alter parameters such as the

time base of a line of video. Fundamentally, the resampler is

a set of low-pass filters. The actual response is chosen by the

system with no requirement for user intervention.

00

01

Slow (TC = 1 sec)

Medium (TC = 0.5 sec)

Fast (TC = 0.1 sec)

Determined by the ADV71±9B, depending on

the I/P video parameters

10 (default)

11

Figure 12 through Figure 15 show the overall response of all

filters together. Unless otherwise noted, the filters are set into

a typical wideband mode.

DCFE Digital Clamp Freeze Enable, Address 0x15[4]

This register bit allows the user to freeze the digital clamp loop

at any time. It is intended for users who would like to do their

own clamping. Users should disable the current sources for

analog clamping via the appropriate register bits, wait until the

digital clamp loop settles, and then freeze it via the DCFE bit.

Y-Shaping Filter

For input signals in CVBS format, the luma shaping filters play

an essential role in removing the chroma component from a

composite signal. YC separation must aim for the best possible

crosstalk reduction while still retaining as much bandwidth

(especially on the luma component) as possible. High quality

YC separation can be achieved by using the internal comb filters

of the ADV7189B. Comb filtering, however, relies on the

frequency relationship of the luma component (multiples of the

video line rate) and the color subcarrier (F_SC). For good quality

CVBS signals, this relationship is known; the comb filter

algorithms can be used to separate out luma and chroma with

high accuracy.

When DCFE is 0 (default), the digital clamp is operational.

When DCFE is 1, the digital clamp loop is frozen.

LUMA FILTER

Data from the digital fine clamp block is processed by three sets

of filters. Note: The data format at this point is CVBS for CVBS

input or luma only for Y/C and YPrPb input formats.

•

Luma antialias filter (YAA). The ADV7189B receives video

at a rate of 27 MHz. (In the case of 4× oversampled video,

the ADCs sample at 54 MHz, and the first decimation is

performed inside the DPP filters. Therefore, the data rate

into the ADV7189B is always 27 MHz.) The ITU-R BT.601

recommends a sampling frequency of 13.5 MHz.

With nonstandard video signals, the frequency relationship may

be disturbed, and the comb filters may not be able to remove all

crosstalk artifacts in an optimum fashion without the assistance

of the shaping filter block.

Rev. B | Page 26 of 104

ADV7189B

YSFM[4:0] Y-Shaping Filter Mode, Address 0x17[4:0]

An automatic mode for Y-shaped filtering is provided. In this

mode, the ADV7189B evaluates the quality of the incoming

video signal and selects the filter responses in accordance with

the signal quality and video standard. YFSM, WYSFMOVR,

and WYSFM allow the user to manually override these

automatic decisions in part or in full.

The Y-shaping filter mode bits allow the user to select from

a wide range of low-pass and notch filters. When switched in

automatic mode, the filter is selected based on other register

selections, for example, detected video standard, as well as

properties extracted from the incoming video itself, for example,

quality, time base stability. The automatic selection always picks

the widest possible bandwidth for the video input encountered.

The luma shaping filter has three control registers:

•

YSFM[4:0] allows the user to manually select a shaping

filter mode (applied to all video signals) or to enable an

automatic selection (dependent on video quality and

video standard).

•

If the YSFM settings specify a filter (that is, YSFM is set

to values other than 00000 or 00001), the chosen filter is

applied to all video, regardless of its quality.

•

In automatic selection mode, the notch filters are only used

for bad quality video signals. For all other video signals, wide

band filters are used.

•

WYSFMOVR allows the user to manually override the

WYSFM decision.

WYSFM[4:0] allows the user to select a different shaping

filter mode for good quality CVBS, component (YPrPb),

and S-VHS (YC) input signals.

WYSFMOVR Wideband Y-Shaping Filter Override,

Address 0x18[7]

Setting the WYSFMOVR bit enables the use of the WYSFM[4:0]

settings for good quality video signals. For more information,

refer to the general discussion of the luma-shaping filters in the

Y-Shaping Filter section and the flowchart shown in Figure 11.

In automatic mode, the system preserves the maximum possible

bandwidth for good CVBS sources (since they can successfully

be combed) as well as for luma components of YPrPb and YC

sources, since they need not be combed. For poor quality signals,

the system selects from a set of proprietary shaping filter

responses that complements comb filter operation in order to

reduce visual artifacts. The decisions of the control logic are

shown in Figure 11.

When WYSFMOVR is 0, the shaping filter for good quality

video signals is selected automatically.

Setting WYSFMOVR to 1 (default) enables manual override via

WYSFM[4:0].

SET YSFM

YSFM IN AUTO MODE?

00000 OR 00001

YES

NO

VIDEO

QUALITY

BAD

GOOD

USE YSFM SELECTED

FILTER REGARDLESS FOR

GOOD AND BAD VIDEO

AUTO SELECT LUMA

SHAPING FILTER TO

COMPLEMENT COMB

WYSFMOVR

1

0

SELECT WIDEBAND

FILTER AS PER

WYSFM[4:0]

SELECT AUTOMATIC

WIDEBAND FILTER

Figure 11. YSFM and WYSFM Control Flowchart

Rev. B | Page 27 of 104

ADV7189B

Table 30. YSFM Function

YSFM[4:0] Description

WYSFM[4:0] Wide Band Y-Shaping Filter Mode,

Address 0x18[4:0]

0'0000

Automatic selection including a wide-notch

The WYSFM[4:0] bits allow the user to manually select a shaping

filter for good quality video signals, for example, CVBS with

stable time base, luma component of YPrPb, luma component

of YC. The WYSFM bits are only active if the WYSFMOVR bit

is set to 1. See the general discussion of the shaping filter settings

in the Y-Shaping Filter section.

response (PAL/NTSC/SECAM)

Automatic selection including a narrow-notch

response (PAL/NTSC/SECAM)

SVHS 1

SVHS 2

SVHS 3

SVHS 4

SVHS 5

SVHS 6

0'0001

(default)

0'0010

0'0011

0'0100

0'0101

0'0110

0'0111

0'1000

0'1001

0'1010

0'1011

0'1100

0'1101

0'1110

0'1111

1'0000

1'0001

1'0010

1'0011

1'0100

1'0101

1'0110

1'0111

1'1000

1'1001

1'1010

1'1011

1'1100

1'1101

1'1110

1'1111

Table 31. WYSFM Function

WYSFM[4:0]

Description

Do not use

SVHS 1

0'0000

0'0001

0'0010

SVHS 7

SVHS ±

SVHS 9

0'0011

SVHS 2

SVHS 10

SVHS 11

SVHS 12

SVHS 13

SVHS 14

SVHS 15

SVHS 16

SVHS 17

SVHS 1± (CCIR 601)

PAL NN 1

PAL NN 2

PAL NN 3

PAL WN 1

PAL WN 2

NTSC NN 1

NTSC NN 2

NTSC NN 3

NTSC WN 1

NTSC WN 2

NTSC WN 3

Reserved

0'0100

SVHS 3

0'0101

SVHS 4

0'0110

SVHS 5

0'0111

SVHS 6

0'1000

SVHS 7

0'1001

SVHS ±

0'1010

SVHS 9

0'1011

0'1100

0'1101

0'1110

0'1111

1'0000

1'0001

1'0010

SVHS 10

SVHS 11

SVHS 12

SVHS 13

SVHS 14

SVHS 15

SVHS 16

SVHS 17

SVHS 1± (CCIR 601)

Do not use

1'0011 (default)

1'0100–1'1111

Rev. B | Page 2± of 104

ADV7189B

COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,

Y RESAMPLE

COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,

Y RESAMPLE

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

FREQUENCY (MHz)

0

2

4

6

8

10

12

Figure 15 . NTSC Notch Filter Response

FREQUENCY (MHz)

Figure 12. Y S-VHS Combined Responses

CHROMA FILTER

The filter plots in Figure 12 show the S-VHS 1 (narrowest) to

S-VHS 18 (widest) shaping filter settings. Figure 14 shows the

PAL notch filter responses. The NTSC-compatible notches are

shown in Figure 15.

Data from the digital fine clamp block is processed by three sets

of filters. Note: the data format at this point is CVBS for CVBS

inputs, or chroma only for Y/C or Cr/Cb interleaved for YCrCb

input formats.

COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,

Y RESAMPLE

•

Chroma Antialias Filter (CAA). The ADV7189B over-

samples the CVBS by a factor of 2 and the Chroma/UV

by a factor of 4. A decimating filter (CAA) is used to

preserve the active video band and to remove any out-of-

band components. The CAA filter has a fixed response.

0

–20

–40

•

Chroma Shaping Filters (CSH). The shaping filter block

can be programmed to perform a variety of low-pass

responses. It can be used to selectively reduce the band-

width of the chroma signal for scaling or compression.

–60

–80

–100

–120

Digital Resampling Filter. This block is used to allow

dynamic resampling of the video signal to alter parameters

such as the time base of a line of video. Fundamentally, the

resampler is a set of low-pass filters. The actual response is

chosen by the system without user intervention.

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 13. Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)

COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,

Y RESAMPLE

0

–10

–20

–30

–40

–50

–60

–70

The plots in Figure 16 show the overall response of all filters

together.

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 14. PAL Notch Filter Response

Rev. B | Page 29 of 104

ADV7189B

GAIN OPERATION

CSFM[2:0] C-Shaping Filter Mode, Address 0x17[7]

The gain control within the ADV7189B is done on a purely

digital basis. The input ADCs support a 12-bit range, mapped

into a 1.6 V analog voltage range. Gain correction takes place

after the digitization in the form of a digital multiplier.

The C-shaping filter mode bits allow the user to select from a

range of low-pass filters, SH1 to SH5, and wideband mode for

the chrominance signal. The auto-selection options

automatically select from the filter options to give the specified

response. (See settings 000 and 001 in Table 32).

Advantages of this architecture over the commonly used

programmable gain amplifier (PGA) before the ADCs include

the fact that the gain is now completely independent of supply,

temperature, and process variations.

Table 32. CSFM Function

CSFM[2:0]

000 (default)

001

Description

Autoselect 1.5 MHz bandwidth

Autoselect 2.17 MHz bandwidth

As shown in Figure 17, the ADV7189B can decode a video signal

as long as it fits into the ADC window. The two components to

this are the amplitude of the input signal and the dc level it resides

on. The dc level is set by the clamping circuitry (see the Clamp

Operation section).

010

011

100

101

SH1

SH2

SH3

SH4

110

SH5

111

Wideband mode

If the amplitude of the analog video signal is too high, clipping

can occur, resulting in visual artifacts. The analog input range

of the ADC, together with the clamp level, determines the

maximum supported amplitude of the video signal.

COMBINED C ANTIALIAS, C SHAPING FILTER,

C RESAMPLER

0

–10

–20

–30

–40

–50

The minimum supported amplitude of the input video is

determined by the ADV7189B’s ability to retrieve horizontal

and vertical timing and to lock to the colorburst, if present.

There are separate gain control units for luma and chroma data.

Both can operate independently of each other. The chroma unit,

however, can also take its gain value from the luma path.

The possible AGC modes are summarized in Table 33.

It is possible to freeze the automatic gain control loops. This

causes the loops to stop updating, and the AGC determined

gain at the time of the freeze to stay active until the loop is

either unfrozen or the gain mode of operation is changed.

–60

0

1

2

3

4

5

6

FREQUENCY (MHz)

Figure 16. Chroma Shaping Filter Responses

Figure 16 shows the responses of SH1 (narrowest) to SH5

(widest) in addition to the wideband mode.

The currently active gain from any of the modes can be read

back. Refer to the description of the dual-function manual gain

registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in

the Luma Gain and the Chroma Gain sections.

ANALOG VOLTAGE

RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7189B)

MAXIMUM

VOLTAGE

SDP

(GAIN SELECTION ONLY)

DATA

PRE-

ADC

PROCESSOR

(DPP)

GAIN

CONTROL

MINIMUM

VOLTAGE

CLAMP

LEVEL

Figure 17. Gain Control Overview

Rev. B | Page 30 of 104

ADV7189B

Table 33. AGC Modes

Input Video Type

Luma Gain

Chroma Gain

Any

Manual gain luma.

Manual gain chroma.

CVBS

Dependent on horizontal sync depth.

Dependent on color burst amplitude.

Taken from luma path.

Peak White.

Dependent on color burst amplitude.

Taken from luma path.

Y/C

Dependent on horizontal sync depth.

Peak White.

Dependent on color burst amplitude.

Taken from luma path.

Dependent on color burst amplitude.

Taken from luma path.

YPrPb

Dependent on horizontal sync depth.

Taken from luma path.

Luma Gain

Table 35. LAGT Function

LAGC[2:0] Luma Automatic Gain Control, Address

0x2C[7:0]

LAGT[1:0]

Description

00

01

10

Slow (TC = 2 sec)

Medium (TC = 1 sec)

Fast (TC = 0.2 sec)

Adaptive

The luma automatic gain control mode bits select the mode of

operation for the gain control in the luma path. There are ADI

internal parameters to customize the peak white gain control.

Contact ADI sakes for more information.

11 (default)

Table 34. LAGC Function

LG[11:0] Luma Gain, Address 0x2F[3:0]; Address

0x30[7:0]; LMG[11:0] Luma Manual Gain, Address

0x2F[3:0]; Address 0x30[7:0]

LAGC[2:0]

Description

000

Manual fixed gain (use LMG[11:0])

001

AGC (blank level to sync tip); peak white

algorithm off

Luma Gain[11:0] is a dual-function register. If written to, a

desired manual luma gain can be programmed. This gain

becomes active if the LAGC[2:0] mode is switched to manual

fixed gain. Equation 1 shows how to calculate a desired gain. If

read back, this register returns the current gain value.

Depending on the setting in the LAGC[2:0] bits, this is one of

the following values:

010 (default)

AGC (blank level to sync tip); peak white

algorithm on

011

100

101

110

111

Reserved

Freeze gain

•

Luma manual gain value (LAGC[2:0] set to luma manual

gain mode)

LAGT[1:0] Luma Automatic Gain Timing, Address

0x2F[7:6]

The luma automatic gain timing register allows the user to

influence the tracking speed of the luminance automatic gain

control. Note this register only has an effect if the LAGC[2:0]

register is set to 001, 010, 011, or 100 (automatic gain control

modes).

•

Luma automatic gain value (LAGC[2:0] set to any of the

automatic modes)

Table 36. LG/LMG Function

LG[11:0]/LMG[11:0] Read/Write Description

LMG[11:0] = X

Write

Manual gain for

luma path

If peak white AGC is enabled and active (see the

LG[11:0]

Read

Actually used gain

STATUS_1[7:0] Address 0x10[7:0] section), the actual gain

update speed is dictated by the peak white AGC loop and, as a

result, the LAGT settings have no effect. As soon as the part

leaves peak white AGC, LAGT becomes relevant again.

(

0 < LG ≤ 4095

)

Luma_Gain =

= 0...2

(1)

2048

The update speed for the peak white algorithm can be

customized by the use of internal parameters. Contact ADI

for more information.

Rev. B | Page 31 of 104

ADV7189B

Table 38. Betacam Levels

For example, program the ADV7189B into manual fixed gain

mode with a desired gain of 0.89:

Betacam

Variant

(mV)

Betacam

SMPTE

(mV)

Name (mV)

MII (mV)

1. Use Equation 1 to convert the gain:

0.89 × 2048 = 1822.72

Y

0 to 714

0 to

700

0 to 700 (incl.

7.5%

pedestal)

Range (incl. 7.5%

pedestal)

U and –467 to +467

2. Truncate to integer value:

1822.72 = 1822

–505 to

+505

–350

to

+350

–324 to +324

V

3. Convert to hexadecimal:

1822d = 0x71E

Range

Sync

2±6

300

4. Split into two registers and program:

Luma Gain Control 1[3:0] = 0x7

Depth

Luma Gain Control 2[7:0] = 0x1E

PW_UPD Peak White Update, Address 0x2B[0]

5. Enable Manual Fixed Gain Mode:

Set LAGC[2:0] to 000

The peak white and average video algorithms determine the

gain based on measurements taken from the active video. The

PW_UPD bit determines the rate of gain change. LAGC[2:0]

must be set to the appropriate mode to enable the peak white or

average video mode in the first place. For more information, refer

to the LAGC[2:0] Luma Automatic Gain Control, Address

0x2C[7:0] section.

BETACAM Enable Betacam Levels, Address 0x01[5]

If YPrPb data is routed through the ADV7189B, the automatic

gain control modes can target different video input levels, as

outlined in. Note the BETACAM bit is valid only if the input

mode is YPrPb (component). The BETACAM bit sets the target

value for AGC operation. A review of the following sections is

useful.

Setting PW_UPD to 0 updates the gain once per video line.

Setting PW_UPD to 1 (default) updates the gain once per field.

Chroma Gain

•

INSEL[3:0] Input Selection, Address 0x00[3:0] to find out

how component video (YPrPb) can be routed through the

ADV7189B.

CAGC[1:0] Chroma Automatic Gain Control,

Address 0x2C[1:0]

•

Video Standard Selection to select the various standards,

for example, with and without pedestal.

The two bits of color automatic gain control mode select

the basic mode of operation for automatic gain control in the

chroma path.

The automatic gain control (AGC) algorithms adjust the levels

based on the setting of the BETACAM bit. See Table 37.

Table 39. CAGC Function

Table 37. BETACAM Function

CAGC[1:0]

Description

BETACAM Description

00

01

Manual fixed gain (use CMG[11:0]).

Use luma gain for chroma.

Automatic gain (based on color burst).

Freeze chroma gain.

0 (default) Assuming YPrPb is selected as input format.

Selecting PAL with pedestal selects MII.

Selecting PAL without pedestal selects SMPTE.

Selecting NTSC with pedestal selects MII.

Selecting NTSC without pedestal selects SMPTE.

10 (default)

11

CAGT[1:0] Chroma Automatic Gain Timing,

Address 0x2D[7:6]

1

Assuming YPrPb is selected as input format.

Selecting PAL with pedestal selects BETACAM.

The chroma automatic gain timing register allows the user

to influence the tracking speed of the chroma automatic gain

control. This register has an effect only if the CAGC[1:0]

register is set to 10 (automatic gain).

Selecting PAL without pedestal selects BETACAM

variant.

Selecting NTSC with pedestal selects BETACAM.

Selecting NTSC without pedestal selects

BETACAM variant.

Table 40. CAGT Function

CAGT[1:0]

Description

00

01

10

Slow (TC = 2 sec)

Medium (TC = 1 sec)

Fast (TC = 0.2 sec)

Adaptive

11 (default)

Rev. B | Page 32 of 104

ADV7189B

CG[11:0] Chroma Gain, Address 0x2D[3:0];

Address 0x2E[7:0]; CMG[11:0] Chroma Manual Gain,

Address 0x2D[3:0]; Address 0x2E[7:0]

If color kill is enabled and if the color carrier of the incoming

video signal is less than the threshold for 128 consecutive video

lines, color processing is switched off (black and white output).

To switch the color processing back on, another 128 consecutive

lines with a color burst greater than the threshold are required.

Chroma Gain[11:0] is a dual-function register. If written to, a

desired manual chroma gain can be programmed. This gain

becomes active if the CAGC[1:0] mode is switched to manual

fixed gain. Refer to Equation 2 for calculating a desired gain. If

read back, this register returns the current gain value. Depending

on the setting in the CAGC[1:0] bits, this is either

The color kill option only works for input signals with a modu-

lated chroma part. For component input (YPrPb), there is no

color kill.

Setting CKE to 0 disables color kill.

Setting CKE to 1 (default), enables color kill.

•

Chroma manual gain value (CAGC[1:0] set to chroma

manual gain mode)

CKILLTHR[2:0] Color Kill Threshold, Address 0x3D[6:4]

•

Chroma automatic gain value (CAGC[1:0] set to any of the

automatic modes)

The CKILLTHR[2:0] bits allow the user to select a threshold

for the color kill function. The threshold applies to only QAM-

based (NTSC and PAL) or FM-modulated (SECAM) video

standards.

Table 41. CG/CMG Function

CG[11:0]/CMG[11:0] Read/Write Description

CMG[11:0]

Write

Manual gain for chroma

path.

Currently active gain.

To enable the color kill function, the CKE bit must be set. For

settings 000, 001, 010, and 011, chroma demodulation inside

the ADV7189B may not work satisfactorily for poor input

video signals.

CG[11:0]

Read

(

0 < CG ≤ 4095

)

Chroma _ Gain =

= 0...4

(2)

1024

Table 42. CKILLTHR Function

For example, freezing the automatic gain loop and reading back

the CG[11:0] register results in a value of 0x47A.

Description

CKILLTHR[2:0] SECAM

NTSC, PAL

000

001

010

011

100 (default)

101

110

No color kill.

Kill at < 0.5%

Kill at < 1.5%

Kill at < 2.5%

Kill at < 4.0%

Kill at < ±.5% (default)

Kill at < 16.0%

Kill at < 32.0%

1. Convert the readback value to decimal

0x47A = 1146d

Kill at < 5%.

Kill at < 7%.

Kill at < ±%.

Kill at < 9.5%.

Kill at < 15%.

Kill at < 32%.

Reserved for ADI

internal use only. Do

not select.

2. Apply Equation 2 to convert the readback value

1146/1024 = 1.12

CKE Color Kill Enable, Address 0x2B[6]

The color kill enable bit allows the optional color kill function

to be switched on or off.

111

For QAM-based video standards (PAL and NTSC) as well as

FM-based systems (SECAM), the threshold for the color kill

decision is selectable via the CKILLTHR[2:0] bits.

Rev. B | Page 33 of 104

ADV7189B

CHROMA TRANSIENT IMPROVEMENT (CTI)

The signal bandwidth allocated for chroma is typically much

smaller than that of luminance. In the past, this was a valid

way to fit a color video signal into a given overall bandwidth

because the human eye is less sensitive to chrominance than

to luminance.

For the alpha blender to be active, the CTI block must be

enabled via the CTI_EN bit.

Setting CTI_AB_EN to 0 disables the CTI alpha blender.

Setting CTI_AB_EN to 1 (default) enables the CTI alpha-blend

mixing function.

The uneven bandwidth, however, can lead to visual artifacts in

sharp color transitions. At the border of two bars of color, both

components (luma and chroma) change at the same time (see

Figure 18). Due to the higher bandwidth, the signal transition

of the luma component is usually a lot sharper than that of the

chroma component. The color edge is not sharp but is blurred,

in the worst case, over several pixels.

CTI_AB[1:0] Chroma Transient Improvement Alpha

Blend, Address 0x4D[3:2]

The CTI_AB[1:0] controls the behavior of alpha-blend circuitry

that mixes the sharpened chroma signal with the original one. It

thereby controls the visual impact of CTI on the output data.

For CTI_AB[1:0] to become active, the CTI block must be

enabled via the CTI_EN bit, and the alpha blender must be

switched on via CTI_AB_EN.

LUMA SIGNAL WITH A

TRANSITION, ACCOMPANIED

LUMA

SIGNAL

BY A CHROMA TRANSITION

Sharp blending maximizes the effect of CTI on the picture, but

can also increase the visual impact of small amplitude, high

frequency chroma noise.

ORIGINAL, "SLOW" CHROMA

DEMODULATED

TRANSITION PRIOR TO CTI

CHROMA

SHARPENED CHROMA

TRANSITION AT THE

OUTPUT OF CTI

SIGNAL

Table 43. CTI_AB Function

CTI_AB[1:0] Description

Figure 18. CTI Luma/Chroma Transition

00

Sharpest mixing between sharpened and original

chroma signal.

The chroma transient improvement block examines the input

video data. It detects transitions of chroma, and can be pro-

grammed to “steepen” the chroma edges in an attempt to

artificially restore lost color bandwidth. The CTI block,

however, operates only on edges above a certain threshold

to ensure that noise is not emphasized. Care has also been

taken to ensure that edge ringing and undesirable saturation

or hue distortion are avoided.

01

10

Sharp mixing.

Smooth mixing.

Smoothest alpha blend function.

11 (default)

CTI_C_TH[7:0] CTI Chroma Threshold, Address

0x4E[7:0]

The CTI_C_TH[7:0] value is an unsigned, 8-bit number speci-

fying how big the amplitude step in a chroma transition is to be

steepened by the CTI block. Programming a small value into

this register causes even smaller edges to be steepened by the

CTI block. Making CTI_C_TH[7:0] a large value causes the

block to only improve large transitions.

Chroma transient improvements are needed primarily for sig-

nals that experienced severe chroma bandwidth limitation. For

those types of signals, it is strongly recommended to enable the

CTI block via CTI_EN.

CTI_EN Chroma Transient Improvement Enable,

Address 0x4D[0]

The default value for CTI_C_TH[7:0] is 0x08, indicating

the threshold for the chroma edges prior to CTI.

The CTI_EN bit enables the CTI function. If set to 0, the CTI

block is inactive and the chroma transients are left untouched.

DIGITAL NOISE REDUCTION (DNR)

Digital noise reduction is based on the assumption that high

frequency signals with low amplitude are probably noise and

their removal, therefore, improves picture quality.

Setting CTI_EN to 0 disables the CTI block.

Setting CTI_EN to 1 (default) enables the CTI block.

CTI_AB_EN Chroma Transient Improvement

Alpha Blend Enable, Address 0x4D[1]

DNR_EN Digital Noise Reduction Enable, Address

0x4D[5]

The CTI_AB_EN bit enables an alpha-blend function within

the CTI block. If set to 1, the alpha blender mixes the transient

improved chroma with the original signal. The sharpness of the

alpha blending can be configured via the CTI_AB[1:0] bits.

The DNR_EN bit enables the DNR block or bypasses it.

Setting DNR_EN to 0 bypasses DNR (disables it).

Setting DNR_EN to 1 (default) enables digital noise reduction

on the luma data.

Rev. B | Page 34 of 104

ADV7189B

NTSC Comb Filter Settings

DNR_TH[7:0] DNR Noise Threshold, Address 0x50[7:0]

Used for NTSC-M/J CVBS inputs.

The DNR_TH[7:0] value is an unsigned 8-bit number used to

determine the maximum edge that is interpreted as noise and

therefore blanked from the luma data. Programming a large

value into DNR_TH[7:0] causes the DNR block to interpret

even large transients as noise and remove them. The effect on

the video data is, therefore, more visible.

NSFSEL[1:0] Split Filter Selection NTSC, Address

0x19[3:2]

The NSFSEL[1:0] control selects how much of the overall signal

bandwidth is fed to the combs. A narrow split filter selection

gives better performance on diagonal lines, but leaves more dot

crawl in the final output image. The opposite is true for selecting

a wide bandwidth split filter.

Programming a small value causes only small transients to be

seen as noise and to be removed.

Table 44. NSFSEL Function

NSFSEL[1:0]

The recommended DNR_TH[7:0] setting for A/V inputs is

0x04, and the recommended DNR_TH[7:0] setting for tuner

inputs is 0x0A.

Description

Narrow

00 (default)

01

10

11

Medium

Wide

The default value for DNR_TH[7:0] is 0x08, indicating the

threshold for maximum luma edges to be interpreted as noise.

COMB FILTERS

CTAPSN[1:0] Chroma Comb Taps NTSC, Address

0x38[7:6]

Table 45. CTAPSN Function

The comb filters of the ADV7189B have been greatly improved

to automatically handle video of all types, standards, and levels

of quality. The NTSC and PAL configuration registers allow the

user to customize comb filter operation, depending on which

video standard is detected (by autodetection) or selected (by

manual programming). In addition to the bits listed in this

section, there are some further ADI internal controls; contact

ADI sales for more information.

CTAPSN[1:0]

Description

00

01

Do not use.

NTSC chroma comb adapts 3 lines (3 taps) to

2 lines (2 taps).

10 (default)

11

NTSC chroma comb adapts 5 lines (5 taps) to

3 lines (3 taps).

NTSC chroma comb adapts 5 lines (5 taps) to

4 lines (4 taps).

Rev. B | Page 35 of 104

ADV7189B

CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38[5:3]

Table 46. CCMN Function

CCMN[2:0]

Description

Configuration

0xx (default)

Adaptive comb mode.

Adaptive 3-line chroma comb for CTAPSN = 01.

Adaptive 4-line chroma comb for CTAPSN = 10.

Adaptive 5-line chroma comb for CTAPSN = 11.

100

101

Disable chroma comb.

Fixed chroma comb (top lines of line memory).

Fixed 2-line chroma comb for CTAPSN = 01.

Fixed 3-line chroma comb for CTAPSN = 10.

Fixed 4-line chroma comb for CTAPSN = 11.

Fixed 3-line chroma comb for CTAPSN = 01.

Fixed 4-line chroma comb for CTAPSN = 10.

Fixed 5-line chroma comb for CTAPSN = 11.

Fixed 2-line chroma comb for CTAPSN = 01.

Fixed 3-line chroma comb for CTAPSN = 10.

Fixed 4-line chroma comb for CTAPSN = 11.

110

111

Fixed chroma comb (all lines of line memory).

Fixed chroma comb (bottom lines of line memory).

YCMN[2:0] Luma Comb Mode NTSC, Address 0x38[2:0]

Table 47.YCMN Function

YCMN[2:0]

0xx (default)

100

101

110

Description

Configuration

Adaptive comb mode.

Disable luma comb.

Fixed luma comb (top lines of line memory).

Fixed luma comb (all lines of line memory).

Fixed luma comb (bottom lines of line memory).

Adaptive 3-line (3 taps) luma comb.

Use low-pass/notch filter; see the Y-Shaping Filter section.

Fixed 2-line (2 taps) luma comb.

Fixed 3-line (3 taps) luma comb.

Fixed 2-line (2 taps) luma comb.

111

Table 48. PSFSEL Function

PSFSEL[1:0]

PAL Comb Filter Settings

Description

Narrow

Medium

Wide

Used for PAL-B/G/H/I/D, PAL-M, PAL-Combinational N, PAL-

60, and NTSC443 CVBS inputs.

00

01 (default)

PSFSEL[1:0] Split Filter Selection PAL, Address 0x19[1:0]

10

11

Widest

The PSFSEL[1:0] control selects how much of the overall signal

bandwidth is fed to the combs. A wide split filter selection

eliminates dot crawl, but shows imperfections on diagonal lines.

The opposite is true for selecting a narrow bandwidth split filter.

Rev. B | Page 36 of 104

ADV7189B

CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39[7:6]

Table 49. CTAPSP Function

CTAPSP[1:0]

Description

00

01

Do not use.

PAL chroma comb adapts 5 lines (3 taps) to

3 lines (2 taps); cancels cross luma only.

10

PAL chroma comb adapts 5 lines (5 taps) to

3 lines (3 taps); cancels cross luma and hue error less well.

11 (default)

PAL chroma comb adapts 5 lines (5 taps) to

4 lines (4 taps); cancels cross luma and hue error well.

CCMP[2:0] Chroma Comb Mode PAL, Address 0x39[5:3]

Table 50. CCMP Function

CCMP[2:0]

Description

Configuration

0xx (default)

Adaptive comb mode.

Adaptive 3-line chroma comb for CTAPSP = 01.

Adaptive 4-line chroma comb for CTAPSP = 10.

Adaptive 5-line chroma comb for CTAPSP = 11.

100

101

Disable chroma comb.

Fixed chroma comb (top lines of line memory).

Fixed 2-line chroma comb for CTAPSP = 01.

Fixed 3-line chroma comb for CTAPSP = 10.

Fixed 4-line chroma comb for CTAPSP = 11.

Fixed 3-line chroma comb for CTAPSP = 01.

Fixed 4-line chroma comb for CTAPSP = 10.

Fixed 5-line chroma comb for CTAPSP = 11.

Fixed 2-line chroma comb for CTAPSP = 01.

Fixed 3-line chroma comb for CTAPSP = 10.

Fixed 4-line chroma comb for CTAPSP = 11.

110

111

Fixed chroma comb (all lines of line memory).

Fixed chroma comb (bottom lines of line memory).

YCMP[2:0] Luma Comb Mode PAL, Address 0x39[2:0]

Table 51. YCMP Function

YCMP[2:0]

0xx (default)

100

101

110

Description

Configuration

Adaptive comb mode.

Disable luma comb.

Fixed luma comb (top lines of line memory).

Fixed luma comb (all lines of line memory).

Fixed luma comb (bottom lines of line memory).

Adaptive 5 lines (3 taps) luma comb.

Use low-pass/notch filter, see the Y-Shaping Filter section.

Fixed 3 lines (2 taps) luma comb.

Fixed 5 lines (3 taps) luma comb.

Fixed 3 lines (2 taps) luma comb.

111

Rev. B | Page 37 of 104

ADV7189B

AV CODE INSERTION AND CONTROLS

This section describes the I²C-based controls that affect:

In an 8-/10-bit-wide output interface (Cb/Y/Cr/Y interleaved

data), the AV codes are defined as FF/00/00/AV, with AV being

the transmitted word that contains information about H/V/F.

•

Insertion of AV codes into the data stream.

Data blanking during the vertical blank interval (VBI).

In this output interface mode, the following assignment takes

place: Cb = FF, Y = 00, Cr = 00, and Y = AV.

The range of data values permitted in the output data

stream.

In a 16-/20-bit output interface where Y and Cr/Cb are delivered

via separate data buses, the AV code is over the whole

16/20 bits. The SD_DUP_AV bit allows the user to replicate the

AV codes on both busses, so the full AV sequence can be found

on the Y bus as well as on the Cr/Cb bus. See Figure 19.

•

The relative delay of luma vs. chroma signals.

Note: Some of the decoded VBI data is being inserted dur-

ing the horizontal blanking interval. See the Gemstar Data

Recovery section for more information.

When SD_DUP_AV is 0 (default), the AV codes are in single

fashion (to suit 8-/10-bit interleaved data output).

BT656-4 ITU Standard BT-R.656-4 Enable, Address

0x04[7]

When SD_DUP_AV is 1, the AV codes are duplicated (for

16-/20-bit interfaces).

The ITU has changed the position for toggling of the V bit

within the SAV EAV codes for NTSC between Revisions 3 and

Revision 4. The BT656-4 standard bit allows the user to select

an output mode that is compliant with either the previous or the

new standard. For further information, review the standard at

www.itu.int.

VBI_EN Vertical Blanking Interval Data Enable,

Address 0x03[7]

The VBI enable bit allows data such as intercast and closed-

caption data to be passed through the luma channel of the

decoder with a minimal amount of filtering. All data for Line 1

to Line 21 is passed through and available at the output port.

The ADV7189B does not blank the luma data, and automatically

switches all filters along the luma data path into their widest

bandwidth. For active video, the filter settings for YSH and YPK

are restored.

Note the standard change affects NTSC only, and has no

bearing on PAL.

When BT656-4 is 0 (default), the BT656-3 specification is used.

The V bit goes low at EAV of Lines 10 and 273.

When BT656-4 is 1, the BT656-4 specification is used.

The V bit goes low at EAV of Lines 20 and 283.

Refer to the BL_C_VBI Blank Chroma during VBI section for

information on the chroma path.

SD_DUP_AV Duplicate AV Codes, Address 0x03[0]

When VBI_EN is 0 (default), all video lines are filtered/scaled.

When VBI_EN is 1, only the active video region is filtered/scaled.

Depending on the output interface width, it can be necessary to

duplicate the AV codes from the luma path into the chroma path.

SD_DUP_AV = 1

SD_DUP_AV = 0

16-/20-BIT INTERFACE

8-/10-BIT INTERFACE

Y DATA BUS

FF

00

AV

Y

00

AV

Y

Cb/Y/Cr/Y

INTERLEAVED

FF

00

AV

Cb

Cr/Cb DATA BUS

00

Cb

FF

00

Cb

AV CODE SECTION

Figure 19. AV Code Duplication Control

Rev. B | Page 3± of 104

ADV7189B

LTA[1:0] Luma Timing Adjust, Address 0x27[1:0]

BL_C_VBI Blank Chroma During VBI, Address 0x04[2]

The Luma Timing Adjust register allows the user to specify a

timing difference between chroma and luma samples.

Setting BL_C_VBI high, the Cr and Cb values of all VBI lines

are blanked. This is done so any data that may arrive during

VBI is not decoded as color and output through Cr and Cb.

As a result, it is possible to send VBI lines into the decoder,

then output them through an encoder again, undistorted.

Without this blanking, any wrongly decoded color is encoded

by the video encoder; therefore, the VBI lines are distorted.

Note there is a certain functionality overlap with the CTA[2:0]

register. For manual programming, use the following defaults:

•

CVBS input LTA[1:0] = 00

YC input LTA[1:0] = 01

YPrPb input LTA[1:0] = 01

Setting BL_C_VBI to 0 decodes and outputs color during VBI.

Setting BL_C_VBI to 1 (default) blanks Cr and Cb values

during VBI.

Table 53. LTA Function

LTA[1:0]

Description

RANGE Range Selection, Address 0x04[0]

00 (default)

No delay.

01

10

11

Luma 1 CLK (37 ns) delayed.

Luma 2 CLK (74 ns) early.

Luma 1 CLK (37 ns) early.

AV codes (as per ITU-R BT-656, formerly known as CCIR-656)

consist of a fixed header made up of 0xFF and 0x00 values.

These two values are reserved and are not to be used for active

video. Additionally, the ITU specifies that the nominal range

for video should be restricted to values between 16 and 235

for luma and 16 to 240 for chroma.

CTA[2:0] Chroma Timing Adjust, Address 0x27[5:3]

The Chroma timing adjust register allows the user to specify a

timing difference between chroma and luma samples. This can

be used to compensate for external filter group delay differences

in the luma vs. chroma path, and to allow a different number of

pipeline delays while processing the video downstream. Review

this functionality together with the LTA[1:0] register.

The RANGE bit allows the user to limit the range of values

output by the ADV7189B to the recommended value range.

This bit ensures the reserved values of 255d (0xFF) and 00d

(0x00) are not presented on the output pins unless they are

part of an AV code header.

Table 52. RANGE Function

RANGE

The chroma can be delayed/advanced only in chroma pixel

steps. One chroma pixel step is equal to two luma pixels. The

programmable delay occurs after demodulation, where one can

no longer delay by luma pixel steps.

Description

16 ≤ C/P ≤ 240

1 ≤ C/P ≤ 254

0

16 ≤ Y ≤ 235

1 ≤ Y ≤ 254

1 (default)

AUTO_PDC_EN Automatic Programmed Delay Control,

Address 0x27[6]

For manual programming, use the following defaults:

•

CVBS input CTA[2:0] = 011.

YC input CTA[2:0] = 101.

YPrPb input CTA[2:0] = 110.

Enabling the AUTO_PDC_EN function activates a function

within the ADV7189B that automatically programs the LTA[1:0]

and CTA[2:0] to have the chroma and luma data match delays

for all modes of operation. If set, manual registers LTA[1:0]

and CTA[2:0] are not used by the ADV7189B. If the automatic

mode is disabled (via setting the AUTO_PDC_EN bit to 0), the

values programmed into the LTA[1:0] and CTA[2:0] registers

become active.

Table 54. CTA Function

CTA[2:0]

Description

000

Not used.

001

010

011 (default)

100

101

Chroma + 2 chroma pixel (early).

Chroma + 1 chroma pixel (early).

No delay.

Chroma – 1 chroma pixel (late).

Chroma – 2 chroma pixel (late).

Chroma – 3 chroma pixel (late).

Not used.

When AUTO_PDC_EN is 0, the ADV7189B uses the LTA[1:0]

and CTA[2:0] values for delaying luma and chroma samples.

Refer to the LTA[1:0] Luma Timing Adjust, Address 0x27[1:0]

and the CTA[2:0] Chroma Timing Adjust, Address 0x27[5:3]

sections.

110

111

When AUTO_PDC_EN is 1 (default), the ADV7189B auto-

matically determines the LTA and CTA values to have luma

and chroma aligned at the output.

Rev. B | Page 39 of 104

ADV7189B

SYNCHRONIZATION OUTPUT SIGNALS

HSE[10:0] HS End, Address 0x34[2:0], Address 0x36[7:0]

HS Configuration

The position of this edge is controlled by placing a binary num-

ber into HSE[10:0]. The number applied offsets the edge with

respect to an internal counter that is reset to 0 immediately after

EAV Code FF, 00, 00, XY (see Figure 20). HSE is set to

The following controls allow the user to configure the behavior

of the HS output pin only:

•

Beginning of HS signal via HSB[10:0]

End of HS signal via HSE[10:0]

Polarity of HS using PHS

00000000000b, which is 0 LLC1 clock cycles from count[0].

The default value of HSE[10:0] is 000, indicating that the HS

pulse ends zero pixels after falling edge of HS.

For example:

The HS Begin and HS End registers allow the user to freely

position the HS output (pin) within the video line. The values

in HSB[10:0] and HSE[10:0] are measured in pixel units from

the falling edge of HS. Using both values, the user can program

both the position and length of the HS output signal.

1. To shift the HS toward active video by 20 LLC1s, add

20 LLC1s to both HSB and HSE, that is, HSB[10:0] =

[00000010110], HSE[10:0] = [00000010100].

2. To shift the HS away from active video by 20 LLC1s,

add 1696 LLC1s to both HSB and HSE (for NTSC), that

is, HSB[10:0] =[1101010010], HSE[10:0] = [11010100000]

(1696 is derived from the NTSC total number of pixels =

1716).

HSB[10:0] HS Begin, Address 0x34[6:4], Address

0x35[7:0]

The position of this edge is controlled by placing a binary

number into HSB[10:0]. The number applied offsets the edge

with respect to an internal counter that is reset to 0 immediately

after EAV code FF, 00, 00, XY (see Figure 20). HSB is set to

00000000010b, which is 2 LLC1 clock cycles from count[0].

To move 20 LLC1s away from active video is equal to subtracting

20 from 1716 and adding the result in binary to both HSB[10:0]

and HSE[10:0].

PHS Polarity HS, Address 0x37[7]

The default value of HSB is 0x002, indicating that the HS pulse

starts two pixels after the falling edge of HS.

The polarity of the HS pin can be inverted using the PHS bit.

When PHS is 0 (default), HS is active high.

When PHS is 1, HS is active low.

Table 55. HS Timing Parameters (See Figure 20)

Characteristic

HS to Active Video (LLC1 Active Video

Clock Cycles) Samples/Line

(HSE[10:0]) (Default) (C in Figure 20) (Default) (D in Figure 20)

Total LLC1

Clock Cycles

(E in Figure 20)

HS Begin Adjust

(HSB[10:0]) (Default)

HS End Adjust

Standard

NTSC

00000000010b

00000000000b

272

276

720Y + 720C = 1440

640Y + 640C = 12±0

1716

1560

NTSC Square

Pixel

PAL

00000000010b

00000000000b

2±4

720Y + 720C = 1440

172±

LLC1

PIXEL

Cr

Y

FF

00

EAV

00

XY

80

10

80

10

80

10

FF

00

SAV

XY

Cb

Y

Cr

Y

Cb

Y

Cr

BUS

ACTIVE

VIDEO

H BLANK

ACTIVE VIDEO

HS

HSE[10:0]

4 LLC1

HSB[10:0]

C

D

E

Figure 20. HS Timing

Rev. B | Page 40 of 104

ADV7189B

VSBHO VS Begin Horizontal Position Odd, Address 0x32[7]

VS and FIELD Configuration

The VSBHO and VSBHE bits select the position within a line at

which the VS pin (not the bit in the AV code) becomes active.

Some follow-on chips require the VS pin to change state only

when HS is high/low.

The following controls allow the user to configure the behav-

ior of the VS and FIELD output pins, as well as to generate

embedded AV codes:

•

ADV encoder-compatible signals via NEWAVMODE

When VSBHO is 0 (default), the VS pin goes high at the middle

of a line of video (odd field).

PVS, PF

HVSTIM

When VSBHO is 1, the VS pin changes state at the start of a line

(odd field).

VSBHO, VSBHE

VSEHO, VSEHE

For NTSC control:

VSBHE VS Begin Horizontal Position Even, Address 0x32[6]

The VSBHO and VSBHE bits select the position within a line at

which the VS pin (not the bit in the AV code) becomes active.

Some follow-on chips require the VS pin to change state only

when HS is high/low.

•

NVBEGDELO, NVBEGDELE, NVBEGSIGN,

NVBEG[4:0]

When VSBHE is 0 (default), the VS pin goes high at the middle

of a line of video (even field).

•

NVENDDELO, NVENDDELE, NVENDSIGN,

NVEND[4:0]

When VSBHE is 1, the VS pin changes state at the start of a line

(even field).

NFTOGDELO, NFTOGDELE, NFTOGSIGN,

NFTOG[4:0]

VSEHO VS End Horizontal Position Odd, Address 0x33{7]

The VSEHO and VSEHE bits select the position within a line at

which the VS pin (not the bit in the AV code) becomes active.

Some follow-on chips require the VS pin to change state only

when HS is high/low.

•

For PAL control:

•

PVBEGDELO, PVBEGDELE, PVBEGSIGN,

PVBEG[4:0]

PVENDDELO, PVENDDELE, PVENDSIGN,

PVEND[4:0]

When VSEHO is 0, the VS pin goes low (inactive) at the middle

of a line of video (odd field).

When VSEHO is 1 (default), the VS pin changes state at the

start of a line (odd field).

PFTOGDELO, PFTOGDELE, PFTOGSIGN,

PFTOG[4:0]

VSEHE VS End Horizontal Position Even, Address 0x33[6]

NEWAVMODE New AV Mode, Address 0x31[4]

The VSEHO and VSEHE bits select the position within a line at

which the VS pin (not the bit in the AV code) becomes active.

Some follow-on chips require the VS pin to change state only

when HS is high/low.

When NEWAVMODE is 0, EAV/SAV codes are generated to

suit ADI encoders. No adjustments are possible.

Setting NEWAVMODE to 1 (default) enables the manual

position of the VSYNC, Field, and AV codes using

Registers 0x34 to 0x37 and Register 0xE5 to 0xEA. Default

register settings are CCIR656 compliant; see Figure 21 for NTSC

and Figure 26 for PAL. For recommended manual user settings,

see Table 56 and Figure 22 for NTSC; see Table 57 and Figure 27

for PAL.

When VSEHE is 0 (default), the VS pin goes low (inactive) at

the middle of a line of video (even field).

When VSEHE is 1, the VS pin changes state at the start of a line

(even field).

PVS Polarity VS, Address 0x37[5]

HVSTIM Horizontal VS Timing, Address 0x31[3]

The polarity of the VS pin can be inverted using the PVS bit.

When PVS is 0 (default), VS is active high. When PVS is 1, VS is

active low.

The HVSTIM bit allows the user to select where the VS signal

is being asserted within a line of video. Some interface circuitry

can require VS to go low while HS is low.

PF Polarity FIELD, Address 0x37[3]

When HVSTIM is 0 (default) the start of the line is relative

to HSE.

The polarity of the FIELD pin can be inverted using the PF bit.

When PF is 0 (default), FIELD is active high. When PF is 1,

FIELD is active low.

When HVSTIM is 1, the start of the line is relative to HSB.

Rev. B | Page 41 of 104

ADV7189B

FIELD 1

525

1

2

3

4

5

6

7

8

9

10

11

12

13

19

20

21

22

OUTPUT

VIDEO

H

V

1

BT.656-4

NVBEG[4:0] = 0x5

NVEND[4:0] = 0x4

REG 0x04. BIT 7 = 1

F

NFTOG[4:0] = 0x3

FIELD 2

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

283

284

285

OUTPUT

VIDEO

H

V

1

BT.656-4

REG 0x04. BIT 7 = 1

NVBEG[4:0] = 0x5

NVEND[4:0] = 0x4

F

NFTOG[4:0] = 0x3

1

APPLIES IF NEMAVMODE = 0:

MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.

Figure 21. NTSC Default (BT.656). The polarity of H, V, and F is embedded in the data.

FIELD 1

525

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

21

22

OUTPUT

VIDEO

HS

OUTPUT

VS

OUTPUT

FIELD

OUTPUT

NVBEG[4:0] = 0x0

NVEND[4:0] = 0x3

NFTOG[4:0] = 0x5

FIELD 2

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

284

285

OUTPUT

VIDEO

HS

OUTPUT

VS

OUTPUT

NVBEG[4:0] = 0x0

NVEND[4:0] = 0x3

FIELD

OUTPUT

NFTOG[4:0] = 0x5

Figure 22. NTSC Typical Vsync/Field Positions Using Register Writes Shown in Table 56

Rev. B | Page 42 of 104

ADV7189B

Table 56. Recommended User Settings for NTSC (See Figure 22)

Register

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0xE5

0xE6

0xE7

Register Name

Write

0x1A

0x±1

0x±4

0x00

0x7D

0xA1

0x41

0x±4

0x06

Vsync Field Control 1

Vsync Field Control 2

Vsync Field Control 3

Hsync Position Control 1

Hsync Position Control 2

Hsync Position Control 3

Polarity

NTSV_V_Bit_Beg

NTSC_V_Bit_End

NTSC_F_Bit_Tog

NVBEGDELO NTSC Vsync Begin Delay on Odd Field,

Address 0xE5[7]

1

NVBEGSIGN

0

When NVBEGDELO is 0 (default), there is no delay.

ADVANCE BEGIN OF

VSYNC BY NVBEG[4:0]

DELAY BEGIN OF

VSYNC BY NVBEG[4:0]

Setting NVBEGDELO to 1 delays Vsync going high on an odd

field by a line relative to NVBEG.

NOT VALID FOR USER

PROGRAMMING

NVBEGDELE NTSC Vsync Begin Delay on Even Field,

Address 0xE5[6]

ODD FIELD?

YES

NO

When NVBEGDELE is 0 (default), there is no delay.

Setting NVBEGDELE to 1 delays Vsync going high on an even

field by a line relative to NVBEG.

NVBEGDELO

1

NVBEGDELE

1

0

NVBEGSIGN NTSC Vsync Begin Sign, Address 0xE5[5]

Setting NVBEGSIGN to 0 delays the start of Vsync. Set for user

manual programming.

ADDITIONAL

DELAY BY

1 LINE

ADDITIONAL

DELAY BY

1 LINE

Setting NVBEGSIGN to 1 (default), advances the start of Vsync.

Not recommended for user programming.

VSBHO

1

VSBHE

1

NVBEG[4:0] NTSC Vsync Begin, Address 0xE5[4:0]

The default value of NVBEG is 00101, indicating the NTSC

Vsync begin position.

0

ADVANCE BY

0.5 LINE

ADVANCE BY

0.5 LINE

For all NTSC/PAL Vsync timing controls, both the V bit in the

AV code and the Vsync on the VS pin are modified.

VSYNC BEGIN

Figure 23. NTSC Vsync Begin

Rev. B | Page 43 of 104

ADV7189B

For all NTSC/PAL Vsync timing controls, both the V bit in the

AV code and the Vsync on the VS pin are modified.

1

NVENDSIGN

0

NFTOGDELO NTSC Field Toggle Delay on Odd Field,

Address 0xE7[7]

ADVANCE END OF

VSYNC BY NVEND[4:0]

DELAY END OF VSYNC

BY NVEND[4:0]

When NFTOGDELO is 0 (default), there is no delay.

NOT VALID FOR USER

PROGRAMMING

Setting NFTOGDELO to 1 delays the field toggle/transition

on an odd field by a line relative to NFTOG.

ODD FIELD?

YES

NO

NFTOGDELE NTSC Field Toggle Delay on Even Field,

Address 0xE7[6]

NVENDDELO

1

NVENDDELE

1

When NFTOGDELE is 0 (default), there is no delay.

0

Setting NFTOGDELE to 1 delays the field toggle/transition on

an even field by a line relative to NFTOG.

ADDITIONAL

DELAY BY

1 LINE

ADDITIONAL

DELAY BY

1 LINE

1

NFTOGSIGN

0

ADVANCE TOGGLE OF

FIELD BY NFTOG[4:0]

DELAY TOGGLE OF

FIELD BY NFTOG[4:0]

VSEHO

1

VSEHE

1

0

NOT VALID FOR USER

PROGRAMMING

ADVANCE BY

0.5 LINE

ADVANCE BY

0.5 LINE

ODD FIELD?

YES

NO

VSYNC END

NFTOGDELO

1

NFTOGDELE

1

Figure 24. NTSC Vsync End

0

NVENDDELO NTSC Vsync End Delay on Odd Field,

Address 0xE6[7]

ADDITIONAL

DELAY BY

1 LINE

ADDITIONAL

DELAY BY

1 LINE

When NVENDDELO is 0 (default), there is no delay.

Setting NVENDDELO to 1 delays Vsync from going low on

an odd field by a line relative to NVEND.

FIELD

TOGGLE

NVENDDELE NTSC Vsync End Delay on Even Field,

Address 0xE6[6]

Figure 25. NTSC FIELD Toggle

NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7[5]

When NVENDDELE is set to 0 (default), there is no delay.

Setting NFTOGSIGN to 0 delays the field transition. Set for

user manual programming.

Setting NVENDDELE to 1 delays Vsync from going low on

an even field by a line relative to NVEND.

Setting NFTOGSIGN to 1 (default) advances the field

transition. Not recommended for user programming.

NVENDSIGN NTSC Vsync End Sign, Address 0xE6[5]

Setting NVENDSIGN to 0 (default) delays the end of Vsync.

Set for user manual programming .

NFTOG[4:0] NTSC Field Toggle, Address 0xE7[4:0]

The default value of NFTOG is 00011, indicating the

NTSC Field toggle position.

Setting NVENDSIGN to 1 advances the end of Vsync. Not

recommended for user programming.

For all NTSC/PAL FIELD timing controls, both the F bit

in the AV code and the FIELD signal on the FIELD

pin are modified.

NVEND NTSC[4:0] Vsync End, Address 0xE6[4:0]

The default value of NVEND is 00100, indicating the NTSC

Vsync end position.

Rev. B | Page 44 of 104

ADV7189B

Table 57. Recommended User Settings for PAL (See Figure 27)

Register

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0xE±

0xE9

0xEA

Register Name

Write

0x1A

0x±1

0x±4

0x00

0x7D

0x29

0x41

0x±4

0x06

Vsync Field Control 1

Vsync Field Control 2

Vsync Field Control 3

Hsync Position. Control 1

Hsync Position. Control 2

Hsync Position. Control 3

Polarity

PAL_V_Bit_Beg

PAL_V_Bit_End

PAL_F_Bit_Tog

FIELD 1

622

623

624

625

1

2

3

4

5

6

7

8

9

10

22

23

24

OUTPUT

VIDEO

H

V

PVBEG[4:0] = 0x5

PVEND[4:0] = 0x4

F

PFTOG[4:0] = 0x3

FIELD 2

310

311

312

313

314

315

316

317

318

319

320

321

322

335

336

337

OUTPUT

VIDEO

H

V

PVBEG[4:0] = 5

PVEND[4:0] = 0x4

F

PFTOG[4:0] = 0x3

Figure 26. PAL Default (BT.656). The polarity of H, V, and F is embedded in the data.

Rev. B | Page 45 of 104

ADV7189B

FIELD 1

622

623

624

1

2

3

4

5

6

7

8

9

10

11

23

24

625

OUTPUT

VIDEO

HS

OUTPUT

VS

OUTPUT

PVBEG[4:0] = 0x1

PVEND[4:0] = 0x4

FIELD

OUTPUT

PFTOG[4:0] = 0x6

FIELD 2

310

311

312

314

315

316

317

318

319

320

321

322

323

336

337

313

OUTPUT

VIDEO

HS

OUTPUT

VS

OUTPUT

PVBEG[4:0] = 0x1

PVEND[4:0] = 0x4

FIELD

OUTPUT

PFTOG[4:0] = 0x6

Figure 27. PAL Typical Vsync/Field Positions Using Register Writes in Table 57

PVBEGDELO PAL Vsync Begin Delay on Odd Field,

Address 0xE8[7]

1

PVBEGSIGN

0

When PVBEGDELO is 0 (default), there is no delay.

ADVANCE BEGIN OF

VSYNC BY PVBEG[4:0]

DELAY BEGIN OF

VSYNC BY PVBEG[4:0]

Setting PVBEGDELO to 1 delays Vsync going high on an odd

field by a line relative to PVBEG.

NOT VALID FOR USER

PROGRAMMING

PVBEGDELE PAL Vsync Begin Delay on Even Field,

Address 0xE8[6]

ODD FIELD?

YES

NO

When PVBEGDELE is 0, there is no delay.

Setting PVBEGDELE to 1 (default) delays Vsync going high on

an even field by a line relative to PVBEG.

PVBEGDELO

1

PVBEGDELE

1

0

PVBEGSIGN PAL Vsync Begin Sign, Address 0xE8[5]

Setting PVBEGSIGN to 0 delays the beginning of Vsync. Set for

user manual programming.

ADDITIONAL

DELAY BY

1 LINE

ADDITIONAL

DELAY BY

1 LINE

Setting PVBEGSIGN to 1 (default) advances the beginning of

Vsync. Not recommended for user programming.

VSBHO

1

VSBHE

1

PVBEG[4:0] PAL Vsync Begin, Address 0xE8[4:0]

0

The default value of PVBEG is 00101, indicating the PAL Vsync

begin position.

ADVANCE BY

0.5 LINE

ADVANCE BY

0.5 LINE

For all NTSC/PAL Vsync timing controls, both the V bit in the

AV code and the Vsync on the VS pin are modified.

VSYNC BEGIN

Figure 28. PAL Vsync Begin

Rev. B | Page 46 of 104

ADV7189B

For all NTSC/PAL Vsync timing controls, both the V bit in the

AV code and the Vsync on the VS pin are modified.

1

PVENDSIGN

0

PFTOGDELO PAL Field Toggle Delay on Odd Field,

Address 0xEA[7]

ADVANCE END OF

VSYNC BY PVEND[4:0]

DELAY END OF VSYNC

BY PVEND[4:0]

When PFTOGDELO is 0 (default), there is no delay.

NOT VALID FOR USER

PROGRAMMING

Setting PFTOGDELO to 1 delays the F toggle/transition on an

odd field by a line relative to PFTOG.

ODD FIELD?

YES

NO

PFTOGDELE PAL Field Toggle Delay on Even Field,

Address 0xEA[6]

PVENDDELO

1

PVENDDELE

1

When PFTOGDELE is 0, there is no delay.

0

Setting PFTOGDELE to 1 (default) delays the F toggle/

transition on an even field by a line relative to PFTOG.

ADDITIONAL

DELAY BY

1 LINE

ADDITIONAL

DELAY BY

1 LINE

PFTOGSIGN PAL Field Toggle Sign, Address 0xEA[5]

Setting PFTOGSIGN to 0 delays the field transition. Set for user

manual programming.

VSEHO

1

VSEHE

1

Setting PFTOGSIGN to 1 (default) advances the field transition.

Not recommended for user programming.

0

PFTOG PAL Field Toggle, Address 0xEA[4:0]

ADVANCE BY

0.5 LINE

ADVANCE BY

0.5 LINE

The default value of PFTOG is 00011, indicating the PAL field

toggle position.

VSYNC END

For all NTSC/PAL field timing controls, the F bit in the AV

code and the Field signal on the FIELD/DE pin are modified.

Figure 29. PAL Vsync End

PVENDDELO PAL Vsync End Delay on Odd Field,

Address 0xE9[7]

1

PFTOGSIGN

0

When PVENDDELO is 0 (default), there is no delay.

ADVANCE TOGGLE OF

FIELD BY PTOG[4:0]

DELAY TOGGLE OF

FIELD BY PFTOG[4:0]

Setting PVENDDELO to 1 delays Vsync going low on an odd

field by a line relative to PVEND.

NOT VALID FOR USER

PROGRAMMING

PVENDDELE PAL Vsync End Delay on Even Field,

Address 0xE9[6]

ODD FIELD?

YES

NO

When PVENDDELE is 0 (default), there is no delay.

PFTOGDELO

1

PFTOGDELE

1

Setting PVENDDELE to 1 delays Vsync going low on an even

field by a line relative to PVEND.

0

PVENDSIGN PAL Vsync End Sign, Address 0xE9[5]

ADDITIONAL

DELAY BY

1 LINE

ADDITIONAL

DELAY BY

1 LINE

Setting PVENDSIGN to 0 (default) delays the end of Vsync.

Set for user manual programming.

Setting PVENDSIGN to 1 advances the end of Vsync.

Not recommended for user programming.

FIELD

TOGGLE

PVEND[4:0] PAL Vsync End, Address 0xE9[4:0]

Figure 30. PAL F Toggle

The default value of PVEND is 10100, indicating the PAL Vsync

end position.

Rev. B | Page 47 of 104

ADV7189B

The Gemstar-compatible data is not available in the I²C

registers, and is inserted into the data stream only during

horizontal blanking.

SYNC PROCESSING

The ADV7189B has two additional sync processing blocks that

postprocess the raw synchronization information extracted from

the digitized input video. If desired, the blocks can be disabled via

the following two I²C bits.

WSSD Wide Screen Signaling Detected, Address 0x90[0]

Logic 1 for this bit indicates the data in the WSS1 and WSS2

registers is valid.

ENHSPLL Enable Hsync Processor, Address 0x01[6]

The Hsync processor is designed to filter incoming Hsyncs that

have been corrupted by noise, providing improved performance

for video signals with stable time bases but poor SNR.

The WSSD bit goes high if the rising edge of the start bit is

detected within a time window, and if the polarity of the parity

bit matches the transmitted data.

Setting ENHSPLL to 0 disables the Hsync processor.

When WSSD is 0, no WSS is detected and confidence in the

decoded data is low.

Setting ENHSPLL to 1 (default) enables the Hsync processor.

When WSSD is 1, WSS is detected and confidence in the

decoded data is high.

ENVSPROC Enable Vsync Processor, Address 0x01[3]

This block provides extra filtering of the detected Vsyncs to give

improved vertical lock.

CCAPD Closed Caption Detected, Address 0x90[1]

Logic 1 for this bit indicates the data in the CCAP1 and CCAP2

registers is valid.

Setting ENVSPROC to 0 disables the Vsync processor.

Setting ENVSPROC to 1 (default) enables the Vsync processor.

VBI DATA DECODE

The CCAPD bit goes high if the rising edge of the start bit is

detected within a time window, and if the polarity of the parity

bit matches the transmitted data.

The following low data rate VBI signals can be decoded by the

ADV7189B:

When CCAPD is 0, no CCAP signals are detected and

confidence in the decoded data is low.

•

Wide screen signaling (WSS)

Copy generation management systems (CGMS)

Closed captioning (CC)

When CCAPD is 1, the CCAP sequence is detected and

confidence in the decoded data is high.

EDTV

EDTVD EDTV Sequence Detected, Address 0x90[2]

Gemstar 1× and 2× compatible data recovery

Logic 1 for this bit indicates the data in the EDTV1, 2, 3

registers is valid.

The presence of any of the above signals is detected and, if

applicable, a parity check is performed. The result of this

testing is contained in a confidence bit in the VBI Info[7:0]

register. Users are encouraged to first examine the VBI Info

register before reading the corresponding data registers. All

VBI data decode bits are read-only.

The EDTVD bit goes high if the rising edge of the start bit is

detected within a time window, and if the polarity of the parity

bit matches the transmitted data.

When EDTVD is 0, no EDTV sequence is detected. Confidence

in decoded data is low.

All VBI data registers are double-buffered with the field sig-

nals. This means that data is extracted from the video lines

and appears in the appropriate I²C registers with the next

field transition. They are then static until the next field.

When EDTVD is 1, an EDTV sequence is detected. Confidence

in decoded data is high.

CGMSD CGMS-A Sequence Detected, Address 0x90[3]

The user should start an I²C read sequence with VS by first

examining the VBI Info register. Then, depending on what data

was detected, the appropriate data registers should be read.

Logic 1 for this bit indicates the data in the CGMS1, 2, 3

registers is valid. The CGMSD bit goes high if a valid CRC

checksum has been calculated from a received CGMS packet.

The data registers are filled with decoded VBI data even if their

corresponding detection bits are low; it is likely that bits within

the decoded data stream are wrong.

When CGMSD is 0, no CGMS transmission is detected and

confidence in the decoded data is low.

The closed captioning data (CCAP) is available in the I²C

registers, and is also inserted into the output video data

stream during horizontal blanking.

When CGMSD is 1, the CGMS sequence is decoded and

confidence in the decoded data is high.

Rev. B | Page 4± of 104

ADV7189B

Figure 31 shows the bit correspondence between the analog

CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2[2]

video waveform and the WSS1/WSS2 registers. WSS2[7:6]

are undetermined and should be masked out by software.

For certain video sources, the CRC data bits can have an invalid

format. In such circumstances, the CRC checksum validation

procedure can be disabled. The CGMSD bit goes high if the

rising edge of the start bit is detected within a time window.

EDTV Data Registers

EDTV1[7:0], Address 0x93[7:0],

EDTV2[7:0], Address 0x94[7:0],

EDTV3[7:0], Address 0x95[7:0]

When CRC_ENABLE is 0, no CRC check is performed.

The CGMSD bit goes high if the rising edge of the start bit

is detected within a time window.

Figure 32 shows the bit correspondence between the analog

video waveform and the EDTV1/EDTV2/EDTV3 registers.

When CRC_ENABLE is 1 (default), CRC checksum is used to

validate the CGMS sequence. The CGMSD bit goes high for a

valid checksum. ADI recommended setting.

EDTV3[7:6] are undetermined and should be masked out by

software. EDTV3[5] is reserved for future use and, for now,

contains a 0. The three LSBs of the EDTV waveform are

currently not supported.

Wide Screen Signaling Data

WSS1[7:0], Address 0x91[7:0], WSS2[7:0], Address

0x92[7:0]

WSS1[7:0]

WSS2[5:0]

0

1

2

3

4

5

6

7

0

1

2

3

4

5

RUN-IN

SEQUENCE

START

CODE

ACTIVE

VIDEO

11.0μs

38.4μs

42.5μs

Figure 31. WSS Data Extraction

Table 58. WSS Access Information

Signal Name

Register Location

Address

Register Default Value

Readback Only

WSS1[7:0]

WSS2[5:0]

WSS 1[7:0]

WSS 2[5:0]

145d

146d

0x91

0x92

EDTV1[7:0]

EDTV2[7:0]

EDTV3[5:0]

0

1

2

NOT SUPPORTED

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

Figure 32. EDTV Data Extraction

Table 59. EDTV Access Information

Signal Name

EDTV1[7:0]

EDTV2[7:0]

EDTV3[7:0]

Register Location

Address

Register Default Value

Readback Only

EDTV 1[7:0]

EDTV 2[7:0]

EDTV 3[7:0]

147d

14±d

149d

0x93

0x94

0x95

Readback Only

Rev. B | Page 49 of 104

ADV7189B

Closed Caption Data Registers

CGMS Data Registers

CCAP1[7:0], Address 0x99[7:0],

CCAP2[7:0], Address 0x9A[7:0]

CGMS1[7:0], Address 0x96[7:0],

CGMS2[7:0], Address 0x97[7:0],

CGMS3[7:0], Address 0x98[7:0]

Figure 34 shows the bit correspondence between the analog

video waveform and the CCAP1/CCAP2 registers. CCAP1[7]

contains the parity bit from the first word. CCAP2[7] contains

the parity bit from the second word. Refer to the GDECAD

Gemstar Decode Ancillary Data Format, Address 0x4C[0]

section.

Figure 33 shows the bit correspondence between the analog

video waveform and the CGMS1/CGMS2/CGMS3 registers.

CGMS3[7:4] are undetermined and should be masked out

by software.

+100 IRE

REF

CGMS1[7:0]

CGMS2[7:0]

CGMS3[3:0]

+70 IRE

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

0 IRE

49.1μs

± 0.5μs

–40 IRE

11.2μs

CRC SEQUENCE

2.235μs

± 20ns

Figure 33. CGMS Data Extraction

Table 60. CGMS Access Information

Signal Name

CGMS1[7:0]

CGMS2[7:0]

CGMS3[3:0]

Register Location

Address

Register Default Value

Readback Only

CGMS 1[7:0]

CGMS 2[7:0]

CGMS 3[3:0]

150d

151d

152d

0x96

0x97

0x9±

Readback Only

10.5

±

0.25μs

12.91μs

7 CYCLES

OF 0.5035MHz

(CLOCK RUN-IN)

CCAP1[7:0]

3 4 5 6

CCAP2[7:0]

0

1

2

7

0 1

2

3

4 5

6

7

S

T

A

R

T

P

A

R

I

T

Y

P

A

R

I

T

Y

50 IRE

40 IRE

BYTE 0

BYTE 1

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003μs

27.382μs

33.764μs

Figure 34. Closed-Caption Data Extraction

Table 61. CCAP Access Information

Signal Name

CCAP1[7:0]

CCAP2[7:0]

Register Location

Address

Register Default Value

Readback Only

CCAP 1[7:0]

CCAP 2[7:0]

153d

154d

0x99

0x9A

Rev. B | Page 50 of 104

ADV7189B

There is no letterbox detected bit. The user is asked to read the

LB_LCT[7:0] and LB_LCB[7:0] register values and to conclude

whether or not the letterbox-type video is present in software.

Letterbox Detection

Incoming video signals may conform to different aspect ratios

(16:9 wide screen of 4:3 standard). For certain transmissions in

the wide screen format, a digital sequence (WSS) is transmitted

with the video signal. If a WSS sequence is provided, the aspect

ratio of the video can be derived from the digitally decoded bits

WSS contains.

LB_LCT[7:0] Letterbox Line Count Top, Address

0x9B[7:0]; LB_LCM[7:0] Letterbox Line Count Mid,

Address 0x9C[7:0]; LB_LCB[7:0] Letterbox Line Count

Bottom, Address 0x9D[7:0]

Table 62. LB_LCx Access Information

In the absence of a WSS sequence, letterbox detection can

be used to find wide screen signals. The detection algorithm

examines the active video content of lines at the start and end

of a field. If black lines are detected, this may indicate the

currently shown picture is in wide screen format.

Signal Name

LB_LCT[7:0]

LB_LCM[7:0]

LB_LCB[7:0]

Address

Register Default Value

0x9B

0x9C

0x9D

Readback only

LB_TH[4:0] Letterbox Threshold Control, Address

0xDC[4:0]

Table 63. LB_TH Function

The active video content (luminance magnitude) over a line of

video is summed together. At the end of a line, this accumulated

value is compared with a threshold, and a decision is made as to

whether or not a particular line is black. The threshold value

needed may depend on the type of input signal; some control

is provided via LB_TH[4:0].

LB_TH[4:0]

Description

01100

Default threshold for detection of black lines.

(default)

01101 to

10000

Increase threshold (need larger active video

content before identifying nonblack lines).

Detection at the Start of a Field

00000 to

01011

Decrease threshold (even small noise levels can

cause the detection of nonblack lines).

The ADV7189B expects a section of at least six consecutive

black lines of video at the top of a field. Once those lines are

detected, Register LB_LCT[7:0] reports back the number of

black lines that were actually found. By default, the ADV7189B

starts looking for those black lines in sync with the beginning of

active video, for example, straight after the last VBI video line.

LB_SL[3:0] allows the user to set the start of letterbox detection

from the beginning of a frame on a line-by-line basis. The

detection window closes in the middle of the field.

LB_SL[3:0] Letterbox Start Line, Address 0xDD[7:4]

The LB_SL[3:0] bits are set at 0100b by default. This means the

letterbox detection window starts after the EDTV VBI data line.

For an NTSC signal this window is from Line 23 to Line 286.

Changing the bits to 0101, the detection window starts on

Line 24 and ends on Line 287.

Detection at the End of a Field

LB_EL[3:0] Letterbox End Line, Address 0xDD[3:0]

The ADV7189B expects at least six continuous lines of black

video at the bottom of a field before reporting back the number

of lines actually found via the LB_LCB[7:0] value. The activity

window for letterbox detection (end of field) starts in the middle

of an active field. Its end is programmable via LB_EL[3:0].

The LB_EL[3:0] bits are set at 1101b by default. This means the

letterbox detection window ends with the last active video line.

For an NTSC signal, this window is from Line 262 to Line 525.

Changing the bits to 1100, the detection window starts on

Line 261 and ends on Line 254.

Detection at the Midrange

Gemstar Data Recovery

Some transmissions of wide screen video include subtitles

within the lower black box. If the ADV7189B finds at least two

black lines followed by more nonblack video, for example, the

subtitle, and is then followed by the remainder of the bottom

black block, it reports back a midcount via LB_LCM[7:0]. If no

subtitles are found, LB_LCM[7:0] reports the same number as

LB_LCB[7:0].

The Gemstar-compatible data recovery block (GSCD) supports

1× and 2× data transmissions. In addition, it can serve as a

closed-caption decoder. Gemstar-compatible data transmissions

can occur only in NTSC. Closed-caption data can be decoded

in both PAL and NTSC.

There is a 2-field delay in the reporting of any line count

parameters.

Rev. B | Page 51 of 104

ADV7189B

Each data packet starts immediately after the EAV code of the

preceding line.

The block is configured via I²C in the following ways:

•

GDECEL[15:0] allow data recovery on selected video lines

on even fields to be enabled and disabled.

Figure 35 and Table 64 show the overall structure of the data

packet.

GDECOL[15:0] enable the data recovery on selected lines

for odd fields.

Entries within the packet are as follows:

GDECAD configures the way in which data is embedded

in the video data stream.

•

Fixed preamble sequence of 0x00, 0xFF, 0xFF.

Data identification word (DID). The value for the DID

marking a Gemstar or CCAP data packet is 0x140 (10-bit

value).

The recovered data is not available through I²C, but is being

inserted into the horizontal blanking period of an

ITU-R. BT656-compatible data stream. The data format

is intended to comply with the recommendation by the

International Telecommunications Union, ITU-R BT.1364.

See Figure 35. For more information, see the ITU website

at www.itu.ch.

•

Secondary data identification word (SDID), which contains

information about the video line from which data was

retrieved, whether the Gemstar transmission was of 1× or

2× format, and whether it was retrieved from an even or

odd field.

The format of the data packet depends on the following criteria:

•

Data count byte, giving the number of user data-words that

follow.

•

Transmission is 1× or 2×.

•

User data section.

Data is output in 8-bit or 4-bit format (see the description

of the GDECAD Gemstar Decode Ancillary Data Format,

Address 0x4C[0] bit).

Optional padding to ensure that the length of the user

data-word section of a packet is a multiple of four bytes

(requirement as set in ITU-R BT.1364).

•

Data is closed caption (CCAP) or Gemstar compatible.

•

Checksum byte.

Data packets are output if the corresponding enable bit is set

(see the GDECEL and GDECOL descriptions), and if the

decoder detects the presence of data. This means for video

lines where no data has been decoded, no data packet is

output even if the corresponding line enable bit is set.

Table 64 lists the values within a generic data packet that is

output by the ADV7189B in 10-bit format.

DATA IDENTIFICATION

SECONDARY DATA IDENTIFICATION

DATA

COUNT

OPTIONAL PADDING CHECK

00

FF

DID

SDID

USER DATA

BYTES

SUM

PREAMBLE FOR ANCILLARY DATA

USER DATA (4 OR 8 WORDS)

Figure 35. Gemstar and CCAP Embedded Data Packet (Generic)

Table 64. Generic Data Output Packet

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

0

D[0]

0

Description

0

1

0

1

0

1

0

Fixed preamble

DID

1

2

1

3

0

1

0

1

0

4

!EP

!CS[±]

EP

CS[±]

EF

0

2X

0

Line[3:0]

DC[1]

0

SDID

5

0

DC[0]

0

Data count (DC)

User data-words

Checksum

6

0

Word1[7:4]

Word1[3:0]

Word2[7:4]

Word2[3:0]

Word3[7:4]

Word3[3:0]

Word4[7:4]

Word4[3:0]

0

7

0

±

0

9

0

10

11

12

13

14

0

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

0

Rev. B | Page 52 of 104

ADV7189B

Table 65. Data Byte Allocation

Raw Information Bytes

Retrieved from the Video Line

User Data-Words

(Including Padding)

2×

1

0

GDECAD

Padding Bytes

DC[1:0]

10

01

4

2

0

1

0

1

±

4

0

2

Gemstar Bit Names

•

CS[8:2]. The checksum is provided to determine the

integrity of the ancillary data packet. It is calculated by

summing up D[8:2] of DID, SDID, the Data Count byte,

and all UDWs, and ignoring any overflow during the

summation. Since all data bytes that are used to calculate

the checksum have their 2 LSBs set to 0, the CS[1:0] bits

are also always 0.

•

DID. The data identification value is 0x140 (10-bit value).

Care has been taken that in 8-bit systems, the 2 LSBs do

not carry vital information.

•

EP and !EP. The EP bit is set to ensure even parity on the

data-word D[8:0]. Even parity means there is always an

even number of 1s within the D[8:0] bit arrangement.

This includes the EP bit. !EP describes the logic inverse of

EP and is output on D[9]. The !EP is output to ensure that

the reserved codes of 00 and FF cannot happen.

!CS[8] describes the logic inversion of CS[8]. The value

!CS[8] is included in the checksum entry of the data packet

to ensure that the reserved values of 0x00 and 0xFF do not

occur.

•

EF. Even field identifier. EF = 1 indicates that the data was

recovered from a video line on an even field.

Table 66 to Table 69 outline the possible data packages.

Gemstar 2× Format, Half-Byte Output

2×. This bit indicates whether the data sliced was in

Gemstar 1× or 2× format. A high indicates 2× format.

Half-byte output mode is selected by setting CDECAD = 0;

full-byte output mode is selected by setting CDECAD = 1.

See the GDECAD Gemstar Decode Ancillary Data Format,

Address 0x4C[0] section.

Line[3:0]. This entry provides a unique code for each of the

possible 16 source lines of video from which Gemstar data

may have been retrieved. See Table 74 and Table 75.

Gemstar 1× Format

•

DC[1:0]. Data count value. The number of user data-words

in the packet divided by 4. The number of user data-words

(UDW) in any packet must be an integral number of 4.

Padding is required at the end if necessary (requirement

as set in ITU-R BT.1364). See Table 65.

Half-byte output mode is selected by setting CDECAD = 0,

full-byte output mode is selected by setting CDECAD = 1.

See the GDECAD Gemstar Decode Ancillary Data Format,

Address 0x4C[0] section.

The 2× bit determines whether the raw information

retrieved from the video line was 2 or 4 bytes. The state

of the GDECAD bit affects whether the bytes are trans-

mitted straight (that is, two bytes transmitted as two bytes)

or whether they are split into nibbles (that is, two bytes

transmitted as four half bytes). Padding bytes are then

added where necessary.

Rev. B | Page 53 of 104

ADV7189B

Table 66. Gemstar 2× Data, Half-Byte Mode

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

Description

0

1

0

1

0

1

0

1

0

Fixed preamble

DID

1

2

1

3

0

1

0

1

0

4

!EP

!CS[±]

EP

CS[±]

EF

0

Line[3:0]

0

SDID

1

5

0

Data count

1

0

6

0

Gemstar word1[7:4]

Gemstar word1[3:0]

Gemstar word2[7:4]

Gemstar word2[3:0]

Gemstar word3[7:4]

Gemstar word3[3:0]

Gemstar word4[7:4]

Gemstar word4[3:0]

0

User data-words

Checksum

7

0

±

0

9

0

10

11

12

13

14

0

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

CS[1]

CS[0]

Table 67. Gemstar 2× Data, Full-Byte Mode

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

0

D[0]

Description

0

1

0

1

0

1

0

1

0

Fixed preamble

DID

1

2

1

3

0

1

0

Line[3:0]

0

4

!EP

EP

EF

0

SDID

5

0

Data count

1

6

Gemstar Word1[7:0]

Gemstar Word2[7:0]

Gemstar Word3[7:0]

Gemstar Word4[7:0]

0

User data-words

Checksum

7

0

±

0

9

0

10

!CS[±]

CS[±]

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

CS[1]

CS[0]

Table 68. Gemstar 1× Data, Half-Byte Mode

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

0

Description

Fixed preamble

DID

0

1

0

1

0

1

0

1

2

1

3

0

1

0

1

0

Line[3:0]

0

4

!EP

!CS[±]

EP

CS[±]

EF

0

SDID

0

5

0

Data count

1

6

0

Gemstar Word1[7:4]

Gemstar Word1[3:0]

Gemstar Word2[7:4]

Gemstar Word2[3:0]

0

User data-words

7

0

±

0

9

0

10

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

CS[1]

CS[0]

Checksum

Rev. B | Page 54 of 104

ADV7189B

Table 69. Gemstar 1× Data, Full-Byte Mode

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

Description

0

1

0

1

0

1

0

1

0

1

0

Fixed preamble

DID

1

2

1

3

0

1

0

4

!EP

EP

EF

0

Line[3:0]

0

SDID

5

0

Data count

0

1

6

Gemstar Word1[7:0]

Gemstar Word2[7:0]

0

User data-words

UDW padding 0x200

Checksum

7

0

±

1

0

9

1

0

10

!CS[±]

CS[±]

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

CS[1]

CS[0]

Table 70. NTSC CCAP Data, Half-Byte Mode

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

Description

Fixed preamble

DID

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

3

0

1

0

1

0

4

!EP

!CS[±]

EP

CS[±]

EF

0

SDID

0

5

0

Data count

6

0

CCAP Word1[7:4]

CCAP Word1[3:0]

CCAP Word2[7:4]

CCAP Word2[3:0]

0

User data-words

Checksum

7

0

±

0

9

0

10

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

CS[1]

CS[0]

Table 71. NTSC CCAP Data, Full-Byte Mode

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

Description

Fixed preamble

DID

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

3

0

1

0

4

!EP

EP

EF

0

SDID

5

0

Data count

6

CCAP Word1[7:0]

CCAP Word2[7:0]

0

User data-words

UDW padding 0x200

Checksum

7

0

±

1

0

9

1

0

10

!CS[±]

CS[±]

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

CS[1]

CS[0]

Rev. B | Page 55 of 104

ADV7189B

PAL CCAP Data

NTSC CCAP Data

Half-byte output mode is selected by setting CDECAD = 0;

full-byte output mode is selected by setting CDECAD = 1.

See the GDECAD Gemstar Decode Ancillary Data Format,

Address 0x4C[0] section. Table 72 and Table 73 list the bytes

of the data packet.

Half-byte output mode is selected by setting CDECAD = 0; the

full-byte mode is enabled by CDECAD = 1. See the GDECAD

Gemstar Decode Ancillary Data Format,

Address 0x4C[0] section. The data packet formats are shown in

Table 70 and Table 71.

PAL closed-caption data is sliced from Lines 22 and 335. The

corresponding enable bits have to be set.

NTSC closed-caption data is sliced on line 21d on even and odd

fields. The corresponding enable bit has to be set high. See the

section and the GDECOL[15:0] Gemstar Decoding Odd Lines,

Address 0x4A[7:0]; Address 0x4B[7:0]section.

See the GDECEL[15:0] Gemstar Decoding Even Lines,

Address 0x48[7:0]; Address 0x49[7:0] section and the

GDECOL[15:0] Gemstar Decoding Odd Lines,

Address 0x4A[7:0]; Address 0x4B[7:0]section.

Table 72. PAL CCAP Data, Half-Byte Mode

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

Description

Fixed preamble

DID

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

3

0

1

0

1

0

4

!EP

!CS[±]

EP

CS[±]

EF

0

SDID

0

5

0

Data count

6

0

CCAP Word1[7:4]

CCAP Word1[3:0]

CCAP Word2[7:4]

CCAP Word2[3:0]

0

User data-words

Checksum

7

0

±

0

9

0

10

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

CS[1]

CS[0]

Table 73. PAL CCAP Data, Full-Byte Mode

Byte

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

0

D[0]

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fixed preamble

DID

1

2

1

3

0

1

0

4

!EP

EP

EF

0

SDID

5

0

Data count

6

CCAP Word1[7:0]

CCAP Word2[7:0]

0

User data-words

UDW padding 0x200

Checksum

7

0

±

1

0

9

1

0

10

!CS[±]

CS[±]

CS[7]

CS[6]

CS[5]

CS[4]

CS[3]

CS[2]

CS[1]

CS[0]

Rev. B | Page 56 of 104

ADV7189B

Table 74. NTSC Line Enable Bits and Corresponding Line

Numbering

GDECEL[15:0] Gemstar Decoding Even Lines,

Address 0x48[7:0]; Address 0x49[7:0]

Line Number

The 16 bits of the GDECEL[15:0] are interpreted as a collection

of 16 individual line decode enable signals. Each bit refers to a

line of video in an even field. Setting a bit to 1 enables the decoder

block to retrieve Gemstar or closed caption-compatible data on

that particular line. Setting a bit to 0 prevents the decoder from

trying to retrieve data. See Table 74 and Table 75.

Line[3:0] (ITU-R BT.470)

Enable Bit

GDECOL[0]

GDECOL[1]

GDECOL[2]

GDECOL[3]

GDECOL[4]

GDECOL[5]

GDECOL[6]

GDECOL[7]

GDECOL[±]

GDECOL[9]

GDECOL[10]

GDECOL[11]

Comment

Gemstar

0

1

2

3

4

5

6

7

±

9

10

11

10

11

12

13

14

15

16

17

1±

19

20

21

To retrieve closed-caption data services on NTSC (Line 284),

GDECEL[11] must be set.

To retrieve closed caption data services on PAL (Line 335),

GDECEL[14] must be set.

The default value of GDECEL[15:0] is 0x0000. This setting

instructs the decoder not to attempt to decode Gemstar or

CCAP data from any line in the even field.

Gemstar or

closed caption

12

13

14

15

0

1

2

3

4

5

6

7

±

9

10

11

22

23

24

25

GDECOL[12]

GDECOL[13]

GDECOL[14]

GDECOL[15]

GDECEL[0]

GDECEL[1]

GDECEL[2]

GDECEL[3]

GDECEL[4]

GDECEL[5]

GDECEL[6]

GDECEL[7]

GDECEL[±]

GDECEL[9]

GDECEL[10]

GDECEL[11]

Gemstar

GDECOL[15:0] Gemstar Decoding Odd Lines,

Address 0x4A[7:0]; Address 0x4B[7:0]

The 16 bits of the GDECOL[15:0] form a collection of 16

individual line decode enable signals. See Table 74 and

Table 75.To retrieve closed caption data services on NTSC (Line

21), GDECOL[11] must be set.

273 (10)

274 (11)

275 (12)

276 (13)

277 (14)

27± (15)

279 (16)

2±0 (17)

2±1 (1±)

2±2 (19)

2±3 (20)

2±4 (21)

To retrieve closed-caption data services on PAL (Line 22),

GDECOL[14] must be set.

The default value of GDEC0L[15:0] is 0x0000. This setting

instructs the decoder not to attempt to decode Gemstar or

CCAP data from any line in the odd field.

GDECAD Gemstar Decode Ancillary Data Format,

Address 0x4C[0]

Gemstar or

closed caption

The decoded data from Gemstar-compatible transmissions

or closed-caption transmission is inserted into the horizontal

blanking period of the respective line of video. A potential

problem can arise if the retrieved data bytes have the value

0x00 or 0xFF. In an ITU-R BT.656-compatible data stream,

these values are reserved and used only to form a

fixed preamble.

12

13

14

15

2±5 (22)

2±6 (23)

2±7 (24)

2±± (25)

GDECEL[12]

GDECEL[13]

GDECEL[14]

GDECEL[15]

Gemstar

The GDECAD bit allows the data to be inserted into the

horizontal blanking period in two ways:

•

Insert all data straight into the data stream, even the reserved

values of 0x00 and 0xFF, if they occur. This can violate the

output data format specification ITU-R BT.1364.

•

Split all data into nibbles and insert the half-bytes over

double the number of cycles in a 4-bit format.

When GDECAD is 0 (default), the data is split into half-bytes

and inserted.

When GDECAD is 1, the data is output straight in 8-bit format.

Rev. B | Page 57 of 104

ADV7189B

6

4

Table 75. PAL Line Enable Bits and

Corresponding Line Numbering

Line Number

2

Line[3:0] (ITU-R BT.470)

Enable Bit

Comment

Not valid

Closed caption

Not valid

Closed caption

Not valid

0

12

13

14

15

0

1

2

3

4

5

6

7

±

9

10

11

12

13

14

15

16

17

1±

19

20

21

22

23

321 (±)

322 (9)

323 (10)

324 (11)

325 (12)

326 (13)

327 (14)

32± (15)

329 (16)

330 (17)

331 (1±)

332 (19)

333 (20)

334 (21)

335 (22)

336 (23)

GDECOL[0]

GDECOL[1]

GDECOL[2]

GDECOL[3]

GDECOL[4]

GDECOL[5]

GDECOL[6]

GDECOL[7]

GDECOL[±]

GDECOL[9]

GDECOL[10]

GDECOL[11]

GDECOL[12]

GDECOL[13]

GDECOL[14]

GDECOL[15]

GDECEL[0]

GDECEL[1]

GDECEL[2]

GDECEL[3]

GDECEL[4]

GDECEL[5]

GDECEL[6]

GDECEL[7]

GDECEL[±]

GDECEL[9]

GDECEL[10]

GDECEL[11]

GDECEL[12]

GDECEL[13]

GDECEL[14]

GDECEL[15]

–2

–4

–6

–8

–10

–12

2.0

2.5

3.0

3.5

4.0

4.5

5.0

FREQUENCY (MHz)

Figure 36. NTSC IF Compensation Filter Responses

6

4

9

2

10

11

12

13

14

15

0

1

2

3

4

5

6

7

±

9

10

11

0

–2

–4

–6

–8

3.0

3.5

4.0

4.5

5.0

5.5

6.0

FREQUENCY (MHz)

Figure 37. PAL IF Compensation Filter Responses

See Table 86 for programming details.

I²C Interrupt System

The ADV7189B has a comprehensive interrupt register set. This

map is located in the Register Access. See Table 85 for details of

the interrupt register map. How to access this map is described

in Figure 38.

IF Compensation Filter

2

COMMON I C SPACE

ADDRESS 0x00 => 0x3F

IFFILTSEL[2:0] IF Filter Select Address 0xF8[2:0]

The IFFILTSEL[2:0] register allows the user to compensate for

SAW filter characteristics on a composite input as would be

observed on tuner outputs. Figure 36 and Figure 37 show IF

filter compensation for NTSC and PAL.

ADDRESS 0x0E BIT 6,5 = 00b

ADDRESS 0x0E BIT 6,5 = 01b

2

I C SPACE

REGISTER ACCESS PAGE 1

ADDRESS 0x40 => 0xFF

REGISTER ACCESS PAGE 2

ADDRESS 0x40 => 0x4C

The options for this feature are as follows:

NORMAL REGISTER SPACE

INTERRUPT REGISTER SPACE

•

Bypass Mode (default)

Figure 38. Register Access, Page 1 and Page 2

NTSC—consists of three filter characteristics

PAL—consists of three filter characteristics

Rev. B | Page 5± of 104

ADV7189B

INTRQ_OP_SEL[1:0], Interrupt Duration Select

Address 0x40 (Interrupt Space)[1:0]

Interrupt Request Output Operation

INTRQ

When an interrupt event occurs, the interrupt pin

goes low with a programmable duration given by

INTRQ_DUR_SEL[1:0].

Table 77. INTRQ_OP_SEL

INTRQ_OP_SEL[1:0] Description

INTRQ_DURSEL[1:0], Interrupt Duration Select

Address 0x40 (Interrupt Space)[7:6]

00 (default)

Open drain

01

10

11

Drive low when active

Drive high when active

Reserved

Table 76. INTRQ_DUR_SEL

INTRQ_DURSEL[1:0] Description

00 (default)

3 Xtal periods

Multiple Interrupt Events

01

10

11

15 Xtal periods

63 Xtal periods

Active until cleared

If Interrupt Event 1 occurs and then Interrupt Event 2 occurs

before the system controller has cleared or masked Interrupt

Event 1, the ADV7189B does not generate a second interrupt

signal. The system controller should check all unmasked

interrupt status bits since more than one can be active.

When the active-until-Cleared interrupt duration is selected

and the event that caused the interrupt is no longer in force,

the interrupt persists until it is masked or cleared.

Macrovision Interrupt Selection Bits

The user can select between pseudo sync pulse and color stripe

detection as follows:

For example, if the ADV7189B loses lock, an interrupt is

INTRQ

returns to the locked state,

generated and the

pin goes low. If the ADV7189B

INTRQ

MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits

Address 0x40 (Interrupt Space)[5:4]

continues to drive low

until the SD_LOCK bit is either masked or cleared.

Interrupt Drive Level

Table 78. MV_INTRQ_SEL

MV_INTRQ_SEL[1:0] Description

The ADV7189B resets with open drain enabled and all

interrupts masked off. Therefore,

impedance state after reset. 01 or 10 has to be written to

INTRQ_OP_SEL[1:0] for a logic level to be driven out

INTRQ

is in a high

00

Reserved

01 (default)

Pseudo sync only

10

11

Color stripe only

Either pseudo sync or color stripe

INTRQ

from the

pin.

It is also possible to write to a register in the ADV7189B that

Additional information relating to the interrupt system is

detailed in Table 84.

INTRQ

manually asserts the

pin. This bit is MPU_STIM_INTRQ.

Rev. B | Page 59 of 104

ADV7189B

PIXEL PORT CONFIGURATION

SWPC Swap Pixel Cr/Cb, Address 0x27[7]

The ADV7189B has a very flexible pixel port that can be config-

ured in a variety of formats to accommodate downstream ICs.

Table 79 and Table 80 summarize the various functions that the

ADV7189B pins can have in different modes of operation.

This bit allows Cr and Cb samples to be swapped.

When SWPC is 0 (default), no swapping is allowed.

When SWPC is 1, the Cr and Cb values can be swapped.

The ordering of components, for example, Cr vs. Cb,

CHA/B/C, can be changed. Refer to the SWPC Swap Pixel

Cr/Cb, Address 0x27[7] section. Table 79 indicates the default

positions for the Cr/Cb components.

LLC1 Output Selection, LLC_PAD_SEL[2:0],

Address 0x8F[6:4]

The following I²C write allows the user to select between the

LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).

OF_SEL[3:0] Output Format Selection, Address 0x03[5:2]

The modes in which the ADV7189B pixel port can be configured

are under the control of OF_SEL[3:0]. See Table 80 for details.

The LLC2 signal is useful for LLC2-compatible wide bus

(16-/20-bit) output modes. See OF_SEL[3:0] for additional

information. The LLC2 signal and data on the data bus are

synchronized. By default, the rising edge of LLC1/LLC2 is

aligned with the Y data; the falling edge occurs when the data

bus holds C data. The polarity of the clock, and therefore the

Y/C assignments to the clock edges, can be altered by using

the Polarity LLC pin.

The default LLC frequency output on the LLC1 pin is approxi-

mately 27 MHz. For modes that operate with a nominal data

rate of 13.5 MHz (0001, 0010), the clock frequency on the

LLC1 pin stays at the higher rate of 27 MHz. For information

on outputting the nominal 13.5 MHz clock on the LLC1 pin,

see the LLC1 Output Selection, LLC_PAD_SEL[2:0],

Address 0x8F[6:4] section.

When LLC_PAD_SEL[2:0] is 000 (default), the output is

nominally 27 MHz LLC on the LLC1 pin.

When LLC_PAD_SEL[2:0] is 101, the output is nominally

13.5 MHz LLC on the LLC1 pin.

Table 79. P19 to P0 Output/Input Pin Mapping

Data Port Pins P[19:0]

19 18 17 16 15 14 13 12 11 10

YCrCb[7:0] OUT

YCrCb[9:0] OUT

Y[7:0] OUT

Y[9:0] OUT

9

8

7

6

5

4

3

2

1

0

Processor, Format, and Mode

Video Out, ±-Bit, 4:2:2

Video Out, 10-Bit, 4:2:2

Video Out, 16-Bit, 4:2:2

Video Out, 20-Bit, 4:2:2

CrCb[7:0] OUT

CrCb[9:0] OUT

Table 80. Standard Definition Pixel Port Modes

Pixel Port Pins P[19:0]

Function

P[19:10]

P[11:10]

YCrCb[1:0]

P9[9:0]

OF_SEL[3:0]

0000

Format

P[19:12]

YCrCb[9:2]

Y[9:2]

P[9:2]

P[1:0]

10-Bit at LLC1 4:2:2

20-Bit at LLC2 4:2:2

16-Bit at LLC2 4:2:2

±-Bit at LLC1 4:2:2

Reserved

Three-State

CrCb[9:2]

CrCb[7:0]

Three-state

Three-State

CrCb[1:0]

0001

Y[1:0]

0010

Y[7:0]

Three-state

0011 (default)

0110-1111

YCrCb[7:0]

Reserved. Do not use.

Rev. B | Page 60 of 104

ADV7189B

MPU PORT DESCRIPTION

The R/W bit determines the direction of the data. Logic 0 on

the LSB of the first byte means the master writes information

to the peripheral. Logic 1 on the LSB of the first byte means the

master reads information from the peripheral.

The ADV7189B supports a 2-wire (I²C-compatible) serial inter-

face. Two inputs, serial data (SDA) and serial clock (SCLK),

carry information between the ADV7189B and the system I²C

master controller. Each slave device is recognized by a unique

address. The ADV7189B’s I²C port allows the user to set up and

configure the decoder and to read back captured VBI data. The

ADV7189B has four possible slave addresses for both read and

write operations, depending on the logic level on the ALSB pin.

These four unique addresses are shown in Table 81. The

ADV7189B’s ALSB pin controls Bit 1 of the slave address. By

altering the ALSB, it is possible to control two ADV7189Bs in

an application without having a conflict with the same slave

address. The LSB (Bit 0) sets either a read or write operation.

Logic 1 corresponds to a read operation; Logic 0 corresponds to

a write operation.

The ADV7189B acts as a standard slave device on the bus.

The data on the SDA pin is eight bits long, supporting the

7-bit addresses plus the R/W bit. The ADV7189B has 249

subaddresses to enable access to the internal registers. It

therefore interprets the first byte as the device address and

the second byte as the starting subaddress. The subaddresses

auto-increment, allowing data to be written to or read from

the starting subaddress. A data transfer is always terminated

by a stop condition. The user can also access any unique

subaddress register on a one-by-one basis without having

to update all the registers.

Table 81. I²C Address for ADV7189B

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCLK high period,

the user should only issue one start condition, one stop condition,

or a single stop condition followed by a single start condition. If

an invalid subaddress is issued by the user, the ADV7189B does

not issue an acknowledge and returns to the idle condition.

ALSB

R/W

Slave Address

0x40

0x41

0x42

0x43

0

1

0

1

0

1

To control the device on the bus, a specific protocol must be

followed. First, the master initiates a data transfer by establish-

ing a start condition, which is defined by a high-to-low transition

on SDA while SCLK remains high. This indicates that an

address/data stream follows. All peripherals respond to the start

condition and shift the next eight bits (7-bit address + R/W bit).

The bits are transferred from MSB down to LSB. The peripheral

that recognizes the transmitted address responds by pulling the

data line low during the ninth clock pulse; this is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition is

where the device monitors the SDA and SCLK lines, waiting for

the start condition and the correct transmitted address.

If in auto-increment mode the user exceeds the highest

subaddress, the following action is taken:

1. In read mode, the highest subaddress register contents

continue to be output until the master device issues a

no-acknowledge. This indicates the end of a read. A no-

acknowledge condition is when the SDA line is not pulled

low on the ninth pulse.

2. In write mode, the data for the invalid byte is not loaded

into any subaddress register, a no acknowledge is issued by

the ADV7189B, and the part returns to the idle condition.

SDATA

SCLOCK

S

P

1–7

8

9

1–7

8

9

1–7

DATA

8

9

START ADDR R/W ACK SUBADDRESS ACK

ACK

STOP

Figure 39. Bus Data Transfer

WRITE

S

SLAVE ADDR A(S) SUB ADDR

LSB = 0

A(S)

DATA

A(S)

DATA

A(S) P

SEQUENCE

LSB = 1

READ

SEQUENCE

SLAVE ADDR A(S) SUB ADDR

A(S)

S

SLAVE ADDR A(S)

DATA

A(M)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(S) = NO-ACKNOWLEDGE BY SLAVE

A(M) = NO-ACKNOWLEDGE BY MASTER

Figure 40. Read and Write Sequence

Rev. B | Page 61 of 104

ADV7189B

REGISTER ACCESSES

I²C SEQUENCER

An I²C sequencer is used when a parameter exceeds eight bits,

and is therefore distributed over two or more I²C registers, for

example, HSB[11:0].

The MPU can write to or read from most of the ADV7189B’s

registers, excepting the registers that are read-only or write-

only. The subaddress register determines which register the next

read or write operation accesses. All communications with the

part through the bus start with an access to the subaddress

register. Then, a read/write operation is performed from/to the

target address, which then increments to the next address until

a stop command on the bus is performed.

When such a parameter is changed using two or more I²C write

operations, the parameter can hold an invalid value for the time

between the first I²C being completed and the last I²C being

completed. In other words, the top bits of the parameter can

already hold the new value while the remaining bits of the

parameter still hold the previous value.

REGISTER PROGRAMMING

This section describes the configuration of each register. The

communications register is an 8-bit, write-only register. After

the part has been accessed over the bus and a read/write opera-

tion is selected, the subaddress is set up. The subaddress register

determines to/from which register the operation takes place.

Table 82 lists the various operations under the control of the

Subaddress register for the control port.

To avoid this problem, the I²C sequencer holds the already

updated bits of the parameter in local memory; all bits of the

parameter are updated together once the last register write

operation has completed.

The correct operation of the I²C sequencer relies on the

following:

All I²C registers for the parameter in question must be

written to in order of ascending addresses. For example, for

HSB[10:0], write to Address 0x34 first followed by 0x35.

Register Select (SR7–SR0)

•

These bits are set up to point to the required starting address.

•

No other I²C taking place between the two (or more) I²C

writes for the sequence. For example, for HSB[10:0], write

to Address 0x34 first immediately followed by 0x35.

Rev. B | Page 62 of 104

ADV7189B

I²C REGISTER MAPS

Table 82. Common and Normal (Page 1) Register Map Details

Subaddress

Hex

Register Name

Input Control

Reset Value

0000 0000

1100 1000

0000 0100

0000 1100

01xx 0101

0000 0000

0000 0010

0111 1111

1000 0000

0000 0000

0011 0110

0111 1100

0000 0000

xxxx xxxx

0001 0010

0100 xxxx

xxxx xxxx

0000 0001

1001 0011

1111 0001

xxxx xxxx

0000 0xxx

xxxx xxxx

0101 1000

xxxx xxxx

1110 0001

1010 1110

1111 0100

0000 0000

1111 xxxx

xxxx xxxx

0001 0010

0100 0001

1000 0100

0000 0000

0000 0010

0000 0000

0000 0001

1000 0000

1100 0000

0001 0000

xxxx xxxx

0100 0011

rw

r

Dec

0

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x0±

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x1±

0x19

Video Selection

Reserved

1

2

Output Control

Extended Output Control

Reserved

3

4

5

Reserved

6

Autodetect Enable

Contrast

7

±

Reserved

9

Brightness

10

11

12

13

14

15

16

17

1±

19

20

21

22

23

24

25

26 to 2±

29

30 to 3±

39

40 to 42

43

44

45

46

47

4±

49

50

51

52

53

54

55

56

57

5±

59 to 60

61

Hue

Default Value Y

Default Value C

ADI Control

Power Management

Status 1

Ident

r

Status 2

r

Status 3

r

Analog Clamp Control

Digital Clamp Control 1

Reserved

rw

Shaping Filter Control

Shaping Filter Control 2

Comb Filter Control

Reserved

0x1A to 0x1C

0x1D

ADI Control 2

Reserved

0x1E to 0x26

0x27

Pixel Delay Control

Reserved

0x2± to 0x2A

0x2B

Misc Gain Control

AGC Mode Control

Chroma Gain Control 1

Chroma Gain Control 2

Luma Gain Control 1

Luma Gain Control 2

Vsync Field Control 1

Vsync Field Control 2

Vsync Field Control 3

Hsync Position Control 1

Hsync Position Control 2

Hsync Position Control 3

Polarity

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

NTSC Comb Control

PAL Comb Control

ADC Control

0x3±

0x39

0x3A

Reserved

0x3B to 0x3C

0x3D

Manual Window Control

Rev. B | Page 63 of 104

ADV7189B

Subaddress

Hex

Register Name

Reserved

Reset Value

xxxx xxxx

0100 0001

xxxx xxxx

00000000

0000 0000

xxxx xxx0

1110 1111

0000 1000

xxxx xxxx

0000 1000

0010 0100

xxxx xxxx

0000 0000

xxxx xxxx

0001 1100

xxxx xxxx

0xxx xxxx

xxxx xxxx

1010 1100

0100 1100

0000 0000

0001 0100

1000 0000

0010 0101

0000 0100

0110 0011

0110 0101

0001 0100

0110 0011

xxxx xxxx

rw

w

Dec

62 to 64

65

0x3E to 0x40

Resample Control

Reserved

0x41

66 to 71

72

0x42 to 0x47

0x4±

Gemstar Ctrl 1

Gemstar Ctrl 2

Gemstar Ctrl 3

Gemstar Ctrl 4

GemStar Ctrl 5

CTI DNR Ctrl 1

CTI DNR Ctrl 2

Reserved

73

0x49

74

0x4A

75

0x4B

76

0x4C

77

0x4D

7±

0x4E

79

0x4F

CTI DNR Ctrl 4

Lock Count

Reserved

±0

0x50

±1

0x51

±2 to 142

143

0x52 to 0x±E

0x±F

Free Run Line Length 1

Reserved

w

144

0x90

VBI Info

r

144

0x90

WSS 1

r

145

0x91

WSS 2

r

146

0x92

EDTV 1

r

147

0x93

EDTV 2

r

14±

0x94

EDTV 3

r

149

0x95

CGMS 1

r

150

0x96

CGMS 2

r

151

0x97

CGMS 3

r

152

0x9±

CCAP 1

r

153

0x99

CCAP 2

r

154

0x9A

Letterbox 1

Letterbox 2

Letterbox 3

Reserved

r

155

0x9B

r

156

0x9C

r

157

0x9D

rw

w

15± to 177

17±

0x9E to 0xB1

0xB2

CRC Enable

Reserved

rw

179 to 194

195

0xB2 to 0xC2

0xC3

ADC Switch 1

ADC Switch 2

Reserved

196

0xC4

197 to 219

220

0xC5 to 0xDB

0xDC

0xDD

0xDE

Letterbox Control 1

Letterbox Control 2

Reserved

221

222

Reserved

223

0xDF

Reserved

224

0xE0

SD Offset Cb

SD Offset Cr

SD Saturation Cb

SD Saturation Cr

NTSC V Bit Begin

NTSC V Bit End

NTSC F Bit Toggle

PAL V Bit Begin

PAL V Bit End

PAL F Bit Toggle

Reserved

225

0xE1

226

0xE2

227

0xE3

22±

0xE4

229

0xE5

230

0xE6

231

0xE7

232

0xE±

233

0xE9

234

0xEA

235 to 243

0xEB to 0xF3

Rev. B | Page 64 of 104

ADV7189B

Subaddress

Hex

Register Name

Drive Strength

Reserved

Reset Value

xx01 0101

xxxx xxxx

rw

Dec

244

0xF4

245 to 247

24±

0xF5 to 0xF7

IF Comp Control

VS Mode Control

0000 0000

0xF±

0xF9

249

Table 83. Common and Normal (Page 1) Register Map Bit Names

Register Name

Input Control

Video Selection

Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VID_SEL.3

VID_SEL.2

ENHSPLL

VID_SEL.1

BETACAM

VID_SEL.0

INSEL.3

INSEL.2

INSEL.1

INSEL.0

ENVSPROC

Output Control

VBI_EN

TOD

OF_SEL.3

OF_SEL.2

OF_SEL.1

TIM_OE

OF_SEL.0

BL_C_VBI

SD_DUP_AV

RANGE

Extended

BT656-4

EN_SFL_PI

Output Control

Reserved

Autodetect

Enable

AD_SEC525_EN

CON.7

AD_SECAM_EN

CON.6

AD_N443_EN

CON.5

AD_P60_EN

CON.4

AD_PALN_EN

CON.3

AD_PALM_EN

CON.2

AD_NTSC_EN

CON.1

AD_PAL_EN

CON.0

Contrast

Reserved

Brightness

Hue

BRI.7

BRI.6

BRI.5

BRI.4

BRI.3

BRI.2

BRI.1

BRI.0

HUE.7

DEF_Y.5

HUE.6

DEF_Y.4

HUE.5

DEF_Y.3

HUE.4

DEF_Y.2

HUE.3

DEF_Y.1

HUE.2

DEF_Y.0

HUE.1

HUE.0

Default Value Y

DEF_VAL_AUTO

_EN

DEF_VAL_EN

Default Value C

ADI Control

DEF_C.7

RES

DEF_C.6

DEF_C.5

PWRDN

DEF_C.4

DEF_C.3

DEF_C.2

PDBP

DEF_C.1

DEF_C.0

SUB_USR_EN.0

Power

Management

Status 1

Ident

COL_KILL

IDENT.7

AD_RESULT.2

IDENT.6

AD_RESULT.1

IDENT.5

AD_RESULT.0

IDENT.4

FOLLOW_PW

IDENT.3

FSC_LOCK

IDENT.2

LOST_LOCK

IDENT.1

IN_LOCK

IDENT.0

Status 2

Status 3

FSC NSTD

LL NSTD

MV AGC DET

MV PS DET

SD_OP_50HZ

MVCS T3

GEMD

MVCS DET

INST_HLOCK

PAL SW LOCK

INTERLACE

DCT.1

STD FLD LEN

FREE_RUN_ACT

CCLEN

Analog Clamp

Control

Digital Clamp

Control 1

DCT.0

Reserved

Shaping Filter

Control

CSFM.2

CSFM.1

CSFM.0

YSFM.4

YSFM.3

YSFM.2

YSFM.1

YSFM.0

Shaping Filter

Control 2

WYSFMOVR

WYSFM.4

WYSFM.3

NSFSEL.1

WYSFM.2

NSFSEL.0

WYSFM.1

PSFSEL.1

WYSFM.0

PSFSEL.0

Comb Filter

Control

Reserved

VS_JIT_COMP_EN

CTA.2

ADI Control 2

Reserved

TRI_LLC

SWPC

EN2±XTAL

Pixel Delay

Control

AUTO_PDC_EN

CTA.1

CTA.0

LTA.1

LTA.0

Reserved

Misc Gain

Control

CKE

PW_UPD

CAGC.0

CMG.±

CMG.0

LMG.±

AGC Mode

Control

LAGC.2

CAGT.0

CMG.6

LGAT.0

LMG.6

LAGC.1

CMG.5

LMG.5

LAGC.0

CMG.4

CAGC.1

CMG.9

CMG.1

LMG.9

LMG.1

Chroma Gain

Control 1

CAGT.1

CMG.7

LAGT.1

LMG.7

CMG.11

CMG.3

LMG.11

LMG.3

CMG.10

CMG.2

LMG.10

LMG.2

Chroma Gain

Control 2

Luma Gain

Control 1

Luma Gain

Control 2

LMG.4

LMG.0

Vsync Field

Control 1

NEWAVMODE

HVSTIM

Rev. B | Page 65 of 104

ADV7189B

Register Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Vsync Field

Control 2

VSBHO

VSEHO

VSBHE

Vsync Field

Control 3

VSEHE

HSB.10

HSB.6

HSE.6

Hsync Position

Control 1

HSB.9

HSB.5

HSE.5

HSB.±

HSB.4

HSE.4

HSE.10

HSB.2

HSE.2

HSE.9

HSB.1

HSE.1

HSE.±

HSB.0

HSE.0

Hsync Position

Control 2

HSB.7

HSE.7

HSB.3

HSE.3

Hsync Position

Control 3

Polarity

PHS

PVS

PF

PCLK

NTSC Comb

Control

CTAPSN.1

CTAPSN.0

CTAPSP.0

CCMN.2

CCMN.1

CCMP.1

CCMN.0

YCMN.2

YCMN.1

YCMN.0

PAL Comb

Control

CTAPSP.1

CCMP.2

CCMP.0

YCMP.2

YCMP.1

YCMP.0

ADC Control

Reserved

PWRDN_AD C_0

PWRDN_AD C_1

PWRDN_ADC_2

Manual

Window

Control

CKILLTHR.2

SFL_INV

CKILLTHR.1

CKILLTHR.0

Reserved

Resample

Control

Reserved

Gemstar Ctrl 1

Gemstar Ctrl 2

Gemstar Ctrl 3

Gemstar Ctrl 4

Gemstar Ctrl 5

CTI DNR Ctrl 1

CTI DNR Ctrl 2

Reserved

GDECEL.15

GDECEL.7

GDECOL.15

GDECOL.7

GDECEL.14

GDECEL.6

GDECOL.14

GDECOL.6

GDECEL.13

GDECEL.5

GDECOL.13

GDECOL.5

GDECEL.12

GDECEL.4

GDECOL.12

GDECOL.4

GDECEL.11

GDECEL.3

GDECOL.11

GDECOL.3

GDECEL.10

GDECEL.2

GDECOL.10

GDECOL.2

GDECEL.9

GDECEL.1

GDECOL.9

GDECOL.1

GDECEL.±

GDECEL.0

GDECOL.±

GDECOL.0

GDECAD

CTI_EN

DNR_EN

CTI_AB.1

CTI_AB.0

CTI_AB_EN

CTI_C_TH.1

CTI_C_TH.7

CTI_C_TH.6

CTI_C_TH.5

CTI_C_TH.4

CTI_C_TH.3

CTI_C_TH.2

CTI_C_TH.0

CTI DNR Ctrl 4

Lock Count

DNR_TH.7

FSCLE

DNR_TH.6

SRLS

DNR_TH.5

COL.2

DNR_TH.4

COL.1

DNR_TH.3

COL.0

DNR_TH.2

CIL.2

DNR_TH.1

CIL.1

DNR_TH.0

CIL.0

Reserved

Free Run Line

Length 1

LLC_PAD_SEL.2

LLC_PAD_SEL.1

LLC_PAD_SEL.0

Reserved

VBI Info

CGMSD

EDTVD

CCAPD

WSSD

WSS 1

WSS1.7

WSS1.6

WSS1.5

WSS1.4

WSS1.3

WSS1.2

WSS1.1

WSS1.0

WSS 2

WSS2.7

WSS2.6

WSS2.5

WSS2.4

WSS2.3

WSS2.2

WSS2.1

WSS2.0

EDTV 1

EDTV1.7

EDTV2.7

EDTV3.7

CGMS1.7

CGMS2.7

CGMS3.7

CCAP1.7

CCAP2.7

LB_LCT.7

LB_LCM.7

LB_LCB.7

EDTV1.6

EDTV2.6

EDTV3.6

CGMS1.6

CGMS2.6

CGMS3.6

CCAP1.6

CCAP2.6

LB_LCT.6

LB_LCM.6

LB_LCB.6

EDTV1.5

EDTV2.5

EDTV3.5

CGMS1.5

CGMS2.5

CGMS3.5

CCAP1.5

CCAP2.5

LB_LCT.5

LB_LCM.5

LB_LCB.5

EDTV1.4

EDTV2.4

EDTV3.4

CGMS1.4

CGMS2.4

CGMS3.4

CCAP1.4

CCAP2.4

LB_LCT.4

LB_LCM.4

LB_LCB.4

EDTV1.3

EDTV2.3

EDTV3.3

CGMS1.3

CGMS2.3

CGMS3.3

CCAP1.3

CCAP2.3

LB_LCT.3

LB_LCM.3

LB_LCB.3

EDTV1.2

EDTV2.2

EDTV3.2

CGMS1.2

CGMS2.2

CGMS3.2

CCAP1.2

CCAP2.2

LB_LCT.2

LB_LCM.2

LB_LCB.2

EDTV1.1

EDTV2.1

EDTV3.1

CGMS1.1

CGMS2.1

CGMS3.1

CCAP1.1

CCAP2.1

LB_LCT.1

LB_LCM.1

LB_LCB.1

EDTV1.0

EDTV2.0

EDTV3.0

CGMS1.0

CGMS2.0

CGMS3.0

CCAP1.0

CCAP2.0

LB_LCT.0

LB_LCM.0

LB_LCB.0

EDTV 2

EDTV 3

CGMS 1

CGMS 2

CGMS 3

CCAP 1

CCAP 2

Letterbox 1

Letterbox 2

Letterbox 3

Reserved

CRC Enable

Reserved

ADC Switch 1

ADC Switch 2

Reserved

CRC_ENABLE

ADC1_SW.3

ADC1_SW.2

LB_SL.2

ADC1_SW.1

LB_SL.1

ADC1_SW.0

ADC0_SW.3

ADC2_SW.3

ADC0_SW.2

ADC2_SW.2

ADC0_SW.1

ADC2_SW.1

ADC0_SW.0

ADC2_SW.0

ADC_SW_M AN

Letterbox

Control 1

LB_TH.4

LB_SL.0

LB_TH.3

LB_EL.3

LB_TH.2

LB_EL.2

LB_TH.1

LB_EL.1

LB_TH.0

LB_EL.0

Letterbox

Control 2

LB_SL.3

Reserved

Rev. B | Page 66 of 104

ADV7189B

Register Name

SD Offset Cb

SD Offset Cr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SD_OFF_CB.7

SD_OFF_CR.7

SD_SAT_CB.7

SD_OFF_CB.6

SD_OFF_CR.6

SD_SAT_CB.6

SD_OFF_CB.5

SD_OFF_CR.5

SD_SAT_CB.5

SD_OFF_CB.4

SD_OFF_CR.4

SD_SAT_CB.4

SD_OFF_CB.3

SD_OFF_CR.3

SD_SAT_CB.3

SD_OFF_CB.2

SD_OFF_CR.2

SD_SAT_CB.2

SD_OFF_CB.1

SD_OFF_CR .1

SD_SAT_CB.1

SD_OFF_CB.0

SD_OFF_CR.0

SD_SAT_CB.0

SD Saturation

Cb

SD Saturation

Cr

SD_SAT_CR.7

NVBEGDEL O

SD_SAT_CR.6

NVBEGDEL E

SD_SAT_CR.5

NVBEGSIGN

SD_SAT_CR.4

NVBEG.4

SD_SAT_CR.3

NVBEG.3

SD_SAT_CR.2

NVBEG.2

SD_SAT_CR.1

NVBEG.1

SD_SAT_CR.0

NVBEG.0

NTSC V Bit

Begin

NTSC V Bit End

NVENDDEL O

NFTOGDEL O

NVENDDEL E

NFTOGDEL E

NVENDSIGN

NFTOGSIGN

NVEND.4

NFTOG.4

NVEND.3

NFTOG.3

NVEND.2

NFTOG.2

NVEND.1

NFTOG.1

NVEND.0

NFTOG.0

NTSC F Bit

Toggle

PAL V Bit Begin

PAL V Bit End

PAL F Bit Toggle

Reserved

PVBEGDEL O

PVENDDEL O

PFTOGDEL O

PVBEGDEL E

PVENDDEL E

PFTOGDEL E

PVBEGSIGN

PVENDSIGN

PFTOGSIGN

PVBEG.4

PVEND.4

PFTOG.4

PVBEG.3

PVEND.3

PFTOG.3

PVBEG.2

PVEND.2

PFTOG.2

PVBEG.1

PVEND.1

PFTOG.1

PVBEG.0

PVEND.0

PFTOG.0

Drive Strength

Reserved

DR_STR.1

DR_STR.0

DR_STR_C.1

DR_STR_C.0

IFFILTSEL.2

DR_STR_S.1

IFFILTSEL.1

DR_STR_S.0

IFFILTSEL.0

IF Comp Control

VS Mode

Control

VS_COAST_

MODE.1

VS_COAST_

MODE.0

EXTEND_VS_

MIN_FREQ

EXTEND_VS_

MAX_FREQ

I²C REGISTER MAP DETAILS

The following registers are located in the Common I2C Register Maps and Register Access sections, Page 2.

Table 84. Interrupt (Page 2) Register Map Details¹

F

Subaddress

Reset

Value

Register Name

rw

7

6

5

4

3

2

1

0

Dec

Hex

Interrupt Config 0

0001

x000

rw

64

0x40

INTRQ_DU

R_SEL.1

INTRQ_

DUR_SEL.0

MV_INTRQ

_SEL.1

MV_INTRQ

_SEL.0

MPU_STIM

_INTRQ

INTRQ_OP

_SEL.1

INTRQ_OP

_SEL.0

Reserved

65

66

0x41

0x42

Interrupt Status 1

r

MV_PS_

CS_Q

SD_FR_

CHNG_Q

SD_

UNLOCK_Q

SD_LOCK_

Q

SD_UNLOCK

_CLR

Interrupt Clear 1

Interrupt Mask b1

x000

0000

w

rw

67

6±

0x43

0x44

MV_PS_

CS_CLR

SD_FR_CH

NG_CLR

SD_LOCK_

CLR

SD_UNLOCK

_MSKB

x000

0000

MV_PS_

CS_MSKB

SD_FR_CH

NG_MSKB

SD_LOCK_

MSKB

Reserved

69

70

0x45

0x46

Interrupt Status 2

r

MPU_STIM

_INTRQ_Q

WSS_CHN

GD_Q

CGMS_

CHNGD_Q

GEMD_Q

CCAPD_Q

Interrupt Clear 2

Interrupt Mask b2

0xxx

0000

w

71

72

0x47

0x4±

MPU_STIM

_INTRQ_

CLR

WSS_

CHNGD_

CLR

CGMS_

CHNGD_

CLR

GEMD_CLR

CCAPD_

CLR

0xxx

0000

rw

MPU_

STIM_INTR

Q_MSKB

WSS_

CHNGD_

MSKB

CGMS_

CHNGD_

MSKB

GEMD_

MSKB

CCAPD_

MSKB

SD_H_LOCK

Raw Status 3

r

73

74

75

0x49

0x4A

0x4B

SCM_LOCK

SD_V_LOCK

SD_OP_

50HZ

PAL_SW_LK

_CHNG_Q

SD_H_LOCK

_CHNG_Q

SD_V_LOCK

_CHNG_Q

Interrupt Status 3

Interrupt Clear 3

r

SCM_LOCK

_CHNG_Q

SD_AD_

CHNG_Q

SD_OP_

CHNG_Q

xx00

0000

w

PAL_SW_L

K_CHNG_

CLR

SCM_LOCK

_CHNG_

CLR

SD_AD_CH

NG_CLR

SD_H_

LOCK_

CHNG_CLR

SD_V_LOCK SD_OP_

_CHNG_

CLR

CHNG_CLR

SD_H_

LOCK_

CHNG_MSKB

SD_V_

LOCK_

CHNG_MSKB

SD_OP_

CHNG_MSKB

Interrupt Mask b3

xx00

0000

rw

76

0x4C

PAL_SW_

LK_CHNG_

MSKB

SCM_LOCK

_CHNG_

MSKB

SD_AD_

CHNG_

MSKB

¹To access the interrupt register map, the register access page[1:0] bits in register address 0x0E must be programmed to 01b.

Rev. B | Page 67 of 104

ADV7189B

I²C INTERRUPT REGISTER MAP

The following registers are located in Register Access Page 2.

Table 85. Interrupt (Page 2) Register Map Details

Bit

3

Subaddress Register

Bit Description

7

6

5

4

2

1

0

1

0

1

0

1

Comments

Notes

0x40

Interrupt

Config 1

INTRQ_OP_SEL[1:0].

Interrupt Drive Level Select

Open drain

Drive low when active

Drive high when active

Reserved

Register

Access

Page 2

MPU_STIM_INTRQ[1:0].

Manual Interrupt Set Mode

0

1

Manual interrupt mode disabled

Manual interrupt mode enabled

Not used

Reserved

x

MV_INTRQ_SEL[1:0].

Macrovision Interrupt Select

0

1

0

1

0

1

Reserved

Pseudo sync only

Color stripe only

Pseudo sync or color stripe

3 Xtal periods

INTRQ_DUR_SEL[1:0].

Interrupt Duration Select

0

1

x

0

1

0

1

x

15 Xtal periods

63 Xtal periods

Active until cleared

0x41

0x42

Reserved

x

0

1

Interrupt

Status 1

SD_LOCK_Q

No change

These bits

can be

SD input has caused the

decoder to go from an unlocked

state to a locked state

cleared or

masked in

Register

0x43 and

Register

0x44,

Read-Only

SD_UNLOCK_Q

0

1

No change

SD input has caused the

decoder to go from a locked

state to an unlocked state

Register

Access

Page 2

respectively.

Reserved

x

Reserved

x

Reserved

x

SD_FR_CHNG_Q

0

1

No change

Denotes a change in the free-

run status

MV_PS_CS_Q

0

1

No change

Pseudo sync / color striping

detected. See Reg 0x40

MV_INTRQ_SEL[1:0] for

selection

Reserved

x

0x43

Interrupt

Clear 1

SD_LOCK_CLR

0

1

Do not clear

Clears SD_LOCK_Q bit

Do not clear

SD_UNLOCK_CLR

0

1

Write-Only

Clears SD_UNLOCK_Q bit

Not used

Reserved

0

Register

Access

Page 2

Reserved

0

Not used

Reserved

0

Not used

SD_FR_CHNG_CLR

0

1

Do not clear

Clears SD_FR_CHNG_Q bit

Do not clear

MV_PS_CS_CLR

Reserved

0

1

Clears MV_PS_CS_Q bit

Not used

x

Rev. B | Page 6± of 104

ADV7189B

Bit

3

Subaddress Register

Bit Description

7

6

5

4

2

1

0

1

Comments

Notes

0x44

Interrupt

Mask 1

SD_LOCK_MSKB

Masks SD_LOCK_Q bit

Unmasks SD_LOCK_Q bit

Masks SD_UNLOCK_Q bit

Unmasks SD_UNLOCK_Q bit

Not used

SD_UNLOCK_MSKB

0

1

Read/Write

Register

Reserved

0

Reserved

0

Not used

Register

Access

Page 2

Reserved

0

x

Not used

SD_FR_CHNG_MSKB

0

1

Masks SD_FR_CHNG_Q bit

Unmasks SD_FR_CHNG_Q bit

Masks MV_PS_CS_Q bit

Unmasks MV_PS_CS_Q bit

Not used

MV_PS_CS_MSKB

Reserved

0

1

x

0x45

0x46

Reserved

x

Interrupt

Status 2

CCAPD_Q

0

Closed captioning not detected

in the input video signal

These bits

can be

cleared or

masked by

Register

0x47 and

Register

1

Closed captioning data

detected in the video input

signal

Read-Only

Register

GEMD_Q

0

1

Gemstar data not detected in

the input video signal

Register

Access

Page 2

0x4±,

respectively.

Gemstar data detected in the

input video signal

CGMS_CHNGD_Q

0

1

No change detected in CGMS

data in the input video signal

A change is detected in the

CGMS data in the input video

signal

WSS_CHNGD_Q

0

1

No change detected in WSS

data in the input video signal

A change is detected in the WSS

data in the input video signal

Reserved

x

Not used

Reserved

x

Not used

Reserved

x

Not used

MPU_STIM_INTRQ_Q

0

1

Manual interrupt not set

Manual interrupt set

Do not clear

0x47

Interrupt

Clear 2

CCAPD_CLR

0

1

Clears CCAPD_Q bit

Do not clear

GEMD_CLR

0

1

Write-Only

Clears GEMD_Q bit

Do not clear

CGMS_CHNGD_CLR

WSS_CHNGD_CLR

0

1

Register

Access

Page 2

Clears CGMS_CHNGD_Q bit

Do not clear

0

1

Clears WSS_CHNGD_Q bit

Not used

Reserved

x

Reserved

x

Not used

Reserved

x

Not used

MPU_STIM_INTRQ_CLR

0

1

Do not clear

Clears MPU_STIM_INTRQ_Q bit

Rev. B | Page 69 of 104

ADV7189B

Bit

3

Subaddress Register

Bit Description

7

6

5

4

2

1

0

1

Comments

Notes

0x4±

Interrupt

Mask 2

CCAPD_MSKB

Masks CCAPD_Q bit

Unmasks CCAPD_Q bit

Masks GEMD_Q bit

Unmasks GEMD_Q bit

Masks CGMS_CHNGD_Q bit

Unmasks CGMS_CHNGD_Q bit

Masks WSS_CHNGD_Q bit

Unmasks WSS_CHNGD_Q bit

Not used

GEMD_MSKB

0

1

Read/

Write

CGMS_CHNGD_MSKB

WSS_CHNGD_MSKB

0

1

Register

Access

Page 2

0

1

Reserved

0

Reserved

0

Not used

Reserved

0

Not used

MPU_STIM_INTRQ_MSKB

0

1

Masks MPU_STIM_INTRQ_Q bit

Unmasks MPU_STIM_INTRQ_Q

bit

0x49

Raw Status

3

SD_OP_50Hz

SD 60/50Hz frame rate at

output

0

1

SD 60 Hz signal output

SD 50 Hz signal output

These bits

cannot be

cleared or

masked.

Register

0x4A is used

for this

Read Only

Register

SD_V_LOCK

0

1

SD vertical sync lock not

established

SD vertical sync lock

established

Register

Access

Page 2

purpose.

SD_H_LOCK

0

1

SD horizontal sync lock not

established

SD horizontal sync lock

established

Reserved

x

Not used

SCM_LOCK

SECAM Lock

Reserved

0

1

SECAM lock not established

SECAM lock established

Not used

x

Reserved

x

Not used

Reserved

x

Not used

0x4A

Interrupt

Status 3

SD_OP_CHNG_Q

SD 60/50 Hz frame rate at

input

0

1

No change in SD signal standard These bits

detected at the input

can be

cleared and

masked by

Register

0x4B and

Register

A change in SD signal standard

is detected at the input

Read Only

Register

SD_V_LOCK_CHNG_Q

0

1

No change in SD vertical sync

lock status

SD vertical sync lock status has

changed.

Register

Access

Page 2

0x4C,

respectively.

SD_H_LOCK_CHNG_Q

0

1

No change in SD horizontal sync

lock status

SD horizontal sync lock status

has changed

SD_AD_CHNG_Q

SD autodetect changed

x

No change in AD_RESULT[2:0]

bits in Status Register 1

AD_RESULT[2:0] bits in Status

Register 1 have changed

SCM_LOCK_CHNG_Q

SECAM Lock

0

1

No change in SECAM lock status

SECAM lock status has changed

PAL_SW_LK_CHNG_Q

x

No change in PAL swinging

burst lock status

PAL swinging burst lock status

has changed

Reserved

x

Not used

x

Rev. B | Page 70 of 104

ADV7189B

Bit

3

Subaddress Register

Bit Description

7

6

5

4

2

1

0

1

Comments

Notes

0x4B

Interrupt

Clear 3

SD_OP_CHNG_CLR

Do not clear

Clears SD_OP_CHNG_Q bit

Do not clear

SD_V_LOCK_CHNG_CLR

SD_H_LOCK_CHNG_CLR

SD_AD_CHNG_CLR

0

1

Write Only

Register

Clears SD_V_LOCK_CHNG_Q bit

Do not clear

0

1

Clears SD_H_LOCK_CHNG_Q bit

Do not clear

Register

Access

Page 2

0

1

Clears SD_AD_CHNG_Q bit

Do not clear

SCM_LOCK_CHNG_CLR

PAL_SW_LK_CHNG_CLR

0

1

Clears SCM_LOCK_CHNG_Q bit

Do not clear

0

1

Clears PAL_SW_LK_CHNG_Q bit

Not used

Reserved

x

Reserved

x

Not used

0x4C

Interrupt

Mask 2

SD_OP_CHNG_MSKB

0

1

Masks SD_OP_CHNG_Q bit

Unmasks SD_OP_CHNG_Q bit

Masks SD_V_LOCK_CHNG_Q bit

SD_V_LOCK_CHNG_ MSKB

SD_H_LOCK_CHNG_ MSKB

0

1

Read /

Write

Register

Unmasks SD_V_LOCK_CHNG_Q

bit

0

1

Masks SD_H_LOCK_CHNG_Q bit

Unmasks SD_H_LOCK_CHNG_Q

bit

Register

Access

Page 2

SD_AD_CHNG_ MSKB

0

1

Masks SD_AD_CHNG_Q bit

Unmasks SD_AD_CHNG_Q bit

Masks SCM_LOCK_CHNG_Q bit

SCM_LOCK_CHNG_ MSKB

0

1

Unmasks SCM_LOCK_CHNG_Q

bit

PAL_SW_LK_CHNG_ MSKB

0

1

Masks PAL_SW_LK_CHNG_Q bit

Unmasks PAL_SW_LK_CHNG_Q

bit

Reserved

x

Not used

x

Rev. B | Page 71 of 104

ADV7189B

The following registers are located in the Common I²C Map and Register Access Page 1.

Table 86. Common and Normal (Page 1) Register Map Details

Bits

Subaddress

Register

Bit Description

7

6

5

4

3

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Comments

Notes

0x00

Input

Control

INSEL[3:0]. The INSEL bits allow the

user to select an input channel as

well as the input format.

CVBS in on AIN1

CVBS in on AIN2

CVBS in on AIN3

CVBS in on AIN4

CVBS in on AIN5

CVBS in on AIN6

Y on AIN1, C on AIN4

Y on AIN2, C on AIN5

Y on AIN3, C on AIN6

Composite

S-Video

YPbPr

Y on AIN1, Pb on AIN4, Pr

on AIN5

1

0

1

0

Y on AIN2, Pb on AIN3, Pr

on AIN6

1

0

1

0

1

0

1

0

1

CVBS in on AIN7

CVBS in on AIN±

CVBS in on AIN9

CVBS in on AIN10

CVBS in on AIN11

Composite

VID_SEL[3:0]. The VID_SEL bits

allow the user to select the input

video standard.

0

1

0

1

0

1

Auto-detect PAL (BGHID),

NTSC J (without pedestal),

SECAM

Auto-detect PAL (BGHID),

NTSC M (with pedestal),

SECAM

Auto-detect PAL (N), NTSC

J, SECAM (PAL with

pedestal)

Auto-detect PAL (N), NTSC

M, SECAM (PAL and NTSC

with pedestal)

0

1

0

1

0

1

0

1

0

1

NTSC(J)

NTSC(M)

PAL 60

NTSC 4.43

PAL BGHID

PAL N (BGHID without

pedestal)

1

0

1

0

1

0

1

0

1

0

1

PAL M (without pedestal)

PAL M

PAL combination N

SECAM (with pedestal)

Rev. B | Page 72 of 104

ADV7189B

Bits

Subaddress

Register

Bit Description

Reserved

7

6

5

4

3

2

1

0

Comments

Notes

0x01

Video

0

Set to default

Selection

ENVSPROC

0

1

Disable Vsync processor

Enable Vsync processor

Set to default

Reserved

BETACAM

0

1

Standard video input

Betacam input enable

Disable Hsync processor

Enable Hsync processor

Set to default

ENHSPLL

0

1

Reserved

1

0x03

Output

Control

SD_DUP_AV. Duplicates the AV

codes from the luma into the

chroma path.

0

1

AV codes to suit ±-bit

interleaved data output

AV codes duplicated (for

16-bit interfaces)

Reserved

0

Set as default

OF_SEL[3:0]. Allows the user to

choose from a set of output

formats.

0

10-bit @ LLC1 4:2:2

ITU-R BT.656

0

1

0

1

20-bit @ LLC1 4:2:2

16-bit @ LLC1 4:2:2

±-bit @ LLC1 4:2:2

ITU-R BT.656

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Not used

Output pins enabled

TOD. Three-State Output Drivers.

This bit allows the user to three-

state the output drivers: P[19:0], HS,

VS, FIELD, and SFL.

0

1


型号：	EVAL-ADV7189BEB
厂家：	ADI
描述：	Multiformat SDTV Video Decoder 多格式SDTV视频解码器解码器电视
文件：	总104页 (文件大小：870K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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