EVAL-ADV7281MEBZ [ADI]
10-Bit, 4 Oversampled SDTV Video Decoder with Differential Inputs; 10位,4个过采样SDTV视频解码器,差分输入型号: | EVAL-ADV7281MEBZ |
厂家: | ADI |
描述: | 10-Bit, 4 Oversampled SDTV Video Decoder with Differential Inputs |
文件: | 总32页 (文件大小:591K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
10-Bit, 4× Oversampled SDTV Video
Decoder with Differential Inputs
Data Sheet
ADV7281
FEATURES
GENERAL DESCRIPTION
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit analog-to-digital converter (ADC), 4× oversampling
per channel for CVBS, Y/C, and YPrPb modes
Analog video input channels with on-chip antialiasing filter
ADV7281: up to 4 input channels
ADV7281-M: up to 6 input channels
ADV7281-MA: up to 8 input channels
Video input support for CVBS (composite), Y/C (S-Video),
and YPrPb (component)
Fully differential, pseudo differential, and single-ended
CVBS video input support
The ADV7281/ADV7281-M/ADV7281-MA are versatile
one-chip, multiformat video decoders. The ADV7281/
ADV7281-M/ADV7281-MA automatically detect standard
analog baseband video signals compatible with worldwide
NTSC, PAL, and SECAM standards in the form of composite,
S-Video, and component video.
The ADV7281 converts the analog video signals into a YCrCb
4:2:2 video data stream that is compatible with the 8-bit ITU-R
BT.656 interface standard.
The ADV7281-M/ADV7281-MA convert the analog video
signals into an 8-bit YCrCb 4:2:2 video data stream that is
output over a mobile industry processor interface (MIPI®)
CSI-2 interface.
NTSC/PAL/SECAM autodetection
Short-to-battery (STB) diagnostics on 2 video inputs
(ADV7281 and ADV7281-M only)
Up to 4 V common-mode input range solution
Excellent common-mode noise rejection capabilities
5-line adaptive 2D comb filter and CTI video enhancement
Adaptive Digital Line Length Tracking (ADLLT), signal
processing, and enhanced FIFO management provide
mini-time base correction (TBC) functionality
Integrated automatic gain control (AGC) with adaptive
peak white mode
The analog video inputs of the ADV7281/ADV7281-M/
ADV7281-MA accept single-ended, pseudo differential, and
fully differential signals. The ADV7281 provides four analog
inputs and two STB diagnostic pins. The ADV7281-M provides
six analog inputs, two STB diagnostic pins, and three general-
purpose outputs. The ADV7281-MA provides eight analog
inputs and three general-purpose outputs.
The ADV7281/ADV7281-M/ADV7281-MA are programmed
via a 2-wire, serial bidirectional port (I2C compatible) and are
fabricated in a 1.8 V CMOS process. The LFCSP package option
makes these decoders ideal for space-constrained portable
applications.
Fast switching capability
Adaptive contrast enhancement (ACE)
Down dither (8-bit to 6-bit)
Rovi (Macrovision) copy protection detection
MIPI CSI-2 output interface (ADV7281-M and ADV7281-MA)
8-bit ITU-R BT.656 YCrCb 4:2:2 output (ADV7281)
Full featured vertical blanking interval (VBI) data slicer
Power-down mode available
2-wire, I2C-compatible serial interface
Qualified for automotive applications
−40°C to +105°C temperature grade
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
APPLICATIONS
Smartphone/multimedia handsets
Automotive infotainment
DVRs for video security
Media players
Rev. A
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Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
ADV7281
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Networks ............................................................................... 17
Single-Ended Input Network.................................................... 17
Differential Input Network ....................................................... 17
Short-to-Battery Protection...................................................... 17
Input Configuration....................................................................... 18
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagrams............................................................. 3
Specifications..................................................................................... 4
Electrical Specifications............................................................... 4
Video Specifications..................................................................... 5
Analog Specifications................................................................... 6
Clock and I2C Timing Specifications......................................... 6
Short-to-Battery (STB) Diagnostics (ADV7281/ADV7281-M
Only) ................................................................................................ 19
Programming the STB Diagnostic Function.......................... 19
Adaptive Contrast Enhancement (ACE)..................................... 21
ITU-R BT.656 Tx Configuration (ADV7281 Only) .................. 22
MIPI CSI-2 Output ........................................................................ 23
I2C Port Description....................................................................... 24
Register Maps.............................................................................. 25
PCB Layout Recommendations.................................................... 27
Analog Interface Inputs............................................................. 27
Power Supply Decoupling ......................................................... 27
VREFN and VREFP Pins .......................................................... 27
Digital Outputs ........................................................................... 27
Exposed Metal Pad..................................................................... 28
Digital Inputs .............................................................................. 28
MIPI Video Output Specifications (ADV7281-M and
ADV7281-MA Only)................................................................... 7
Pixel Port Timing Specifications (ADV7281 Only)................. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
Reflow Solder .............................................................................. 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Theory of Operation ...................................................................... 14
Analog Front End (AFE)........................................................... 14
Standard Definition Processor (SDP)...................................... 15
Power Supply Sequencing.............................................................. 16
Optimal Power-Up Sequence.................................................... 16
Simplified Power-Up Sequence ................................................ 16
Power-Down Sequence.............................................................. 16
DVDDIO Supply Voltage ................................................................ 16
MIPI Outputs (D0P, D0N, CLKP, CLKN) (ADV7281-M/
ADV7281-MA only)................................................................... 28
Typical Circuit Connections......................................................... 29
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
Automotive Products................................................................. 32
REVISION HISTORY
11/13—Rev. 0 to Rev. A
Changes to Programming the STB Diagnostic Function
Section.............................................................................................. 19
Added ITU-R BT.656 Tx Configuration (ADV7281 Only)
Section.............................................................................................. 22
Changes to Register Maps Section ............................................... 25
Changes to Power Supply Decoupling Section and Digital
Outputs Section .............................................................................. 27
Changes to Typical Circuit Connections Section ...................... 29
Updated Outline Dimensions....................................................... 32
Changes to Ordering Guide.......................................................... 32
Changes to Features and General Description Sections.............. 1
Added Figure 1; Renumbered Sequentially .................................. 3
Changes to Table 1............................................................................ 4
Added Pixel Port Timing Specifications (ADV7281 Only)
Section................................................................................................ 9
Added Endnote 1; Table 7 ............................................................. 10
Added Figure 7 and Table 9........................................................... 11
Changes to Theory of Operation Section.................................... 14
Changes to Optimal Power-Up Sequence Section and DVDDIO
Supply Voltage Section................................................................... 16
Changes to Table 13........................................................................ 18
8/13—Revision 0: Initial Version
Rev. A | Page 2 of 32
Data Sheet
ADV7281
FUNCTIONAL BLOCK DIAGRAMS
ADV7281
CLOCK PROCESSING BLOCK
XTALP
XTALN
LCC
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
AA
FILTER
A
A
1
2
IN
IN
ACE
2D COMB
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
8-BIT
PIXEL DATA
P0 TO P7
+
DOWN
DITHER
FILTER
SHA
–
ADC
VBI SLICER
AA
FILTER
A
A
3
4
IN
IN
COLOR
DEMOD
AA
FILTER
2
INTRQ
DIAGNOSTICS
REFERENCE
I C/CONTROL
DIAG1
DIAG2
SCLK SDATA ALSB RESET PWRDWN
Figure 1. ADV7281 Functional Block Diagram
CLKP
CLKN
D0P
ADV7281-M
CLOCK PROCESSING BLOCK
MIPI
Tx
XTALP
XTALN
PLL
ADLLT PROCESSING
D0N
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
AA
FILTER
A
A
1
2
IN
IN
ACE
2D COMB
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
+
DOWN
DITHER
FILTER
A
A
3
4
IN
IN
SHA
–
ADC
VBI SLICER
AA
FILTER
GPO0
GPO1
GPO2
A
A
5
6
IN
IN
COLOR
DEMOD
AA
FILTER
2
INTRQ
DIAGNOSTICS
REFERENCE
I C/CONTROL
DIAG1
DIAG2
SCLK SDATA ALSB RESET PWRDWN
Figure 2. ADV7281-M Functional Block Diagram
CLKP
CLKN
D0P
ADV7281-MA
CLOCK PROCESSING BLOCK
MIPI
Tx
XTALP
XTALN
PLL
ADLLT PROCESSING
D0N
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
AA
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
IN
IN
IN
IN
IN
IN
IN
IN
FILTER
ACE
2D COMB
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
FILTER
+
DOWN
DITHER
SHA
–
ADC
VBI SLICER
AA
FILTER
GPO0
GPO1
GPO2
COLOR
DEMOD
AA
FILTER
2
INTRQ
REFERENCE
I C/CONTROL
SCLK SDATA ALSB RESET PWRDWN
Figure 3. ADV7281-MA Functional Block Diagram
Rev. A | Page 3 of 32
ADV7281
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
STATIC PERFORMANCE
ADC Resolution
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
N
INL
DNL
10
Bits
LSB
LSB
CVBS mode
CVBS mode
2
0.6
Input High Voltage
VIH
VIL
IIN
DVDDIO = 3.3 V
DVDDIO = 1.8 V, ADV7281 only
DVDDIO = 3.3 V
DVDDIO = 1.8 V, ADV7281 only
RESET pin
2
1.2
V
V
V
V
µA
µA
µA
pF
Input Low Voltage
0.8
0.4
+10
+15
+50
10
Input Leakage Current
−10
−10
−10
SDATA, SCLK pins
PWRDWN, ALSB pins
Input Capacitance
CRYSTAL INPUT
CIN
Input High Voltage
Input Low Voltage
DIGITAL OUTPUTS
Output High Voltage
VIH
VIL
XTALN pin
XTALN pin
1.2
V
V
0.4
VOH
DVDDIO = 3.3 V, ISOURCE = 0.4 mA
DVDDIO = 1.8 V, ISOURCE = 0.4 mA,
ADV7281 only
2.4
1.4
V
V
Output Low Voltage
VOL
DVDDIO = 3.3 V, ISINK = 3.2 mA
DVDDIO = 1.8 V, ISINK = 1.6 mA,
ADV7281 only
0.4
0.2
V
V
High Impedance Leakage Current
Output Capacitance
ILEAK
COUT
10
20
µA
pF
POWER REQUIREMENTS1, 2
Digital I/O Power Supply
DVDDIO
ADV7281-M/ADV7281-MA
ADV7281
2.97
1.62
1.71
1.71
1.71
1.71
3.3
3.3
1.8
1.8
1.8
1.8
1.5
5
3.63
3.63
1.89
1.89
1.89
1.89
V
V
V
V
V
V
mA
mA
mA
mA
PLL Power Supply
PVDD
Analog Power Supply
Digital Power Supply
MIPI Tx Power Supply
Digital I/O Supply Current
AVDD
DVDD
MVDD
IDVDDIO
ADV7281-M/ADV7281-MA only
ADV7281-M/ADV7281-MA
ADV7281
PLL Supply Current
IPVDD
IMVDD
IAVDD
12
14
MIPI Tx Supply Current
Analog Supply Current
Single-Ended CVBS Input
Differential CVBS Input
ADV7281-M/ADV7281-MA only
35
69
mA
mA
Fully differential and pseudo
differential CVBS
Y/C Input
YPrPb Input
60
75
mA
mA
Digital Supply Current
Single-Ended CVBS Input
Differential CVBS Input
IDVDD
60
60
mA
mA
Fully differential and pseudo
differential CVBS
Y/C Input
YPrPb Input
60
60
mA
mA
Rev. A | Page 4 of 32
Data Sheet
ADV7281
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER-DOWN CURRENTS1
Digital I/O Supply Power-Down
Current
IDVDDIO_PD
DVDDIO = 3.3 V, ADV7281-M/
ADV7281-MA
73
µA
DVDDIO = 3.3 V, ADV7281
84
46
0.2
420
4.5
1
µA
µA
µA
µA
µA
mW
PLL Supply Power-Down Current
Analog Supply Power-Down Current
Digital Supply Power-Down Current
MIPI Tx Supply Power-Down Current
IPVDD_PD
IAVDD_PD
IDVDD_PD
IMVDD_PD
ADV7281-M and ADV7281-MA only
Total Power Dissipation
in Power-Down Mode
1 Guaranteed by characterization.
2 Typical current consumption values are measured with nominal voltage supply levels and an SMPTE bar test pattern.
VIDEO SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
NONLINEAR SPECIFICATIONS1
Differential Phase
Differential Gain
Luma Nonlinearity
DP
DG
LNL
CVBS input, modulated 5-step
CVBS input, modulated 5-step
CVBS input, 5-step
0.9
0.5
2.0
Degrees
%
%
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted
SNR
Luma ramp
Luma flat field
57.1
58
60
dB
dB
dB
dB
Analog Front-End Crosstalk
Common-Mode Rejection Ratio2
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
CMRR
73
−5
40
+5
70
%
Hz
fSC Subcarrier Lock Range
Color Lock-In Time
Synchronization Depth Range
Color Burst Range
1.3
60
kHz
Lines
%
20
5
200
200
%
Vertical Lock Time
Autodetection Switch Speed3
Fast Switch Speed4
2
100
100
Fields
Lines
ms
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
CVBS, 1 V input
1
1
%
%
1 These specifications apply for all CVBS input types (NTSC, PAL, and SECAM), as well as for single-ended and differential CVBS inputs.
2 The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Networks section). The CMRR measurement
was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
3 Autodetection switch speed is the time required for the ADV7281/ADV7281-M/ADV7281-MA to detect which video format is present at its input, for example, PAL I or
NTSC M.
4 Fast switch speed is the time required for the ADV7281/ADV7281-M/ADV7281-MA to switch from one analog input (single-ended or differential) to another, for
example, switching from AIN1 to AIN2.
Rev. A | Page 5 of 32
ADV7281
Data Sheet
ANALOG SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7281-M/ADV7281-MA.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
0.1
10
0.4
0.4
10
µF
Clamps switched off
MΩ
mA
mA
µA
10
µA
CLOCK AND I2C TIMING SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7281-M/ADV7281-MA.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
28.63636
MHz
ppm
50
I2C PORT
SCLK Frequency
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Times
SCLK and SDATA Fall Times
Setup Time (Stop Condition)
RESET INPUT
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
RESET Pulse Width
5
ms
t5
t3
t3
SDATA
SCLK
t1
t6
t4
t7
t8
t2
Figure 4. I2C Timing Diagram
Rev. A | Page 6 of 32
Data Sheet
ADV7281
MIPI VIDEO OUTPUT SPECIFICATIONS (ADV7281-M AND ADV7281-MA ONLY)
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
The CSI-2 clock lane of the ADV7281-M/ADV7281-MA remains in high speed (HS) mode even when the data lane enters low power (LP)
mode. For this reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated,
all high speed measurements were performed with the ADV7281-M/ADV7281-MA operating in interlaced mode and with a nominal
216 Mbps output data rate. Specifications guaranteed by characterization.
Table 5.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
UNIT INTERVAL
UI
Interlaced Output
4.63
ns
DATA LANE LP TX DC SPECIFICATIONS1
Thevenin Output High Level
Thevenin Output Low Level
DATA LANE LP TX AC SPECIFICATIONS1
Rise Time, 15% to 85%
VOH
VOL
1.1
−50
1.2
0
1.3
+50
V
mV
25
25
35
ns
ns
ns
Fall Time, 85% to 15%
Rise Time, 30% to 85%
Data Lane LP Slew Rate vs. CLOAD
Maximum Slew Rate over Entire
Vertical Edge Region
Rising edge
Falling edge
150
150
mV/ns
mV/ns
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV
400 mV ≤ VOUT ≤ 700 mV
700 mV ≤ VOUT ≤ 930 mV
Pulse Width of LP Exclusive-OR Clock
Falling edge
Rising edge
Rising edge
First clock pulse after stop state or
last pulse before stop state
30
30
>0
40
mV/ns
mV/ns
mV/ns
ns
All other clock pulses
20
90
ns
ns
Period of LP Exclusive-OR Clock
CLOCK LANE LP TX DC SPECIFICATIONS1
Thevenin Output High Level
Thevenin Output Low Level
CLOCK LANE LP TX AC SPECIFICATIONS1
Rise Time, 15% to 85%
VOH
VOL
1.1
−50
1.2
0
1.3
+50
V
mV
25
25
ns
ns
Fall Time, 85% to 15%
Clock Lane LP Slew Rate
Maximum Slew Rate over Entire
Vertical Edge Region
Rising edge
Falling edge
150
150
mV/ns
mV/ns
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV
400 mV ≤ VOUT ≤ 700 mV
700 mV ≤ VOUT ≤ 930 mV
Falling edge
Rising edge
Rising edge
See Figure 5
30
30
>0
mV/ns
mV/ns
mV/ns
DATA LANE HS TX SIGNALING
REQUIREMENTS
Low Power to High Speed Transition
Stage
t9
Time that the D0P pin is at VOL and
the D0N pin is at VOH
Time that the D0P and D0N pins
are at VOL
50
ns
ns
t10
40 + (4 × UI)
85 + (6 × UI)
t11
|V1|
t10 plus the HS-zero period
145 + (10 × UI)
140
ns
mV p-p
mV
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
Static Common-Mode Voltage Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz
200
200
270
10
360
250
5
mV
mV
mV
150
25
15
mV
mV
Above 450 MHz
Rev. A | Page 7 of 32
ADV7281
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
Rise Time, 20% to 80%
Fall Time, 80% to 20%
High Speed to Low Power Transition
Stage
0.15
0.15
0.3 × UI
0.3 × UI
ns
ns
ns
t12
Time that the ADV7281-M/
ADV7281-MA drive the flipped last
data bit after sending the last
payload data bit of an HS
transmission burst
60 + (4 × UI)
t13
t14
Post-end-of-transmission rise time
(30% to 85%)
Time from start of t12 to start of low
power state following an HS
transmission burst
35
ns
105 + (12 × UI) ns
t15
Time that a low power state is
transmitted after an HS trans-
mission burst
100
ns
CLOCK LANE HS TX SIGNALING
REQUIREMENTS
See Figure 5
Low Power to High Speed Transition
Stage2
Time that the CLKP pin is at VOL and
the CLKN pin is at VOH
Time that the CLKP and CLKN pins
are at VOL
50
38
ns
ns
95
Clock HS-zero period
300
140
500
200
ns
mV p-p
mV
High Speed Differential Voltage Swing
Differential Voltage Mismatch
Single-Ended Output High Voltages
Static Common-Mode Voltage Level
Static Common-Mode Voltage Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz
|V2|
270
10
360
250
5
mV
mV
mV
150
200
25
15
mV
mV
ns
Above 450 MHz
Rise Time, 20% to 80%
Fall Time, 80% to 20%
0.15
0.15
0.3 × UI
0.3 × UI
ns
HS TX CLOCK TO DATA LANE TIMING
REQUIREMENTS
Data to Clock Skew
0.35 × UI
0.65 × UI
ns
1 These measurements were performed with CLOAD = 50 pF.
2 The clock lane remains in high speed mode throughout normal operation. These results apply only to the ADV7281-M/ADV7281-MA during startup.
|V |
2
CLKP/CLKN
t9
t10
t11
D0P/D0N
V
OH
|V |
1
V
OL
t13
TRANSMIT FIRST
DATA BIT
t14
t12
t15
LOW POWER
TO
HIGH SPEED
TRANSITION
HS-ZERO
START OF
TRANSMISSION
SEQUENCE
HIGH SPEED DATA
TRANSMISSION
HS-TRAIL
HIGH SPEED
TO
LOW POWER
TRANSITION
Figure 5. ADV7281-M/ADV7281-MA Output Timing Diagram (Conforms with MIPI CSI-2 Specification)
Rev. A | Page 8 of 32
Data Sheet
ADV7281
PIXEL PORT TIMING SPECIFICATIONS (ADV7281 ONLY)
AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 6.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
t16:t17
45:55
55:45
% duty cycle
Data Output Transitional Time t18
Negative clock edge to start of valid data
(tSETUP = t17 − t18)
End of valid data to negative clock edge
(tHOLD = t16 − t19)
3.8
6.9
ns
ns
t19
t16
t17
OUTPUT LLC
t18
t19
OUTPUTS P0 TO P7
Figure 6. ADV7281 Pixel Port and Control Output Timing Diagram
Rev. A | Page 9 of 32
ADV7281
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter
Rating
The thermal resistance values in Table 8 are specified for the
device soldered onto a 4-layer printed circuit board (PCB) with
a common ground plane and with the exposed pad of the device
connected to DGND. The values in Table 8 are maximum values.
AVDD to DGND
DVDD to DGND
PVDD to DGND
MVDD to DGND1
DVDDIO to DGND
PVDD to DVDD
2.2 V
2.2 V
2.2 V
2.2 V
Table 8. Thermal Resistance for the 32-Lead LFCSP
4 V
Thermal Characteristic
Symbol Value
Unit
−0.9 V to +0.9 V
−0.9 V to +0.9 V
−0.9 V to +0.9 V
DGND − 0.3 V to DVDDIO + 0.3 V
DGND − 0.3 V to DVDDIO + 0.3 V
Ground − 0.3 V to AVDD + 0.3 V
1
Junction-to-Ambient Thermal θJA
Resistance (Still Air)
32.5
°C/W
MVDD to DVDD
AVDD to DVDD
Junction-to-Case Thermal
Resistance
θJC
2.3
°C/W
Digital Inputs Voltage
Digital Outputs Voltage
Analog Inputs to Ground
Maximum Junction Temperature 140°C
(TJ max)
Storage Temperature Range
Infrared Reflow Soldering
(20 sec)
REFLOW SOLDER
The ADV7281/ADV7281-M/ADV7281-MA are Pb-free,
environmentally friendly products. They are manufactured using
the most up-to-date materials and processes. The coating on the
leads of each device is 100% pure Sn electroplate. The devices
are suitable for Pb-free applications and can withstand surface-
mount soldering at up to 255°C ( 5°C).
−65°C to +150°C
260°C
1 MVDD applies to the ADV7281-M and ADV7281-MA only.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
In addition, the ADV7281/ADV7281-M/ADV7281-MA are
backward-compatible with conventional SnPb soldering
processes. This means that the electroplated Sn coating can
be soldered with Sn/Pb solder pastes at conventional reflow
temperatures of 220°C to 235°C.
ESD CAUTION
These devices are high performance integrated circuits with
an ESD rating of <2 kV, and they are ESD sensitive. Proper
precautions must be taken for handling and assembly.
Rev. A | Page 10 of 32
Data Sheet
ADV7281
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DGND
1
2
3
4
5
6
7
8
24
23
A 3
IN
DIAG2
D
VDDIO
D
22 DIAG1
VDD
ADV7281
DGND
P7
21
20
19
18
17
A
VDD
TOP VIEW
VREFN
VREFP
(Not to Scale)
P6
P5
P4
A
A
2
1
IN
IN
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 7. Pin Configuration, ADV7281
Table 9. Pin Function Descriptions, ADV7281
Pin No.
Mnemonic
Type
Description
1, 4
2
3, 13
5 to 12
14
DGND
DVDDIO
DVDD
P7 to P0
XTALP
Ground
Power
Power
Output
Output
Ground for Digital Supply.
Digital I/O Power Supply (1.8 V or 3.3 V).
Digital Power Supply (1.8 V).
Video Pixel Output Ports.
Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7281. The crystal used
with the ADV7281 must be a fundamental crystal.
15
16
17, 18,
24, 25
XTALN
Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7281must be
a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to
clock the ADV7281, the output of the oscillator is fed into the XTALN pin.
PLL Power Supply (1.8 V).
Analog Video Input Channels.
PVDD
AIN1 to AIN4
Power
Input
19
20
21
22
23
26
VREFP
VREFN
AVDD
DIAG1
DIAG2
INTRQ
Output
Output
Power
Input
Input
Output
Internal Voltage Reference Output.
Internal Voltage Reference Output.
Analog Power Supply (1.8 V).
Diagnostic Input 1.
Diagnostic Input 2.
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
27
28
RESET
ALSB
Input
Input
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7281 circuitry.
This pin selects the I2C write address for the ADV7281. When ALSB is set to Logic 0, the
write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
I2C Port Serial Data Input/Output.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Power-Down Pin. A logic low on this pin places the ADV7281 in power-down mode.
29
30
31
32
SDATA
SCLK
PWRDWN
LLC
Input/output
Input
Input
Output
Line-Locked Output Clock for Output Pixel Data. The clock output is nominally 27 MHz, but
it increases or decreases according to the video line length.
EPAD (EP)
Exposed Pad. The exposed pad must be connected to DGND.
Rev. A | Page 11 of 32
ADV7281
Data Sheet
DGND
1
2
3
4
5
6
7
8
24
23
A
A
4
3
IN
D
VDDIO
IN
D
22 DIAG1
VDD
ADV7281-M
DGND
INTRQ
GPO2
GPO1
GPO0
21
20
19
18
17
A
VDD
TOP VIEW
VREFN
VREFP
A
A
(Not to Scale)
2
1
IN
IN
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 8. Pin Configuration, ADV7281-M
Table 10. Pin Function Descriptions, ADV7281-M
Pin No.
Mnemonic
DGND
DVDDIO
DVDD
INTRQ
Type
Description
1, 4
2
3
Ground
Power
Power
Output
Ground for Digital Supply.
Digital I/O Power Supply (3.3 V).
Digital Power Supply (1.8 V).
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
5
6 to 8
GPO2 to
GPO0
Output
General-Purpose Outputs. These pins can be configured via I2C to allow control of external
devices.
9
D0P
D0N
CLKP
CLKN
MVDD
XTALP
Output
Output
Output
Output
Power
Positive MIPI Differential Data Output.
Negative MIPI Differential Data Output.
Positive MIPI Differential Clock Output.
Negative MIPI Differential Clock Output.
MIPI Digital Power Supply (1.8 V).
Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7281-M. The crystal used
with the ADV7281-M must be a fundamental crystal.
10
11
12
13
14
Output
15
XTALN
Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7281-M must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to
clock the ADV7281-M, the output of the oscillator is fed into the XTALN pin.
16
PVDD
AIN1 to AIN6
Power
Input
PLL Power Supply (1.8 V).
Analog Video Input Channels.
17, 18, 23,
24, 26, 27
19
20
21
22
25
28
VREFP
VREFN
AVDD
DIAG1
DIAG2
RESET
Output
Output
Power
Input
Input
Input
Internal Voltage Reference Output.
Internal Voltage Reference Output.
Analog Power Supply (1.8 V).
Diagnostic Input 1.
Diagnostic Input 2.
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7281-M circuitry.
29
ALSB
Input
This pin selects the I2C write address for the ADV7281-M. When ALSB is set to Logic 0, the
write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
30
31
32
SDATA
SCLK
PWRDWN
EPAD (EP)
Input/output
Input
Input
I2C Port Serial Data Input/Output.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Power-Down Pin. A logic low on this pin places the ADV7281-M in power-down mode.
Exposed Pad. The exposed pad must be connected to DGND.
Rev. A | Page 12 of 32
Data Sheet
ADV7281
DGND
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
A
A
A
A
5
4
3
IN
IN
IN
D
VDDIO
D
VDD
ADV7281-MA
DGND
INTRQ
GPO2
GPO1
GPO0
VDD
TOP VIEW
VREFN
VREFP
(Not to Scale)
A
A
2
1
IN
IN
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 9. Pin Configuration, ADV7281-MA
Table 11. Pin Function Descriptions, ADV7281-MA
Pin No.
Mnemonic
DGND
DVDDIO
DVDD
INTRQ
Type
Description
1, 4
2
3
Ground
Power
Power
Output
Ground for Digital Supply.
Digital I/O Power Supply (3.3 V).
Digital Power Supply (1.8 V).
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
5
6 to 8
GPO2 to
GPO0
Output
General-Purpose Outputs. These pins can be configured via I2C to allow control of external
devices.
9
D0P
D0N
CLKP
CLKN
MVDD
XTALP
Output
Output
Output
Output
Power
Positive MIPI Differential Data Output.
Negative MIPI Differential Data Output.
Positive MIPI Differential Clock Output.
Negative MIPI Differential Clock Output.
MIPI Digital Power Supply (1.8 V).
Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7281-MA. The crystal
used with the ADV7281-MA must be a fundamental crystal.
10
11
12
13
14
Output
15
16
XTALN
Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7281-MA
must be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source
is used to clock the ADV7281-MA, the output of the oscillator is fed into the XTALN pin.
PLL Power Supply (1.8 V).
Analog Video Input Channels.
PVDD
AIN1 to AIN8
Power
Input
17, 18, 22,
23, 24, 25,
26, 27
19
20
21
28
VREFP
VREFN
AVDD
Output
Output
Power
Input
Internal Voltage Reference Output.
Internal Voltage Reference Output.
Analog Power Supply (1.8 V).
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7281-MA circuitry.
RESET
29
ALSB
Input
This pin selects the I2C write address for the ADV7281-MA. When ALSB is set to Logic 0, the
write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
30
31
32
SDATA
SCLK
PWRDWN
EPAD (EP)
Input/output
Input
Input
I2C Port Serial Data Input/Output.
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Power-Down Pin. A logic low on this pin places the ADV7281-MA in power-down mode.
Exposed Pad. The exposed pad must be connected to DGND.
Rev. A | Page 13 of 32
ADV7281
Data Sheet
THEORY OF OPERATION
The ADV7281/ADV7281-M/ADV7281-MA are versatile one-
chip, multiformat video decoders. The ADV7281/ADV7281-M/
ADV7281-MA automatically detect standard analog baseband
video signals compatible with worldwide NTSC, PAL, and
SECAM standards in the form of composite, S-Video, and
component video.
ANALOG FRONT END (AFE)
The analog front end (AFE) of the ADV7281/ADV7281-M/
ADV7281-MA comprises a single high speed, 10-bit ADC
that digitizes the analog video signal before applying it to the
standard definition processor (SDP). The AFE uses differential
channels to the ADC to ensure high performance in mixed-
signal applications and to enable differential CVBS inputs
to be connected directly to the ADV7281/ADV7281-M/
ADV7281-MA.
The ADV7281 converts the analog video signal into an 8-bit
YCrCb 4:2:2 video data stream that is compatible with the 8-bit
ITU-R BT.656 interface standard.
The ADV7281-M/ADV7281-MA convert the analog video
signals into an 8-bit YCrCb 4:2:2 video data stream that is
output over a MIPI CSI-2 interface.
The AFE also includes an input mux that enables multiple
video signals to be applied to the ADV7281/ADV7281-M/
ADV7281-MA. The input mux allows
The MIPI CSI-2 output interface connects to a wide range of
video processors and FPGAs. The accurate 10-bit analog-to-digital
conversion provides professional quality video performance for
consumer applications with true 8-bit data resolution.
•
•
•
Up to four composite video signals to be applied to the
ADV7281
Up to six composite video signals to be applied to the
ADV7281-M
Up to eight composite video signals to be applied to the
ADV7281-MA.
The analog video inputs of the ADV7281/ADV7281-M/
ADV7281-MA accept single-ended, pseudo differential, and
fully differential composite video signals, as well as S-Video and
YPrPb video signals, supporting a wide range of consumer and
automotive video sources.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see the Input Networks section). Fine clamping of
the video signal is performed downstream by digital fine clamp-
ing within the ADV7281/ADV7281-M/ADV7281-MA.
In differential CVBS mode, the ADV7281/ADV7281-M/
ADV7281-MA, along with an external resistor divider, provide a
common-mode input range of up to 4 V, enabling the removal
of large signal, common-mode transients present on the video
lines.
Table 12 lists the three ADC clock rates that are determined by
the video input format to be processed. These clock rates ensure
4× oversampling per channel for CVBS, Y/C, and YPrPb modes.
The automatic gain control (AGC) and clamp restore circuitry
allows an input video signal peak-to-peak range of 0 V to 1.0 V at
the analog video input pins of the ADV7281/ADV7281-M/
ADV7281-MA. Alternatively, the AGC and clamp restore circuitry
can be bypassed for manual settings.
Table 12. ADC Clock Rates
Oversampling
Rate per Channel
Input Format
CVBS
Y/C (S-Video)
YPrPb
ADC Clock Rate (MHz)1
AC coupling of the input video signals provides short-to-battery
(STB) protection. In the ADV7281 and ADV7281-M, STB
diagnostics can be performed on two input video signals.
57.27
114
172
4×
4×
4×
The ADV7281/ADV7281-M/ADV7281-MA support a number
of other functions, including 8-bit to 6-bit down dither mode
and adaptive contrast enhancement (ACE).
1 Based on a 28.63636 MHz crystal between the XTALP and XTALN pins.
The fully differential AFE of the ADV7281/ADV7281-M/
ADV7281-MA provides inherent small and large signal noise
rejection, improved electromagnetic interference (EMI)
protection, and the ability to absorb ground bounce. Support is
provided for both true differential and pseudo differential
signals.
The ADV7281/ADV7281-M/ADV7281-MA are programmed
via a 2-wire, serial bidirectional port (I2C compatible) and are
fabricated in a 1.8 V CMOS process. The monolithic CMOS
construction of the ADV7281/ADV7281-M/ADV7281-MA
ensures greater functionality with lower power dissipation. The
LFCSP package option makes these decoders ideal for space-
constrained portable applications.
Rev. A | Page 14 of 32
Data Sheet
ADV7281
as VCRs. ADLLT enables the ADV7281/ADV7281-M/
STANDARD DEFINITION PROCESSOR (SDP)
ADV7281-MA to track and decode poor quality video sources
such as VCRs and noisy sources from tuner outputs and cam-
corders. The ADV7281/ADV7281-M/ ADV7281-MA contain a
chroma transient improvement (CTI) processor that sharpens
the edge rate of chroma transitions, resulting in sharper vertical
transitions.
The ADV7281/ADV7281-M/ADV7281-MA are capable
of decoding a large selection of baseband video signals in
composite (both single-ended and differential), S-Video, and
component formats. The video standards supported by the
video processor include
•
PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,
PAL Nc, PAL 60
Adaptive contrast enhancement (ACE) offers improved visual
detail using an algorithm that automatically varies contrast levels
to enhance picture detail. ACE increases the contrast in dark areas
of an image without saturating the bright areas of the image. This
feature is particularly useful in automotive applications, where
it can be important to discern objects in shaded areas.
•
•
NTSC J, NTSC M, NTSC 4.43
SECAM B, SECAM D, SECAM G, SECAM K, SECAM L
Using the standard definition processor (SDP), the ADV7281/
ADV7281-M/ADV7281-MA can automatically detect the video
standard and process it accordingly.
Down dithering converts the output of the ADV7281/
ADV7281-M/ADV7281-MA from an 8-bit to a 6-bit
output, enabling ease of design for standard LCD panels.
The ADV7281/ADV7281-M/ADV7281-MA have a five-line
adaptive 2D comb filter that provides superior chrominance
and luminance separation when decoding a composite video
signal. This highly adaptive filter automatically adjusts its
processing mode according to the video standard and signal
quality without user intervention. Video user controls such as
brightness, contrast, saturation, and hue are also available
with the ADV7281/ADV7281-M/ADV7281-MA.
The SDP can process a variety of VBI data services, such as
closed captioning (CCAP), wide screen signaling (WSS), and
copy generation management system (CGMS). VBI data is
transmitted via the MIPI CSI-2 link as ancillary data packets.
The ADV7281/ADV7281-M/ADV7281-MA are fully Rovi®
(Macrovision®) compliant; detection circuitry enables Type I,
Type II, and Type III protection levels to be identified and
reported to the user. The decoders are also fully robust to all
Macrovision signal inputs.
The ADV7281/ADV7281-M/ADV7281-MA implement the
patented Adaptive Digital Line Length Tracking (ADLLT™)
algorithm to track varying video line lengths from sources such
Rev. A | Page 15 of 32
ADV7281
Data Sheet
POWER SUPPLY SEQUENCING
While the supplies are being established, care must be taken to
ensure that a lower rated supply does not go above a higher rated
supply level. During power-up, all supplies must adhere to the
specifications listed in the Absolute Maximum Ratings section.
OPTIMAL POWER-UP SEQUENCE
The optimal power-up sequence for the ADV7281/ADV7281-M/
ADV7281-MA is to first power up the 3.3 V DVDDIO supply,
followed by the 1.8 V supplies DVDD, PVDD, AVDD, and MVDD
.
MVDD only applies to the ADV7281-M/ADV7281-MA models.
POWER-DOWN SEQUENCE
When powering up the ADV7281/ADV7281-M/ADV7281-MA,
follow these steps. During power-up, all supplies must adhere
to the specifications listed in the Absolute Maximum Ratings
section.
The ADV7281/ADV7281-M/ADV7281-MA supplies can be
deasserted simultaneously as long as DVDDIO does not go below
a lower rated supply.
DVDDIO SUPPLY VOLTAGE
PWRDWN
RESET
pins (pull the pins low).
1. Assert the
and
For correct operation of the ADV7281-M/ADV7281-MA, the
2. Power up the DVDDIO supply.
3. After DVDDIO is fully asserted, power up the 1.8 V supplies.
4. After the 1.8 V supplies are fully asserted, pull
DVDDIO supply must be from 2.97 V to 3.63 V.
The ADV7281 can operate with a nominal DVDDIO voltage of
1.8 V. In this case, apply the power-up sequences described
previously. The only change is that DVDDIO is powered up to
1.8 V instead of 3.3 V.
PWRDWN
the
pin high.
RESET
5. Wait 5 ms and then pull the
pin high.
PWRDWN
RESET
and
6. After all power supplies and the
Note that when the ADV7281 operates with a nominal DVDDIO
voltage of 1.8 V, the n drive strength of all digital outputs must
be set to maximum.
Note that when DVDDIO is 1.8 V, the I2C pins of the ADV7281
(SCLK and SDATA) should be pulled up to 1.8V.
pins are powered up and stable, wait an additional 5 ms
before initiating I2C communication with the ADV7281/
ADV7281-M/ADV7281-MA.
SIMPLIFIED POWER-UP SEQUENCE
Alternatively, the ADV7281/ADV7281-M/ADV7281-MA can
PWRDWN
be powered up by asserting all supplies and the
RESET
and
pins simultaneously. After this operation, perform a
software reset, then wait 10 ms before initiating I2C commu-
nication with the ADV7281/ADV7281-M/ADV7281-MA.
3.3V
1.8V
3.3V SUPPLY
PWRDWN PIN
RESET PIN
1.8V SUPPLIES
PWRDWN PIN
POWER-UP
RESET PIN
POWER-UP
3.3V SUPPLY
POWER-UP
1.8V SUPPLIES
POWER-UP
TIME
5ms
5ms
WAIT
RESET
OPERATION
Figure 10. Optimal Power-Up Sequence
Rev. A | Page 16 of 32
Data Sheet
ADV7281
INPUT NETWORKS
An input network (external resistor and capacitor circuit) is
required on the AINx input pins of the decoder. The components
of the input network depend on the video format selected for
the analog input.
Fully differential video transmission involves transmitting
two complementary CVBS signals. Pseudo differential video
transmission involves transmitting a CVBS signal and a source
ground signal.
Differential video transmission has several key advantages over
single-ended transmission, including the following:
SINGLE-ENDED INPUT NETWORK
Figure 11 shows the input network to use on each AINx input
pin of the ADV7281/ADV7281-M/ADV7281-MA when any
of the following video input formats is used:
•
•
•
Inherent small signal and large signal noise rejection
Improved EMI performance
Ability to absorb ground bounce
•
•
•
Single-ended CVBS
YC (S-Video)
YPrPb
Resistor R1 provides the RF end termination for the differential
CVBS input lines. For a pseudo differential CVBS input, a value
of 75 Ω is recommended for R1. For a fully differential CVBS
input, a value of 150 Ω is recommended for R1.
INPUT
CONNECTOR
100nF
24Ω
VIDEO INPUT
FROM SOURCE
EXT
ESD
A
3
IN
The 1.3 kΩ and 430 Ω resistors create a resistor divider with a
gain of 0.25. The resistor divider attenuates the amplitude of the
input analog video, but increases the input common-mode range
of the ADV7281/ADV7281-M/ADV7281-MA to 4 V p-p. Note
that amplifiers within the ADC restore the amplitude of the
input signal so that SNR performance is maintained.
51Ω
Figure 11. Single-Ended Input Network
The 24 Ω and 51 Ω resistors supply the 75 Ω end termination
required for the analog video input. These resistors also create
a resistor divider with a gain of 0.68. The resistor divider attenu-
ates the amplitude of the input analog video and scales the input
to the ADC range of the ADV7281/ADV7281-M/ADV7281-MA.
This allows an input range to the ADV7281/ADV7281-M/
ADV7281-MA of up to 1.47 V p-p. Note that amplifiers within
the ADC restore the amplitude of the input signal so that
signal-to-noise ratio (SNR) performance is maintained.
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into the AINx pin of the ADV7281/
ADV7281-M/ADV7281-MA. The clamping circuitry within the
ADV7281/ADV7281-M/ADV7281-MA restores the dc bias of
the input signal to the optimal level before it is fed into the
ADC of the ADV7281/ADV7281-M/ADV7281-MA.
The combination of the 1.3 kΩ and 430 Ω resistors and the
100 nF ac coupling capacitors limits the current flow into the
ADV7281/ADV7281-M/ADV7281-MA during short-to-battery
(STB) events (see the Short-to-Battery Protection section).
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into the AINx pin of the ADV7281/
ADV7281-M/ADV7281-MA. The clamping circuitry within the
ADV7281/ADV7281-M/ADV7281-MA restores the dc bias
of the input signal to the optimal level before it is fed into the
ADC of the ADV7281/ADV7281-M/ADV7281-MA.
To achieve optimal performance, the 1.3 kΩ and 430 Ω resistors
must be closely matched; that is, all 1.3 kΩ and 430 Ω resistors
must have the same resistance tolerance, and this tolerance must
be as low as possible.
DIFFERENTIAL INPUT NETWORK
Figure 12 shows the input network to use when differential
CVBS video is input on the AINx input pins of the ADV7281/
ADV7281-M/ADV7281-MA.
SHORT-TO-BATTERY PROTECTION
In differential mode, the ADV7281/ADV7281-M/ADV7281-MA
are protected against short-to-battery (STB) events by ac
coupling capacitors (see Figure 12). The input network resistors
are sized to reduce the current flow during an STB event, thus
preventing damage to the resistors. The R1 resistor is protected
because no current or limited current flows through it during
an STB event.
INPUT
CONNECTOR
100nF
1.3kΩ
A
1
IN
430Ω
EXT
ESD
VIDEO INPUT
FROM SOURCE
R1
430Ω
100nF
1.3kΩ
The ADV7281/ADV7281-M provides two STB diagnostic pins
that can be used to generate an interrupt when an STB event
occurs. For more information, see the Short-to-Battery (STB)
Diagnostics section.
A
2
IN
INPUT
CONNECTOR
Figure 12. Differential Input Network
Rev. A | Page 17 of 32
ADV7281
Data Sheet
INPUT CONFIGURATION
The input format of the ADV7281-M/ADV7281-MA is
specified using the INSEL[4:0] bits (see Table 13). These bits
also configure the SDP core to process CVBS, differential
CVBS, Y/C (S-Video), or component (YPbPr) format. The
INSEL[4:0] bits are located in the user sub map of the register
space at Address 0x00[4:0]. For more information about the
registers, see the Register Maps section.
The INSEL[4:0] bits specify predefined analog input routing
schemes, eliminating the need for manual mux programming
and allowing the user to route the various video signal types
to the decoder. For example, if the CVBS input is selected, the
remaining channels are powered down.
Table 13. Input Format Specified by the INSEL[4:0] Bits
Analog Inputs
INSEL[4:0] Bit Value
00000
00001
00010
00011
00100
00101
00110
00111
Video Format
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
ADV7281
ADV7281-M
ADV7281-MA
CVBS input on AIN1
CVBS input on AIN2
Reserved
Reserved
Reserved
Reserved
CVBS input on AIN3
CVBS input on AIN4
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
Reserved
Reserved
CVBS input on AIN5
CVBS input on AIN6
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
CVBS input on AIN5
CVBS input on AIN6
CVBS input on AIN7
CVBS input on AIN8
01000
Y/C (S-Video)
Y input on AIN1;
C input on AIN2
Y input on AIN1;
C input on AIN2
Y input on AIN1;
C input on AIN2
01001
01010
01011
01100
Y/C (S-Video)
Y/C (S-Video)
Y/C (S-Video)
YPrPb
Reserved
Y input on AIN3;
C input on AIN4
Reserved
Y input on AIN3;
C input on AIN4
Y input on AIN5;
C input on AIN6
Y input on AIN7;
C input on AIN8
Reserved
Y input on AIN3;
C input on AIN4
Reserved1
Y input on AIN5;
C input on AIN6
Y input on AIN1;
Pb input on AIN2;
Pr input on AIN3
Y input on AIN1;
Pb input on AIN2;
Pr input on AIN3
Y input on AIN4;
Pb input on AIN5;
Pr input on AIN6
01101
YPrPb
Reserved1
Reserved
01110
Differential CVBS
Differential CVBS
Differential CVBS
Differential CVBS
Reserved
Positive input on AIN1;
Negative input on AIN2
Reserved
Positive input on AIN1;
Negative input on AIN2
Positive input on AIN3;
Negative input on AIN4
Positive input on AIN1;
Negative input on AIN2
Positive input on AIN3;
Negative input on AIN4
Positive input on AIN5;
Negative input on AIN6
Positive input on AIN7;
Negative input on AIN8
01111
10000
Reserved
Reserved
10001
Positive input on AIN3;
Negative input on AIN4
Positive input on AIN5;
Negative input on AIN6
10010 to 11111
Reserved
Reserved
Reserved
1 Note that it is possible for the ADV7281 to receive YPbPr formats; however, a manual muxing scheme is required. In this case luma(Y) is fed in on AIN1 or AIN3, Blue
chroma(Pb) is fed in on AIN4 and red chroma (Pr) is fed in on AIN2.
Rev. A | Page 18 of 32
Data Sheet
ADV7281
SHORT-TO-BATTERY (STB) DIAGNOSTICS (ADV7281/ADV7281-M ONLY)
The ADV7281/ADV7281-M senses an STB event via the DIAG1
and DIAG2 pins. The DIAG1 and DIAG2 pins can sense an
STB event on either the positive or negative differential input
because of the negligible voltage drop across Resistor R1.
PROGRAMMING THE STB DIAGNOSTIC FUNCTION
By default, the STB diagnostic function is disabled on the
ADV7281/ADV7281-M. To enable the diagnostic function,
follow the instructions in this section.
DIAG1 Pin
R5
DIAG1
DIAG1_SLICER_PWRDN, User Sub Map, Address
0x5D[6]
INPUT
R4
CONNECTOR
100nF
1.3kΩ
A
1
IN
This bit powers up or powers down the diagnostic circuitry for
the DIAG1 pin.
430Ω
EXT
ESD
VIDEO INPUT
FROM SOURCE
R1
Table 14. DIAG1_SLICER_PWRDN Function
430Ω
100nF
DIAG1_SLICER_PWRDN
Diagnostic Slice Level
1.3kΩ
A
2
IN
0
Power up the diagnostic circuitry
for the DIAG1 pin.
INPUT
CONNECTOR
1 (default)
Power down the diagnostic
circuitry for the DIAG1 pin.
Figure 13. Diagnostic Connections
Resistors R4 and R5 divide down the voltage at the input con-
nector to protect the DIAGx pin from an STB event. The DIAGx
pin circuitry compares this voltage to a programmable reference
voltage, known as the diagnostic slice level. When the diagnostic
slice level is exceeded, an STB event has occurred.
DIAG1_SLICE_LEVEL[2:0], User Sub Map, Address
0x5D[4:2]
The DIAG1_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG1 pin. When a voltage greater
than the diagnostic slice level is seen on the DIAG1 pin, an STB
interrupt is triggered.
When the DIAGx pin voltage exceeds the diagnostic slice level
voltage, a hardware interrupt is triggered and indicated by
In order for the diagnostic slice level to be set correctly, the
diagnostic circuitry for the DIAG1 pin must be powered up
(see Table 14).
INTRQ
the
pin. A readback register is also provided, which
allows the user to determine the DIAGx pin on which the STB
event occurred.
Table 15. DIAG1_SLICE_LEVEL[2:0] Settings
Use Equation 1 to find the trigger voltage for a selected
diagnostic slice level.
DIAG1_SLICE_LEVEL[2:0]
Diagnostic Slice Level
000
001
010
75 mV
225 mV
375 mV
R5+R4
VSTB _TRIGGER
=
× DIAGNOSTIC_SLICE_LEVEL
(1)
R5
where:
011 (default)
100
525 mV
675 mV
VSTB_TRIGGER is the minimum voltage required at the
input connector to trigger the STB interrupt on the
ADV7281/ADV7281-M.
101
110
825 mV
975 mV
DIAGNOSTIC_SLICE_LEVEL is the programmable reference
voltage.
111
1.125 V
Rev. A | Page 19 of 32
ADV7281
Data Sheet
In order for the diagnostic slice level to be set correctly, the
diagnostic circuitry for the DIAG2 pin must be powered up (see
Table 16).
DIAG2 Pin
DIAG2_SLICER_PWRDN, User Sub Map, Address
0x5E[6]
Table 17. DIAG2_SLICE_LEVEL[2:0] Settings
This bit powers up or powers down the diagnostic circuitry for
the DIAG2 pin.
DIAG2_SLICE_LEVEL[2:0]
Diagnostic Slice Level
000
75 mV
Table 16. DIAG2_SLICER_PWRDN Function
001
225 mV
010
375 mV
DIAG2_SLICER_PWRDN
Diagnostic Slice Level
011 (default)
100
525 mV
675 mV
0
Power up the diagnostic circuitry
for the DIAG2 pin.
1 (default)
Power down the diagnostic
circuitry for the DIAG2 pin.
101
110
825 mV
975 mV
111
1.125 V
DIAG2_SLICE_LEVEL[2:0], User Sub Map, Address
0x5E[4:2]
The DIAG2_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG2 pin. When a voltage greater
than the diagnostic slice level is seen on the DIAG2 pin, an STB
interrupt is triggered.
Rev. A | Page 20 of 32
Data Sheet
ADV7281
ADAPTIVE CONTRAST ENHANCEMENT (ACE)
The ADV7281/ADV7281-M/ADV7281-MA can increase the
contrast of an image depending on the content of the picture,
allowing bright areas to be made brighter and dark areas to be
made darker. The optional ACE feature enables the contrast
within dark areas to be increased without significantly affecting
the bright areas. The ACE feature is particularly useful in
automotive applications, where it can be important to discern
objects in shaded areas.
The ACE function is disabled by default. To enable the ACE
function, execute the register writes shown in Table 18. To
disable the ACE function, execute the register writes shown
in Table 19.
Table 18. Register Writes to Enable the ACE Function
Register Map
Register Address
Register Write
0x40
0x80
Description
User Sub Map (0x40 or 0x42)
User Sub Map 2 (0x40 or 0x42)
User Sub Map 2 (0x40 or 0x42)
0x0E
0x80
0x0E
Enter User Sub Map 2
Enable ACE
Reenter user sub map
0x00
Table 19. Register Writes to Disable the ACE Function
Register Map
Register Address
Register Write
0x40
0x00
Description
User Sub Map (0x40 or 0x42)
User Sub Map 2 (0x40 or 0x42)
User Sub Map 2 (0x40 or 0x42)
0x0E
0x80
0x0E
Enter User Sub Map 2
Disable ACE
Reenter user sub map
0x00
Rev. A | Page 21 of 32
ADV7281
Data Sheet
ITU-R BT.656 Tx CONFIGURATION (ADV7281 ONLY)
The ADV7281 receives analog video and outputs digital video
according to the ITU-R BT.656 specification. The ADV7281
outputs the ITU-R BT.656 video data stream over the P0 to P7
data pins and has a line-locked clock (LLC) pin.
Video data is output over the P0 to P7 pins in YCrCb 4:2:2 format.
Synchronization signals are automatically embedded in the video
data signal in accordance with the ITU-R BT.656 specification.
The LLC output is used to clock the output data on the P0 to P7
pins at a nominal frequency of 27 MHz.
P0
VIDEO
DECODER
ADV7281
P1
P2
P3
P4
ITU-R BT.656
P5
DATA
STREAM
P6
ANALOG
VIDEO
INPUT
ANALOG STANDARD
P7
FRONT
END
DEFINITION
PROCESSOR
LLC
Figure 14. ITU-R BT.656 Output Stage of the ADV7281
Rev. A | Page 22 of 32
Data Sheet
ADV7281
MIPI CSI-2 OUTPUT
The decoder in the ADV7281-M/ADV7281-MA outputs an
ITU-R BT.656 data stream. The ITU-R BT.656 data stream is
connected into a CSI-2 Tx module. Data from the CSI-2 Tx
module is fed into a D-PHY physical layer and output serially
from the device.
The clock lanes are used to clock the output video. After the
ADV7281-M/ADV7281-MA are programmed, the clock lanes
exit low power mode and remain in high speed mode until the
part is reset or powered down.
The ADV7281-M/ADV7281-MA output video data in an 8-bit
YCrCb 4:2:2 format. The video data is output in an interlaced
format at a nominal data rate of 216 Mbps.
The output of the ADV7281-M/ADV7281-MA consists of a
single data channel on the D0P and D0N lanes and a clock
channel on the CLKP and CLKN lanes.
Video data is output over the data lanes in high speed mode.
The data lanes enter low power mode during the horizontal
and vertical blanking periods.
D0P
(1 BIT)
CSI Tx DATA
OUTPUT (8 BITS)
D0N
ITU-R BT.656
DATA
STREAM
ANALOG
VIDEO
INPUT
(1 BIT)
DATA LANE LP
SIGNALS (2 BITS)
VIDEO
DECODER
CSI-2
Tx
D-PHY
Tx
CLKP
(1 BIT)
CLOCK LANE LP
SIGNALS (2 BITS)
CLKN
(1 BIT)
Figure 15. MIPI CSI-2 Output Stage of the ADV7281-M/ADV7281-MA
Rev. A | Page 23 of 32
ADV7281
Data Sheet
I2C PORT DESCRIPTION
The ADV7281/ADV7281-M/ADV7281-MA support a 2-wire,
I2C-compatible serial interface. Two inputs, serial data (SDATA)
and serial clock (SCLK), carry information between the
ADV7281/ADV7281-M/ADV7281-MA and the system I2C
master controller. The I2C port of the ADV7281/ADV7281-M/
ADV7281-MA allows the user to set up and configure the
decoder and to read back captured VBI data.
4. All other devices withdraw from the bus and maintain an
idle condition. In the idle condition, the device monitors
the SDATA and SCLK lines for the start condition and the
correct transmitted address.
W
The R/ bit determines the direction of the data. Logic 0 on the
LSB of the first byte means that the master writes information
to the peripheral. Logic 1 on the LSB of the first byte means that
the master reads information from the peripheral.
The ADV7281/ADV7281-M/ADV7281-MA act as standard I2C
slave devices on the bus. The data on the SDATA pin is eight bits
The ADV7281/ADV7281-M/ADV7281-MA have a number of
possible I2C slave addresses and subaddresses (see the Register
Maps section). The main map of the ADV7281/ADV7281-M/
ADV7281-MA has four possible slave addresses for read and
write operations, depending on the logic level of the ALSB pin
(see Table 20).
W
long, supporting the 7-bit address plus the R/ bit. The device has
subaddresses to enable access to the internal registers; therefore, it
interprets the first byte as the device address and the second byte
as the starting subaddress. The subaddresses auto-increment,
allowing data to be written to or read from the starting
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register individually without updating all the registers.
Table 20. Main Map I2C Address for the ADV7281-M/
ADV7281-MA
R/W Bit
ALSB Pin
Slave Address
0x40 (write)
0x41 (read)
0x42 (write)
0x43 (read)
0
0
1
1
0
1
0
1
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCLK high period, the user
should issue only one start condition, one stop condition, or a single
stop condition followed by a single start condition. If an invalid
subaddress is issued by the user, the ADV7281/ADV7281-M/
ADV7281-MA do not issue an acknowledge and return to the
idle condition.
The ALSB pin controls Bit 1 of the slave address. By changing
the logic level of the ALSB pin, it is possible to control two
ADV7281/ADV7281-M/ADV7281-MA devices in an applica-
tion without using the same I2C slave address. The LSB (Bit 0)
specifies either a read or write operation: Logic 1 corresponds to
a read operation, and Logic 0 corresponds to a write operation.
To control the device on the bus, a specific protocol is followed.
If the highest subaddress is exceeded in auto-increment mode,
one of the following actions is taken:
1. The master initiates a data transfer by establishing a start
condition, which is defined as a high to low transition on
SDATA while SCLK remains high, and indicates that an
address/data stream follows.
In read mode, the register contents of the highest sub-
address continue to be output until the master device issues
a no acknowledge, which indicates the end of a read. A no
acknowledge condition occurs when the SDATA line is not
pulled low on the ninth pulse.
2. All peripherals respond to the start condition and shift
W
the next eight bits (the 7-bit address plus the R/ bit).
The bits are transferred from MSB to LSB.
3. The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth
clock pulse; this is known as an acknowledge (ACK) bit.
In write mode, the data for the invalid byte is not loaded
into a subaddress register. A no acknowledge is issued by
the ADV7281/ADV7281-M/ADV7281-MA, and the part
returns to the idle condition.
SDATA
SCLK
S
P
1–7
8
9
1–7
8
9
1–7
DATA
8
9
START ADDR R/W ACK SUBADDRESS ACK
ACK
STOP
Figure 16. Bus Data Transfer
WRITE
S
S
SLAVE ADDR A(S) SUBADDRESS A(S)
LSB = 0
DATA
A(S)
DATA
A(S) P
SEQUENCE
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S) SUBADDRESS A(S)
S
SLAVE ADDR A(S)
DATA
A(M)
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 17. Read and Write Sequence
Rev. A | Page 24 of 32
Data Sheet
ADV7281
The user sub map has the same I2C slave address as the main
map. To access the user sub map, set the SUB_USR_EN bits in
the main map (Address 0x0E[6:5]) to 00.
REGISTER MAPS
The ADV7281 contains a single main register map. The
main register map contains three sub maps: user sub map,
interrupt/VDP map, User Sub Map2.
Interrupt/VDP Sub Map
The ADV7281-M/ADV7281-MA contain two register maps:
the main register map and the CSI register map (see Figure 18).
The main register map of the ADV7281-M/ADV7281-MA
contains three sub maps in a similar manner as the ADV7281.
The interrupt/VDP sub map contains registers that can be used to
INTRQ
program internal interrupts, control the
vertical blanking interval (VBI) data.
pin, and decode
The interrupt/VDP sub map has the same I2C slave address
as the main map. To access the interrupt/VDP sub map, set the
SUB_USR_EN bits in the main map (Address 0x0E[6:5]) to 01.
Main Map
The I2C slave address of the main map of the ADV7281-M/
ADV7281-MA is set by the ALSB pin (see Table 20). The main
map allows the user to program the I2C slave address of the CSI
map. The main map contains three sub maps: the user sub map,
the interrupt/VDP sub map, and User Sub Map 2. These three
sub maps are accessed by writing to the SUB_USR_EN bits
(Address 0x0E[6:5]) within the main map (see Figure 18 and
Table 21).
User Sub Map 2
User Sub Map 2 contains registers that control the ACE, down
dither, and fast lock functions. It also contains controls that set the
acceptable input luma and chroma limits before the ADV7281-M/
ADV7281-MA enter free run and color kill modes.
User Sub Map 2 has the same I2C slave address as the main map.
To access User Sub Map 2, set the SUB_USR_EN bits in the main
map (Address 0x0E[6:5]) to 10.
User Sub Map
The user sub map contains registers that program the analog
front end and digital core of the ADV7281-M/ADV7281-MA.
MAIN MAP
CSI MAP
DEVICE ADDRESS
DEVICE ADDRESS
ALSB PIN LOW
WRITE: 0x40
READ: 0x41
ALSB PIN HIGH
WRITE: 0x42
READ: 0x43
WRITE: 0x88 (RECOMMENDED
READ: 0x89 SETTINGS)
CSI MAP ADDRESS IS
PROGRAMMABLE AND SET BY
REGISTER 0xFE IN THE USER
SUB MAP
0x0E[6:5] = 00
0x0E[6:5] = 01
0x0E[6:5] = 10
USER
SUB MAP
INTERRUPT/VDP
SUB MAP
USER SUB
MAP 2
NOTES
1. CSI MAP ONLY APPLIES TO THE ADV7281-M/ADV7281-MA MODELS.
Figure 18. Register Map and Sub Map Access
Table 21. I2C Register Map and Sub Map Addresses
SUB_USR_EN Bits
(Address 0x0E[6:5]) Register Map or Sub Map
R/ Bit
W
ALSB Pin
Slave Address
0x40
0x41
0x40
0x41
0x40
0x41
0x42
0x43
0x42
0x43
0x42
0x43
0x88
0x89
0
0
0
0
0
0
1
1
1
1
1
1
X1
X1
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
00
00
01
01
10
10
00
00
01
01
10
10
XX1
XX1
User sub map
User sub map
Interrupt/VDP sub map
Interrupt/VDP sub map
User Sub Map 2
User Sub Map 2
User sub map
User sub map
Interrupt/VDP sub map
Interrupt/VDP sub map
User Sub Map 2
User Sub Map 2
CSI map (ADV7281-M/ADV7281-MA only)
CSI map (ADV7281-M/ADV7281-MA only)
1 X and XX mean don’t care.
Rev. A | Page 25 of 32
ADV7281
Data Sheet
CSI Map (ADV7281-M/ADV7281-MA)
SUB_USR_EN Bits, Address 0x0E[6:5]
The CSI map contains registers that control the MIPI CSI-2
output stream from the ADV7281-M/ADV7281-MA.
The ADV7281-M/ADV7281-MA main map contains three
sub maps: the user sub map, the interrupt/VDP sub map, and
User Sub Map 2 (see Figure 18). The user sub map is available
by default. The other two sub maps are accessed using the
SUB_USR_EN bits. When programming of the interrupt/VDP
map or User Sub Map 2 is completed, it is necessary to write to
the SUB_USR_EN bits to return to the user sub map.
The CSI map has a programmable I2C slave address, which is
programmed using Register 0xFE in the user sub map of the
main map. The default value for the CSI map address is 0x00;
however, the CSI map cannot be accessed until the I2C slave
address is reset. The recommended I2C slave address for the
CSI map is 0x88.
To reset the I2C slave address of the CSI map, write to the
CSI_TX_SLAVE_ADDRESS[7:1] bits in the main register map
(Address 0xFE[7:1]). Set these bits to a value of 0x88 (I2C write
address; I2C read address is 0x89).
Rev. A | Page 26 of 32
Data Sheet
ADV7281
PCB LAYOUT RECOMMENDATIONS
The ADV7281/ADV7281-M/ADV7281-MA are high precision,
high speed, mixed-signal devices. To achieve maximum perfor-
mance from the parts, it is important to use a well-designed PCB.
This section provides guidelines for designing a PCB for use
with the ADV7281/ADV7281-M/ADV7281-MA.
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This disparity can
result in a measurable change in the voltage supplied to the analog
supply regulator, which can, in turn, produce changes in the regu-
lated analog supply voltage. This problem can be mitigated by
regulating the analog supply, or at least the PVDD supply, from a
different, cleaner power source, for example, from a 12 V supply.
ANALOG INTERFACE INPUTS
When routing the analog interface inputs on the PCB, keep
track lengths to a minimum. Use 75 Ω trace impedances when
possible; trace impedances other than 75 Ω increase the chance
of reflections.
Using a single ground plane for the entire board is also recom-
mended. Experience has shown that the noise performance is
the same or better with a single ground plane. Using multiple
ground planes can be detrimental because each separate ground
plane is smaller, and long ground loops can result.
POWER SUPPLY DECOUPLING
It is recommended that each power supply pin be decoupled
with 100 nF and 10 nF capacitors. The basic principle is to place
a decoupling capacitor within approximately 0.5 cm of each power
pin. Avoid placing the decoupling capacitors on the opposite
side of the PCB from the ADV7281/ADV7281-M/ADV7281-MA
because doing so introduces inductive vias in the path.
VREFN AND VREFP PINS
Place the circuit associated with the VREFN and VREFP pins as
close as possible to the ADV7281/ADV7281-M/ADV7281-MA
and on the same side of the PCB as the part.
DIGITAL OUTPUTS
Place the decoupling capacitors between the power plane and
the power pin. Current should flow from the power plane to the
capacitor and then to the power pin. Do not apply the power
connection between the capacitor and the power pin. The best
approach is to place a via near, or beneath, the decoupling capaci-
tor pads down to the power plane (see Figure 19).
INTRQ
The ADV7281 digital outputs are
ADV7281-M/ADV7281-MA are
, LLC, P0:P7. The
INTRQ
, GPO0 to GPO2.
Minimize the trace length that the digital outputs must drive.
Longer traces have higher capacitance, requiring more current
and, in turn, causing more internal digital noise. Shorter traces
reduce the possibility of reflections.
VIA TO SUPPLY
SUPPLY
10nF
100nF
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce current spikes inside the ADV7281/
ADV7281-M/ADV7281-MA. If series resistors are used,
place them as close as possible to the pins of the ADV7281/
ADV7281-M/ ADV7281-MA. However, try not to add vias or
extra length to the output trace in an attempt to place the resistors
closer.
VIA TO GND
GROUND
Figure 19. Recommended Power Supply Decoupling
It is especially important to maintain low noise and good
stability for the PVDD pin. Careful attention must be paid to
regulation, filtering, and decoupling. It is highly desirable to
provide separate regulated supplies for each circuit group
VDD, DVDD, DVDDIO, PVDD, and MVDD. MVDD only applies to the
ADV7281-M/ADV7281-MA models.
If possible, limit the capacitance that each digital output must
drive to less than 15 pF. This recommendation can be easily
accommodated by keeping traces short and by connecting the
outputs to only one device. Loading the outputs with excessive
capacitance increases the current transients inside the ADV7281/
ADV7281-M/ADV7281-MA, creating more digital noise on the
power supplies.
A
Rev. A | Page 27 of 32
ADV7281
Data Sheet
EXPOSED METAL PAD
MIPI OUTPUTS (D0P, D0N, CLKP, CLKN)
ADV7281-M/ADV7281-MA ONLY
The ADV7281/ADV7281-M/ADV7281-MA have an exposed
metal pad on the bottom of the package. This pad must be
soldered to ground. The exposed pad is used for proper heat
dissipation, noise suppression, and mechanical strength.
It is recommended that the MIPI output traces be kept as short
as possible and on the same side of the PCB as the ADV7281-M/
ADV7281-MA device. It is also recommended that a solid plane
(preferably a ground plane) be placed on the layer adjacent to
the MIPI traces to provide a solid reference plane.
DIGITAL INPUTS
The digital inputs of the ADV7281/ADV7281-M/ADV7281-MA
are designed to work with 1.8 V signals (3.3 V for DVDDIO) and are
not tolerant of 5 V signals. Extra components are required if 5 V
logic signals must be applied to the decoder.
MIPI transmission operates in both differential and single-
ended modes. During high speed transmission, the pair of
outputs operates in differential mode; in low power mode, the
pair operates as two independent single-ended traces. There-
fore, it is recommended that each output pair be routed as two
loosely coupled 50 Ω single-ended traces to reduce the risk of
crosstalk between the two traces in low power mode.
Rev. A | Page 28 of 32
Data Sheet
ADV7281
TYPICAL CIRCUIT CONNECTIONS
Figure 20 provides an example of how to connect the ADV7281. For detailed schematics of the ADV7281 evaluation board, contact a
local Analog Devices, Inc., field applications engineer or an Analog Devices distributor.
0.1µF
1
A
IN
DIFF1+
1.3kꢀ
430ꢀ
430ꢀ
FULLY
DIFFERENTIAL
CVBS INPUT
150ꢀ
0.1µF
D
_1.8V
0.1µF
D
_3.3V
10nF
A
_1.8V
10nF
2
A
IN
VDD
VDDIO
VDD
DIFF1–
1.3kꢀ
9.1kꢀ
1kꢀ
DIAG1
0.1µF
0.1µF
10nF
0.1µF
10nF
0.1µF
3
A
DIFF2+
IN
1.3kꢀ
1.3kꢀ
430ꢀ
P
_1.8V
10nF
VDD
PSEUDO
DIFFERENTIAL
CVBS INPUT
D
_3.3V
VDDIO
75ꢀ
D
_1.8V
VDD
430ꢀ
0.1µF
0.1µF
A
_1.8V
4
VDD
A
IN
DIFF2–
9.1
kꢀ
DIAG2
1kꢀ
P0 TO P7
17
18
A
A
1
2
A
A
1
2
IN
IN
IN
IN
12
P0
P1
P2
P3
P4
P5
P6
P7
P0
P1
P2
P3
P4
P5
P6
P7
11
10
9
8
7
YCrCb
8-BIT
ITU-R BT.656 DATA
22
24
DIAG1
DIAG1
A
3
ADV7281
A
A
3
4
IN
IN
IN
6
5
25
23
A
4
IN
DIAG2
VREFP
DIAG2
19
20
LOCATE VREFP AND VREFN CAPACITOR AS
CLOSE AS POSSIBLE TO THE ADV7281 AND ON
THE SAME SIDE OF THE PCB AS THE ADV7281
0.1µF
VREFN
32
26
LLC
INTRQ
LLC
INTRQ
LOCATE CLOSE TO, AND ON THE
SAME SIDE OF THE PCB AS, THE ADV7281
14
15
XTALP
XTALN
47pF
28.63636MHz
47pF
D
VDDIO
4kΩ
28
ALSB
2
ALSB TIED HIGH: I C ADDRESS = 0x42
2
ALSB TIED LOW: I C ADDRESS = 0x40
31
27
30
29
PWRDWN
RESET
SCLK
PWRDWN
RESET
SCLK
SDATA
SDATA
Figure 20. Typical Connection Diagram, ADV7281
Rev. A | Page 29 of 32
ADV7281
Data Sheet
Figure 21 provides an example of how to connect the ADV7281-M. For detailed schematics of the ADV7281-M evaluation board, contact
a local Analog Devices, Inc., field applications engineer or an Analog Devices distributor.
D
_1.8V
D
_3.3V
A
_1.8V
M
_1.8V
VDD
VDDIO
VDD
VDD
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
1
AIN
10nF
DIFF1+
10nF
10nF
10nF
1.3kꢀ
1.3kꢀ
430ꢀ
430ꢀ
FULLY
DIFFERENTIAL
CVBS INPUT
150ꢀ
P
VDD_1.8V
0.1µF
DVDDIO_3.3V
DVDD_1.8V
2
AIN
DIFF1–
MVDD_1.8V
9.1kꢀ
1kꢀ
0.1µF
AVDD_1.8V
10nF
DIAG1
0.1µF
17
18
3
AIN
AIN
1
2
AIN
AIN
1
2
DIFF2+
1.3kꢀ
1.3kꢀ
AIN
430ꢀ
9
D0P
D0N
D0P
PSEUDO
DIFFERENTIAL
CVBS INPUT
75ꢀ
10
D0N
22
430ꢀ
DIAG1
DIAG1
0.1µF
4
AIN
DIFF2–
11
12
23
24
CLKP
CLKN
CLKP
CLKN
9.1
kꢀ
AIN3
AIN
3
DIAG2
AIN4
AIN
4
1kꢀ
ADV7281-M
25
DIAG2
DIAG2
0.1µF
SINGLE-ENDED
CVBS INPUT
5
AIN
26
27
24ꢀ
24ꢀ
AIN
5
EXAMPLE
AIN
AIN
5
6
51ꢀ
AIN6
6
7
8
GPO2
GPO1
GPO2
GPO1
GPO0
LOCATE CLOSE TO, AND
ON THE SAME SIDE OF
THE PCB AS, THE ADV7281-M
0.1µF
SINGLE-ENDED
CVBS INPUT
EXAMPLE
6
AIN
GPO0
51ꢀ
14
15
XTALP
XTALN
47pF
28.63636MHz
5
INTRQ
INTRQ
47pF
LOCATE VREFN AND VREFP CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADV7281-M AND ON THE SAME
SIDE OF THE PCB AS THE ADV7281-M
DVDDIO
4kꢀ
29
32
ALSB
19
2
VREFP
VREFN
ALSB TIED HIGH: I C ADDRESS = 0x42
ALSB TIED LOW: I C ADDRESS = 0x40
2
0.1µF
20
PWRDWN
PWRDWN
RESET
28
31
RESET
SCLK
SCLK
30
SDATA
SDATA
Figure 21. Typical Connection Diagram, ADV7281-M
Rev. A | Page 30 of 32
Data Sheet
ADV7281
Figure 22 provides an example of how to connect the ADV7281-MA. For detailed schematics of the ADV7281-MA evaluation board,
contact a local Analog Devices field applications engineer or an Analog Devices distributor.
0.1µF
1
A
Y
IN
24ꢀ
51ꢀ
0.1µF
2
A
Pb
IN
24ꢀ
51ꢀ
0.1µF
3
A
Pr
IN
24ꢀ
24ꢀ
51ꢀ
SINGLE-
ENDED
CVBS
0.1µF
4
A
IN
51ꢀ
INPUT
D
_1.8V
0.1µF
D
_3.3V
10nF
A
_1.8V
10nF
M
VDD
_1.8V
10nF
VDD
VDDIO
VDD
0.1µF
0.1µF
0.1µF
0.1µF
5
A
A
IN
DIFF1+
PSEUDO
DIFFERENTIAL
CVBS INPUT
10nF
1.3kꢀ
1.3kꢀ
430ꢀ
75ꢀ
430ꢀ
P
_1.8V
10nF
0.1µF
VDD
D
_3.3V
D
VDDIO
6
DIFF1–
IN
M
VDD _1.8V
_1.8V
A
VDD
0.1µF
_1.8V
VDD
17
18
0.1µF
A
A
1
2
A
A
1
2
IN
IN
IN
IN
7
8
A
A
DIFF2+
IN
1.3kꢀ
1.3kꢀ
9
430ꢀ
430ꢀ
D0P
D0P
FULLY
10
D0N
D0N
DIFFERENTIAL
CVBS INPUT
150ꢀ
22
A
3
A
3
IN
IN
0.1µF
DIFF2–
IN
11
12
23
24
CLKP
CLKN
CLKP
CLKN
A
A
4
5
A
A
4
5
IN
IN
IN
IN
ADV7281-MA
25
A
6
A
6
IN
IN
26
27
A
A
7
8
A
A
7
8
IN
IN
IN
IN
6
7
8
GPO2
GPO1
GPO2
GPO1
GPO0
LOCATE CLOSE TO, AND
ON THE SAME SIDE OF
THE PCB AS, THE ADV7281-MA
GPO0
14
15
XTALP
XTALN
47pF
28.63636MHz
5
INTRQ
INTRQ
47pF
LOCATE VREFN AND VREFP CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADV7281-MA AND ON THE
SAME SIDE OF THE PCB AS THE ADV7281-MA
D
VDDIO
4kꢀ
29
32
ALSB
19
2
VREFP
VREFN
ALSB TIED HIGH: I C ADDRESS = 0x42
ALSB TIED LOW: I C ADDRESS = 0x40
2
0.1µF
20
PWRDWN
PWRDWN
RESET
28
31
RESET
SCLK
SCLK
30
SDATA
SDATA
Figure 22. Typical Connection Diagram, ADV7281-MA
Rev. A | Page 31 of 32
ADV7281
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
*
3.75
EXPOSED
PAD
3.60 SQ
3.55
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
Figure 23. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +105°C
Package Description
Package Option
CP-32-12
CP-32-12
CP-32-12
CP-32-12
ADV7281WBCPZ
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board for the ADV7281-M
ADV7281WBCPZ-RL
ADV7281WBCPZ-M
ADV7281WBCPZ-M-RL
ADV7281WBCPZ-MA
ADV7281WBCPZ-MA-RL
EVAL-ADV7281MEBZ
EVAL-ADV7281MAEBZ
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
CP-32-12
CP-32-12
Evaluation Board for the ADV7281-MA
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADV7281W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should
review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive
applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific
Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11633-0-11/13(A)
Rev. A | Page 32 of 32
相关型号:
EVAL-ADV7282MEBZ
10-Bit, 4 Oversampled SDTV Video Decoder with Differential Inputs and Deinterlacer
ADI
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