MVTX2603AG [ZARLINK]
Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch; 非网管型24端口10/100兆+ 2端口1 Gb以太网交换机
| 型号： | MVTX2603AG |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb Ethernet Switch |
| 文件： | 总109页 (文件大小：793K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MVTX2603
Unmanaged 24-Port 10/100 Mb + 2-Port 1 Gb
Ethernet Switch
Data Sheet
February 2004
Features
Ordering Information
•
•
•
Integrated Single-Chip 10/100/1000 Mbps
Ethernet Switch
MVTX2603AG
553 Pin HSBGA
24 10/100 Mbps Autosensing, Fast Ethernet
Ports with RMII or Serial Interface (7WS)
-40°C to +85°C
2 Gigabit Ports with GMII, PCS, 10/100 and
stacking (2 G per port) interface options per port
•
•
Supports per-system option to enable flow control
for best effort frames even on QoS-enabled ports
Load sharing among trunked ports can be based
on source MAC and/or destination MAC. The
Gigabit trunking group has one more option,
based on source port.
•
•
Serial interface for configuration
Supports two Frame Buffer Memory domains with
SRAM at 100 MHz
•
Supports memory size 2 MB, or 4 MB
• For 24+2, two SRAM domains (2 MB or 4 MB) are
required.
•
•
Port Mirroring to a dedicated port or port 23
Built-in reset logic triggered by system
• For 24+2 stacking (2 G per stacking port), two ZBT
domains (2 MB or 4 MB) are required.
malfunction
•
•
•
•
Applies centralized shared memory architecture
Up to 64K MAC addresses
•
•
I2C EEPROM for configuration
Traffic Classification
Maximum throughput is 6.4 Gbps non-blocking
• 4 transmission priorities for Fast Ethernet ports with 2
dropping levels
High performance packet forwarding (19.047 M
packets per second) at full wire speed
• Classification based on:
•
•
•
Full Duplex Ethernet IEEE 802.3x Flow Control
Backpressure flow control for Half Duplex ports
-
-
Port based priority
VLAN Priority field in VLAN tagged frame
Supports Ethernet multicasting and broadcasting
and flooding control
Frame Data Buffer A
SRAM (1 M / 2 M)
Frame Data Buffer B
SRAM (1 M / 2 M)
FDB Interface
LED
Search
Engine
MCT
Link
FCB
Frame Engine
GMII/
GMII/
24 x 10 /100
PCS
PCS
Port
24
Management
Module
Parallel/
Serial
RMII
Port
25
Ports 0 - 23
Figure 1 - MVTX2603 System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
MVTX2603
Data Sheet
-
-
DS/TOS field in IP packet
UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
• The precedence of the above classifications is programmable
QoS Support
•
• Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and
WFQ service disciplines
• Provides 2 levels of dropping precedence with WRED mechanism
• User controls the WRED thresholds
• Buffer management: per class and per port buffer reservations
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID.
•
•
3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10/100 ports, with up to 4 10/100
ports per group
Full set of LED signals provided by a serial interface or 6 LED signals dedicated to Gigabit port status only
(without serial interface)
•
•
•
Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports
Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports
Built-In Self Test for internal and external SRAM
Description
The MVTX2603 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 24 ports at 10/100 Mbps, 2 ports at 1000 Mbps. The Gigabit ports can also support 10/100 M and 2 G
stacking modes.
The chip supports up to 64 K MAC addresses. The centralized shared memory architecture permits a very high
performance packet forwarding rate at up to 9.524 M packets per second at full wire speed. The chip is optimized to
provide low-cost, high-performance workgroup switching.
Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate
bandwidth of 12.8 Gbps to support full wire speed on all ports simultaneously. In the 24+2 stacking (2 G per
stacking port) configuration, 2 ZBT domains are needed.
With delay bounded, strict priority, and/or WFQ transmission scheduling and WRED dropping schemes, the
MVTX2603 provides powerful QoS functions for various multimedia and mission-critical applications. The chip
provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is
assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged
frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The MVTX2603 recognizes a total of
16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).
The MVTX2603 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports
and the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load
sharing can be used to group ports between interlinked switches to increase the effective network bandwidth.
In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The MVTX2603 also supports a per-
system option to enable flow control for best effort frames even on QoS-enabled ports.
The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to
SERDES chips. The PCS can be bypassed to provide a GMII interface.
The MVTX2603 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are
capable of directly interfacing to LVTTL levels. The MVTX2603 is packaged in a 553-pin Ball Grid Array package.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Table of Contents
1.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Frame Data Buffer (FDB) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 GMII/PCS MAC Module (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Physical Coding Sublayer (PCI) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 10/100 MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Configuration Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7 Search Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.8 LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.9 Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.0 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Read Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Stacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 MVTX2603 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.0 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 ZBT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Detailed Memory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Search Engine Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Search, Learning, and Aging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 Port Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 TxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Table of Contents
7.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Four QoS Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.3 Delay Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.4 Strict Priority and Best Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.5 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.6 Shaper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.7 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.8 Buffer Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.8.1 Dropping When Buffers Are Scarce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.9 MVTX2603 Flow Control Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.9.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.9.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.10 Mapping to IETF Diffserv Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.4 Trunking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.0 Port Mirroring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.1 Port Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2 Setting Registers for Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.0 TBI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.0 GPSI (7WS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.1 GPSI Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.2 SCAN LINK and SCAN COL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.0 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.1 LED Interface Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.2 Port Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.3 LED Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
13.0 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.1 MVTX2603 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.2 Group 0 Address MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.2.1 ECR1Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.2.2 ECR2Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.2.3 GGControl – Extra GIGA Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.3 Group 1 Address VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.3.1 AVTCL – VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.3.2 AVTCH – VLAN Type Code Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.3.3 PVMAP00_0 – Port 00 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
13.3.4 PVMAP00_1 – Port 00 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.3.5 PVMAP00_2 – Port 00 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.3.6 PVMAP00_3 – Port 00 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.4 Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.4.1 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
13.4.2 TRUNK0_MODE– Trunk group 0 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13.4.3 TRUNK1_MODE – Trunk group 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
13.5 Group 4 Address Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.5.1 TX_AGE – Tx Queue Aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.5.2 AGETIME_LOW – MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.5.3 AGETIME_HIGH –MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Data Sheet
Table of Contents
13.5.4 SE_OPMODE – Search Engine Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13.6 Group 5 Address Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13.6.1 FCBAT – FCB Aging Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13.6.2 QOSC – QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13.6.3 FCR – Flooding Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13.6.4 AVPML – VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.6.5 AVPMM – VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.6.6 AVPMH – VLAN Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.6.7 TOSPML – TOS Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.6.8 TOSPMM – TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.6.9 TOSPMH – TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.6.10 AVDM – VLAN Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.6.11 TOSDML – TOS Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.6.12 BMRC - Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.6.13 UCC – Unicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.6.14 MCC – Multicast Congestion Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.6.15 PR100 – Port Reservation for 10/100 ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.6.16 PRG – Port Reservation for Giga ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.6.17 SFCB – Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.6.18 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.6.19 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.6.20 C4RS – Class 4 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.6.21 C5RS – Class 5 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.6.22 C6RS – Class 6 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.6.23 C7RS – Class 7 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.6.24 Classes Byte Limit Set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13.6.25 Classes Byte Limit Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13.6.26 Classes Byte Limit Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13.6.27 Classes Byte Limit Set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13.6.28 Classes Byte Limit Giga Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13.6.29 Classes Byte Limit Giga Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13.6.30 Classes WFQ Credit Set 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13.6.31 Classes WFQ Credit Set 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.6.32 Classes WFQ Credit Set 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.6.33 Classes WFQ Credit Set 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13.6.34 Classes WFQ Credit Port G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.6.35 Classes WFQ Credit Port G2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13.6.36 Class 6 Shaper Control Port G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.6.37 Class 6 Shaper Control Port G2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.6.38 RDRC0 – WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.6.39 RDRC1 – WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.6.40 User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.6.40.1 USER_PORT0_(0~7) – User Define Logical Port (0~7). . . . . . . . . . . . . . . . . . . . . . . . . . . 62
13.6.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority. . . . . . . . . . . . . 63
13.6.40.3 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority. . . . . . . . . . . . . 63
13.6.40.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority. . . . . . . . . . . . . 63
13.6.40.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority. . . . . . . . . . . . . 63
13.6.40.6 USER_PORT_ENABLE [7:0] – User Define Logic 7 to 0 Port Enables . . . . . . . . . . . . . . . 63
13.6.40.7 WELL_KNOWN_PORT [1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . 64
13.6.40.8 WELL_KNOWN_PORT [3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . 64
13.6.40.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . 64
13.6.40.10 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority . . . . . 64
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13.6.40.11 WELL KNOWN_PORT_ENABLE [7:0] – Well Known Logic 7 to 0 Port Enables. . . . . . . 65
13.6.40.12 RLOWL – User Define Range Low Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.6.40.13 RLOWH – User Define Range Low Bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.6.40.14 RHIGHL – User Define Range High Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.6.40.15 RHIGHH – User Define Range High Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.6.40.16 RPRIORITY – User Define Range Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
13.7 Group 6 Address MISC Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7.1 MII_OP0 – MII Register Option 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7.2 MII_OP1 – MII Register Option 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7.3 FEN – Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13.7.4 MIIC0 – MII Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.7.5 MIIC1 – MII Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.7.6 MIIC2 – MII Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
13.7.7 MIIC3 – MII Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.7.8 MIID0 – MII Data Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.7.9 MIID1 – MII Data Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.7.10 LED Mode – LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
13.7.11 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.8 Group 7 Address Port Mirroring Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.8.1 MIRROR1_SRC – Port Mirror source port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.8.2 MIRROR1_DEST – Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
13.8.3 MIRROR2_SRC – Port Mirror source port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.8.4 MIRROR2_DEST – Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.9 Group F Address CPU Access Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.9.1 GCR-Global Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.9.2 DCR-Device Status and Signature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.9.3 DCR1-Giga port status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
13.9.4 DPST – Device Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.9.5 DTST – Data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
13.9.6 PLLCR - PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13.9.7 LCLK - LA_CLK delay from internal OE_CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
13.9.8 OECLK - Internal OE_CLK delay from SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13.9.9 DA – DA Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
13.10 TBI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
13.10.1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
13.10.2 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
13.10.3 Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
13.10.4 Link Partner Ability Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
13.10.5 Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
13.10.6 Extended Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.1.1 Encapsulated View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.2 Ball – Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.2.1 Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.3 Ball – Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.4 AC/DC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.4.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.4.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.4.4 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14.5 Local Frame Buffer SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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Table of Contents
14.5.1 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.6 Local Switch Database SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.6.1 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.7 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.7.1 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.7.2 Gigabit Media Independent Interface - Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14.7.3 Ten Bit Interface - Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14.7.4 Gigabit Media Independent Interface - Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14.7.5 Ten Bit Interface - Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
14.7.6 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14.7.7 SCANLINK SCANCOL Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14.7.8 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
14.7.9 I2C Input Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
14.7.10 Serial Interface Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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MVTX2603
Data Sheet
List of Figures
Figure 1 - MVTX2603 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Data Transfer Format for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3 - Write Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4 - Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - MVTX2603 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only) . . . . . . . . . . . . . . . . . . . . 15
Figure 6 - Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 - Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8 - Memory Configuration For: 2 Banks, 1 Layer, 2 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9 - Memory Configuration For: 2 Banks, 2 Layer, 4 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11 - Memory Configuration For: 2 Banks, 2 Layers, 4 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13 - Buffer Partition Scheme Used to Implement MVTX2603 Buffer Management . . . . . . . . . . . . . . . . . . 30
Figure 14 - TBI Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15 - GPSI (7WS) Mode Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16 - SCAN LINK and SCAN COLLISON Status Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17 - Timing Diagram of LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18 - Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 19 - Local Memory Interface – Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 20 - Local Memory Interface - Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 21 - Local Memory Interface – Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 22 - Local Memory Interface - Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 23 - AC Characteristics – Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 24 - AC Characteristics – Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 25 - AC Characteristics- GMII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 26 - AC Characteristics – Gigabit Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 27 - Gigabit TBI Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 28 - Gigabit TBI Interface Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 29 - AC Characteristics- GMII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 30 - AC Characteristics – Gigabit Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 31 - Gigabit TBI Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 32 - Gigabit TBI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 33 - AC Characteristics – LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 34 - SCANLINK SCANCOL Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 35 - SCANLINK, SCANCOL Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 36 - MDIO Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 37 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 38 - I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 39 - I2C Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 40 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 41 - Serial Interface Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
List of Tables
Table 1 - Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2 - PVMAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3 - Supported Memory Configurations (Pipeline SBRAM Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4 - Supported Memory Configurations (ZBT Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5 - Options for Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6 - Two-dimensional World Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8 - Four QoS Configurations for a Gigabit Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7 - Four QoS Configurations for a 10/100 Mbps Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9 - WRED Drop Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10 - Mapping between MVTX2603 and IETF Diffserv Classes for Gigabit Ports . . . . . . . . . . . . . . . . . . . . . 32
Table 11 - Mapping between MVTX2603 and IETF Diffserv Classes for 10/100 Ports . . . . . . . . . . . . . . . . . . . . . 32
Table 12 - MVTX2603 Features Enabling IETF Diffserv Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13 - Reset & Bootstrap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 14 - AC Characteristics – Local Frame Buffer SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 15 - AC Characteristics – Local Switch Database SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . 98
Table 16 - AC Characteristics – Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 17 - AC Characteristics – Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 18 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 19 - Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 20 - AC Characteristics – Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 21 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 22 - Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 23 - AC Characteristics – LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 24 - SCANLINK, SCANCOL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 25 - MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 26 - I2C Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 27 - Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
1.0 Block Functionality
1.1 Frame Data Buffer (FDB) Interfaces
The FDB interface supports pipelined synchronrous burst SRAM (SBRAM) memory at 100 MHz. To ensure a non-
blocking switch, two memory domains are required. Each domain has a 64 bit wide memory bus. At 100 MHz, the
aggregate memory bandwidth is 12.8 Gbps, which is enough to support 24 10/100 Mbps and 2 Gigabit ports at full
wire speed switching. For 24+ 2 stacking application, ZBT memory at 125 MHz is required.
The Switching Database is also located in the external SBRAM; it is used for storing MAC addresses and their
physical port number. It is duplicated and stored in both memory domains. Therefore, when the system updates the
contents of the switching database, it has to write the entry to both domains at the same time.
1.2 GMII/PCS MAC Module (GMAC)
The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface between
the Frame Engine (FE) and the external physical device (PHY).
The MVTX2603 GMAC implements both GMII and MII interfaces, which offers a simple migration from 10/100 to
1 G. The GMAC of the MVTX2603 meets the IEEE 802.3Z specification. It is able to operate in 10 M/100 M either
Half or Full Duplex mode with a back pressure/flow control mechanism or in 1 G full duplex mode with flow control
mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. PHY
addresses for GMAC are 01h and 02h.
1.3 Physical Coding Sublayer (PCI) Interface
For the MVTX2603, the 1000BASE-X PCI Interface is designed internally and may be utilized in the absence of a
GMII. The PCS incorporates all the functions required by the GMII to include encoding (decoding) 8B GMII data to
(from) 8B/10B TBI format for PHY communication and generating Collision Detect (COL) signals for half-duplex
mode. It also manages the Auto negotiation process by informing the management entity that the PHY is ready for
communications. The on-chip TBI may be disabled if TBI exists within the Gigabit PHY. The TBI interface provides
a uniform interface for all 1000 Mbps PHY implementations.
The PCS comprises the PCS Transmit, Synchronization, PCS Receive and Auto negotiation processes for
1000BASE-X.
The PCS Transmit process sends the TBI signals TXD [9:0] to the physical medium and generates the GMII
Collision Detect (COL) signal based on whether a reception is occurring simultaneously with transmission.
Additionally, the Transmit process generates an internal “transmitting” flag and monitors Auto negotiation to
determine whether to transmit data or to reconfigure the link.
The PCS Synchronization process determines whether or not the receive channel is operational.
The PCS Receive process generates RXD [7:0] on the GMII from the TBI data [9:0], and the internal “receiving” flag
for use by the Transmit processes.
The PCS Auto negotiation process allows the MVTX2603 to exchange configuration information between two
devices that share a link segment and to automatically configure the link for the appropriate speed of operation for
both devices.
1.4 10/100 MAC Module (RMAC)
The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame
Engine (FE) and the external physical device (PHY). The MVTX2603 has two interfaces, RMII or Serial (only for
10 M). The 10/100 MAC of the MVTX2603 device meets the IEEE 802.3 specification. It is able to operate in either
Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit
upon collision for up to 16 total transmissions. The PHY address for 24 10/100 MAC are from 08h to 1fh.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
1.5 Configuration Interface Module
The MVTX2603 supports a serial and an I2C interface, which provides an easy way to configure the system. Once
configured, the resulting configuration can be stored in an I2C EEPROM.
1.6 Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent to
the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch
response from the search engine, the frame engine performs transmission scheduling based on the frame’s priority.
The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.7 Search Engine
The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2). It
also performs MAC learning, priority assignment and trunking functions.
1.8 LED Interface
The LED interface provides a serial interface for carrying 24+2 port status signals. It can also provide direct status
pins (6) for the two Gigabit ports.
1.9 Internal Memory
Several internal tables are required and are described as follows:
•
Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame
stored in the FDB, e.g., frame size, read/write pointer, transmission priority, etc.
•
MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the
external MAC Table. The external MAC table is located in the FDB Memory.
Note: the external MAC table is located in the external SBRAM Memory.
2.0 System Configuration
2.1 Configuration Mode
The MVTX2603 can be configured by EEPROM (24C02 or compatible) via an I2C interface at boot time, or via a
synchronous serial interface during operation.
2
2.2 I C Interface
The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure
2 depicts the data transfer format.
START SLAVE ADDRESS R/W ACK DATA 1 (8 bits) ACK DATA 2 ACK
DATA M
ACK STOP
Figure 2 - Data Transfer Format for I2C Interface
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
2.2.1 Start Condition
Generated by the master (in our case, the MVTX2603). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus is
free, both lines are High.
2.2.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.2.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.2.4 Acknowledgment
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let
the master generate the Stop condition.
2.2.5 Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB first.
2.2.6 Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition
occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
The I2C interface serves the function of configuring the MVTX2603 at boot time. The master is the MVTX2603 and
the slave is the EEPROM memory.
2.3 Synchronous Serial Interface
The synchronous serial interface serves the function of configuring the MVTX2603 not at boot time but via a PC.
The PC serves as master and the MVTX2603 serves as slave. The protocol for the synchronous serial interface is
nearly identical to the I2C protocol. The main difference is that there is no acknowledgment bit after each byte of
data transferred.
The unmanaged MVTX2603 uses a synchronous serial interface to program the internal registers. To reduce the
number of signals required, the register address, command and data are shifted in serially through the D0 pin.
STROBE- pin is used as the shift clock. AUTOFD- pin is used as data return path.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Each command consists of four parts.
START pulse
Register Address
Read or Write command
Data to be written or read back
Any command can be aborted in the middle by sending a ABORT pulse to the MVTX2603.
A START command is detected when D0 is sampled high when STROBE- rise and D0 is sampled low when
STROBE- fall.
An ABORT command is detected when D0 is sampled low when STROBE- rise and D0 is sampled high when
STROBE- fall.
2.3.1 Write Command
STROBE-
2 extra clock cycles
after last transfer
transfer
D0 D1 D2 D3 D4 D5 D6 D7
D0
A0 A1 A2 ... A9 A10 A11
W
START ADDRESS
COMMAND DATA
Figure 3 - Write Command
2.3.2 Read Command
STROBE-
R
A10 A11
A0 A1 A2 ...
A
9
D0
START
AUTOFD-
ADDRESS
COMMAND
DATA
4
D0
D
1
D2 D3 D4 D5 D6 D7
Figure 4 - Read Command
All registers in MVTX2603 can be modified through this synchronous serial interface.
2.4 Stacking
The two Gigabits ports can be used as link between boxes. Each Gigabit port can be accelerated to 2 Gpbs if
desired (in conjunction with ZBT memory domains at 125 MHz). If both Gigabit ports are used for this purpose, this
provides a total of 4 Gbps of bandwidth between devices.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
3.0 MVTX2603 Data Forwarding Protocol
3.1 Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available, because of advance buffer reservations.
The memory (SRAM) interface consists of two 64-bit buses, connected to two SRAM banks, A and B. The Receive
DMA (RxDMA) is responsible for multiplexing the data and the address. On a port’s “turn,” the RxDMA will move 8
bytes (or up to the end-of-frame) from the port’s associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response
queue of the frame engine when done. Among other information, the search engine will have resolved the
destination port of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to
decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy
at the destination. If the frame is not dropped, then the TxQ manager links the frame’s FCB to the correct per-port-
per-class TxQ. Unicast TxQ’s are linked lists of transmission jobs, represented by their associated frames’ FCB’s.
There is one linked list for each transmission class for each port. There are 4 transmission classes for each of the
24 10/100 ports and 8 classes for each of the two Gigabit ports – a total of 112 unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a
port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for
another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among
the head-of-line (HOL) frames from the per-class queues for that port using a Zarlink Semiconductor scheduling
algorithm.
The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port’s turn, the
TxDMA will move 8 bytes (or up to the EOF) from memory into the port’s associated TxFIFO. After reading the EOF,
the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release
requests.
The frame is transmitted from the TxFIFO to the line.
3.2 Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop
can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is
dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the
multicast packet’s destinations. If so, then the frame is dropped at some destinations but not others and the FCB is
not released.
If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast
queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames).
There are 2 multicast queues for each of the 24 10/100 ports. The queue with higher priority has room for 32 entries
and the queue with lower priority has room for 64 entries. There are 4 multicast queues for each of the two Gigabit
ports. The sizes of the queues are: 32 entries (higher priority queue, 32 entries, 32 entries and 64 entries (lower
priority queue). There is one multicast queue for every two priority classes. For the 10/100 ports to map the 8
transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the gigabit ports to map the 8 transmit
priorities into 4 multicast queues, the LSB are discarded.
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Data Sheet
During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one
logical queue. The older head of line of the two queues is forwarded first.
The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to
which the frame is destined.
4.0 Memory Interface
4.1 Overview
The MVTX2603 provides two 64-bit wide SRAM banks, SRAM Bank A and SRAM Bank B, with a 64-bit bus
connected to each. Each DMA can read and write from both bank A and bank B. The following figure provides an
overview of the MVTX2603 SRAM banks.
SRAM Bank A
SRAM Bank B
TXDMA
16-23
TXDMA
0-7
TXDMA
8-15
RXDMA
0-7
RXDMA
8-15
RXDMA
16-23
Figure 5 - MVTX2603 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only)
4.2 ZBT Support
The MVTX2603 supports Zero Bus Turnaround (ZBT). ZBT is a synchronous SRAM architecture that is optimized
for networking and telecommunications applications. It can significantly increase the switch’s internal bandwidth
when compared to standard Pipeline SyncBurst SRAM.
The ZBT architecture is optimized for switching and other applications with highly random READs and WRITEs.
ZBT SRAMs eliminate all idle cycles when turning the data bus around from a WRITE operation to a READ
operation (or vice versa). This feature results in dramatic performance improvements in systems that have such
traffic patterns (that is, frequent and random read and write access to the SRAM).
Please refer to the ZBT Application Note for further details.
4.3 Detailed Memory Information
Because the bus for each bank is 64-bits wide, frames are broken into 8-byte granules, written to and read from
memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B, and so
on in alternating fashion. When reading frames from memory, the same procedure is followed, first from A, then
from B and so on.
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Data Sheet
The reading and writing from alternating memory banks can be performed with minimal waste of memory
bandwidth. What’s the worst case? For any speed port, in the worst case, a 1-byte-long EOF granule gets
written to Bank A. This means that a 7-byte segment of Bank A bandwidth is idle, and furthermore, the next 8-byte
segment of Bank B bandwidth is idle, because the first 8 bytes of the next frame will be written to Bank A, not B.
This scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the
interframe gap is 20 bytes.
Search engine data is written to both banks in parallel. In this way, a search engine read operation can be
performed by either bank at any time without a problem.
4.4 Memory Requirements
To speed up searching and decrease memory latency, the external MCT database is duplicated in both memory
banks. To support 64 K MCT, 4 MB memory is required. Up to 2 K frame buffers are supported and they will use
3 MB of memory. The maximum system memory requirement is 4 MB. If less memory is desired, the configuration
can scale down proportionally.
Bank A
Bank B
Frame Buffer
Max MAC Address
32 K
64 k
1 M
2 M
1 M
2 M
1 K
2 K
Table 1 - Memory Configuration
1 M Bank A
1 M Bank B 2 M Bank A 2 M Bank B
0.75 M
0.25 M
0.75 M
0.25 M
1.5 M
0.5 M
1.5 M
0.5 M
Frame Data Buffer (FDR) Area
MAC Address Control Table (MCT) Area
Figure 6 - Memory Map
5.0 Search Engine
5.1 Search Engine Overview
The MVTX2603 search engine is optimized for high throughput searching, with enhanced features to support:
•
•
•
•
•
•
Up to 64 K MAC addresses
3 groups of port trunking (1 for the two Gigabit ports, and 2 others)
Traffic classification into 4 (or 8 for Gigabit) transmission priorities, and 2 drop precedence levels
Flooding, Broadcast, Multicast Storm Control
MAC address learning and aging
Port based VLAN
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Data Sheet
5.2 Basic Flow
Shortly after a frame enters the MVTX2603 and is written to the Frame Data Buffer (FDB), the frame engine
generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of
the frame, which contain all the necessary information for the search engine to perform its task. When the search
engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that
queue for scheduling and forwarding.
In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch
request. Among the information extracted are the source and destination MAC addresses, the transmission and
discard priorities, whether the frame is unicast or multicast. Requests are sent to the external SRAM to locate the
associated entries in the external hash table.
When all the information has been collected from external SRAM, the search engine has to compare the MAC
address on the current entry with the MAC address for which it is searching. If it is not a match, the process is
repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to
the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address
unknown) or flooding (destination MAC address unknown).
In addition, port based VLAN information is used to select the correct set of destination ports for the frame (for
multicast) or to verify that the frame’s destination port is associated with the VLAN (for unicast).
If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port
number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the
source and destination MAC addresses.
As stated earlier, when all the information is compiled the switch response is generated.
5.3 Search, Learning, and Aging
5.3.1 MAC Search
The search block performs source MAC address and destination MAC address searching. As we indicated earlier,
if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or
the end of the list is reached.
The port based VLAN bitmap is used to determine whether the frame should be forwarded to the outgoing port.
When the egress port is not included in the ingress port VLAN bitmap, the packet is discarded.
The MAC search block is also responsible for updating the source MAC address timestamp and the VLAN port
association timestamp, used for aging.
5.3.2 Learning
The learning module learns new MAC addresses and performs port change operations on the MCT database. The
goal of learning is to update this database as the networking environment changes over time. Learning and port
change will be performed based on memory slot availability only.
5.3.3 Aging
Aging time is controlled by register 400h and 401h.
The aging module scans and ages MCT entries based on a programmable “age out” time interval. As we indicated
earlier, the search module updates the source MAC address timestamps for each frame it processes. When an
entry is ready to be aged, the entry is removed from the table.
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Data Sheet
5.4 Quality of Service
Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over
various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by
some real-time and interactive traffic) and improved loss characteristics.
Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate
traffic, a service level known as “best effort” attempts to get all the packets to their intended destinations with
minimum delay; however, there are no guarantees. In a congested network or when a low-performance
switch/router is overloaded, “best effort” becomes unsuitable for delay-sensitive traffic and mission-critical data
transmission.
The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and
multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously
plagued such “best effort” networking systems. QoS provides Ethernet networks with the breakthrough technology
to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth.
Extensive core QoS mechanisms are built into the MVTX2603 architecture to ensure policy enforcement and
buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port.
In the MVTX2603, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly.
The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is
provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which
the frames and packets belong. For example, the overall service given to frames and packets in the premium class
will be better than that given to the standard class; the premium class is expected to experience lower loss rate or
delay.
The MVTX2603 supports the following QoS techniques:
•
•
•
In a port-based setup, any station connected to the same physical port of the switch will have the same
transmit priority.
In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be
mapped to different queues in the switch to provide QoS.
In a TOS/DS-based set up, TOS stands for “Type of Service” that may include “minimize delay,” “maximize
throughput,” or “maximize reliability.” Network nodes may select routing paths or forwarding behaviours that
are suitably engineered to satisfy the service request.
•
In a logical port-based set up, a logical port provides the application information of the packet. Certain
applications are more sensitive to delays than others; using logical ports to classify packets can help speed
up delay sensitive applications, such as VoIP.
5.5 Priority Classification Rule
Figure 7 on page 19 shows the MVTX2603 priority classification rule
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MVTX2603
Data Sheet
Yes
Use Default Port Settings
Fix Port Priority ?
No
Yes
TOS Precedence over VLAN?
(FCR Register, Bit 7)
Use Default Port Settings
No
No
No
No
IP Frame ?
IP
VLAN Tag ?
Yes
Yes
Use Logical Port
Yes
Use Logical Port
Yes
No
Use TOS
Use VLAN Priority
Figure 7 - Priority Classification Rule
5.6 Port Based VLAN
An administrator can use the PVMAP Registers to configure the MVTX2603 for port-based VLAN. For example,
ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the
Administrative VLAN. The MVTX2603 determines the VLAN membership of each packet by noting the port on
which it arrives. From there, the MVTX2603 determines which outgoing port(s) is/are eligible to transmit each
packet, or whether the packet should be discarded.
Destination Port Numbers Bit Map
Port Registers
26
0
…
2
1
1
1
0
0
Register for Port #0
PVMAP00_0[7:0] to PVMAP00_3[2:0]
Register for Port #1
0
0
1
0
0
0
1
0
PVMAP01_0[7:0] to PVMAP01_3[2:0]
Register for Port #2
PVMAP02_0[7:0] to PVMAP02_3[2:0]
…
Register for Port #26
0
0
0
0
PVMAP26_0[7:0] to PVMAP26_3[2:0]
Table 2 - PVMAP Register
For example, in the above table, a 1 denotes that an outgoing port is eligible to receive a packet from an incoming
port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port.
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Data Sheet
In this example:
•
•
•
Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2
Data packets received at port #1 are eligible to be sent to outgoing ports 0, and 2
Data packets received at port #2 are not eligible to be sent to ports 0 and 1
5.7 Memory Configurations
The MVTX2603 supports the following memory configurations. SBRAM modes support 1 M and 2 M configurations,
while ZBT mode supports 4 M configurations, 2 M per domain (bank). For detail connection information, please
reference the memory application note.
1 M per bank
(Bootstrap pin
TSTOUT7 = open)
2 M per bank
(Bootstrap pin
Configuration
Connections
TSTOUT7 = pull down)
Single Layer
Two 128 K x 32
Two 256 K x 32
SRAM/bank
Connect 0E# and WE#
(Bootstrap pin
SRAM/bank or
TSTOUT13 = open)
One 128 K x 64 SRAM/bank
Double Layer
NA
Four 128 K x 32
Connect 0E0# and
WE0# Connect 0E1#
and WE1#
(Bootstrap pin
SRAM/bank or
TSTOUT13 = pull down)
Two 128 K x 64 SRAM/bank
Table 3 - Supported Memory Configurations (Pipeline SBRAM Mode)
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Data Sheet
Configuration
2 M per bank
Connections
Single Layer
Two 256 K x 32 ZBT SRAM/bank
or One 256 K x 64 ZBT SRAM/bank
Connect ADS# to Layer 0 chipselect pin
(Bootstrap pin
TSTOUT13 = open)
Double Layer
Four 128 K x 32 ZBT SRAM/bank
or Two 128 K x 64 ZBT SRAM/bank
Connect ADS# to Layer 0 chipselect pin
and 0E# to Layer 1 chipselect pin
(Bootstrap pin
TSTOUT13 = pull down)
Table 4 - Supported Memory Configurations (ZBT Mode)
Frame data Buffer
Only Bank A
Bank A and Bank B
1 M/bank 2 M/bank
Bank A and Bank B
1 M
2 M
1 M/bank
2 M/bank
(SRAM)
(SRAM)
(SRAM)
(SRAM)
(ZBT SRAM)
(ZBT SRAM)
MVTX2601
MVTX2602
MVTX2603
X
X
X
X
X
X
MVTX2603
X (125 Mhz)
X (125 Mhz)
X (125 Mhz)
X (125 Mhz)
(Gigabit ports in 2 giga mode)
MVTX2604
X
X
MVTX2604
(Gigabit ports in 2 giga mode)
Table 5 - Options for Memory Configuration
Bank B (1M One Layer)
Bank A (1M One Layer)
Data LA_D[63:32]
Data LB_D[63:32]
Data LB_D[31:0]
Data LA_D[31:0]
SRAM
Memory
128K
SRAM
Memory
128K
Memory
128K
32 bits
Memory
128K
32 bits
32 bits
32 bits
Address LB_A[19:3]
Address LA_A[19:3]
Figure 8 - Memory Configuration For: 2 Banks, 1 Layer, 2 MB Total
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Data Sheet
BANK A (2M Two Layers)
BANK B (2M Two Layers)
Data LA_D[63:32]
Data LB_D[63:32]
Data LA_D[31:0]
Data LB_D[31:0]
SRAM
Memory
128 K
SRAM
SRAM
Memory
128 K
SRAM
Memory
128 K
Memory
128 K
32 bits
32 bits
32 bits
32 bits
SRAM
Memory
128 K
SRAM
Memory
128 K
SRAM
Memory
128 K
SRAM
Memory
128 K
32 bits
32 bits
32 bits
32 bits
Address LA_A[19:3]
Address LB_A[19:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Pull Down, TSTOUT4 = Open
Figure 9 - Memory Configuration For: 2 Banks, 2 Layer, 4 MB Total
BANK A (2M One Layer)
BANK B (2M One Layer)
Data LA_D[63:32]
Data LB_D[63:32]
Data LA_D[31:0]
Data LB_D[31:0]
SRAM
Memory
256 K
SRAM
Memory
256 K
Memory
256 K
Memory
256 K
32 bits
32 bits
32 bits
32 bits
Address LA_A[20:3]
Address LB_A[20:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open
Figure 10 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB
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Data Sheet
BANK A (2M Two Layers)
BANK B (2M Two Layers)
Data LA_D[63:32]
Data LB_D[63:32]
Data LA_D[31:0]
Data LB_D[31:0]
ZBT
ZBT
ZBT
ZBT
Memory
128 K
32 bits
Memory
128 K
Memory
128 K
32 bits
Memory
128 K
32 bits
32 bits
ZBT
ZBT
ZBT
ZBT
Memory
128 K
32 bits
Memory
128 K
32 bits
Memory
128 K
32 bits
Memory
128 K
32 bits
Address LA_A[19:3]
Address LB_A[19:3]
Figure 11 - Memory Configuration For: 2 Banks, 2 Layers, 4 MB Total
BANK A (2M One Layer)
BANK B (2M One Layer)
Data LA_D[63:32]
Data LB_D[63:32]
Data LA_D[31:0]
Data LB_D[31:0]
ZBT
ZBT
ZBT
ZBT
Memory
256 K
32 bits
Memory
256 K
32 bits
Memory
256 K
32 bits
Memory
256 K
32 bits
Address LA_A[20:3]
Address LB_A[20:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Pull Down
Figure 12 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB
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Data Sheet
6.0 Frame Engine
6.1 Data Forwarding Summary
•
When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the
FDB. Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
•
•
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast
and its destination port or ports.
•
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon
receiving a Transmission Scheduling Request, the device will format an entry in the appropriate
Transmission Scheduling Queue (TxSch Q) or Queues. There are 4 TxSch Q for each 10/100 port (and 8
per Gigabit port), one for each priority. Creation of a queue entry either involves linking a new job to the
appropriate linked list if unicast or adding an entry to a physical queue if multicast.
•
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of
one of the TxSch Qs, according to the transmission scheduling algorithm (to ensure per-class quality of
service). The unicast linked list and the multicast queue for the same port-class pair are treated as one
logical queue. The older HOL between the two queues goes first. For 10/100 ports multicast queue 0 is
associated with unicast queue 0 and multicast queue 1 is associated with unicast queue 2. For Gigabit ports
multicast queue 0 is associated with unicast queue 0, multicast queue 1 with unicast queue 2, multicast
queue 2 with unicast queue 4 and multicast queue 3 with unicast queue 6.
•
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of
the destination port.
6.2 Frame Engine Details
This section briefly describes the functions of each of the modules of the MVTX2603 frame engine.
6.2.1 FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure.
The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be
determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging and for linking
unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin
and the aging time is defined in register FCBAT.
6.2.2 Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch
request.
6.2.3 RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each
frame for use by the search engine when the switch request has been made.
6.2.4 TxQ Manager
First, the TxQ manager checks the per-class queue status and global reserved resource situation, and using this
information, makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the
TxQ manager requests that the FCB manager link the unicast frame’s FCB to the correct per-port-per-class TxQ. If
multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger
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Data Sheet
source port flow control for the incoming frame’s source if that port is flow control enabled. Second, the TxQ
manager handles transmission scheduling; it schedules transmission among the queues representing different
classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to
the correct port control module.
6.3 Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes
start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control
module requests that the buffer be released.
6.4 TxDMA
The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the
port control modules.
7.0 Quality of Service and Flow Control
7.1 Model
Quality of service is an all-encompassing term for which different people have different interpretations. In general,
the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also
assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager
knows his applications, such as voice, file transfer, or web browsing, and their relative importance. The manager
can then subdivide the applications into classes and set up a service contract with each. The contract may consist
of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to
the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic
is policed or shaped, we may be able to provide additional assurances about our switch’s performance.
Table 6 on page 25 shows examples of QoS applications with three transmission priorities, but best effort (P0)
traffic may form a fourth class with no bandwidth or latency assurances. Gigabit ports actually have eight total
transmission priorities.
Total
Low Drop Probability
(low-drop)
High Drop Probability
(high-drop)
Goals
Assured Bandwidth
(user defined)
Highest transmission 50 Mbps
priority, P3
Apps: phone calls, circuit
emulation.
Apps: training video.
Latency: < 1 ms.
Latency: < 1 ms.
Drop: No drop if P3 not
oversubscribed.
Drop: No drop if P3 not
oversubscribed; first P3 to
drop otherwise.
Middle transmission
priority, P2
37.5 Mbps
Apps: interactive apps, Web
business.
Apps: non-critical interactive
apps.
Latency: < 4-5 ms.
Drop: No drop if P2 not
oversubscribed.
Latency: < 4-5 ms.
Drop: No drop if P2 not
oversubscribed; first P2 to
drop otherwise.
Table 6 - Two-dimensional World Traffic
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Data Sheet
Low transmission
priority, P1
12.5 Mbps
100 Mbps
Apps: emails, file backups.
Latency: < 16 ms desired, but
not critical.
Apps: casual web browsing.
Latency: < 16 ms desired, but
not critical.
Drop: No drop if P1 not
oversubscribed.
Drop: No drop if P1 not
oversubscribed; first to drop
otherwise.
Total
Table 6 - Two-dimensional World Traffic
A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a
rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-
upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link
utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade the
quality of service (QoS) received by well-behaved classes.
As Table 6 illustrates, the six traffic types may each have their own distinct properties and applications. As shown,
classes may receive bandwidth assurances or latency bounds. In the table, P3, the highest transmission class,
requires that all frames be transmitted within 1 ms, and receives 50% of the 100 Mbps of bandwidth at that port.
Best-effort (P0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any
traffic to offer. It is also possible to add a fourth class that has strict priority over the other three; if this class has
even one frame to transmit, then it goes first. In the MVTX2603, each 10/100 Mbps port will support four total
classes, and each 1000 Mbps port will support eight classes. We will discuss the various modes of scheduling
these classes in the next section.
In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely
lose packets. But poorly behaved users – users who send frames at too high a rate – will encounter frame loss, and
the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some
low-drop frames are dropped, and then all frames in the worst case.
Table 6 shows that different types of applications may be placed in different boxes in the traffic table. For example,
casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the
category of low-loss, low-latency traffic.
7.2 Four QoS Configurations
There are four basic pieces to QoS scheduling in the MVTX2603: strict priority (SP), delay bound, weighted fair
queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation, as shown
in Table 4, “Supported Memory Configurations (ZBT Mode),” and Table 6, “Two-dimensional World Traffic,” . For
10/100 Mbps ports, these modes are selected by the following registers:
QOSC24 [7:6]
QOSC28 [7:6]
QOSC32 [7:6]
QOSC36 [7:6]
CREDIT_C00
CREDIT_C10
CREDIT_C20
CREDIT_C30
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
P3
P2
P1
P0
Op1 (default)
Op2
Delay Bound
BE
BE
SP
Delay Bound
WFQ
Op3
SP
Op4
WFQ
Table 7 - Four QoS Configurations for a 10/100 Mbps Port
These modes are selected by QOSC40 [7:6] and QOSC48 [7:6] for the first and second gigabit ports, respectively.
P7
P6
P5
P4
P3
P2
P1
BE
BE
P0
Op1 (default)
Op2
Delay Bound
SP
Delay Bound
WFQ
Op3
SP
Op4
WFQ
Table 8 - Four QoS Configurations for a Gigabit Port
The default configuration for a 10/100 Mbps port is three delay-bounded queues and one best-effort queue. The
delay bounds per class are 0.8 ms for P3, 2 ms for P2, and 12.8 ms for P1. For a 1 Gbps port, we have a default of
six delay-bounded queues and two best-effort queues. The delay bounds for a 1 Gbps port are 0.16 ms for P7 and
P6, 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. Best effort traffic is only served when there
is no delay-bounded traffic to be served. For a 1 Gbps port, where there are two best-effort queues, P1 has strict
priority over P0.
We have a second configuration for a 10/100 Mbps port in which there is one strict priority queue, two delay
bounded queues, and one best effort queue. The delay bounds per class are 3.2 ms for P2 and 12.8 ms for P1. If
the user is to choose this configuration, it is important that P3 (SP) traffic be either policed or implicitly bounded
(e.g., if the incoming P3 traffic is very light and predictably patterned). Strict priority traffic, if not admission-
controlled at a prior stage to the MVTX2603, can have an adverse effect on all other classes’ performance. For a 1
Gbps port, P7 and P6 are both SP classes and P7 has strict priority over P6. In this case, the delay bounds per
class are 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2.
The third configuration for a 10/100 Mbps port contains one strict priority queue and three queues receiving a
bandwidth partition via WFQ. As in the second configuration, strict priority traffic needs to be carefully controlled. In
the fourth configuration, all queues are served using a WFQ service discipline.
7.3 Delay Bound
In the absence of a sophisticated QoS server and signaling protocol, the MVTX2603 may not know the mix of
incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically adjusts its
scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (HOL)
frames. As a result, we assure latency bounds for all admitted frames with high confidence, even in the presence of
system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards frames at no
detriment to well-behaved classes. Our algorithm also differentiates between high-drop and low-drop traffic with a
weighted random early drop (WRED) approach. Random early dropping prevents congestion by randomly dropping
a percentage of high-drop frames even before the chip’s buffers are completely full, while still largely sparing low-
drop frames. This allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. Finally,
the delay bound algorithm also achieves bandwidth partitioning among classes.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
7.4 Strict Priority and Best Effort
When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. Two
of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used for IETF
expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is important that
strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes.
When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other
classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for best
effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance.
However, in a typical network setting, much best effort traffic will indeed be transmitted and with an adequate
degree of expediency.
Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best
effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the
MVTX2603, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to
enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best
effort and strict priority queues when global buffer resources become scarce.
7.5 Weighted Fair Queuing
In some environments – for example, in an environment in which delay assurances are not required, but precise
bandwidth partitioning on small time scales is essential, WFQ may be preferable to a delay-bounded scheduling
discipline. The MVTX2603 provides the user with a WFQ option with the understanding that delay assurances can
not be provided if the incoming traffic pattern is uncontrolled. The user sets four WFQ “weights” (eight for Gigabit
ports) such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with
error within 2%.
In WFQ mode, though we do not assure frame latency, the MVTX2603 still retains a set of dropping rules that helps
to prevent congestion and trigger higher level protocol end-to-end flow control.
As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority
queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do
indeed drop frames from SP queues for global buffer management purposes. In addition, queue P0 for a 10/100
port (and queues P0 and P1 for a Gigabit port) are treated as best effort from a dropping perspective, though they
still are assured a percentage of bandwidth from a WFQ scheduling perspective. What this means is that these
particular queues are only affected by dropping when the global buffer count becomes low.
7.6 Shaper
Although traffic shaping is not a primary function of the MVTX2603, the chip does implement a shaper for expedited
forwarding (EF). Our goal in shaping is to control the peak and average rate of traffic exiting the MVTX2603.
Shaping is limited to the two Gigabit ports only, and only to class P6 (the second highest priority). This means that
class P6 will be the class used for EF traffic. If shaping is enabled for P6, then P6 traffic must be scheduled using
strict priority. With reference to Table 8 only the middle two QoS configurations may be used.
Peak rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then the
peak rate for shaped traffic is 32/64 * 1000 Mbps = 500 Mbps. Average rate is also a programmable whole number,
no greater than 64, and no greater than the peak rate. For example, if the setting is 16, then the average rate for
shaped traffic is 16/64 * 1000 Mbps = 250 Mbps. As a consequence of the above settings in our example, shaped
traffic will exit the MVTX2603 at a rate always less than 500 Mbps and averaging no greater than 250 Mbps. See
Programming QoS Registers Application Note for more information.
Also, when shaping is enabled, it is possible for a P6 queue to explode in length if fed by a greedy source. The
reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if
the line is idle. Though we do have global resource management, we do nothing to prevent this situation locally. We
assume SP traffic is policed at a prior stage to the MVTX2603.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
7.7 WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified
parameters. The following table summarizes the behavior of the WRED logic.
Table 9 - WRED Drop Thresholds
Px is the total byte count, in the priority queue x. The WRED logic has three drop levels, depending on the value of
N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals
P3*16+P2*4+P1. If using WFQ scheduling, N equals P3+P2+P1. Each drop level from one to three has defined
high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can
be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. In Level 3, all packets are
dropped if the bytes in each priority queue exceed the threshold. Parameters A, B, C are the byte count thresholds
for each priority queue. They can be programmed by the QOS control register (refer to the register group 5).
7.8 Buffer Management
Because the number of FDB slots is a scarce resource and because we want to ensure that one misbehaving
source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept
of buffer management into the MVTX2603. Our buffer management scheme is designed to divide the total buffer
space into numerous reserved regions and one shared pool as shown in Figure 13 on page 30.
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the MVTX2603, its destination port and class are as yet unknown and so the decision to drop or not needs to
be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame
drop discipline after classifying.
Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per
class. The lowest two classes do not receive any buffer reservation. Furthermore, even for 10/100 Mbps ports, a
frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only
four transmission scheduling queues for 10/100 Mbps ports, but as far as buffer usage is concerned, there are still
eight distinguishable classes.
Another segment of the FDB reserves space for each of the 26 ports ethernet port. Two parameters can be set, one
for the source port reservation for 10/100 Mbps ports, and one for the source port reservation for 1 Gbps ports.
These 26 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving
source port.
In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in
the six priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the
shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
The following registers define the size of each section of the frame data buffer:
PR100- Port Reservation for 10/100 Ports
PRG- Port Reservation for Giga Ports
SFCB- Share FCB Size
C2RS- Class 2 Reserve Size
C3RS- Class 3 Reserve Size
C4RS- Class 4 Reserve Size
C5RS- Class 5 Reserve Size
C6RS- Class 6 Reserve Size
C7RS- Class 7 Reserve Size
temporary
reservation
shared pool
S
per-class
reservation
per-source
reservations
per-source
reservations
(2 G)
(24 10/100 M, CPU)
Figure 13 - Buffer Partition Scheme Used to Implement MVTX2603 Buffer Management
7.8.1 Dropping When Buffers Are Scarce
Summarizing the two examples of local dropping discussed earlier in this chapter:
•
If a queue is a delay-bounded queue, we have a multi-level WRED drop scheme, designed to control delay
and partition bandwidth in case of congestion.
•
If a queue is a WFQ-scheduled queue, we have a multi-level WRED drop scheme, designed to prevent
congestion.
In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The
function of buffer management is to make sure that such dropping causes as little blocking as possible.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
7.9 MVTX2603 Flow Control Basics
Because frame loss is unacceptable for some applications, the MVTX2603 provides a flow control option. When
flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a
source port that is sending a packet to this switch to temporarily hold off.
While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When
a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not,
are halted. A single packet destined for a congested output can block other packets destined for uncongested
outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high
confidence when flow control is enabled.
In the MVTX2603, each source port can independently have flow control enabled or disabled. For flow control
enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done so
that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports feed to
only one queue at the destination, the queue of lowest priority. What this means is that if flow control is enabled for
a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible
expense of minimum bandwidth or maximum delay assurances. In addition, these “downgraded” frames may only
use the shared pool or the per-source reserved pool in the FDB; frames from flow control enabled sources may not
use reserved FDB slots for the highest six classes (P2-P7).
The MVTX2603 does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for
frames originating from flow control enabled ports. When this programmable option is active, it is possible that
some packets may be dropped, even though flow control is on. The reason is that intelligent packet dropping is a
major component of the MVTX2603’s approach to ensuring bounded delay and minimum bandwidth for high priority
flows.
7.9.1 Unicast Flow Control
For unicast frames, flow control is triggered by source port resource availability. Recall that the MVTX2603’s buffer
management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a
source port’s reserved FDB slots have been used, then flow control Xoff is triggered.
Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been
released.
Note that the MVTX2603’s per-source-port FDB reservations assure that a source port that sends a single frame to
a congested destination will not be flow controlled.
7.9.2 Multicast Flow Control
In unmanaged mode, flow control for multicast frames is triggered by a global buffer counter. When the system
exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns
below this threshold.
In managed mode, per-VLAN flow control is used for multicast frames. In this case, flow control is triggered by
congestion at the destination. How so? The MVTX2603 checks each destination to which a multicast packet is
headed. For each destination port, the occupancy of the lowest-priority transmission multicast queue (measured in
number of frames) is compared against a programmable congestion threshold. If congestion is detected at even
one of the packet’s destinations then Xoff is triggered.
In addition, each source port has a 26-bit port map recording which port or ports of the multicast frame’s fanout
were congested at the time Xoff was triggered. All ports are continuously monitored for congestion, and a port is
identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were
originally marked as congested in the port map have become uncongested, then Xon is triggered and the 26-bit
vector is reset to zero.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
The MVTX2603 also provides the option of disabling VLAN multicast flow control.
Note: If per-Port flow control is on, QoS performance will be affected. To determine the most efficient way to
program, please refer to the QoS Application Note.
7.10 Mapping to IETF Diffserv Classes
The mapping between priority classes discussed in this chapter and elsewhere is shown below.
P7
P6
EF
P5
P4
P3
P2
P1
P0
VTX
NM
AF0
AF1
AF2
AF3
BE0
BE1
IETF
Table 10 - Mapping between MVTX2603 and IETF Diffserv Classes for Gigabit Ports
As the table illustrates, P7 is used solely for network management (NM) frames. P6 is used for expedited
forwarding service (EF). Classes P2 through P5 correspond to an assured forwarding (AF) group of size 4. Finally,
P0 and P1 are two best effort (BE) classes.
For 10/100 Mbps ports, the classes of Table 12 are merged in pairs—one class corresponding to NM+EF, two AF
classes, and a single BE class.
VTX
P3
P2
P1
P0
IETF
NM+EF
AF0
AF1
BE0
Table 11 - Mapping between MVTX2603 and IETF Diffserv Classes for 10/100 Ports
Features of the MVTX2603 that correspond to the requirements of their associated IETF classes are summarized in
the table below.
Network management (NM) and
Expedited forwarding (EF)
•
•
•
•
Global buffer reservation for NM and EF
Shaper for EF traffic on 1 Gbps ports
Option of strict priority scheduling
No dropping if admission controlled
Assured forwarding (AF)
•
•
•
Four AF classes for 1 Gbps ports
Programmable bandwidth partition, with option of WFQ service
Option of delay-bounded service keeps delay under fixed levels even
if not admission-controlled
•
•
Random early discard, with programmable levels
Global buffer reservation for each AF class
Best effort (BE)
•
•
Two BE classes for 1 Gbps ports
Service only when other queues are idle means that QoS not
adversely affected
Random early discard, with programmable levels
Traffic from flow control enabled ports automatically classified as BE
•
•
Table 12 - MVTX2603 Features Enabling IETF Diffserv Standards
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
8.0 Port Trunking
8.1 Features and Restrictions
A port group (i.e., trunk) can include up to 4 physical ports but all of the ports in a group must be in the same
MVTX2603.
The two Gigabit ports may also be trunked together. There are three trunk groups total including the option to trunk
Gigabit ports.
Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address
and destination MAC address. Three other options include source MAC address only, destination MAC address
only and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly.
If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN
member map.
The MVTX2603 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking
group goes down, the MVTX2603 will automatically redistribute the traffic over to the remaining ports in the trunk.
8.2 Unicast Packet Forwarding
The search engine finds the destination MCT entry, and if the status field says that the destination port found
belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the source address
belongs to a trunk, then the source port’s trunk membership register is checked.
A hash key, based on some combination of the source and destination MAC addresses for the current packet
selects the appropriate forwarding port.
8.3 Multicast Packet Forwarding
For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the
packet based on the VLAN index and hash key.
Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port
trunking environment.
Determining one forwarding port per group. For multicast packets, all but one port per group, the forwarding port,
must be excluded. Preventing the multicast packet from looping back to the source trunk.
The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with
the source port. This is because, when we select the primary forwarding port for each group, we do not take the
source port into account. To prevent this, we simply apply one additional filter, so as to block that forwarding port for
this multicast packet.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
8.4 Trunking
3 trunk groups are supported. Groups 0 and 1 can trunk up to 4 10/100 ports. Group 2 can trunk 2 Gigabit ports.
The supported combinations are shown in the following table.
Group 0
Port 0
Port 1
Port 2
Port 3
X
X
X
X
X
X
X
X
X
Select via trunk0_mode register
Group 1
Port 4
Port 5
Port 6
X
Port 7
X
X
X
X
X
Select via trunk1_mode register
Group 2
Port 25(Giga 0)
X
Port 26 (Giga 1)
X
The trunks are individually enabled/disabled by controlling pin trunk 0, 1, 2.
9.0 Port Mirroring
9.1 Port Mirroring Features
The received or transmitted data of any 10/100 port in the MVTX2603 chip can be “mirrored” to any other port. We
support two such mirrored source-destination pairs. A mirror port cannot also serve as a data port. Please refer to
the Port Mirroring Application Note for further details.
9.2 Setting Registers for Port Mirroring
•
MIRROR1_SRC: Sets the source port for the first port mirroring pair. Bits [4:0] select the source port to be
mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to
select between ingress (Rx) or egress (Tx) data.
•
•
MIRROR1_DEST: Sets the destination port for the first port mirroring pair. Bits [4:0] select the destination
port to be mirrored. The default is port 23.
MIRROR2_SRC: Sets the source port for the second port mirroring pair. Bits [4:0] select the source port to
be mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used
to select between ingress (Rx) or egress (Tx) data.
•
MIRROR2_DEST: Sets the destination port for the second port mirroring pair. Bits [4:0] select the
destination port to be mirrored. The default is port 0.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
10.0 TBI Interface
The TBI interface can be used for 1000Mbps fiber operation. In this mode, the MVTX2603 is connected to the
Serdes as shown in Figure 14. There are two TBI interfaces in the MVTX2603 devices. To enable to TBI function,
the corresponding TXEN and TXER pins need to be boot strapped. See Ball – Signal Description for details.
M25/26_TXD[9:0]
M25/26_TXCLK
T[9:0]
REFCLK
MVTX2603
SERDES
M25/26_RXD[9:0]
M25/26_RXCLK
M25/26_COL
R[9:0]
RBC0
RBC1
Figure 14 - TBI Connection
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
11.0 GPSI (7WS) Interface
11.1 GPSI Connection
The 10/100 RMII ethernet port can function in GPSI (7WS) mode when the corresponding TXEN pin is strapped
low with a 1 K pull down resistor. In this mode, the TXD[0], TXD[1], RXD[0] and RXD[1] serve as TX data, TX clock,
RX data and RX clock respectively. The link status and collision from the PHY are multiplexed and shifted into the
switch device through external glue logic. The duplex of the port can be controlled by programming the ECR
register.
The GPSI interface can be operated in port based VLAN mode only
crs
rxd
CRS_DV
RXD[0]
RXD[1]
TXD[1]
rx_clk
tx_clk
txd
link0
col0
Port 0
Ethernet
PHY
TXD[0]
TXEN
txen
link1
link2
col1
col2
260X
link23
col23
Port 23
Ethernet
PHY
Link
Serializer
(CPLD)
Collision
Serializer
(CPLD)
Figure 15 - GPSI (7WS) Mode Connection Diagram
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
11.2 SCAN LINK and SCAN COL interface
An external CPLD logic is required to take the link signals and collision signals from the GPSI PHYs and shift them
into the switch device. The switch device will drive out a signature to indicate the start of the sequence. After that,
the CPLD should shift in the link and collision status of the PHYS as shown in the figure. The extra link status
indicates the polarity of the link signal. One indicates the polarity of the link signal is active high.
scan_clk
scan_link/
scan_col
25 cycles for link/
24 cycles for col
Drived by VTX260x
Driven by MVTX260x
Drived by CPLD
Driven by CPLD
Ttaolt3a2l 3cy2ccleyscpleesriopderiod
To
Figure 16 - SCAN LINK and SCAN COLLISON Status Diagram
12.0 LED Interface
12.1 LED Interface Introduction
A serial output channel provides port status information from the MVTX2603 chips. It requires three additional pins:
•
•
•
LED_CLK at 12.5 MHz
LED_SYN a sync pulse that defines the boundary between status frames
LED_DATA a continuous serial stream of data for all status LEDs that repeats once every frame time
A non-serial interface is also allowed, but in this case, only the Gigabit ports will have status LEDs.
A low cost external device (44 pin PAL) is used to decode the serial data and to drive an LED array for display. This
device can be customized for different needs.
12.2 Port Status
In the MVTX2603, each port has 8 status indicators, each represented by a single bit. The 8 LED status indicators
are
•
•
•
•
•
•
•
•
Bit 0: Flow control
Bit 1:Transmit data
Bit 2: Receive data
Bit 3: Activity (where activity includes either transmission or reception of data)
Bit 4: Link up
Bit 5: Speed (1= 100 Mb/s; 0= 10 Mb/s)
Bit 6: Full-duplex
Bit 7: Collision
Eight clocks are required to cycle through the eight status bits for each port.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
When the LED_SYN pulse is asserted, the LED interface will present 256 LED clock cycles with the clock cycles
providing information for the following ports.
Port 0 (10/100): cycles #0 to cycle #7
Port 1 (10/100): cycles#8 to cycle #15
Port 2 (10/100): cycle #16 to cycle #23
...
Port 22 (10/100): cycle #176 to cycle #183
Port 23 (10/100): cycle #184 to cycle #191
Port 24 (Gigabit 0): cycle #192 to cycle #199
Port 25 (Gigabit 1): cycle #200 to cycle #207
Byte 26 (additional status): cycle #208 to cycle #215
Byte 27 (additional status): cycle #216 to cycle #223
Cycles #224 to 256 present data with a value of zero.
The first two bits of byte 26 provides the speed information for the Gigabit ports while the remainder of byte 26 and
byte 27 provides bit status
•
26[0]: G0 port (1= port 24 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on
speed bit of Port 24)
•
26[1]: G1 port (1= port 25 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on
speed bit of Port 25)
•
•
•
•
•
•
•
•
26[2]: initialization done
26[3]: initialization start
26[4]: checksum ok
26[5]: link_init_complete
26[6]: bist_fail
26[7]: ram_error
27[0]: bist_in_process
27[1]: bist_done
12.3 LED Interface Timing Diagram
The signal from the MVTX2603 to the LED decoder is shown in Figure 17.
Figure 17 - Timing Diagram of LED Interface
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
13.0 Register Definition
13.1 MVTX2603 Register Description
CPU Addr
(Hex)
I2C Addr
(Hex)
Register
Description
R/W
Default
Notes
0. ETHERNET Port Control Registers Substitute [N] with Port number (0..17h, 19h, 1Ah)
ECR1P”N”
ECR2P”N”
Port Control Register 1 for Port N
Port Control Register 2 for Port N
0000 + 2 x N
001 + 2 x N
R/W 000-018
R/W 01B-033
020
000
1. VLAN Control Registers Substitute [N] with Port number (0..17h, 19h, 1Ah)
AVTCL
VLAN Type Code Register Low
VLAN Type Code Register High
Port “N” Configuration Register 0
Port “N” Configuration Register 1
Port “N” Configuration Register 2
Port “N” Configuration Register 3
VLAN Operating Mode
100
R/W 036
000
081
0FF
0FF
0FF
007
000
AVTCH
101
R/W 037
PVMAP”N”_0
PVMAP”N”_1
PVMAP”N”_2
PVMAP”N”_3
PVMODE
102 + 4N
103 + 4N
104 + 4N
105 + 4N
170
R/W 038-052
R/W 053-06D
R/W 06E-088
R/W 089-0A3
R/W 0A4
2. TRUNK Control Registers
TRUNK0_ MODE
TRUNK1_ MODE
TRUNK2_ MODE
TX_AGE
Trunk Group 0 Mode
203
20B
210
325
R/W 0A5
R/W 0A6
R/W NA
R/W 0A7
003
003
003
008
Trunk Group 1 Mode
Trunk Group 2 Mode
Transmission Queue Aging Time
3. Search Engine Configurations
AGETIME_LOW
MAC Address Aging Time Low
400
R/W 0A8
2M:05C/
4M:02E
AGETIME_ HIGH
SE_OPMODE
MAC Address Aging Time High
Search Engine Operating Mode
401
403
R/W 0A9
R/W NA
000
000
4. Buffer Control and QOS Control
FCBAT
QOSC
FCB Aging Timer
500
501
502
503
504
505
506
507
R/W 0AA
R/W 0AB
R/W 0AC
R/W 0AD
R/W 0AE
R/W 0AF
R/W 0B0
R/W 0B1
0FF
000
008
000
000
000
000
000
QOS Control
FCR
Flooding Control Register
VLAN Priority Map Low
VLAN Priority Map Middle
VLAN Priority Map High
TOS Priority Map Low
TOS Priority Map Middle
AVPML
AVPMM
AVPMH
TOSPML
TOSPMM
39
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
CPU Addr
(Hex)
I2C Addr
(Hex)
Register
TOSPMH
Description
TOS Priority Map High
R/W
Default
Notes
508
509
50A
50B
50C
R/W 0B2
R/W 0B3
R/W 0B4
R/W 0B5
R/W 0B6
000
000
000
000
AVDM
TOSDML
BMRC
UCC
VLAN Discard Map
TOS Discard Map
Broadcast/Multicast Rate Control
Unicast Congestion Control
2M:008/
4M:010
MCC
Multicast Congestion Control
50D
50E
R/W 0B7
R/W 0B8
050
PR100
Port Reservation for 10/100 Ports
2M:024/
4M:036
SFCB
Share FCB Size
510
R/W 0BA
2M:014/
4M:064
C2RS
Class 2 Reserve Size
Class 3 Reserve Size
Class 4 Reserve Size
Class 5 Reserve Size
Class 6 Reserve Size
Class 7 Reserve Size
QOS Control (N=0 59)
WRED Drop Rate Control 0
WRED Drop Rate Control 1
511
512
513
514
515
516
R/W 0BB
R/W 0BC
R/W 0BD
R/W 0BE
R/W 0BF
R/W 0C0
R/W 0C1-0D2
R/W 0FB
R/W 0FC
000
000
000
000
000
000
000
08F
088
C3RS
C4RS
C5RS
C6RS
C7RS
QOSC”N”
RDRC0
RDRC1
517 512
553
554
USER_
User Define Logical Port “N” Low
(N=0-7)
580 + 2N
R/W 0D6-0DD 000
PORT”N”_LOW
USER_
User Define Logical Port “N” High
581 + 2N
590
R/W 0DE-0E5 000
PORT”N”_HIGH
USER_ PORT1:0_
PRIORITY
User Define Logic Port 1 and 0 Priority
User Define Logic Port 3 and 2 Priority
User Define Logic Port 5 and 4 Priority
User Define Logic Port 7 and 6 Priority
R/W 0E6
R/W 0E7
R/W 0E8
R/W 0E9
000
000
000
000
USER_ PORT3:2_
PRIORITY
591
USER_ PORT5:4_
PRIORITY
592
USER_
593
PORT7:6_PRI
ORITY
USER_PORT_
ENABLE
User Define Logic Port Enable
594
595
596
R/W 0EA
R/W 0EB
R/W 0EC
000
000
000
WLPP10
Well known Logic Port Priority for 1
and 0
WLPP32
Well known Logic Port Priority for 3
and 2
40
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
CPU Addr
(Hex)
I2C Addr
(Hex)
Register
WLPP54
Description
R/W
Default
Notes
Well known Logic Port Priority for 5
and 4
597
R/W 0ED
000
WLPP76
WLPE
Well-known Logic Port Priority for 7 & 6 598
R/W 0EE
R/W 0EF
R/W 0F4
R/W 0F5
R/W 0D3
R/W 0D4
R/W 0D5
000
000
000
000
000
000
000
Well known Logic Port Enable
User Define Range Low Bit7:0
User Define Range Low Bit 15:8
User Define Range High Bit 7:0
User Define Range High Bit 15:8
User Define Range Priority
599
59A
59B
59C
59D
59E
RLOWL
RLOWH
RHIGHL
RHIGHH
RPRIORITY
5. MISC Configuration Registers
MII_OP0
MII_OP1
FEN
MII Register Option 0
600
601
602
603
604
605
606
607
608
609
60B
R/W 0F0
R/W 0F1
R/W 0F2
R/W N/A
R/W N/A
R/W N/A
R/W N/A
000
000
010
000
000
000
000
N/A
N/A
000
000
MII Register Option 1
Feature Registers
MIIC0
MIIC1
MIIC2
MIIC3
MIID0
MIID1
LED
MII Command Register 0
MII Command Register 1
MII Command Register 2
MII Command Register 3
MII Data Register 0
RO
RO
N/A
N/A
MII Data Register 1
LED Control Register
EEPROM Checksum Register
R/W 0F3
R/W 0FF
SUM
6. Port Mirroring Controls
MIRROR1_SRC
MIRROR1_ DEST
MIRROR2_SRC
MIRROR2_ DEST
Port Mirror 1 Source Port
700
701
702
703
R/W N/A
R/W N/A
R/W N/A
R/W N/A
07F
017
0FF
000
Port Mirror 1 Destination Port
Port Mirror 2 Source Port
Port Mirror 2 Destination Port
F. Device Configuration Register
GCR
DCR
DCR1
DPST
DTST
DA
Global Control Register
F00
F01
F02
F03
F04
FFF
R/W N/A
000
N/A
N/A
000
N/A
DA
Device Status and Signature Register
Giga Port status
RO
RO
N/A
N/A
Device Port Status Register
Data read back register
DA Register
R/W N/A
RO
RO
N/A
N/A
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
13.2 Group 0 Address MAC Ports Group
13.2.1 ECR1Pn: Port N Control Register
2
•
•
I C Address h000-01A; CPU Address: 0000+2xN
2
Accessed by serial interface and I C (R/W)
7
6
5
4
3
2
1
0
Sp State
A-FC
Port Mode
Bit [0]
•
•
1 - Flow Control Off
0 - Flow Control On
• When Flow Control On:
• In half duplex mode, the MAC transmitter applies back pressure for flow control.
• In full duplex mode, the MAC transmitter sends Flow Control frames when
necessary. The MAC receiver interprets and processes incoming flow control
frames. The Flow Control Frame Received counter is incremented whenever a
flow control is received.
• When Flow Control off:
• In half duplex mode, the MAC Transmitter does not assert flow control by sending
flow control frames or jamming collision.
• In full duplex mode, the Mac transmitter does not send flow control frames. The
MAC receiver does not interpret or process the flow control frames. The Flow
Control Frame Received counter is not incremented.
Bit [1]
•
•
1 - Half Duplex - Only 10/100 mode
0 - Full Duplex
Bit [2]
•
•
1 - 10 Mbps
0 - 100 Mbps
Bit [4:3]
•
•
•
00 - Automatic Enable Auto Neg. This enables hardware state machine for
auto-negotiation.
01 - Limited Disable auto Neg. This disables hardware for speed auto-
negotiation. Poll MII for link status.
10 - Link Down. Disable auto Neg. state machine and force link down
(disable the port)
•
•
11 - Link Up. User ERC1 [2:0] for config.
Bit [5]
Asymmetric Flow Control Enable
• 0 - Disable asymmetric flow control
• 1 - Enable asymmetric flow control
•
•
Asymmetric Flow Control Enable. When this bit is set and flow control is on
(bit [0] = 0, don't send out a flow control frame. But MAC receiver interprets
and process flow control frames. Default is 0
Bit [7:6]
SS - Spanning tree state Default is 11
• 00 – Blocking: Frame is dropped
• 01 - Listening:
• 10 - Learning:
Frame is dropped
Frame is dropped. Source MAC address is learned.
• 11 - Forwarding: Frame is forwarded. Source MAC address is learned.
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
13.2.2 ECR2Pn: Port N Control Register
2
•
•
I C Address: h01B-035; CPU Address: h0001+2xN
2
Accessed by and serial interface and I C (R/W)
7
6
5
4
3
2
1
0
QoS Sel
Reserve
DisL
Ftf
Futf
Bit [0]:
Bit [1]:
Bit [2]:
•
•
•
•
Filter untagged frame (Default 0)
• 0: Disable
• 1: All untagged frames from this port are discarded
Filter Tag frame (Default 0)
• 0: Disable
• 1: All tagged frames from this port are discarded
Learning Disable (Default 0)
• 1 Learning is disabled on this port
• 0 Learning is enabled on this port
Bit [3]:
Must be set to ‘1’
Bit [5:4:]
•
•
•
QOS mode selection (Default 00)
Determines which of the 4 sets of QoS settings is used for 10/100 ports.
Note that there are 4 sets of per-queue byte thresholds, and 4 sets of WFQ
ratios programmed. These bits select among the 4 choices for each 10/100
port. Refer to QoS Application Note.
• 00: select class byte limit set 0 and classes WFQ credit set 0
• 01: select class byte limit set 1 and classes WFQ credit set 1
• 10: select class byte limit set 2 and classes WFQ credit set 2
• 11: select class byte limit set 3 and classes WFQ credit set 3
Bit [7:6]
•
Reserved
13.2.3 GGControl – Extra GIGA Port Control
•
•
CPU Address: h036
Accessed by serial interface (R/W)
7
6
5
4
3
2
1
0
DF
MiiB
RstA
DF
MiiA
RstA
Bit [0]:
Bit [1]:
Bit [2]:
•
•
•
Reset GIGA port A
• 0: Normal operation (default)
• 1: Reset Gigabit port A
GIGA port A use MII interface (10/100 M)
• 0: Gigabit port operations at 1000 mode
• 1: Gigabit port operations at 10/100 mode
Reserved - Must be zero
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Bit [3]:
•
GIGA port A direct flow control (MAC to MAC connection). The MVTX2603
supports direct flow control mechanism, the flow control frame is therefore
not sent through the Gigabit port data path.
• 0: Direct flow control disabled (default)
• 1: Direct flow control enabled
Bit [4]:
Bit [5]:
•
•
Reset GIGA port B
• 0: Normal operation (default)
• 1: Reset Gigabit port B
GIGA port B use MII interface (10/100 M)
• 0: Gigabit port operates at 1000 mode
• 1: Gigabit port operates at 10/100 mode
Bit [6]:
Bit [7]:
•
•
Reserved. Must be zero.
GIGA port B direct flow control (MAC to MAC connection). The MVTX2603
supports direct flow control mechanism, the flow control frame is therefore
not sent through the Gigabit port data path.
• 0: Direct flow control disabled (default)
• 1: Direct flow control enabled
13.3 Group 1 Address VLAN Group
13.3.1 AVTCL – VLAN Type Code Register Low
2
•
•
I C Address h036; CPU Address: h100
2
Accessed by serial interface and I C (R/W)
Bit [7:0]:
•
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00)
13.3.2 AVTCH – VLAN Type Code Register High
2
•
•
I C Address h037; CPU Address: h101
2
Accessed by serial interface and I C (R/W)
Bit [7:0]:
•
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81)
13.3.3 PVMAP00_0 – Port 00 Configuration Register 0
2
•
•
I C Address h038, CPU Address: h102
2
Accessed by serial interface and I C (R/W)
Bit [7:0]:
•
VLAN Mask for ports 7 to 0 (Default FF)
This register indicates the legal egress ports. A “1” on bit 7 means that the packet can be sent to port 7. A “0” on bit
7 means that any packet destined to port 7 will be discarded. This register works with registers 1, 2 and 3 to form a
27 bit mask to all egress ports.
44
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
13.3.4 PVMAP00_1 – Port 00 Configuration Register 1
2
•
•
I C Address h53, CPU Address: h103
2
Accessed by serial interface and I C (R/W)
Bit [7:0]:
•
VLAN Mask for ports 15 to 8 (Default is FF)
13.3.5 PVMAP00_2 – Port 00 Configuration Register 2
2
•
•
I C Address h6E, CPU Address: h104
2
Accessed by serial interface and I C (R/W)
Bit [7:0]:
•
VLAN Mask for ports 23 to 16 (Default FF)
13.3.6 PVMAP00_3 – Port 00 Configuration Register 3
2
•
•
I C Address h89, CPU Address: h105
2
Accessed by serial interface and I C (R/W)
7
6
5
3
2
1
0
FP en
Drop
Default tx priority
VLAN Mask
Bit [0]:
Reserved (Default 1)
Bit [2:1]:
Bit [5:1]:
VLAN Mask for ports 26 to 25 (Default 3)
Default Transmit priority. Used when Bit [7] = 1 (Default 0)
•
•
•
•
•
•
•
•
000 Transmit Priority Level 0 (Lowest)
001 Transmit Priority Level 1
010 Transmit Priority Level 2
011 Transmit Priority Level 3
100 Transmit Priority Level 4
101 Transmit Priority Level 5
110 Transmit Priority Level 6
111 Transmit Priority Level 7 (Highest)
Bit [6]:
Bit [7]:
Default Discard priority (Default 0)
•
•
0 - Discard Priority Level 0 (Lowest)
1 - Discard Priority Level 7(Highest)
Enable Fix Priority (Default 0)
•
0 Disable fix priority. All frames are analysed. Transmit Priority and
Discard Priority are based on VLAN Tag, TOS field or Logical Port.
•
1 Transmit Priority and Discard Priority are based on values programmed
in bit [6:3]
45
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
13.4 Port Configuration Register
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PVMAP01_0,1,2,3 I C Address h39,54,6F,8A; CPU Address:h106,107,108,109)
2
PVMAP02_0,1,2,3 I C Address h3A,55,70,8B; CPU Address:h10A, 10B, 10C, 10D)
2
PVMAP03_0,1,2,3 I C Address h3B,56,71,8C; CPU Address:h10E, 10F, 110, 111)
2
PVMAP04_0,1,2,3 I C Address h3C,57,72,8D; CPU Address:h112, 113, 114, 115)
2
PVMAP05_0,1,2,3 I C Address h3D,58,73,8E; CPU Address:h116, 117, 118, 119)
2
PVMAP06_0,1,2,3 I C Address h3E,59,74,8F; CPU Address:h11A, 11B, 11C, 11D)
2
PVMAP07_0,1,2,3 I C Address h3F,5A,75,90; CPU Address:h11E, 11F, 120, 121)
2
PVMAP08_0,1,2,3 I C Address h40,5B,76,91; CPU Address:h122, 123, 124, 125)
2
PVMAP09_0,1,2,3 I C Address h41,5C,77,92; CPU Address:h126, 127, 128, 129)
2
PVMAP10_0,1,2,3 I C Address h42,5D,78,93; CPU Address:h12A, 12B, 12C, 12D)
2
PVMAP11_0,1,2,3 I C Address h43,5E,79,94; CPU Address:h12E, 12F, 130, 131)
2
PVMAP12_0,1,2,3 I C Address h44,5F,7A,95; CPU Address:h132, 133, 134, 135)
2
PVMAP13_0,1,2,3 I C Address h45,60,7B,96; CPU Address:h136, 137, 138, 139)
2
PVMAP14_0,1,2,3 I C Address h46,61,7C,97; CPU Address:h13A, h13B, 13C, 13D)
2
PVMAP15_0,1,2,3 I C Address h47,62,7D,98; CPU Address:h13E, 13F, 140, 141)
2
PVMAP16_0,1,2,3 I C Address h48,63,7E,99; CPU Address:h142, 143, 144, 145)
2
PVMAP17_0,1,2,3 I C Address h49,64,7F,9A; CPU Address:h146, 147, 148, 149)
2
PVMAP18_0,1,2,3 I C Address h4A,65,80,9B; CPU Address:h14A, 14B, 14C, 14D)
2
PVMAP19_0,1,2,3 I C Address h4B,66,81,9C; CPU Address:h14E, 14F, 150, 151)
2
PVMAP20_0,1,2,3 I C Address h4C,67,82,9D; CPU Address:h152, 153, 154, 155)
2
PVMAP21_0,1,2,3 I C Address h4D,68,83,9E; CPU Address:h156, 157, 158, 159)
2
PVMAP22_0,1,2,3 I C Address h4E,69,84,9F; CPU Address:h15A, 15B, 15C, 15D)
2
PVMAP23_0,1,2,3 I C Address h4F,6A,85,A0; CPU Address:h15E, 15F, 160, 161)
2
PVMAP25_0,1,2,3 I C Address h51,6C,87,A2; CPU Address:h166, 167, 168, 169) (Gigabit port 1)
2
PVMAP26_0,1,2,3 I C Address h52,6D,88,A3; CPU Address:h16A, 16B, 16C, 16D) (Gigabit port 2)
13.4.1 PVMODE
2
•
•
I C Address: h0A4, CPU Address: h170
2
Accessed by serial interface, and I C (R/W)
7
5
4
3
2
1
0
SM0 rPCS
DF
SL
Bit [0]:
Bit [1]:
•
•
Reserved
Must be ‘0’
•
Slow learning
Same function as SE_OP MODE bit 7. Either bit can enable the function; both need to
be turned off to disable the feature.
Bit [2]:
Bit [3]:
•
Disable dropping of frames with destination MAC addresses 0180C2000001 to
0180C200000F (Default = 0)
• 0: Drop all frames in this range
• 1: Disable dropping of frames in this range
• 1: Disable reset PCS
• 0: Enable reset PCS. PCS FIFO will be reset when receiving a PCS symbol error
46
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Bit [4]:
•
•
Support MAC address 0
• 0: MAC address 0 is not learned.
• 1: MAC address 0 is learned.
Bit [7:5]:
Reserved
13.4.2 TRUNK0_MODE– Trunk group 0 mode
2
•
•
I C Address: h0A5; CPU Address: h203
2
Accessed by serial interface and I C (R/W)
7
4
3
2
1
0
Hash Select
Port Select
Bit [1:0]:
Bit [3:2]
•
•
Port selection in unmanaged mode. Input pin TRUNK0 enable/disable
trunk group 0
• 00 Reserved
• 01 Port 0 and 1 are used for trunk 0
• 10 Port 0,1 and 2 are used for trunk 0
• 11 Port 0,1,2 and 3 are used for trunk 0
Hash Select. The Hash selected is valid for Trunk 0, 1 and 2. (Default
00)
• 00 Use Source and Destination Mac Address for hashing
• 01 Use Source Mac Address for hashing
• 10 Use Destination Mac Address for hashing
• 11 Use source destination MAC address and ingress physical port number
for hashing
Note: Trunk group 2 (two gigabit ports) is enabled/disabled using input pin TRUNK2.
13.4.3 TRUNK1_MODE – Trunk group 1 mode
2
•
•
I C Address: h0A6; CPU Address: h20B
2
Accessed by serial interface and I C (R/W)
7
2
1
0
Port Select
Bit [1:0]:
•
Port selection in unmanaged mode. Input pin TRUNK1
enable/disable trunk group 1
•
•
•
•
00 Reserved
01 Port 4 and 5 are used for trunk1
10 Reserved
11 Port 4, 5, 6 and 7 are used for trunk1
47
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
13.5 Group 4 Address Search Engine Group
13.5.1 TX_AGE – Tx Queue Aging timer
2
•
•
I C Address: h07;CPU Address: h325
Accessed by serial interface (RW)
7
6
5
0
Tx Queue Agent
•
•
•
Bit [5:0]: Unit of 100 ms (Default 8)
Disable transmission queue aging if value is zero. Aging timer for all ports and queues.
For no packet loss flow control, this register must be set to 0.
13.5.2 AGETIME_LOW – MAC address aging time Low
2
•
•
•
•
I C Address: h0A8; CPU Address: h400
2
Accessed by serial interface and I C (R/W)
Bit [7:0] Low byte of the MAC address aging timer.
MAC address aging is enable/disable by boot strap TSTOUT9
13.5.3 AGETIME_HIGH –MAC address aging time High
2
•
•
•
•
•
I C Address: h0A9; CPU Address: h401
2
Accessed by serial interface and I C (R/W)
Bit [7:0]: High byte of the MAC address aging timer.
The default setting provide 300 seconds aging time. Aging time is based on the following equation:
{AGETIME_HIGH,AGETIME_LOW} X (# of MAC address entries in the memory x 100 µsec). Number of
MAC entries = 32 K when 1 MB is used per bank. Number of MAC entries = 64 K when 2 MB is used per
bank.
13.5.4 SE_OPMODE – Search Engine Operation Mode
•
•
•
CPU Address: h403
Accessed by serial interface (R/W)
{SE_OPMODE} X(# of entries 100 usec)
7
6
5
0
SL
DMS
Bit [5:0]:
•
•
Reserved
Bit [6]:
Disable MCT speedup aging
• 1 – Disable speedup aging when MCT resource is low.
• 0 – Enable speedup aging when MCT resource is low.
Bit [7]:
•
Slow Learning
• 1– Enable slow learning. Learning is temporary disabled when search
demand is high
• 0 – Learning is performed independent of search demand
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
13.6 Group 5 Address Buffer Control/QOS Group
13.6.1 FCBAT – FCB Aging Timer
2
•
I C Address: h0AA; CPU Address: h500
7
0
FCBAT
FCB Aging time. Unit of 1ms. (Default FF)
This function is for buffer aging control. It is used to configure the aging
time, and can be enabled/ disabled through bootstrap pin. It is not
recommended to use this function for normal operation.
Bit [7:0]:
•
•
13.6.2 QOSC – QOS Control
2
•
•
I C Address: h0AB; CPU Address: h501
2
Accessed by serial interface and I C (R/W)
7
6
5
4
3
1
0
L
Tos-d
Tos-p
VF1c
Bit [0]:
Bit [4]:
•
•
QoS frame lost is OK. Priority will be available for flow control enabled
source only when this bit is set (Default 0)
Per VLAN Multicast Flow Control (Default 0)
• 0 - Disable
• 1 - Enable
Bit [5]:
Bit [6]:
•
•
Reserved
Select TOS bits for Priority (Default 0)
• 0 - Use TOS [4:2] bits to map the transmit priority
• 1 - Use TOS [7:5] bits to map the transmit priority
Bit [7]:
•
Select TOS bits for Drop Priority (Default 0)
• 0 - Use TOS[4:2] bits to map the drop priority
• 1 - Use TOS[7:5] bits to map the drop priority
13.6.3 FCR – Flooding Control Register
2
•
•
I C Address: h0AC; CPU Address: h502
2
Accessed by serial interface and I C (R/W)
7
6
4
3
0
Tos
TimeBase
U2MR
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Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Bit [3:0]:
Bit [6:4]:
•
•
U2MR: Unicast to Multicast Rate. Units in terms of time base defined in
bits [6:4]. This is used to limit the amount of flooding traffic. The value
in U2MR specifies how many packets are allowed to flood within the
time specified by bit [6:4]. To disable this function, program U2MR to 0.
(Default = 8)
TimeBase:
000 = 100 us
001 = 200 us
010 = 400 us
011 = 800 us
100 = 1.6 ms
101 = 3.2 ms
110 = 6.4 ms
111 = 100 us (same as 000)
•
•
(Default = 000)
Bit [7]:
Select VLAN tag or TOS (IP packets) to be preferentially picked to map
transmit priority and drop priority (Default = 0).
• 0 – Select VLAN Tag priority field over TOS
• 1 – Select TOS over VLAN tag priority field
13.6.4 AVPML – VLAN Priority Map
2
•
•
I C Address: h0AD; CPU Address: h503
2
Accessed by serial interface and I C (R/W)
7
6
5
3
2
0
VP2
VP1
VP0
Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit
priorities. Under the internal transmit priority, seven is highest priority where as zero is the lowest. This feature
allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0
of the AVPML register would map VLAN priority 0 into internal transmit priority 7. The new priority is used inside the
2603. When the packet goes out it carries the original priority.
Bit [2:0]:
Bit [5:3]:
Bit [7:6]:
•
•
•
Priority when the VLAN tag priority field is 0 (Default 0)
Priority when the VLAN tag priority field is 1 (Default 0)
Priority when the VLAN tag priority field is 2 (Default 0)
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13.6.5 AVPMM – VLAN Priority Map
2
•
•
I C Address: h0AE, CPU Address: h504
2
Accessed by serial interface and I C (R/W)
7
6
4
3
1
0
VP5
VP4
VP3
VP2
Map VLAN priority into eight level transmit priorities:
Bit [0]:
•
•
•
•
Priority when the VLAN tag priority field is 2 (Default 0)
Priority when the VLAN tag priority field is 3 (Default 0)
Priority when the VLAN tag priority field is 4 (Default 0)
Priority when the VLAN tag priority field is 5 (Default 0)
Bit [3:1]:
Bit [6:4]:
Bit [7]:
13.6.6 AVPMH – VLAN Priority Map
2
•
•
I C Address: h0AF, CPU Address: h505
2
Accessed by serial interface and I C (R/W)
7
5
4
2
1
0
VP7
Map VLAN priority into eight level transmit priorities:
VP6
VP5
Bit [1:0]:
Bit [4:2]:
Bit [7:5]:
•
•
•
Priority when the VLAN tag priority field is 5 (Default 0)
Priority when the VLAN tag priority field is 6 (Default 0)
Priority when the VLAN tag priority field is 7 (Default 0)
13.6.7 TOSPML – TOS Priority Map
2
•
•
I C Address: h0B0, CPU Address: h506
2
Accessed by serial interface and I C (R/W)
7
6
5
3
2
0
TP2
TP1
TP0
Map TOS field in IP packet into eight level transmit priorities:
Bit [2:0]:
Bit [5:3]:
Bit [7:6]:
•
•
Priority when the TOS field is 0 (Default 0)
Priority when the TOS field is 1 (Default 0)
Priority when the TOS field is 2 (Default 0)
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13.6.8 TOSPMM – TOS Priority Map
2
•
•
I C Address: h0B1, CPU Address: h507
2
Accessed by serial interface and I C (R/W)
7
6
4
3
1
0
TP5
TP4
TP3
TP2
Map TOS field in IP packet into four level transmit priorities:
Bit [0]:
•
•
•
•
Priority when the TOS field is 2 (Default 0)
Priority when the TOS field is 3 (Default 0)
Priority when the TOS field is 4 (Default 0)
Priority when the TOS field is 5 (Default 0)
Bit [3:1]:
Bit [6:4]:
Bit [7]:
13.6.9 TOSPMH – TOS Priority Map
2
•
•
I C Address: h0B2, CPU Address: h508
2
Accessed by serial interface and I C (R/W)
7
5
4
2
1
0
TP7
Map TOS field in IP packet into four level transmit priorities:
TP6
TP5
Bit [1:0]:
Bit [4:2]:
Bit [7:5]:
•
•
•
Priority when the TOS field is 5 (Default 0)
Priority when the TOS field is 6 (Default 0)
Priority when the TOS field is 7 (Default 0)
13.6.10 AVDM – VLAN Discard Map
2
•
•
I C Address: h0B3, CPU Address: h509
2
Accessed by serial interface and I C (R/W)
7
6
5
4
3
2
1
0
FDV7
FDV6
FDV5 FDV4 FDV3 FDV2 FDV1 FDV0
Map VLAN priority into frame discard when low priority buffer usage is above threshold
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
•
•
•
•
Frame drop priority when VLAN tag priority field is 0 (Default 0)
Frame drop priority when VLAN tag priority field is 1 (Default 0)
Frame drop priority when VLAN tag priority field is 2 (Default 0)
Frame drop priority when VLAN tag priority field is 3 (Default 0)
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Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
Frame drop priority when VLAN tag priority field is 4 (Default 0)
Frame drop priority when VLAN tag priority field is 5 (Default 0)
Frame drop priority when VLAN tag priority field is 6 (Default 0)
Frame drop priority when VLAN tag priority field is 7 (Default 0)
13.6.11 TOSDML – TOS Discard Map
2
•
•
I C Address: h0B4, CPU Address: h50A
2
Accessed by serial interface and I C (R/W)
7
6
5
4
3
2
1
0
FDT7
FDT6
FDT5
FDT4 FDT3
FDT2
FDT1
FDT0
Map TOS into frame discard when low priority buffer usage is above threshold
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
Frame drop priority when TOS field is 0 (Default 0)
Frame drop priority when TOS field is 1 (Default 0)
Frame drop priority when TOS field is 2 (Default 0)
Frame drop priority when TOS field is 3 (Default 0)
Frame drop priority when TOS field is 4 (Default 0)
Frame drop priority when TOS field is 5 (Default 0)
Frame drop priority when TOS field is 6 (Default 0)
Frame drop priority when TOS field is 7 (Default 0)
13.6.12 BMRC - Broadcast/Multicast Rate Control
2
•
•
I C Address: h0B5, CPU Address: h50B
2
Accessed by serial interface and I C (R/W)
7
4
3
0
Broadcast Rate
Multicast Rate
•
This broadcast and multicast rate defines for each port the number of packet allowed to be forwarded within
a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit,
program the field to 0. Timebase is based on register 502 [6:4].
Bit [3:0]:
•
Multicast Rate Control Number of multicast packets allowed within the
time defined in bits 6 to 4 of the Flooding Control Register (FCR).
(Default 0).
Bit [7:4]:
•
Broadcast Rate Control Number of broadcast packets allowed within
the time defined in bits 6 to 4 of the Flooding Control Register (FCR).
(Default 0)
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13.6.13 UCC – Unicast Congestion Control
2
•
•
I C Address: h0B6, CPU Address: h50C
2
Accessed by serial interface and I C (R/W)
7
0
Unicast congest threshold
Bit [7:0]:
•
Number of frame count. Used for best effort dropping at B% when
destination port’s best effort queue reaches UCC threshold and shared
pool is all in use. Granularity 1 frame. (Default: h10 for 2 MB/bank or
h08 for 1 MB/bank)
13.6.14 MCC – Multicast Congestion Control
2
•
•
I C Address: h0B7, CPU Address: h50D
2
Accessed by serial interface and I C (R/W)
7
5
4
0
FC reaction prd
Multicast congest threshold
Bit [4:0]:
Bit [7:5]:
•
•
In multiples of two. Used for triggering MC flow control when
destination multicast port’s best effort queue reaches MCC threshold.
(Default 0x10)
Flow control reaction period (Default 2) Granularity 4 uSec.
13.6.15 PR100 – Port Reservation for 10/100 ports
2
•
•
I C Address: h0B8, CPU Address: h50E
2
Accessed by serial interface and I C (R/W)
7
4
3
0
Buffer low thd
SP Buffer reservation
Bit [3:0]:
•
•
Per port buffer reservation.
Define the space in the FDB reserved for each 10/100 port. Expressed
in multiples of 4 packets. For each packet 1536 bytes are reserved in
the memory.
Bits [7:4]:
•
•
Expressed in multiples of 4 packets. Threshold for dropping all best
effort frames when destination port best efforts queues reach UCC
threshold and shared pool all used and source port reservation is at or
below the PR100[7:4] level. Also the threshold for initiating UC flow
control.
Default:
• h36 for 24+2 configuration with memory 2 MB/bank;
• h24 for 24+2 configuration with 1 MB/bank;
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13.6.16 PRG – Port Reservation for Giga ports
2
•
•
I C Address: h0B9, CPU Address: h50F
2
Accessed by serial interface and I C (R/W)
7
3
0
Buffer low thd
SP buffer reservation
Bit [3:0]:
•
•
Per source port buffer reservation.
Define the space in the FDB reserved for each Gigabit port. Expressed
in multiples of 16 packets. For each packet 1536 bytes are reserved in
the memory.
Bits [7:4]:
•
•
Expressed in multiples of 16 packets. Threshold for dropping all best
effort frames when destination port best effort queues reach UCC
threshold and shared pool is all used and source port reservation is at
or below the PRG[7:4] level. Also the threshold for initiating UC flow
control.
Default:
• H58 for memory 2 MB/bank;
• H35 for 1 MB/bank;
13.6.17 SFCB – Share FCB Size
2
•
•
I C Address: h0BA, CPU Address: h510
2
Accessed by serial interface and I C (R/W)
7
0
Shared buffer size
Bits [7:0]:
•
•
Expressed in multiples of 4 packets. Buffer reservation for shared pool.
Default:
• h64 for 24+2 configuration with memory of 2 MB/bank;
• h14 for 24+2 configuration with memory of 1 MB/bank;
13.6.18 C2RS – Class 2 Reserve Size
2
•
•
I C Address: h0BB, CPU Address: h511
2
Accessed by serial interface and I C (R/W)
7
0
Class 2 FCB Reservation
•
Buffer reservation for class 2 (third lowest priority). Granularity 1. (Default 0)
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13.6.19 C3RS – Class 3 Reserve Size
2
•
•
I C Address: h0BC, CPU Address: h512
2
Accessed by serial interface and I C (R/W)
7
0
0
0
0
0
Class 3 FCB Reservation
Buffer reservation for class 3. Granularity 1. (Default 0)
•
13.6.20 C4RS – Class 4 Reserve Size
2
•
•
I C Address: h0BD, CPU Address: h513
Accessed by serial interface and I C (R/W)
2
7
Class 4 FCB Reservation
Buffer reservation for class 4. Granularity 1. (Default 0)
•
13.6.21 C5RS – Class 5 Reserve Size
2
•
•
I C Address: h0BE; CPU Address: h514
Accessed by serial interface and I C (R/W)
2
7
Class 5 FCB Reservation
Buffer reservation for class 5. Granularity 1. (Default 0)
•
13.6.22 C6RS – Class 6 Reserve Size
2
•
•
I C Address: h0BF; CPU Address h515
Accessed by serial interface and I C (R/W)
2
7
Class 6 FCB Reservation
Buffer reservation for class 6 (second highest priority). Granularity 1. (Default 0)
•
13.6.23 C7RS – Class 7 Reserve Size
2
•
•
I C Address: h0C0; CPU Address: h516
Accessed by serial interface and I C (R/W)
2
7
Class 7 FCB Reservation
•
Buffer reservation for class 7 (highest priority). Granularity 1. (Default 0)
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13.6.24 Classes Byte Limit Set 0
2
•
•
•
•
Accessed by serial interface and I C (R/W)
2
C — QOSC00 – BYTE_C01 (I C Address h0C1, CPU Address 517)
2
B — QOSC01 – BYTE_C02 (I C Address h0C2, CPU Address 518)
2
A — QOSC02 – BYTE_C03 (I C Address h0C3, CPU Address 519)
QOSC00 through QOSC02 represents one set of values A-C for a 10/100 port when using the Weighted Random
Early Drop (WRED) Scheme described in Chapter 7.7. There are four such sets of values A-C specified in Classes
Byte Limit Set 0, 1, 2 and 3.
Each 10/ 100 port can choose one of the four Byte Limit Sets as specified by the QoS Select field located in bits 5
to 4 of the ECR2n register. The values A-C are per-queue byte thresholds for random early drop. QOSC02
represents A, and QOSC00 represents C.
Granularity when Delay bound is used: QOSC02: 128 bytes, QOSC01: 256 bytes. QOSC00: 512 bytes. Granularity
when WFQ is used: QOSC02: 512 bytes, QOSC01: 512 bytes, QOSC00: 512 bytes.
13.6.25 Classes Byte Limit Set 1
2
•
Accessed by serial interface and I C (R/W)
2
C - QOSC03 – BYTE_C11 (I C Address h0C4, CPU Address 51a)
2
B - QOSC04 – BYTE_C12 (I C Address h0C5, CPU Address 51b)
2
A - QOSC05 – BYTE_C13 (I C Address h0C6, CPU Address 51c)
QOSC03 through QOSC05 represents one set of values A-C for a 10/100 port when using the Weighted Random
Early Detect (WRED) Scheme.
Granularity when Delay bound is used: QOSC05: 128 bytes, QOSC04: 256 bytes. QOSC03: 512 bytes. Granularity
when WFQ is used: QOSC05: 512 bytes, QOSC04: 512 bytes, QOSC03: 512 bytes.
13.6.26 Classes Byte Limit Set 2
2
•
Accessed by serial interface and I C (R/W)
C - QOSC06 – BYTE_C21 (CPU Address 51d)
B - QOSC07 – BYTE_C22 (CPU Address 51e)
A - QOSC08 – BYTE_C23 (CPU Address 51f)
QOSC06 through QOSC08 represents one set of values A-C for a 10/100 port when using the Weighted Random
Early Detect (WRED) Scheme.
Granularity when Delay bound is used: QOSC08: 128 bytes, QOSC07: 256 bytes. QOSC06: 512 bytes. Granularity
when WFQ is used: QOSC08: 512 bytes, QOSC07: 512 bytes, QOSC06: 512 bytes.
13.6.27 Classes Byte Limit Set 3
2
•
Accessed by serial interface and I C (R/W)
C - QOSC09 – BYTE_C31 (CPU Address 520)
B - QOSC10 – BYTE_C32 (CPU Address 521)
A - QOSC11 – BYTE_C33 (CPU Address 522)
QOSC09 through QOSC011 represents one set of values A-C for a 10/100 port when using the Weighted Random
Early Detect (WRED) Scheme.
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Granularity when Delay bound is used: QOSC11: 128 bytes, QOSC10: 256 bytes. QOSC09: 512 bytes. Granularity
when WFQ is used: QOSC11: 512 bytes, QOSC10: 512 bytes, QOSC09: 512 bytes.
13.6.28 Classes Byte Limit Giga Port 1
2
•
Accessed by serial interface and I C (R/W)
2
F - QOSC12 – BYTE_C2_G1 (I C Address h0C7, CPU Address 523)
2
E - QOSC13 – BYTE_C3_G1 (I C Address h0C8, CPU Address 524)
2
D - QOSC14 – BYTE_C4_G1 (I C Address h0C9, CPU Address 525)
2
C - QOSC15 – BYTE_C5_G1 (I C Address h0CA, CPU Address 526)
2
B - QOSC16 – BYTE_C6_G1 (I C Address h0CB, CPU Address 527)
2
A - QOSC17 – BYTE_C7_G1 (I C Address h0CC, CPU Address 528)
QOSC12 through QOSC17 represent the values A-F for Gigabit port 24. They are per-queue byte thresholds for
random early drop. QOSC17 represents A, and QOSC12 represents F.
Granularity when Delay bound is used: QOSC17 and QOSC16: 256 bytes, QOSC15 and QOSC14: 512 bytes,
QOSC13 and QOSC12: 1024 bytes.
Granularity when WFQ is used: QOSC17 to QOSC12: 1024 bytes
13.6.29 Classes Byte Limit Giga Port 2
2
•
Accessed by serial interface and I C (R/W)
2
F - QOSC18 – BYTE_C2_G2 (I C Address h0CD, CPU Address 529)
2
E - QOSC19 – BYTE_C3_G2 (I C Address h0CE, CPU Address 52a)
2
D - QOSC20 – BYTE_C4_G2 (I C Address h0CF, CPU Address 52b)
2
C - QOSC21 – BYTE_C5_G2 (I C Address h0D0, CPU Address 52c)
2
B - QOSC22 – BYTE_C6_G2 (I C Address h0D1, CPU Address 52d)
2
A - QOSC23 – BYTE_C7_G2 (I C Address h0D2, CPU Address 52e)
QOSC18 through QOSC23 represent the values A-F for Gigabit port 2. They are per-queue byte thresholds for
random early drop. QOSC23 represents A, and QOSC18 represents F.
Granularity when Delay Bound is used: QOSC23 and QOSC22: 256 bytes, QOSC21 and QOSC20: 512 bytes,
QOSC19 and QOSC18: 1024 bytes.
Granularity when WFQ is used: QOSC18 to QOSC23: 1024 bytes
13.6.30 Classes WFQ Credit Set 0
•
Accessed by serial interface (R/W)
W0 - QOSC24[5:0] – CREDIT_C00 (CPU Address 52f)
W1 - QOSC25[5:0] – CREDIT_C01 (CPU Address 530)
W2 - QOSC26[5:0] – CREDIT_C02 (CPU Address 531)
W3 - QOSC27[5:0] – CREDIT_C03 (CPU Address 532)
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QOSC24 through QOSC27 represents one set of WFQ parameters for a 10/100 port. There are four such sets of
values. The granularity of the numbers is 1 and their sum must be 64. QOSC27 corresponds to W3 and QOSC24
corresponds to W0.
•
•
•
QOSC24[7:6]: Priority service type for the ports select this parameter set. Option 1 to 4
QOSC25[7]: Priority service allow flow control for the ports select this parameter set
QOSC25[6]: Flow control pause best effort traffic only
Both flow control allow and flow control best effort only can take effect only the priority type is WFQ.
13.6.31 Classes WFQ Credit Set 1
•
Accessed by serial interface (R/W)
W0 - QOSC28[5:0] – CREDIT_C10 (CPU Address 533)
W1 - QOSC29[5:0] – CREDIT_C11 (CPU Address 534)
W2 - QOSC30[5:0] – CREDIT_C12 (CPU Address 535)
W3 - QOSC31[5:0] – CREDIT_C13 (CPU Address 536)
QOSC28 through QOSC31 represents one set of WFQ parameters for a 10/100 port. There are four such sets of
values. The granularity of the numbers is 1 and their sum must be 64. QOSC31 corresponds to W3 and QOSC28
corresponds to W0.
QOSC28[7:6]: Priority service type for the ports select this parameter set. Option 1 to 4
QOSC29[7]: Priority service allow flow control for the ports select this parameter set
QOSC29[6]: Flow control pause best effort traffic only
13.6.32 Classes WFQ Credit Set 2
•
Accessed by serial interface (R/W)
W0 - QOSC32[5:0] – CREDIT_C20 (CPU Address 537)
W1 - QOSC33[5:0] – CREDIT_C21 (CPU Address 538)
W2 - QOSC34[5:0] – CREDIT_C22 (CPU Address 539)
W3 - QOSC35[5:0] – CREDIT_C23 (CPU Address 53a)
QOSC35 through QOSC32 represents one set of WFQ parameters for a 10/100 port. There are four such sets of
values. The granularity of the numbers is 1 and their sum must be 64. QOSC35 corresponds to W3 and QOSC32
corresponds to W0.
•
•
•
QOSC32[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4
QOSC33[7]: Priority service allow flow control for the ports select this parameter set
QOSC33[6]: Flow Control pause best effort traffic only
13.6.33 Classes WFQ Credit Set 3
•
Accessed by serial interface (R/W)
W0 - QOSC36[5;0] – CREDIT_C30 (CPU Address 53b)
W1 - QOSC37[5:0] – CREDIT_C31 (CPU Address 53c)
W2 - QOSC38[5:0] – CREDIT_C32 (CPU Address 53d)
W3 - QOSC39[5:0] – CREDIT_C33 (CPU Address 53e)
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QOSC39 through QOSC36 represents one set of WFQ parameters for a 10/100 port. There are four such sets of
values. The granularity of the numbers is 1, and their sum must be 64. QOSC39 corresponds to W3 and QOSC36
corresponds to W0.
•
•
•
QOSC36[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4
QOSC37[7]: Priority service allow flow control for the ports select this parameter set
QOSC37[6]: Flow Control pause best effort traffic only
13.6.34 Classes WFQ Credit Port G1
•
Accessed by serial interface (R/W)
W0 - QOSC40[5:0] – CREDIT_C0_G1 (CPU Address 53F)
[7:6] - Priority service type. Option 1 to 4.
W1 - QOSC41[5:0] – CREDIT_C1_G1 (CPU Address 540)
[7]: Priority service allow flow control for the ports select this parameter set.
[6]: Flow Control pause best effort traffic only
W2 - QOSC42[5:0] – CREDIT_C2_G1 (CPU Address 541)
W3 - QOSC43[5:0] – CREDIT_C3_G1 (CPU Address 542)
W4 - QOSC44[5:0] – CREDIT_C4_G1 (CPU Address 543)
W5 - QOSC45[5:0] – CREDIT_C5_G1 (CPU Address 544)
W6 - QOSC46[5:0] – CREDIT_C6_G1 (CPU Address 545)
W7 - QOSC47[5:0] – CREDIT_C7_G1 (CPU Address 546)
QOSC40 through QOSC47 represents the set of WFQ parameters for Gigabit port 24. The granularity of the
numbers is 1 and their sum must be 64. QOSC47 corresponds to W7 and QOSC40 corresponds to W0. In the 2G
trunk configuration, the sum of all values QOSC40 through QOSC47 must equal 128.
13.6.35 Classes WFQ Credit Port G2
•
Accessed by serial interface (R/W)
W0 - QOSC48[5:0] – CREDIT_C0_G2 (CPU Address 547)
[7:6] - Priority service type. Option 1 to 4.
W1 - QOSC49[5:0] – CREDIT_C1_G2 (CPU Address 548)
[7]: Priority service allow flow control for the ports select this parameter set.
[6]: Flow Control pause best effort traffic only
W2 - QOSC50[5:0] – CREDIT_C2_G2 (CPU Address 549)
W3 - QOSC51[5:0] – CREDIT_C3_G2 (CPU Address 54a)
W4 - QOSC52[5:0] – CREDIT_C4_G2 (CPU Address 54b)
W5 - QOSC53[5:0] – CREDIT_C5_G2 (CPU Address 54c)
W6 - QOSC54[5:0] – CREDIT_C6_G2 (CPU Address 54d)
W7 - QOSC55[5:0] – CREDIT_C7_G2 (CPU Address 54e)
QOSC48 through QOSC55 represents the set of WFQ parameters for Gigabit port 25. The granularity of the
numbers is 1, and their sum must be 64. QOSC55 corresponds to W7 and QOSC48 corresponds to W0. In the 2G
trunk configuration, the sum of all values QOSC48 through QOSC55 must equal 128.
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13.6.36 Class 6 Shaper Control Port G1
Accessed by serial interface (R/W)
•
• QOSC56[5:0] – TOKEN_RATE_G1 (Address 54f). Programs the average rate for Gigabit port 1. When equal to 0,
shaper is disable. Granularity is 1.
• QOSC57[7:0] – TOKEN_LIMIT_G1 (Address 550). Programs the maximum counter for Gigabit port1. Granularity is
16 bytes.
Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is
limited to gigabit ports and queue P6 when it is in strict priority. QOSC41 programs the peak rate for Gigabit port 1.
See Programming QoS Registers Application Note for more information.
13.6.37 Class 6 Shaper Control Port G2
•
Accessed by serial interface (R/W)
• QOSC58[5:0] – TOKEN_RATE_G2 (CPU Address 551). Programs the average rate for Gigabit port 2. When equal to
0, shaper is disable. Granularity is 1.
• QOSC59[7:0] – TOKEN_LIMIT_G2 (CPU Address 552). Programs the maximum counter for Gigabit port2.
Granularity is 16 bytes.
Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is
limited to gigabit ports and queue P6 when it is in strict priority. QOSC49 programs the peak rate for Gigabit port 2.
See Programming QoS Registers Application Note for more information.
13.6.38 RDRC0 – WRED Rate Control 0
2
•
•
I C Address: h0FB, CPU Address: h553
c
Accessed by serial Interface and I C (R/W)
7
4
3
0
X Rate
Y Rate
Bits [7:4]:
Bits [3:0]:
•
•
Corresponds to the frame drop percentage X% for WRED. Granularity
6.25%.
Corresponds to the frame drop percentage Y% for WRED. Granularity
6.25%.
See Programming QoS Registers Application Note for more information.
13.6.39 RDRC1 – WRED Rate Control 1
2
•
•
I C Address: h0FC, CPU Address: h554
2
Accessed by serial Interface and I C (R/W)
7
4
3
0
Z Rate
B Rate
Bits [7:4]:
Bits [3:0]:
•
•
Corresponds to the frame drop percentage Z% for WRED. Granularity 6.25%.
Corresponds to the best effort frame drop percentage B%, when shared pool is
all in use and destination port best effort queue reaches UCC. Granularity
6.25%.
See Programming QoS Register Application Note for more information.
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Data Sheet
13.6.40 User Defined Logical Ports and Well Known Ports
The MVTX2603 supports classifying packet priority through layer 4 logical port information. It can be setup by 8
Well Known Ports, 8 User Defined Logical Ports and 1 User Defined Range. The 8 Well Known Ports supported are
•
•
•
•
•
•
•
•
0:23
1:512
2:6000
3:443
4:111
5:22555
6:22
7:554
Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_ Enable
can individually turn on/off each Well Known Port if desired.
Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select
specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7
registers. Two registers are required to be programmed for the logical port number. The respective priority can be
programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via
User_Port_Enable register.
The User Defined Range provides a range of logical port numbers with the same priority level. Programming is
similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need
to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit
is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the
upper limit and more than the lower limit will use the priority specified in RPRIORITY.
13.6.40.1 USER_PORT0_(0~7) – User Define Logical Port (0~7)
2
•
•
•
•
•
•
•
•
•
USER_PORT_0 - I C Address h0D6 + 0DE; CPU Address 580(Low) + 581(High)
2
USER_PORT_1 - I C Address h0D7 + 0DF; CPU Address 582 + 583
2
USER_PORT_2 - I C Address h0D8 + 0E0; CPU Address 584 + 585
2
USER_PORT_3 - I C Address h0D9 + 0E1; CPU Address 586 + 587
2
USER_PORT_4 - I C Address h0DA + 0E2; CPU Address 588 + 589
2
USER_PORT_5 - I C Address h0DB + 0E3; CPU Address 58a + 58b
2
USER_PORT_6 - I C Address h0DC + 0E4; CPU Address 58c + 58d
2
USER_PORT_7 - I C Address h0DD + 0E5; CPU Address 58e + 58f
2
Accessed by serial interface and I C (R/W)
7
0
0
TCP/UDP Logic Port Low
7
TCP/UDP Logic Port High
•
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the definition of
eight separate ports.
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Data Sheet
13.6.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
2
•
•
I C Address: h0E6, CPU Address: h590
2
Accessed by serial interface and I C (R/W)
7
5
4
3
1
0
Priority 1
The chip allows the definition of the priority
Drop
Priority 0
Drop
•
Bits [3:0]:
Bits [7:4]:
•
•
Priority setting, transmission + dropping, for logic port 0
Priority setting, transmission + dropping, for logic port 1 (Default 00)
13.6.40.3 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
2
•
•
I C Address: h0E7, CPU Address: h591
2
Accessed by serial interface and I C (R/W)
7
5
4
3
1
0
Priority 3
Drop
Priority 2
Drop
13.6.40.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
2
•
•
I C Address: h0E8, CPU Address: h592
2
Accessed by serial interface and I C (R/W)
7
5
4
3
1
0
Priority 5
Drop
Priority 4
Drop
•
(Default 00)
13.6.40.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority
2
•
•
I C Address: h0E9, CPU Address: h593
2
Accessed by serial interface and I C (R/W)
7
5
4
3
1
0
Priority 7
Drop
Priority 6
Drop
•
(Default 00)
13.6.40.6 USER_PORT_ENABLE [7:0] – User Define Logic 7 to 0 Port Enables
2
•
•
I C Address: h0EA, CPU Address: h594
2
Accessed by serial interface and I C (R/W)
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
•
(Default 00)
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Data Sheet
13.6.40.7 WELL_KNOWN_PORT [1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority
2
•
•
I C Address: h0EB, CPU Address: h595
2
Accessed by serial interface and I C (R/W)
7
5
4
3
1
0
Priority 1
Drop
Priority 0
Drop
•
•
•
Priority 0 - Well known port 23 for telnet applications
Priority 1 - Well known port 512 for TCP/UDP
(Default 00)
13.6.40.8 WELL_KNOWN_PORT [3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority
2
•
•
I C Address: h0EC, CPU Address: h596
2
Accessed by serial interface and I C (R/W)
7
5
4
3
1
0
Priority 3
Priority 2 - Well known port 6000 for XWIN.
Priority 3 - Well known port 443 for http. sec
(Default 00)
Drop
Priority 2
Drop
•
•
•
13.6.40.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority
2
•
•
I C Address: h0ED, CPU Address: h597
2
Accessed by serial interface and I C (R/W)
7
5
4
3
1
0
Priority 5
Priority 4 - Well known port 111 for sun rpe.
Priority 5 - Well known port 22555 for IP Phone call setup
(Default 00)
Drop
Priority 4
Drop
•
•
•
13.6.40.10 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority
2
•
•
I C Address: h0EE, CPU Address: h598
2
Accessed by serial interface and I C (R/W)
7
5
4
3
1
0
Priority 7
Drop
Priority 6
Drop
•
•
•
Priority 6 - Well known port 22 for ssh.
Priority 7 - Well known port 554 for rtsp.
(Default 00)
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Data Sheet
13.6.40.11 WELL KNOWN_PORT_ENABLE [7:0] – Well Known Logic 7 to 0 Port Enables
2
•
•
I C Address: h0EF, CPU Address: h599
2
Accessed by serial interface and I C (R/W)
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• 1 - Enable
• 0 - Disable
(Default 00)
•
13.6.40.12 RLOWL – User Define Range Low Bit 7:0
2
•
•
•
I C Address: h0F4, CPU Address: h59a
2
Accessed by serial interface and I C (R/W)
(Default 00)
13.6.40.13 RLOWH – User Define Range Low Bit 15:8
2
•
•
•
I C Address: h0F5, CPU Address: h59b
2
Accessed by serial interface and I C (R/W)
(Default 00)
13.6.40.14 RHIGHL – User Define Range High Bit 7:0
2
•
•
•
I C Address: h0D3, CPU Address: h59c
2
Accessed by serial interface and I C (R/W)
(Default 00)
13.6.40.15 RHIGHH – User Define Range High Bit 15:8
2
•
•
•
I C Address: h0D4, CPU Address: h59d
2
Accessed by serial interface and I C (R/W)
(Default 00)
13.6.40.16 RPRIORITY – User Define Range Priority
2
•
•
I C Address: h0D5, CPU Address: h59e
2
Accessed by serial interface and I C (R/W)
7
4
3
1
0
Range Transmit Priority
Drop
•
RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY
Bit [3:1]
Bits [0]:
•
•
Transmit Priority
Drop Priority
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Data Sheet
13.7 Group 6 Address MISC Group
13.7.1 MII_OP0 – MII Register Option 0
2
•
•
I C Address: hF0, CPU Address:h600
2
Accessed by serial interface and I C (R/W)
7
6
5
4
0
hfc
1prst
DisJ
Vendor Spc. Reg Addr
Bits [7]:
•
Half duplex flow control feature
• 0 = Half duplex flow control always enable
• 1 = Half duplex flow control by negotiation
Bits [6]:
Bits [5]:
•
•
Link partner reset auto-negotiate disable
Disable jabber detection. This is for HomePNA application or any serial
operation slower than 10 Mbps.
• 1 = disable
• 0 = enable
Bit [4:0]:
•
Vendor specified link status register address (null value means don’t
use it) (Default 00); used when the Linkup bit position in the PHY is
non-standard.
13.7.2 MII_OP1 – MII Register Option 1
2
•
•
I C Address: hF1, CPU Address:h601
2
Accessed by serial interface and I C (R/W)
7
4
3
0
Speed bit location
Duplex bit location
Bits [3:0]:
Bits [7:4]:
•
Duplex bit location in vendor specified register
•
•
Speed bit location in vendor specified register
(Default 00)
13.7.3 FEN – Feature Register
2
•
•
I C Address: hF2, CPU Address: h602
2
Accessed by serial interface and I C (R/W)
7
6
5
3
2
1
0
DML
MII
DS
Bits [1:0]:
•
Reserved (Default 0)
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Zarlink Semiconductor Inc.
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Data Sheet
Bit [2]:
•
•
Support DS EF Code. (Default 0)
When 101110 is detected in DS field (TOS [7:2]), the frame priority is
set for 110 and drop is set for 0
Bit [5:3]:
Bit [6]:
•
•
Reserved (Default 010)
Disable MII Management State Machine
• 0: Enable MII Management State Machine (Default 0)
• 1: Disable MII Management State Machine
Bit [7]:
•
Disable using MCT link list structure
• 0: Enable using MCT Link List structure (Default 0)
• 1: Disable using MCT Link List structure
13.7.4 MIIC0 – MII Command Register 0
•
•
•
CPU Address: h603
Accessed by serial interface only (R/W)
Bit [7:0] MII Data [7:0]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
13.7.5 MIIC1 – MII Command Register 1
•
•
•
CPU Address: h604
Accessed by serial interface only (R/W)
Bit [7:0] MII Data [15:8]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
13.7.6 MIIC2 – MII Command Register 2
•
•
CPU Address :h605
Accessed by serial interface only (R/W)
7
6
5
4
0
Mii OP
Register address
Bits [4:0]:
Bit [6:5]
•
•
REG_AD – Register PHY Address
OP – Operation code “10” for read command and “01” for write
command
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command. Writing to this register will initiate a serial management cycle to the MII management
interface. For detail information, please refer to the PHY Control Application Note.
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Data Sheet
13.7.7 MIIC3 – MII Command Register 3
•
•
CPU Address: h606
Accessed by serial interface only (R/W)
7
6
5
4
0
Rdy
Valid
PHY address
Bits [4:0]:
Bit [6]
•
•
•
PHY_AD – 5 Bit PHY Address
VALID – Data Valid from PHY (Read Only)
Bit [7]
RDY – Data is returned from PHY (Ready Only)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
13.7.8 MIID0 – MII Data Register 0
•
•
•
CPU Address: h607
Accessed by serial interface only (RO)
Bit [7:0] MII Data [7:0]
13.7.9 MIID1 – MII Data Register 1
•
•
•
CPU Address: h608
Accessed by serial interface only (RO)
Bit [7:0] MII Data [15:8]
13.7.10 LED Mode – LED Control
•
•
CPU Address: h609
Accessed by serial interface and I C (R/W)
2
7
5
4
3
2
1
0
Clock rate
Hold Time
Bit [0]
•
•
Reserved (Default 0)
Bit [2:1]:
Hold time for LED signal (Default= 00)
• 00 = 8 msec 01 = 16 msec
10 = 32 msec 11 = 64 msec
Bit [4:3]:
•
LED clock frequency (Default 0)
For 100MHz SCLK
00 = 100 M/8 = 12.5 MHz
10 = 100 M/32 = 3.125 MHz
01 = 100 M/16 = 6.25 MHz
11 = 100 M/64 = 1.5625 MHz
For 125 MHz SCLK
00 = 125 M/64 = 1953 KHz
10 = 125M/512=244 KHz
01 = 125 M/128 = 977 KHz
11 = 125 M/1024 = 122 KHz
Bit [7:6]:
•
Reserved. Must be 0. (Default 0)
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Data Sheet
13.7.11 CHECKSUM - EEPROM Checksum
2
•
•
I C Address: FF, CPU Address: h60b
2
Accessed by serial interface and I C (R/W)
Bit [7:0]:
•
(Default 0)
Before requesting that the MVTX2603 updates the EEPROM device, the correct checksum needs to be calculated
and written into this checksum register. When the MVTX2603 boots from the EEPROM the checksum is calculated
and the value must be zero. If the checksum is not zeroed the MVTX2603 does not start and pin CHECKSUM_OK
is set to zero.
The checksum formula is:FF
2
Σ I C register = 0
I=0
13.8 Group 7 Address Port Mirroring Group
13.8.1 MIRROR1_SRC – Port Mirror source port
•
•
CPU Address: h700
Accessed by serial interface (R/W) (Default 7F)
7
6
5
4
0
I/O
Src Port Select
Bit [4:0]:
Bit [5]:
•
Source port to be mirrored. Use illegal port number to disable mirroring
•
•
1 – select ingress data
0 – select egress data
Bit [7]:
•
Must be ‘1’
13.8.2 MIRROR1_DEST – Port Mirror destination
•
•
CPU Address: h701
Accessed by serial interface (R/W) (Default 17)
7
5
4
0
Dest Port Select
Bit [4:0]:
•
Port Mirror Destination
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Data Sheet
13.8.3 MIRROR2_SRC – Port Mirror source port
•
•
CPU Address: h702
Accessed by serial interface (R/W) (Default FF)
7
6
5
4
0
I/O
Src Port Select
Bit [4:0]:
Bit [5]:
•
Source port to be mirrored. Use illegal port number to disable mirroring
•
•
1 – select ingress data
0 – select egress data
Bit [7]
•
Must be 1
13.8.4 MIRROR2_DEST – Port Mirror destination
•
•
CPU Address: h703
Accessed by serial interface (R/W) (Default 00)
7
5
4
0
Dest Port Select
Bit [4:0]:
•
Port Mirror Destination
13.9 Group F Address CPU Access Group
13.9.1 GCR-Global Control Register
•
•
CPU Address: hF00
Accessed by serial interface. (R/W)
7
4
3
2
1
0
Reset
Bist
SR
SC
Bit [0]:
Bit [1]:
Bit [2]:
•
•
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
•
•
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
•
•
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result
is found in the DCR register.
Bit [3]:
•
•
Soft Reset (Default = 0)
Write ‘1’ to reset chip
Bit [7:4]:
•
Reserved.
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Data Sheet
13.9.2 DCR-Device Status and Signature Register
•
•
CPU Address: hF01
Accessed by serial interface. (RO)
7
6
5
4
3
2
1
0
Revision
Signature
RE
BinP
BR
BW
2
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [5:4]:
Bit [7:6]:
•
•
1: Busy writing configuration to I C
2
0: Not busy writing configuration to I C
2
•
•
1: Busy reading configuration from I C
0: Not busy reading configuration from I C
2
•
•
1: BIST in progress
0: BIST not running
•
•
1: RAM Error
0: RAM OK
•
•
Device Signature
01: MVTX2603 device
•
•
•
Revision
00: Initial Silicon
01: XA1 Silicon
13.9.3 DCR1-Giga port status
•
•
CPU Address: hF02
Accessed by serial interface (RO)
7
6
4
3
2
1
0
CIC
GIGA1
GIGA0
Bit [1:0]:
Bit [3:2]
Bit [7]
•
•
•
•
•
Giga port 0 strap option
00 – 100 Mb MII mode
01 – 2 G mode
10 – GMII
11 – PCS
•
•
•
•
•
Giga port 1 strap option
00 – 100 Mb MII mode
01 – 2 G mode
10 – GMII
11 – PCS
•
Chip initialization completed
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Data Sheet
13.9.4 DPST – Device Port Status Register
•
•
CPU Address: hF03
Accessed by serial interface (R/W)
Bit[4:0]:
•
Read back index register. This is used for selecting what to read back from
DTST. (Default 00)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5’b00000 - Port 0 Operating mode and Negotiation status
5’b00001 - Port 1 Operating mode/Neg status
5’b00010 - Port 2 Operating mode/Neg status
5’b00011 - Port 3 Operating mode/Neg status
5’b00100 - Port 4 Operating mode/Neg status
5’b00101 - Port 5 Operating mode/Neg status
5’b00110 - Port 6 Operating mode/Neg status
5’b00111 - Port 7 Operating mode/Neg status
5’b01000 - Port 8 Operating mode/Neg status
5’b01001 - Port 9 Operating mode/Neg status
5’b01010 - Port 10 Operating mode/Neg status
5’b01011 - Port 11 Operating mode/Neg status
5’b01100 - Port 12 Operating mode/Neg status
5’b01101 - Port 13 Operating mode/Neg status
5’b01110 - Port 14 Operating mode/Neg status
5’b01111 - Port 15 Operating mode/Neg status
5’b10000 - Port 16 Operating mode/Neg status
5’b10001 - Port 17 Operating mode/Neg status
5’b10010 - Port 18 Operating mode/Neg status
5’b00011 - Port 19 Operating mode/Neg status
5’b10100 - Port 20 Operating mode/Neg status
5’b10101 - Port 21 Operating mode/Neg status
5’b10110 - Port 22 Operating mode/Neg status
5’b10111 - Port 23 Operating mode/Neg status
5’b11000 - Reserved
5’b11001 - Port 25 Operating mode/Neg status (Gigabit port 1)
5’b11010 - Port 26 Operating mode/Neg status (Gigabit port 2)
13.9.5 DTST – Data read back register
•
•
•
CPU Address: hF04
Accessed by serial interface (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Control
Application Note.
7
6
5
4
3
2
1
0
MD
Info
Sig
Giga
Inkdn
FE
Fdpx
FcEn
When bit is 1
•
•
•
•
•
Bit [0] – Flow control enable
Bit [1] – Full duplex port
Bit [2] – Fast Ethernet port (if not gigabit port)
Bit [3] – Link is down
Bit [4] – Giga port
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Data Sheet
•
•
•
Bit [5] – Signal detect (when PCS interface mode)
Bit [6] – 2 G signal detect (2 G mode only)
Bit [7] – Module detected (for hot swap purpose)
13.9.6 PLLCR - PLL Control Register
•
•
CPU Address: hF05
Accessed by serial interface (RW)
Bit [3] Must be '1'
Bit [7] Selects strap option or LCLK/OECLK registers
0 - Strap option (default)
1 - LCLK/OECLK registers
13.9.7 LCLK - LA_CLK delay from internal OE_CLK
•
•
CPU Address: hF06
Accessed by serial interface (RW)
PD[12:10]
000b
001b
010b
011b
100b
101b
110b
LCLK
80h
40h
20h
10h
08h
04h
02h
01h
Delay
8 Buffers Delay
7 Buffers Delay
6 Buffers Delay
5 Buffers Delay (Recommend)
4 Buffers Delay
3 Buffers Delay
2 Buffers Delay
1 Buffers Delay
111b
The LCLK delay from SCLK is the sum of the delay programmed in here and the delay in OECLK register.
13.9.8 OECLK - Internal OE_CLK delay from SCLK
•
•
CPU Address: hF07
Accessed by serial interface (RW)
The OE_CLK is used for generating the OE0 and OE1 signals.
PD[15:13]
000b
001b
010b
011b
OECLK Delay
80h
40h
20h
10h
08h
8 Buffers Delay
7 Buffers Delay (Recommend)
6 Buffers Delay
5 Buffers Delay
4 Buffers Delay
100b
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Data Sheet
101b
110b
111b
04h
02h
01h
3 Buffers Delay
2 Buffers Delay
1 Buffers Delay
13.9.9 DA – DA Register
•
•
•
CPU Address: hFFF
Accessed by CPU and serial interface (RO)
Always return 8’h DA. Indicate the serial port connection is good.
13.10 TBI Registers
Two sets of TBI registers are used for configure the two Gigabit ports if they are operating in TBI mode. These TBI
registers are located inside the switching chip and they are accessed through the MII command and MII data
registers.
13.10.1 Control Register
•
•
MII Address: h00
Read/Write
Bit [15]
Reset PCS logic and all TBI registers
1 = Reset
0 = Normal operation
Bit [14]
Bit [13]
Bit [12]
Reserved. Must be programmed with “0”.
Speed selection (See bit 6 for complete details)
•
•
•
Auto Negotiation Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process (Default)
Bit [11:10]
Bit [9]
•
Reserved. Must be programmed with “0”
•
•
•
Restart Auto Negotiation
1 = Restart auto-negotiation process
0 = Normal operation (Default)
Bit [8:7]
Bit [6]
•
•
Reserved
Speed Selection
-
-
-
-
-
Bit [6][13]
1 1 = Reserved
0 =1000 Mb/s (Default)
1
0
= 100 Mb/s
= 10 Mb/s
0
Bit [5:0]
•
Reserved. Must be programmed with “0”.
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Data Sheet
13.10.2 Status Register
•
•
MII Address: h01
Read Only
Bit [15:9]
Bit [8]
Reserved. Always read back as “0”.
Reserved. Always read back as “1”.
Reserved. Always read back as “0”.
Bit [7:6]
Bit [5]
•
•
•
Auto-Negotiation Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
Bit [4]
Bit [3]
Bit [2]
•
•
Reserved. Always read back as “0”
Reserved. Always read back as “1”
•
•
•
Link Status
1 = Link is up.
0 = Link is down.
Bit [1]
Bit [0]
•
•
Reserved. Always read back as “0”.
Reserved. Always read back as “1”
13.10.3 Advertisement Register
•
•
MII Address: h04
Read/Write
Bit [15]
Next Page
1 = Has next page capabilities.
0 = Do not has next page capabilities (Default)
Bit [14]
Reserved. Always read back as “0”. Read Only
Remote Fault. Default is “0”.
Bit [13:12]
Bit [11:9]
Bit [8:7]
Bit [6]
•
•
Reserved. Always read back as “0”. Read Only.
Pause. Default is “00”
•
•
•
Half Duplex
1 = Support half duplex (Default)
0 = Do not support half duplex
Bit [5]
•
•
•
Full duplex
1 = Support full duplex (Default)
0 = Do not support full duplex
Bit [4:0]
•
Reserved. Always read back as “0”. Read Only.
75
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
13.10.4 Link Partner Ability Register
•
•
MII Address: h05
Read Only
Bit [15]
Next Page
1 = Has next page capabilities
0 = Do not has next page capabilities
Bit [14]
Acknowledge
Remote Fault.
Bit [13:12]
Bit [11:9]
Bit [8:7]
Bit [6]
•
•
Reserved. Always read back as “0”
Pause
•
•
•
Half Duplex
1 = Support half duplex
0 = Do not support half duplex
Bit [5]
•
•
•
Full duplex
1 = Support full duplex
0 = Do not support full duplex
Bit [4:0]
•
Reserved. Always read back as “0”
13.10.5 Expansion Register
•
•
MII Address: h06
Read Only
Bit [15:2]
Bit [1]
•
Reserved. Always read back as “0”
•
•
•
Page Received
1 = A new page has been received
0 = A new page has not been received
Bit [0]
•
Reserved. Always read back as “0”
13.10.6 Extended Status Register
•
•
MII Address: h15
Read Only
Bit [15]
Bit [14]
Bit [13:0]
•
•
•
1000 Full Duplex
1 = Support 1000 full duplex operation (Default)
0 = Do not support 1000 full duplex operation
•
•
•
1000 Half Duplex
1 = Support 1000 half duplex operation (Default)
0 = Do not support 1000 half duplex operation
•
Reserved. Always read back as “0”
76
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.0 BGA and Ball Signal Descriptions
14.1 BGA Views (Top-View)
14.1.1 Encapsulated View
1
2
3
4
5
6
7
8
9
1 0
1 1
1 3
1 2
1 6
1 3
1 9
1 4
3 3
1 5
3 6
1 6
3 9
1 7
4 2
1 8
4 5
1 9
2 0
2 1
K 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D L A _ D O E _ C L A _ C T R U N M I R R M I R R
S T R O T S T O
A
B
C
S C L S D A
4
7
1 0
1 3
1 5
4
E 0 _
8
L K 0 L K 0
O R 4 O R 1
B E
D 0
U T 7
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D L A _ D O E _ C L A _ C L A _ D M I R R M I R R T R U N R E S E
T S T O T S T O
U T 8 U T 3
1
3
6
9
1 2
1 4 D S C _ E 1 _
7
1 2
1 5
1 8
3 2
3 5
3 8
4 1
4 4
L K 1 L K 1
6 2
O R 5 O R 2
K 2 R V E D
L A _ C L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ W T _ M O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D O E _ C L A _ C
T R U N M I R R M I R R A U T O T S T O T S T O T S T O T S T O
P _ D
L K
0
2
5
8
1 1
3
E _ E _
D E 1
1 1
1 4
1 7
2 0
3 4
3 7
4 0
4 3
L K 2 L K 2
K 0
O R 3 O R 0
F D U T 1 1 U T 9 U T 4 U T 0
A G N L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ A L A _ W L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D S C A N S C A N T S T O T S T O T S T O T S T O T S T O T S T O
D
E
F
D
1 7
1 9
2 1
2 3
2 5
2 7
2 9
3 1
6
1 0
E 0 _
4 9
5 1
5 3
5 5
5 7
5 9
6 1
6 3
4 7
C O L C L K U T 1 4 U T 1 3 U T 1 2 U T 1 0 U T 5 U T 1
S C A N
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ A L A _ W L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D R E S E L A _ D
S C A N T S T O M 2 6 _ M 2 6 _
L I N K U T 1 5 C R S T X E R
T S T O T S T O
U T 6 U T 2
S C L K
M O D
1 6
1 8
2 0
2 2
2 4
2 6
2 8
3 0
5
9
E 1 _
4 8
5 0
5 2
5 4
5 6
5 8
6 0 R V E D 4 6
E
M 2 6 _
M 2 6 _
T X C L
T X E N
K
M 2 6 _ M 2 6 _ M 2 6 _
M T X R X D R X C L
A V C R E S I S C A N L B _ D L B _ D
V C C V C C V C C V C C V C C
C
N _
E N
6 3
6 2
C L K
V
K
R E S E
T O UT
_
M 2 6 _ M 2 6 _ M 2 6 _
L B _ C
L K
L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _
R X E R C O L
G
H
J
T X D 1 T X D 1 R X D 1
4 7 6 1 6 0
4
5
5
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
L B _ D L B _ D L B _ D L B _ D L B _ D
4 6 4 5 4 4 5 9 5 8
T X D 1 T X D 1 R X D 1 R X D 1 R X D 1
2
3
2
3
4
M 2 6 _ M 2 6 _
M 2 6 _ M 2 6 _
L B _ D L B _ D L B _ D L B _ D L B _ D
4 3 4 2 4 1 5 7 5 6
M 2 6 _
R X D 9
T X D 1 T X D 1
R X D 1 R X D 1
0
1
0
1
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 9 T X D 8 R X D 6 R X D 7 R X D 8
K
L
V D D V D D
V D D V D D
4 0
3 9
3 8
5 5
5 4
L B _ D L B _ D L B _ D L B _ D L B _ D
3 7 3 6 3 5 5 3 5 2
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 4 T X D 6 R X D 3 R X D 4 R X D 5
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 7 T X D 5 R X D 0 R X D 1 R X D 2
M
N
P
V D D
V D D
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V D D
V D D
3 4
3 3
3 2
5 1
5 0
G R E F
L B _ A L B _ A L B _ A L B _ D L B _ D
M 2 6 _ M 2 6 _
_ C L K
V C C
V C C
V C C
V C C
V C C
V C C
V C C
V C C
1 8
1 9
2 0
4 9
4 8
T X D 2 T X D 3
1
G R E F
L B _ A L B _ A L B _ A L B _ W L B _
M 2 6 _ M 2 6 _
M D I O _ C L K
T X D 0 T X D 1
0
1 5 1 6 1 7 E 0 _ W E 1 _
L B _ A L B _ A L B _ A L B _ A L B _ A
M 2 5 _ M 2 5 _
C R S T X E R
M _ C L
M D C
K
R
T
1 0
1 1
1 2
1 3
1 4
M 2 5 _
M 2 5 _ M 2 5 _ M 2 5 _
V C C T X C L
M T X R X D R X C L
T X E N
K C L K
L B _ A L B _ A L B _ A L B _ A L B _ A
M 2 5 _
5
6
7
8
9
V
K
M 2 5 _ M 2 5 _ M 2 5 _
L B _ O L B _ O T _ M O L B _ D L B _ D
M 2 5 _ M 2 5 _
R X E R C O L
U
V
V D D
V D D
V D D
V D D
V C C T X D 1 T X D 1 R X D 1
E 0 _
E 1 _ D E 0
3 1
3 0
4
5
5
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
L B _ A L B _ O L B _ W L B _ D L B _ D
T X D 1 T X D 1 R X D 1 R X D 1 R X D 1
D S C _ E _ E _ 2 9 2 8
2
3
2
3
4
M 2 5 _ M 2 5 _
M 2 5 _ M 2 5 _
L B _ D L B _ A L B _ A L B _ D L B _ D
M 2 5 _
R X D 9
W
Y
T X D 1 T X D 1
R X D 1 R X D 1
1 5
3
4
2 7
2 6
0
1
0
1
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
R X D 6 T X D 8 T X D 9 R X D 7 R X D 8
V D D V D D
V D D V D D
1 4 1 3 1 2 2 5 2 4
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
T X D 6 T X D 7 R X D 3 R X D 4 R X D 5
A
A
1 1
1 0
9
2 3
2 2
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
T X D 4 T X D 5 R X D 0 R X D 1 R X D 2
A
B
8
7
6
2 1
2 0
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 3 _ M 2 3 _ M 2 3 _
T X D 2 T X D 3 C R S R X D 0 R X D 1
A
C
5
4
3
1 9
1 8
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 3 _ M 2 3 _ M 2 3 _
T X D 0 T X D 1 T X D 1 T X D 0 T X E N
A
D
V C C V C C V C C V C C V C C
2
1
0
1 7
1 6
M 0 _ T M 0 _ T M 0 _ T M 3 _ T M 3 _ T M 3 _ R M 5 _ T M 5 _ T M 5 _ R M 8 _ T M 8 _ T M 8 _ R M 1 0 _ M 1 0 _ M 1 0 _ M 1 3 _ M 1 6 _ M 1 5 _ M 1 6 _ M 1 5 _ M 1 5 _ M 1 8 _ M 1 8 _ M 1 8 _ M 2 0 _ M 2 0 _ M 2 0 _ M 2 2 _
X E N X D 0 X D 1 X D 1 X E N X D 0 X D 1 X E N X D 0 X D 1 X E N X D 0 T X D 1 T X E N R X D 0 T X D 1 T X D 0 T X D 1 R X D 1 T X E N R X D 0 T X D 1 T X E N R X D 0 T X D 1 T X E N R X D 0 R X D 1
A
E
M 0 _ R M 0 _ R M 0 _ C M 3 _ T M 3 _ C M 3 _ R M 5 _ T M 5 _ C M 5 _ R M 8 _ T M 8 _ C M 8 _ R M 1 0 _ M 1 0 _ M 1 0 _ M 1 3 _ M 1 3 _ M 1 3 _ M 1 4 _ M 1 6 R M 1 5 _ M 1 7 _ M 1 7 _ M 1 8 _ M 2 0 _ M 2 0 _ M 2 0 _ M 2 2 _ M 2 2 _
A F
X D 1 X D 0
R S
X D 0
R S
X D 1 X D 0
R S
X D 1 X D 0
R S
X D 1 T X D 0 C R S R X D 1 T X D 0 C R S R X D 1 C R S X D 0 R X D 1 R X D 0 C R S R X D 1 T X D 0 C R S R X D 1 R X D 0 C R S
M 1 _ T M 1 _ T M 1 _ T M 2 _ T M 2 _ C M 4 _ T M 4 _ C M 6 _ T M 6 _ C M 7 _ T M 7 _ C M 9 _ T M 9 _ C M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 5 _ M 1 6 _ M 1 6 _ M 1 8 _ M 1 8 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _ M 2 2 _ M 2 2 _
A
G
X E N X D 0 X D 1 X D 1
R S
X D 1
R S
X D 1
R S
X D 1
R S
X D 1
R S T X D 1 C R S T X D 1 C R S T X D 1 T X D 0 T X D 1 C R S T X D 0 C R S T X D 1 C R S T X D 1 C R S T X E N T X D 0
M 1 _ R M 1 _ C M 2 _ T M 2 _ R M 4 _ T M 4 _ R M 6 _ T M 6 _ R M 7 _ T M 7 _ R M 9 _ T M 9 _ R M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 4 _ M 1 3 _ M 1 5 _ M 1 7 _ M 1 7 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _ M 2 2 _
A
H
X D 0
R S
X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 T X D 0 R X D 0 T X D 0 R X D 0 T X D 0 R X D 0 R X D 0 C R S T X D 0 R X D 1 T X D 0 R X D 0 T X D 0 R X D 0 T X D 1
M 1 _ R M 2 _ T M 2 _ R M 4 _ T M 4 _ R M 6 _ T M 6 _ R M 7 _ T M 7 _ R M 9 _ T M 9 _ R M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 4 _ M 1 6 _ M 1 3 _ M 1 7 _ M 1 7 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _
X D 1 X E N X D 1 X E N X D 1 X E N X D 1 X E N X D 1 X E N X D 1 T X E N R X D 1 T X E N R X D 1 T X E N R X D 1 T X E N T X E N T X E N T X D 1 T X E N R X D 1 T X E N R X D 1
A J
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
77
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.2 Ball – Signal Descriptions
All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive.
14.2.1 Ball Signal Descriptions
Ball Signal Descriptions Table
Ball No(s)
Symbol
I/O
Description
I2C Interface Note: Use I2C and Serial control interface to configure the system
SCL
SDA
Output
I2C Data Clock
I2C Data I/O
A24
I/O-TS with pull up
A25
Serial Control Interface
STROBE
Input with weak internal Serial Strobe Pin
pull up
A26
D0
Input
Serial Data Input
B26
AUTOFD
Output with pull up
Serial Data Output (AutoFD)
Frame Bank A– Data Bit [63:0]
C25
Frame Buffer Interface
LA_D[63:0]
I/O-TS with pull up
D20, B21, D19, E19,D18,
E18, D17, E17, D16, E16,
D15, E15, D14, E14, D13,
E13, D21, E21, A18, B18,
C18, A17, B17, C17, A16,
B16, C16, A15, B15, C15,
A14, B14, D9, E9, D8, E8,
D7, E7, D6, E6, D5, E5, D4,
E4, D3, E3, D2, E2, A7, B7,
A6, B6, C6, A5, B5, C5, A4,
B4, C4, A3, B3, C3, B2, C2
LA_A[20:3]
LA_ADSC#
Output
Frame Bank A – Address Bit [20:3]
C14, A13, B13, C13, A12,
B12, C12, A11, B11, C11,
D11, E11, A10, B10, D10,
E10, A8, C7
Output with pull up
Frame Bank
Control
A
Address Status
B8
LA_CLK
LA_WE#
Output
Frame Bank A Clock Input
C1
C9
Output with pull up
Frame Bank A Write Chip Select for
one layer SRAM application
LA_WE0#
LA_WE1#
Output with pull up
Output with pull up
Frame Bank A Write Chip Select for
lower layer of two layers SRAM
application
D12
E12
Frame Bank A Write Chip Select for
upper layer of two layers SRAM
application
78
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball Signal Descriptions Table (continued)
Ball No(s)
Symbol
LA_OE#
I/O
Description
Output with pull up
Output with pull up
Frame Bank A Read Chip Select for
one layer SRAM application
C8
A9
LA_OE0#
LA_OE1#
LB_D[63:0]
Frame Bank A Read Chip Select for
lower layer of two layers SRAM
application
Output with pull up
I/O-TS with pull up.
Frame Bank A Read Chip Select for
upper layer of two layers SRAM
application
B9
Frame Bank B– Data Bit [63:0]
F4, F5, G4, G5, H4, H5, J4,
J5, K4, K5, L4, L5, M4, M5,
N4, N5, G3, H1, H2, H3, J1,
J2, J3, K1, K2, K3, L1, L2,
L3, M1, M2, M3, U4, U5, V4,
V5, W4, W5, Y4, Y5, AA4,
AA5, AB4, AB5, AC4, AC5,
AD4, AD5, W1, Y1, Y2, Y3,
AA1, AA2, AA3, AB1, AB2,
AB3, AC1, AC2, AC3, AD1,
AD2, AD3
LB_A[20:3]
LB_ADSC#
Output
Frame Bank B – Address Bit [20:3]
N3, N2, N1, P3, P2, P1, R5,
R4, R3, R2, R1, T5, T4, T3,
T2, T1, W3, W2
Output with pull up
Frame Bank
Control
B
Address Status
V1
LB_CLK
LB_WE#
Output
Frame Bank B Clock Input
G1
V3
Output with pull up
Frame Bank B Write Chip Select for
one layer SRAM application
LB_WE0#
LB_WE1#
Output with pull up
Output with pull up
Frame Bank B Write Chip Select for
lower layer of two layers SRAM
application
P4
P5
Frame Bank B Write Chip Select for
upper layer of two layers SRAM
application
LB_OE#
Output with pull up
Output with pull up
Frame Bank B Read Chip Select for
one layer SRAM application
V2
U1
LB_OE0#
Frame Bank B Write Chip Select for
lower layer of two layers SRAM
application
LB_OE1#
Output with pull up
Output
Frame Bank B Write Chip Select for
upper layer of two layers SRAM
application
U2
Fast Ethernet Access Ports [23:0] RMII
M_MDC
MII Management Data Clock
(Common for all MII Ports [23:0])
–
R28
79
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball Signal Descriptions Table (continued)
Ball No(s)
Symbol
M_MDIO
I/O
Description
I/O-TS with pull up
MII Management Data I/O
(Common for all MII Ports –[23:0]))
–
P28
R29
M_CLKI
Input
Reference Input Clock
M[23:0]_RXD[1]
Input with weak internal Ports [23:0] – Receive Data Bit [1]
pull up resistors.
AC29, AE28, AJ27, AF27,
AJ25, AF24, AH23, AE19,
AF21, AJ19, AF18, AJ17,
AJ15, AF15, AJ13, AF12,
AJ11, AJ9, AF9, AJ7, AF6,
AJ5, AJ3, AF1
M[23:0]_RXD[0]
M[23:0]_CRS_DV
M[23:0]_TXEN
M[23:0]_TXD[1]
M[23:0]_TXD[0]
Input with weak internal Ports [23:0] – Receive Data Bit [0]
pull up resistors
AC28, AF28, AH27, AE27,
AH25, AE24, AF22, AF20,
AE21, AH19, AH20, AH17,
AH15, AE15, AH13, AE12,
AH11, AH9, AE9, AH7, AE6,
AH5, AH2, AF2
Input with weak internal Ports [23:0] – Carrier Sense and
AC27, AF29, AG27, AF26,
AG25, AG23, AF23, AG21,
AH21, AF19, AF17, AG17,
AG15, AF14, AG13, AF11,
AG11, AG9, AF8, AG7, AF5,
AG5, AH3, AF3
pull down resistors.
Receive Data Valid
I/O- TS with pull up, slew
Ports [23:0] – Transmit Enable
Strap option for RMII/GPSI
AD29, AG28, AJ26, AE26,
AJ24, AE23, AJ22, AJ20,
AE20, AJ18, AJ21, AJ16,
AJ14, AE14, AJ12, AE11,
AJ10, AJ8, AE8, AJ6, AE5,
AJ4, AG1, AE1
Output, slew
Output, slew
Ports [23:0] – Transmit Data Bit [1]
Ports [23:0] – Transmit Data Bit [0]
AD27, AH28, AG26, AE25,
AG24, AE22, AJ23, AG20,
AE18, AG18, AE16, AG16,
AG14, AE13, AG12, AE10,
AG10, AG8, AE7, AG6, AE4,
AG4, AG3, AE3
AD28, AG29, AH26, AF25,
AH24, AG22, AH22, AE17,
AG19, AH18, AF16, AH16,
AH14, AF13, AH12, AF10,
AH10, AH8, AF7, AH6, AF4,
AH4, AG2, AE2
GMII/TBI Gigabit Ethernet Access Ports 0 & 1
M25_TXD[15:0]
Transmit Data Bit [15:0]
[7:0] - GMII
U26, U25, V26, V25, W26,
W25, Y27, Y26, AA26, AA25,
AB26, AB25, AC26, AC25,
AD26, AD25
Output
[9:0] - TBI
[15:0] - 2G
80
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball Signal Descriptions Table (continued)
Ball No(s)
Symbol
I/O
Description
Receive Data Valid
M25_RX_DV
M25_RX_ER
M25_CRS
Input w/ pull down
Input w/ pull up
Input w/ pull down
Input w/ pull up
Input w/ pull up
Input w/ pull up
T28
U28
R25
U29
T29
Receive Error
Carrier Sense
Collision Detected
Receive Clock
M25_COL
M25_RXCLK
M25_RXD[15:0]
Receive Data Bit [15:0]
U27, V29, V28, V27, W29,
W28, W27, Y29, Y28, Y25,
AA29, AA28, AA27, AB29,
AB28, AB27
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
M25_TX_EN
M25_TX_ER
M25_MTXCLK
M25_ TXCLK
GREF_CLK0
M26_TXD[15:0]
Transmit Data Enable
Transmit Error
Output w/ pull up
Output w/ pull up
Input w/ pull down
Output
T26
R26
T27
T25
P29
MII Mode Transmit Clock
Gigabit Transmit Clock
Gigabit Reference Clock
Transmit Data Bit [15:0]
Input w/ pull up
G26, G25, H26, H25, J26,
J25, K25, K26, M25, L26,
M26, L25, N26, N25, P26,
P25
Output
[7:0] - GMII
[9:0] - TBI
[15:0] - 2 G
M26_RX_DV
M26_RX_ER
M26_CRS
Input w/ pull down
Input w/ pull up
Input w/ pull down
Input w/ pull up
Input w/ pull up
Input w/ pull up
Receive Data Valid
Receive Error
F28
G28
E25
G29
F29
Carrier Sense
M26_COL
Collision Detected
Receive Clock
M26_RXCLK
M26_RXD[15:0]
Receive Data Bit [15:0]
G27,H29, H28, H27, J29,
J28, J27, K29, K28, K27,
L29, L28, L27, M29, M28,
M27
[7:0] - GMII
[9:0] - TBI
[15:0] - 2 G
M26_TX_EN
M26_TX_ER
M26_MTXCLK
M26_ TXCLK
GREF_CLK1
Output w/ pull up
Output w/ pull up
Input w/ pull down
Output
Transmit Data Enable
Transmit Error
F26
E26
F27
F25
N29
MII Mode Transmit Clock
Gigabit Transmit Clock
Gigabit Reference Clock
Input w/ pull up
81
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball Signal Descriptions Table (continued)
Ball No(s)
LED Interface
Symbol
I/O
Description
LED_CLK/TSTOUT0
LED_SYN/TSTOUT1
LED_BIT/TSTOUT2
I/O- TS with pull up
I/O- TS with pull up
I/O- TS with pull up
I/O- TS with pull up
LED Serial Interface Output Clock
C29
D29
E29
B28
LED Output Data Stream Envelope
LED Serial Data Output Stream
G1_RXTX#/TSTOUT
3
LED for Gigabit port 1 (receive +
transmit)
G1_DPCOL#/TSTOU
T4
I/O- TS with pull up
C28
LED for Gigabit port 1 (full duplex +
collision)
G1_LINK#/TSTOUT5
I/O- TS with pull up
I/O- TS with pull up
D28
E28
LED for Gigabit port 1
G2_RXTX#/TSTOUT
6
LED for Gigabit port 2 (receive +
transmit)
G2_DPCOL#/TSTOU
T7
I/O- TS with pull up
A27
LED for Gigabit port 2 (full duplex +
collision)
G2_LINK#/TSTOUT8
I/O- TS with pull up
B27
C27
LED for Gigabit port 2
System start operation
INIT_DONE/TSTOUT I/O- TS with pull up
9
INIT_START/TSTOU
T10
I/O- TS with pull up
I/O- TS with pull up
I/O- TS with pull up
Start initialization
D27
C26
D26
D25
D24
E24
CHECKSUM_OK/TS
TOUT11
EEPROM read OK
FCB_ERR/TSTOUT1
2
FCB memory self test fail
MCT memory self test fail
Processing memory self test
Memory self test done
MCT_ERR/TSTOUT1 I/O- TS with pull up
3
BIST_IN_PRC/TSTO
UT14
I/O- TS with pull up
BIST_DONE/TSTOU
T15
I/O- TS with pull up
Trunk Enable
TRUNK0
TRUNK1
TRUNK2
Input w/ weak internal pull Trunk Port Enable
down resistors
C22
Input w/ weak internal pull Trunk Port Enable
down resistors
A21
Input w/ weak internal pull Trunk Port Enable
down resistors
B24
Test Facility
82
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball Signal Descriptions Table (continued)
Ball No(s)
Symbol
T_MODE0
I/O
Description
I/O-TS
I/O-TS
Test Pin – Set Mode upon Reset, and
provides NAND Tree test output
during test mode (Pull Up)
U3
T_MODE1
Test Pin – Set Mode upon Reset, and
provides NAND Tree test output
during test mode (Pull Up)
C10
T_MODE1 T_MODE0
0
0
1
1
0
1
0
NandTree
Reserved
Reserved
Regular
1
operation
T_MODE0 and T_MODE1 are used
for manufacturing tests. The signals
should both be set to 1 for regular
operation.
SCAN_EN
Input with pull down
Input with pull down
Scan Enable
F3
0 - Normal mode (unconnected)
1 - Enables Test mode.
SCANMODE
E27
0 - Normal mode (unconnected)
System Clock, Power, and Ground Pins
SCLK
VDD
Input
System Clock at 100 MHz
+2.5 Volt DC Supply
E1
Power
K12, K13, K17,K18 M10,
N10, M20, N20, U10, V10,
U20, V20, Y12, Y13, Y17,
Y18
VCC
VSS
Power
+3.3 Volt DC Supply
Ground
F13, F14, F15, F16, F17, N6,
P6, R6, T6, U6, N24, P24,
R24, T24, U24, AD13, AD14,
AD15, AD16, AD17
Power Ground
M12, M13, M14, M15, M16,
M17, M18, N12, N13, N14,
N15, N16, N17, N18, P12,
P13, P14, P15, P16, P17,
P18, R12, R13, R14, R15,
R16, R17, R18, T12, T13,
T14, T15, T16, T17, T18,
U12, U13, U14, U15, U16,
U17, U18, V12, V13, V14,
V15, V16, V17, V18,
AVCC
AGND
Analog Power
Analog Ground
Analog +2.5 Volt DC Supply
Analog Ground
F1
D1
83
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball Signal Descriptions Table (continued)
Ball No(s) Symbol
I/O
Description
MISC
SCANCOL
Input
Scans the Collision signal of Home
PHY
D22
SCANCLK
Input/ output
Clock for scanning Home PHY
collision and link
D23
SCANLINK
RESIN#
Input
Link up signal from Home PHY
Reset Input
E23
Input
F2
RESETOUT#
Reserved
Output
I/O-TS
Reset PHY
G2
Reserved Pins. Leave
unconnected.
E20, B25
Bootstrap Pins (Default= pull up, 1= pull up 0= pull down)
After reset TSTOUT0 to TSTOUT15 are used by the LED interface.
TSTOUT0
TSTOUT1
TSTOUT2
Default: Active High (1)
GIGA Link polarity
C29
D29
E29
0 - Active low
1 - Active high
Default: Enable (1)
RMII MAC Power Saving Enable
0 - No power saving
1 - Power saving
Default: Enable (1)
Recommend disable
(0) with pull-down
Giga Half Duplex Support
0 - Disable
1 - Enable
TSTOUT[4:3]
TSTOUT4
C28, B28
C28
Reserved
Default: SBRAM (1)
Default: SCLK (1)
Memory is SBRAM/ZBT
0 - ZBT
1 – Pipeline SBRAM
TSTOUT5
Scan Speed
D28
0 - ¼ SCLK(HPNA)
1 - SCLK
TSTOUT6
TSTOUT7
Reserved
E28
A27
Default: 128 K x 32 or Memory Size
128 K x 64 (1)
0 - 256 K x 32 or 256 K x 64
(4 M total)
1 - 128 K x 32 or 128 K x 64
(2 M total)
84
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball Signal Descriptions Table (continued)
Ball No(s)
Symbol
TSTOUT8
I/O
Default: Not Installed (1)
Description
EEPROM Installed
B27
C27
D27
C26
0 - EEPROM installed
1 - EEPROM not installed
TSTOUT9
TSTOUT10
TSTOUT11
Default:
MCT
FCB
aging MCT Aging
enable (1)
0 - MCT aging disable
1 - MCT aging enable
Default:
aging FCB Aging
enable (1)
0 - FCB aging disable
1 - FCB aging enable
Default: Timeout reset Timeout Reset
enable (1)
0 - Time out reset disable
1 - Time out reset enable. Issue reset
if any state machine did not go back
to idle for 5 Sec.
TSTOUT12
TSTOUT13
Default: Normal (1)
Test Speed Up
D26
D25
0 - Enable test speed up. Do not use.
1 - Disable test speed up
Default: Single depth (1)
FDB RAM depth (1 or 2 layers)
0 - Two layers
1 - One layer
TSTOUT14
TSTOUT15
Reserved.
D24
E24
Default: Normal operation SRAM Test Mode
0 - Enable test mode
1 - Normal operation
G0_TXEN, G0_TXER Default: PCS
G1_TXEN, G1_TXER Default: PCS
Giga0
T26, R26
F26, E26
Mode: G0_TXEN G0_TXER
0
0
MII
2 G
GMII
PCS
0
1
1
1
0
1
Giga1
Mode: G1_TXEN G1_TXER
0
0
MII
0
1
0
1
2 G
1
1
GMII
PCS
85
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball Signal Descriptions Table (continued)
Ball No(s)
Symbol
I/O
Description
M[23:0]_TXEN
Default: RMII
0 – GPSI
1 - RMII
AD29, AG28, AJ26, AE26,
AJ24, AE23, AJ22, AJ20,
AE20, AJ18, AJ21, AJ16,
AJ14, AE14, AJ12, AE11,
AJ10, AJ8, AE8, AJ6, AE5,
AJ4, AG1, AE1,
P_D
Must be pulled-down
Default: 111
C21
Reserved. Must be pulled-down.
OE_CLK[2:0]
Programmable delay for internal
OE_CLK from SCLK input. The
OE_CLK is used for generating the
OE0 and OE1 signals
C19, B19, A19
Suggested value is 001.
LA_CLK[2:0]
MIRROR[5:0]
Default: 111
Programmable delay for LA_CLK and
LB_CLK from internal OE_CLK. The
LA_CLK and LB_CLK delay from
SCLK is the sum of the delay
programmed in here and the delay in
P_D[15:13].
C20, B20, A20
Suggested value is 011.
Default: 111111
Dedicated Port Mirror Mode. The first
5 bits select the port to be mirrored.
The last bit selects either ingress or
egress data.
B22, A22, C23, B23, A23,
C24
Note:
# = Active low signal
Input = Input signal
In-ST = Input signal with Schmitt-Trigger
Output = Output signal (Tri-State driver)
Out-OD = Output signal with Open-Drain driver
I/O-TS = Input & Output signal with Tri-State driver
I/O-OD = Input & Output signal with Open-Drain driver
14.3 Ball – Signal Name
Ball – Signal Name Table
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Signal Name
Ball No.
LA_D[63]
LA_D[62]
LA_D[61]
LA_D[60]
LA_D[59]
LA_D[58]
D3
LA_D[19]
LA_D[18]
LA_D[17]
LA_D[16]
LA_D[15]
LA_D[14]
A9
B9
F4
F5
G4
G5
LA_OE0#
LA_OE1#
LB_D[63]
LB_D[62]
LB_D[61]
LB_D[60]
D20
E3
D2
E2
A7
B7
B21
D19
E19
D18
E18
86
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball – Signal Name Table (continued)
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Signal Name
Ball No.
H4
LA_D[57]
LA_D[56]
LA_D[55]
LA_D[54]
LA_D[53]
LA_D[52]
LA_D[51]
LA_D[50]
LA_D[49]
LA_D[48]
LA_D[47]
LA_D[46]
LA_D[45]
LA_D[44]
LA_D[43]
LA_D[42]
LA_D[41]
LA_D[40]
LA_D[39]
LA_D[38]
LA_D[37]
LA_D[36]
LA_D[35]
LA_D[34]
LA_D[33]
LA_D[32]
LA_D[31]
LA_D[30]
LA_D[29]
LA_D[28]
A6
LA_D[13]
LA_D[12]
LA_D[11]
LA_D[10]
LA_D[9]
LA_D[8]
LA_D[7]
LA_D[6]
LA_D[5]
LA_D[4]
LA_D[3]
LA_D[2]
LA_D[1]
LA_D[0]
LA_A[20]
LA_A[19]
LA_A[18]
LA_A[17]
LA_A[16]
LA_A[15]
LA_A[14]
LA_A[13]
LA_A[12]
LA_A[11]
LA_A[10]
LA_A[9]
LA_A[8]
LA_A[7]
LA_A[6]
LA_A[5]
LB_D[59]
LB_D[58]
LB_D[57]
LB_D[56]
LB_D[55]
LB_D[54]
LB_D[53]
LB_D[52]
LB_D[51]
LB_D[50]
LB_D[49]
LB_D[48]
LB_D[47]
LB_D[46]
LB_D[45]
LB_D[44]
LB_D[43]
LB_D[42]
LB_D[41]
LB_D[40]
LB_D[39]
LB_D[38]
LB_D[37]
LB_D[36]
LB_D[35]
LB_D[34]
LB_D[33]
LB_D[32]
LB_D[31]
LB_D[30]
D17
B6
H5
J4
E17
D16
E16
D15
E15
D14
E14
D13
E13
D21
E21
A18
B18
C18
A17
B17
C17
A16
B16
C16
A15
B15
C15
A14
B14
D9
C6
A5
J5
B5
K4
K5
L4
L5
M4
M5
N4
N5
G3
H1
H2
H3
J1
C5
A4
B4
C4
A3
B3
C3
B2
C2
C14
A13
B13
C13
A12
B12
C12
A11
B11
C11
D11
E11
A10
B10
D10
E10
J2
J3
K1
K2
K3
L1
L2
L3
M1
M2
M3
U4
U5
E9
D8
E8
87
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball – Signal Name Table (continued)
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Signal Name
Ball No.
V4
LA_D[27]
LA_D[26]
LA_D[25]
LA_D[24]
LA_D[23]
LA_D[22]
LA_D[21]
LA_D[20]
LB_D[21]
LB_D[20]
LB_D[19]
LB_D[18]
LB_D[17]
LB_D[16]
LB_D[15]
LB_D[14]
LB_D[13]
LB_D[12]
LB_D[11]
LB_D[10]
LB_D[9]
A8
LA_A[4]
LB_D[29]
D7
C7
LA_A[3]
V5
LB_D[28]
E7
B8
LA_ADSC#
LA_CLK
W4
LB_D[27]
D6
C1
W5
LB_D[26]
E6
C9
LA_WE#
Y4
LB_D[25]
D5
D12
E12
LA_WE0#
Y5
LB_D[24]
E5
LA_WE1#
AA4
LB_D[23]
D4
C8
LA_OE#
AA5
LB_D[22]
E4
U2
LB_OE1#
AH7
M[4]_RXD[0]
M[3]_RXD[0]
M[2]_RXD[0]
M[1]_RXD[0]
M[0]_RXD[0]
AB4
AB5
AC4
AC5
AD4
AD5
W1
R28
P28
MDC
AE6
MDIO
AH5
R29
AC29
AE28
AJ27
AF27
AJ25
AF24
AH23
AE19
AF21
AJ19
AF18
AJ17
AJ15
AF15
AJ13
AF12
AJ11
AJ9
M_CLK
AH2
AF2
M[23]_RXD[1]
M[22]_RXD[1]
M[21]_RXD[1]
M[20]_RXD[1]
M[19]_RXD[1]
M[18]_RXD[1]
M[17]_RXD[1]
M[16]_RXD[1]
M[15]_RXD[1]
M[14]_RXD[1]
M[13]_RXD[1]
M[12]_RXD[1]
M[11]_RXD[1]
M[10]_RXD[1]
M[9]_RXD[1]
M[8]_RXD[1]
M[7]_RXD[1]
M[6]_RXD[1]
AC27
AF29
AG27
AF26
AG25
AG23
AF23
AG21
AH21
AF19
AF17
AG17
AG15
AF14
AG13
AF11
AG11
M[23]_CRS_DV
M[22]_CRS_DV
M[21]_CRS_DV
M[20]_CRS_DV
M[19]_CRS_DV
M[18]_CRS_DV
M[17]_CRS_DV
M[16]_CRS_DV
M[15]_CRS_DV
M[14]_CRS_DV
M[13]_CRS_DV
M[12]_CRS_DV
M[11]_CRS_DV
M[10]_CRS_DV
M[9]_CRS_DV
M[8]_CRS_DV
M[7]_CRS_DV
Y1
Y2
Y3
AA1
AA2
AA3
AB1
AB2
AB3
AC1
AC2
AC3
AD1
AD2
AD3
LB_D[8]
LB_D[7]
LB_D[6]
LB_D[5]
LB_D[4]
LB_D[3]
LB_D[2]
LB_D[1]
LB_D[0]
88
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball – Signal Name Table (continued)
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Signal Name
Ball No.
AG9
LB_A[20]
LB_A[19]
LB_A[18]
LB_A[17]
LB_A[16]
LB_A[15]
LB_A[14]
LB_A[13]
LB_A[12]
LB_A[11]
LB_A[10]
LB_A[9]
AF9
M[5]_RXD[1]
M[4]_RXD[1]
M[3]_RXD[1]
M[2]_RXD[1]
M[1]_RXD[1]
M[0]_RXD[1]
M[23]_RXD[0]
M[22]_RXD[0]
M[21]_RXD[0]
M[20]_RXD[0]
M[19]_RXD[0]
M[18]_RXD[0]
M[17]_RXD[0]
M[16]_RXD[0]
M[15]_RXD[0]
M[14]_RXD[0]
M[13]_RXD[0]
M[12]_RXD[0]
M[11]_RXD[0]
M[10]_RXD[0]
M[9]_RXD[0]
M[8]_RXD[0]
M[7]_RXD[0]
M[6]_RXD[0]
M[5]_RXD[0]
M[6]_TXD[0]
M[5]_TXD[0]
M[4]_TXD[0]
M[3]_TXD[0]
M[2]_TXD[0]
M[6]_CRS_DV
N3
AJ7
AF8
M[5]_CRS_DV
M[4]_CRS_DV
M[3]_CRS_DV
M[2]_CRS_DV
M[1]_CRS_DV
M[0]_CRS_DV
M[23]_TXEN
M[22]_TXEN
M[21]_TXEN
M[20]_TXEN
M[19]_TXEN
M[18]_TXEN
M[17]_TXEN
M[16]_TXEN
M[15]_TXEN
M[14]_TXEN
M[13]_TXEN
M[12]_TXEN
M[11]_TXEN
M[10]_TXEN
M[9]_TXEN
N2
N1
P3
AF6
AG7
AF5
AJ5
AJ3
AG5
AH3
P2
AF1
P1
AC28
AF28
AH27
AE27
AH25
AE24
AF22
AF20
AE21
AH19
AH20
AH17
AH15
AE15
AH13
AE12
AH11
AH9
AF3
R5
R4
R3
R2
R1
T5
AD29
AG28
AJ26
AE26
AJ24
AE23
AJ22
AJ20
AE20
AJ18
AJ21
AJ16
AJ14
AE14
AJ12
AE11
AJ10
AJ8
LB_A[8]
T4
LB_A[7]
T3
LB_A[6]
T2
LB_A[5]
T1
LB_A[4]
W3
W2
V1
LB_A[3]
LB_ADSC#
LB_CLK
G1
V3
LB_WE#
LB_WE0#
LB_WE1#
LB_OE#
P4
M[8]_TXEN
P5
M[7]_TXEN
V2
LB_OE0#
M[5]_TXEN
M[4]_TXEN
M[3]_TXEN
M[2]_TXEN
M[1]_TXEN
AE9
M[6]_TXEN
U1
AE8
AJ6
AE5
AJ4
AG1
AH8
G27
M26_RXD[15]
M26_RXD[14]
M26_RXD[13]
M26_RXD[12]
M26_RXD[11]
AF7
H29
AH6
H28
AF4
H27
AH4
J29
89
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball – Signal Name Table (continued)
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Signal Name
Ball No.
J28
M[0]_TXEN
AG2
M[1]_TXD[0]
M[0]_TXD[0]
M25_TXD[15]
M25_TXD[14]
M25_TXD[13]
M25_TXD[12]
M25_TXD[11]
M25_TXD[10]
M25_TXD[9]
M25_TXD[8]
M25_TXD[7]
M25_TXD[6]
M25_TXD[5]
M25_TXD[4]
M25_TXD[3]
M25_TXD[2]
M25_TXD[1]
M25_TXD[0]
M25_RXD[15]
M25_RXD[14]
M25_RXD[13]
M25_RXD[12]
M25_RXD[11]
M25_RXD[10]
M25_RXD[9]
M25_RXD[8]
M25_RXD[7]
M25_RXD[6]
M25_RXD[5]
M25_RXD[4]
M26_RXD[10]
M26_RXD[9]
M26_RXD[8]
M26_RXD[7]
M26_RXD[6]
M26_RXD[5]
M26_RXD[4]
M26_RXD[3]
M26_RXD[2]
M26_RXD[1]
M26_RXD[0]
M26_TXD[15]
M26_TXD[14]
M26_TXD[13]
M26_TXD[12]
M26_TXD[11]
M26_TXD[10]
M26_TXD[9]
M26_TXD[8]
M26_TXD[7]
M26_TXD[6]
M26_TXD[5]
M26_TXD[4]
M26_TXD[3]
M26_TXD[2]
M26_TXD[1]
M26_TXD[0]
M26_RX_DV
M26_RX_ER
M26_CRS
AE1
M[23]_TXD[1]
M[22]_TXD[1]
M[21]_TXD[1]
M[20]_TXD[1]
M[19]_TXD[1]
M[18]_TXD[1]
M[17]_TXD[1]
M[16]_TXD[1]
M[15]_TXD[1]
M[14]_TXD[1]
M[13]_TXD[1]
M[12]_TXD[1]
M[11]_TXD[1]
M[10]_TXD[1]
M[9]_TXD[1]
M[8]_TXD[1]
M[7]_TXD[1]
M[6]_TXD[1]
M[5]_TXD[1]
M[4]_TXD[1]
M[3]_TXD[1]
M[2]_TXD[1]
M[1]_TXD[1]
M[0]_TXD[1]
M[23]_TXD[0]
M[22]_TXD[0]
M[21]_TXD[0]
M[20]_TXD[0]
M[19]_TXD[0]
AE2
U26
J27
AD27
AH28
AG26
AE25
AG24
AE22
AJ23
AG20
AE18
AG18
AE16
AG16
AG14
AE13
AG12
AE10
AG10
AG8
K29
K28
K27
L29
L28
L27
M29
M28
M27
G26
G25
H26
H25
J26
U25
V26
V25
W26
W25
Y27
Y26
AA26
AA25
AB26
AB25
AC26
AC25
AD26
AD25
U27
J25
K25
K26
M25
L26
M26
L25
N26
N25
P26
P25
F28
G28
E25
V29
AE7
V28
AG6
V27
AE4
W29
W28
W27
Y29
AG4
AG3
AE3
AD28
AG29
AH26
AF25
AH24
Y28
Y25
AA29
AA28
90
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball – Signal Name Table (continued)
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Signal Name
Ball No.
G29
M[18]_TXD[0]
AA27
AB29
AB28
AB27
R26
T25
T26
T28
U28
R25
U29
T29
U18
V12
V13
V14
V15
V16
V17
V18
N14
N15
N16
N17
N18
P12
P13
P14
P15
P16
M25_RXD[3]
M25_RXD[2]
M25_RXD[1]
M25_RXD[0]
M25_TX_ER
M25_TXCLK
M25_TX_EN
M25_RX_DV
M25_RX_ER
M25_CRS
M25_COL
M25_RXCLK
VSS
M26_COL
AG22
AH22
AE17
AG19
AH18
AF16
AH16
AH14
AF13
AH12
AF10
AH10
B27
M[17]_TXD[0]
F29
F26
E26
F25
E24
D24
D25
D26
C26
D27
C27
N12
N13
K17
K18
M10
N10
M20
N20
U10
V10
U20
V20
Y12
Y13
Y17
Y18
K12
K13
M26_RXCLK
M26_TX_EN
M26_TX_ER
M26_TXCLK
M[16]_TXD[0]
M[15]_TXD[0]
M[14]_TXD[0]
M[13]_TXD[0]
BIST_DONE/TSTOUT[15]
M[12]_TXD[0]
BIST_IN_PRC/TST0UT[14]
M[11]_TXD[0]
MCT_ERR/TSTOUT[13]
M[10]_TXD[0]
FCB_ERR/TSTOUT[12]
M[9]_TXD[0]
CHECKSUM_OK/TSTOUT[11]
M[8]_TXD[0]
INIT_START/TSTOUT[10]
M[7]_TXD[0]
INIT_DONE/TSTOUT[9]
G2_LINK#/TSTOUT[8]
G2_DPCOL#/TSTOUT[7]
G2_RXTX#/TSTOUT[6]
G1_LINK#/TSTOUT[5]
G1_DPCOL#/TSTOUT[4]
G1_RXTX#/TSTOUT[3]
LED_BIT/TSTOUT[2]
LED_SYN/TSTOUT[1]
LED_CLK/TSTOUT[0]
GREF_CLK1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A27
VSS
E28
VSS
D28
VSS
C28
VSS
B28
VSS
E29
VSS
D29
VSS
C29
VSS
N29
GREF_CLK0
VSS
P29
SCAN_EN
VSS
F3
SCLK
VSS
E1
T_MODE0
VSS
U3
T_MODE1
VSS
C10
TRUNK2
VSS
B24
TRUNK1
VSS
A21
TRUNK0
VSS
C22
91
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
Ball – Signal Name Table (continued)
Ball
No.
Signal
Name
Ball
No.
Signal
Name
Signal Name
Ball No.
M16
STROBE
D0
C19
OE_CLK2
OE_CLK1
OE_CLK0
VSS
VSS
A26
B19
A19
R13
R14
R15
R16
R17
R18
T12
T13
T14
T15
T16
M17
M18
F16
F17
N6
VSS
B26
C25
A24
A25
F1
AUTOFD
SCL
VSS
VCC
SDA
VSS
VCC
AVCC
VSS
VCC
AGND
VSS
P6
VCC
D1
SCANCOL
SCANLINK
VSS
R6
VCC
D22
E23
E27
N28
N27
F2
VSS
T6
VCC
SCANMODE
VSS
U6
VCC
VSS
N24
P24
R24
T24
U24
AD13
AD14
AD15
AD16
AD17
F13
F14
F15
R12
B25
E20
P18
VCC
VSS
VCC
RESIN#
VSS
VCC
RESETOUT#
VSS
VCC
G2
VSS
VCC
B22
A22
C23
B23
A23
C24
D23
T27
F27
C20
B20
A20
C21
T17
T18
U12
U13
U14
MIRROR5
MIRROR4
VSS
VCC
MIRROR3
MIRROR2
MIRROR1
MIRROR0
SCANCLK
M25_MTXCLK
M26_MTXCLK
LA_CLK2
LA_CLK1
LA_CLK0
P_D
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
U15
U16
VSS
VCC
U17
M12
M13
M14
M15
P17
VSS
VCC
VSS
VCC
VSS
VSS
VSS
RESERVED
RESERVED
VSS
VSS
VSS
92
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.4 AC/DC Timing
14.4.1 Absolute Maximum Ratings
Storage Temperature
-65°C to +150°C
Operating Temperature
-40°C to +85°C
+125°C
Maximum Junction Temperature
Supply Voltage VCC with Respect to V
Supply Voltage VDD with Respect to V
Voltage on Input Pins
+3.0 V to +3.6 V
+2.38 V to +2.75 V
-0.5 V to (VCC + 0.3 V)
SS
SS
Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for
extended periods may affect device reliability. Functionality at or above these limits is not implied.
14.4.2 DC Electrical Characteristics
VCC = 3.0 V to 3.6 V (3.3v +/- 10%)T
VDD = 2.5 V +10% - 5%
= -40°C to +85°C
AMBIENT
14.4.3 Recommended Operating Conditions
Symbol
fosc
Parameter Description
Frequency of Operation
Min.
Typ.
100
Max.
Unit
MHz
ICC
Supply Current – @ 100 MHz (VCC =3.3 V)
Supply Current – @ 100 MHz (VDD =2.5 V)
Output High Voltage (CMOS)
450
mA
mA
V
IDD
1500
VOH
VOL
2.4
2.0
Output Low Voltage (CMOS)
0.4
V
VIH-TTL
Input High Voltage (TTL 5 V tolerant)
VCC +
2.0
V
VIL-TTL
IIL
Input Low Voltage (TTL 5 V tolerant)
0.8
10
V
Input Leakage Current (0.1 V < VIN < VCC) (all pins
except those with internal pull-up/pull-down resistors)
µA
IOL
CIN
COUT
CI/O
θja
Output Leakage Current (0.1 V < VOUT < VCC)
Input Capacitance
10
5
µA
pF
Output Capacitance
5
pF
I/O Capacitance
7
pF
Thermal resistance with 0 air flow
Thermal resistance with 1 m/s air flow
Thermal resistance with 2 m/s air flow
Thermal resistance between junction and case
Thermal resistance between junction and board
11.2
10.2
8.9
3.1
6.6
C/W
C/W
C/W
C/W
C/W
θja
θja
θjc
θjb
93
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.4.4 Typical Reset & Bootstrap Timing Diagram
RESIN#
RESETOUT#
Tri-Stated
R1
R3
Bootstrap Pins
Outputs
Inputs
Outputs
R2
Figure 18 - Typical Reset & Bootstrap Timing Diagram
Symbol
R1
Parameter
Min.
Typ.
Note:
Delay until RESETOUT# is tri-stated
10 ns
RESETOUT# state is then determined
by the external pull-up/down resistor
R2
R3
Bootstrap stabilization
1 µs
10 µs
Bootstrap pins sampled on rising
a
edge of RESIN#
RESETOUT# assertion
2 ms
Table 13 - Reset & Bootstrap Timing
a. The TSTOUT[8:0] pins will switch over to the LED interface functionality in 3 SCLK cycles after RESIN# goes high
94
Zarlink Semiconductor Inc.
MVTX2603
14.5 Local Frame Buffer SBRAM Memory Interface
14.5.1 Local SBRAM Memory Interface
Data Sheet
LA_CLK
L1
L2
LA_D[63:0]
Figure 19 - Local Memory Interface – Input Setup and Hold Timing
LA_CLK
L3-max
L3-min
LA_D[63:0]
L4-max
L4-min
LA_A[20:3]
L6-max
L6-min
LA_ADSC#
L7-max
L7-min
LA_WE[1:0]#
L8-max
L8-min
LA_OE[1:0]#
L9-max
L9-min
LA_WE#
L10-max
L10-min
LA_OE#
Figure 20 - Local Memory Interface - Output Valid Delay Timing
95
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
-100 MHz
Symbol
Parameter
Min. (ns) Max. (ns)
Note
L1
L2
L3
L4
L6
L7
L8
L9
L10
LA_D[63:0] input set-up time
LA_D[63:0] input hold time
LA_D[63:0] output valid delay
LA_A[20:3] output valid delay
LA_ADSC# output valid delay
4
1.5
1.5
2
7
7
7
7
1
7
5
C = 25 pf
L
C = 30 pf
L
1
C = 30 pf
L
LA_WE[1:0]#output valid delay
LA_OE[1:0]# output valid delay
LA_WE# output valid delay
LA_OE# output valid delay
1
C = 25 pf
L
-1
1
C = 25 pf
L
C = 25 pf
L
1
C = 25 pf
L
Table 14 - AC Characteristics – Local Frame Buffer SBRAM Memory Interface
96
Zarlink Semiconductor Inc.
MVTX2603
14.6 Local Switch Database SBRAM Memory Interface
14.6.1 Local SBRAM Memory Interface
Data Sheet
LB_CLK
L1
L2
LB_D[63:0]
Figure 21 - Local Memory Interface – Input Setup and Hold Timing
LB_CLK
LB_D[31:0]
LB_A[21:2]
L3-max
L3-min
L4-max
L4-min
L6-max
L6-min
LB_ADSC#
L8-max
L8-min
LB_WE[1:0]#
L9-max
L9-min
LB_OE[1:0]#
L10-max
L10-min
LB_WE#
LB_OE#
L11-max
L11-min
Figure 22 - Local Memory Interface - Output Valid Delay Timing
97
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
-100 MHz
Symbol
Parameter
Min. (ns) Max. (ns)
Note
L1
L2
LB_D[63:0] input set-up time
LB_D[63:0] input hold time
LB_D[63:0] output valid delay
LB_A[20:3] output valid delay
LB_ADSC# output valid delay
4
1.5
L3
1.5
2
7
7
7
7
1
7
5
C = 25 pf
L
L4
C = 30 pf
L
L6
1
C = 30 pf
L
L8
LB_WE[1:0]#output valid delay
LB_OE[1:0]# output valid delay
LB_WE# output valid delay
LB_OE# output valid delay
1
C = 25 pf
L
L9
-1
1
C = 25 pf
L
L10
L11
C = 25 pf
L
1
C = 25 pf
L
Table 15 - AC Characteristics – Local Switch Database SBRAM Memory Interface
98
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.7 AC Characteristics
14.7.1 Reduced Media Independent Interface
M_CLKI
M6-max
M6-min
M[23:0]_TXEN
M7-max
M7-min
M[23:0] _TXD[1:0]
Figure 23 - AC Characteristics – Reduced Media Independent Interface
M_CLKI
M2
M[23:0]_RXD
M3
M4
M[23:0]_CRS_DV
M5
Figure 24 - AC Characteristics – Reduced Media Independent Interface
-50 MHz
Symbol
Parameter
Note
Min. (ns)
Max. (ns)
M2
M3
M4
M5
M6
M7
M[23:0]_RXD[1:0] Input Setup Time
M[23:0]_RXD[1:0] Input Hold Time
M[23:0]_CRS_DV Input Setup Time
M[23:0]_CRS_DV Input Hold Time
M[23:0]_TXEN Output Delay Time
M[23:0]_TXD[1:0] Output Delay Time
4
1
4
1
2
2
11
11
C = 20 pF
L
C = 20 pF
L
Table 16 - AC Characteristics – Reduced Media Independent Interface
99
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.7.2 Gigabit Media Independent Interface - Port A
M25_TXCLK
G12-max
G12-min
M25_TXD [15:0]
M25_TX_EN]
M25_TX_ER
G13-max
G13-min
G14-max
G14-min
Figure 25 - AC Characteristics- GMII
M25_RXCLK
G1
G3
G5
G7
G2
G4
M25_RXD[15:0]
M25_RX_DV
M25_RX_ER
M25_RX_CRS
G6
G8
Figure 26 - AC Characteristics – Gigabit Media Independent Interface
-125 Mhz
Symbol
Parameter
Note
Min. (ns)
Max. (ns)
G1
G2
G3
G4
G5
G6
G7
G8
M[25]_RXD[15:0] Input Setup Times
M[25]_RXD[15:0] Input Hold Times
M[25]_RX_DV Input Setup Times
M[25]_RX_DV Input Hold Times
M[25]_RX_ER Input Setup Times
M[25]_RX_ER Input Hold Times
M[25]_CRS Input Setup Times
M[25]_CRS Input Hold Times
2
1
2
1
2
1
2
1
Table 17 - AC Characteristics – Gigabit Media Independent Interface
100
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
-125 Mhz
Symbol
Parameter
Note
C = 20 pf
Min. (ns)
Max. (ns)
G12
G13
G14
M[25]_TXD[15:0] Output Delay Times
M[25]_TX_EN Output Delay Times
M[25]_TX_ER Output Delay Times
1
1
1
6
6.5
6
L
C = 20 pf
L
C = 20 pf
L
Table 17 - AC Characteristics – Gigabit Media Independent Interface (continued)
14.7.3 Ten Bit Interface - Port A
M25_TXCLK
TIMIN
M25_TXD [9:0]
TIMAX
Figure 27 - Gigabit TBI Interface Transmit Timing
M25_RXCLK
M25_COL
T2
T2
M25_RXD[9:0]
T3
T3
Figure 28 - Gigabit TBI Interface Receive Timing
Symbol
Parameter
Min. (ns)
Max. (ns)
Note
T1
M25_TXD[9:0] Output Delay Time
1
6
C = 20 pf
L
Table 18 - Output Delay Timing
Symbol
Parameter
Min. (ns)
Max. (ns)
Note
T2
T3
M25_RXD[9:0] Input Setup Time
M25_RXD[9:0] Input Hold Time
3
3
Table 19 - Input Setup Timing
101
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.7.4 Gigabit Media Independent Interface - Port B
M26_TXCLK
G12-max
G12-min
M26_TXD [15:0]
G13-max
G13-min
M26_TX_EN]
G14-max
G14-min
M26_TX_ER
Figure 29 - AC Characteristics- GMII
M26_RXCLK
G1
G3
G5
G7
G2
G4
M26_RXD[15:0]
M26_RX_DV
M26_RX_ER
M26_RX_CRS
G6
G8
Figure 30 - AC Characteristics – Gigabit Media Independent Interface
-125 Mhz
Symbol
Parameter
Note
Min. (ns)
Max. (ns)
G1
G2
G3
G4
G5
G6
G7
G8
M[26]_RXD[15:0] Input Setup Times
M[26]_RXD[15:0] Input Hold Times
M[26]_RX_DV Input Setup Times
M[26]_RX_DV Input Hold Times
M[26]_RX_ER Input Setup Times
M[26]_RX_ER Input Hold Times
M[26]_CRS Input Setup Times
M[26]_CRS Input Hold Times
2
1
2
1
2
1
2
1
Table 20 - AC Characteristics – Gigabit Media Independent Interface
102
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
-125 Mhz
Symbol
Parameter
Note
C = 20 pf
Min. (ns)
Max. (ns)
G12
G13
G14
M[26]_TXD[15:0] Output Delay Times
M[26]_TX_EN Output Delay Times
M[26]_TX_ER Output Delay Times
1
1
1
6
6.5
6
L
C = 20 pf
L
C = 20 pf
L
Table 20 - AC Characteristics – Gigabit Media Independent Interface (continued)
14.7.5 Ten Bit Interface - Port B
M26_TXCLK
TIMIN
M26_TXD [9:0]
TIMAX
Figure 31 - Gigabit TBI Interface Transmit Timing
M26_RXCLK
M26_COL
T2
T2
M26_RXD[9:0]
T3
T3
Figure 32 - Gigabit TBI Interface Timing
Symbol
Parameter
Min. (ns)
Max. (ns)
Note
T1
M26_TXD[9:0] Output Delay Time
1
6
C = 20 pf
L
Table 21 - Output Delay Timing
Symbol
Parameter
Min. (ns)
Max. (ns)
Note
T2
T3
M26_RXD[9:0] Input Setup Time
M26_RXD[9:0] Input Hold Time
3
3
Table 22 - Input Setup Timing
103
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.7.6 LED Interface
LED_CLK
LED_SYN
LED_BIT
LE5-max
LE5-min
LE6-max
LE6-min
Figure 33 - AC Characteristics – LED Interface
Variable FREQ.
Parameter
Symbol
Note
C = 30 pf
Min. (ns)
Max. (ns)
LE5
LE6
LED_SYN Output Valid Delay
LED_BIT Output Valid Delay
-1
-1
7
7
L
C = 30 pf
L
Table 23 - AC Characteristics – LED Interface
14.7.7 SCANLINK SCANCOL Output Delay Timing
SCANCLK
C5-max
C5-min
SCANLINK
SCANCOL
C7-max
C7-min
Figure 34 - SCANLINK SCANCOL Output Delay Timing
SCANCLK
C1
C2
SCANLINK
C3
C4
SCANCOL
Figure 35 - SCANLINK, SCANCOL Setup Timing
104
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
-25 MHz
Symbol
Parameter
Note
Min. (ns) Max. (ns)
C1
C2
C3
C4
C5
C7
SCANLINK input set-up time
SCANLINK input hold time
SCANCOL input setup time
SCANCOL input hold time
SCANLINK output valid delay
SCANCOL output valid delay
20
2
20
1
0
0
10
10
C = 30 pf
L
C = 30 pf
L
Table 24 - SCANLINK, SCANCOL Timing
14.7.8 MDIO Input Setup and Hold Timing
MDC
D1
D2
MDIO
Figure 36 - MDIO Input Setup and Hold Timing
MDC
D3-max
D3-min
MDIO
Figure 37 - MDIO Output Delay Timing
1 MHz
Parameter
Symbol
Note
Min. (ns) Max. (ns)
D1
D2
D3
MDIO input setup time
10
2
MDIO input hold time
MDIO output delay time
1
20
C = 50 pf
L
Table 25 - MDIO Timing
105
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
2
14.7.9 I C Input Setup Timing
SCL
SDA
S2
S1
Figure 38 - I2C Input Setup Timing
SCL
S3-max
S3-min
SDA
Figure 39 - I2C Output Delay Timing
50 KHz
Symbol
Parameter
Note
Min. (ns) Max. (ns)
S1
S2
SDA input setup time
SDA input hold time
SDA output delay time
20
1
S3*
4 usec
6 usec
C = 30 pf
L
* Open Drain Output. Low to High transistor is controlled by external pullup resistor.
Table 26 - I2C Timing
106
Zarlink Semiconductor Inc.
MVTX2603
Data Sheet
14.7.10 Serial Interface Setup Timing
STROBE
D4
D5
D1
D1
D2
D2
D0
Figure 40 - Serial Interface Setup Timing
STROBE
D3-max
D3-min
AutoFd
Figure 41 - Serial Interface Output Delay Timing
Symbol
Parameter
Min. (ns) Max. (ns)
Note
D1
D2
D3
D4
D5
D0 setup time
D0 hold time
20
3 µs
AutoFd output delay time
Strobe low time
1
50
C = 100 pf
L
5 µs
5 µs
Strobe high time
Table 27 - Serial Interface Timing
107
Zarlink Semiconductor Inc.
DIMENSION
MIN
MAX
A
A1
A2
D
D1
E
2.20
0.50
2.46
0.70
1.17 REF
37.70
37.30
37.30
34.50 REF
37.70
E1
E
E1
b
e
34.50 REF
0.60
0.90
1.27
553
Conforms to JEDEC MS - 034
e
D
D1
A2
b
NOTE:
1. CONTROLLING DIMENSIONS ARE IN MM
2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER
3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
4. N IS THE NUMBER OF SOLDER BALLS
5. NOT TO SCALE.
6. SUBSTRATE THICKNESS IS 0.56 MM
Package Code
Previous package codes:
ISSUE
ACN
DATE
APPRD.
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
MVTX2603AG2
DATACOM, LAN SWITCHING CIRCUIT, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553
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MVTX2604AG2
LAN Switching Circuit, CMOS, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553
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MVTX2802AG
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