MVTX2801A [ETC]
Unmanaged 4 port Gigabit Ethernet switch ; 非托管的4端口千兆以太网交换机\n
| 型号： | MVTX2801A |
| 厂家： | 
ETC |
| 描述： | Unmanaged 4 port Gigabit Ethernet switch
|
| 文件： | 总131页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MVTX2801AG
4-Port 1000 Mbps Ethernet Distributed Switch
Data Sheet
DS5748
Issue 1.1
May 2002
Features
•
4 Gigabit Ports with GMII and PCS interface
• Gigabit Port can also support 100/10 Mbps MII
interface
Ordering Information
MVTX2801AG 596-pin BGA
•
High Performance Layer 2 Packet Forwarding
(11.904M packets per second) and Filtering at
Full-Wire Speed
-40oC to + 85oC
WRED mechanism
• User controlled thresholds for WRED
•
•
•
Maximum throughput is 4 Gbps non-blocking
Centralized shared-memory architecture
Consists of two Memory Domains at 133 MHz
•
Classification based on layer 2, 3 markings
• VLAN Priority field in VLAN tagged frame.
• DS/TOS field in IP packet
• Frame Buffer Domain: one bank of ZBT-SRAM with
1M/2MB total
• The precedence of above two classifications can be
programmable
• Switch Database Domain with 256K/512K SRAM.
•
Up to 64K MAC addresses to provide large node
aggregation in wiring closet switches
•
•
QoS Support
Supports IEEE 802.1p/Q Quality of Service with 8
Priority
•
•
•
•
Buffer Management: reserve buffers on per class
and per port basis
Traffic Classification
•
•
•
Classify traffic into 8 transmission priorities per
port
Port-based Priority: VLAN Priority with Tagged
frame can be overwritten by the priority of PVID
Supports Delay bounded, Strict Priority, and
WFQ
QoS features can be configured on a per port
basis Control
Provides 2 level dropping precedence with
Full Duplex Ethernet IEEE 802.3x Flow Control
SRAM 256/512K
SW Databasee
MAC Table
Frame Data Buffer A
ZBT-SRAM (1M/2MB)
64bit
32bit
VTX2801
SDB Interface
LED
FDB Interface
Frame
Engine
Search
Engine
Scheduler
Management
Module
GMII
/PCS
Port 0
GMII
/PCS
Port 1
GMII
/PCS
Port 2
GMII
/PCS
Port 3
Serial/
I C
2
Figure 1 - Chip Block Diagram
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MVTX2801AG
Data Sheet
•
•
Provides Ethernet Multicast and Broadcast Control
2 Port Trunking groups, max of 3 ports per group (Trunking can be based on source MAC and/or
destination MAC and source port)
•
•
•
LED signals provided by a serial or parallel interface
Synchronous Serial Interface and I2C interface in unmanaged mode.
Hardware auto-negotiation through serial management interface (MDIO) for Gigabit Ethernet ports,
supports 10/100/1000 Mbps
•
•
•
BIST for internal and external SRAM-ZBT
I2C EEPROM or synchronous serial port for configuration
Packaged in 596-pin BGA
Description
The MVTX2800AG family is a group of 8-port 1000 Mbps non-blocking Ethernet switch chips with on-chip address
memory. A single chip provides a maximum of eight 1000 Mbps ports and a dedicated CPU interface with a 16/8-bit
bus for managed and unmanaged switch applications. The VTX2800 family consists of the following four products:
• VTX2804 8 Gigabit ports Managed
• VTX2803 8 Gigabit ports Unmanaged
• VTX2802 4 Gigabit ports Managed
• VTX2801 4 Gigabit ports Unmanaged
The MVTX2801AG supports up to 64K MAC addresses to aggregate traffic from multiple wiring closet stacks. The
centralized shared-memory architecture allows a very high performance packet-forwarding rate of 11.904M packet
per second at full wire speed. The chip is optimized to provide a low-cost, high performance workgroup, and wiring
closet, layer 2 switching solution with 4 Gigabit Ethernet ports.
One Frame Buffer Memory domain utilize cost effective, high-performance ZBT-SRAM with aggregated bandwidth
of 8.5Gbps to support full wire speed on all external ports simultaneously.
With Strict priority, Delay Bounded, and WRR transmission scheduling, plus WRED memory congestion scheme,
the chip provides powerful QoS functions for convergent network multimedia and mission-critical applications. The
chip provides 8 transmission priorities and 2 level drop precedence. Traffic is assigned its transmission priority and
dropping precedence based on the frame VLAN Tag priority.
The MVTX2801AG supports port trunking/load sharing on the 1000 Mbps ports with fail-over capability. The port
trunking/load sharing can be used to group ports between interlinked switches to increase the effective network
bandwidth.
In full-duplex mode, IEEE 802.3x flow control is provided. The Physical Coding Sublayer (PCS) is integrated on-chip
to provide a direct 10-bit GMII interface, or the PCS can be bypassed to provide an interface to existing fiber-based
Gigabit Ethernet transceivers.
The MVTX2801AG is fabricated using 0.25(mm technology. Inputs, however, are 3.3V tolerant and the outputs are
capable of directly interfacing to LVTTL levels. The MVTX2801AG is packaged in a 596-pin Ball Grid Array package.
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Data Sheet
MVTX2801AG
Table of Contents
Features ................................................................................................................................... i
Traffic Classification ............................................................................................................... i
Description .............................................................................................................................. ii
List of Figures ........................................................................................................................ xi
List of Tables ....................................................................................................................... xiii
1.0 Block Functionality ......................................................................................................... 15
1.1 Frame Data Buffer (FDB) Interfaces..........................................................................................................15
1.2 Switch Database (SDB) Interface..............................................................................................................15
1.3 GMII/PCS MAC Module (GMAC) ..............................................................................................................15
1.4 Frame Engine............................................................................................................................................15
1.5 Search Engine...........................................................................................................................................15
1.6 LED Interface.............................................................................................................................................15
1.7 Internal Memory.........................................................................................................................................15
2.0 System Configuration..................................................................................................... 16
2.1 I2C Interface ..............................................................................................................................................16
2.1.1 Start Condition .................................................................................................................................16
2.1.2 Address............................................................................................................................................16
2.1.3 Data Direction ..................................................................................................................................16
2.1.4 Acknowledgment..............................................................................................................................16
2.1.5 Data .................................................................................................................................................16
2.1.6 Stop Condition .................................................................................................................................17
2.2 Synchronous Serial Interface ...................................................................................................................17
2.2.1 Write Command ..............................................................................................................................17
2.2.2 Read Command..............................................................................................................................18
3.0 Data Forwarding Protocol .............................................................................................. 18
3.1 Unicast Data Frame Forwarding................................................................................................................18
3.2 Multicast Data Frame Forwarding .............................................................................................................19
4.0 Memory Interface............................................................................................................. 19
4.1 Overview....................................................................................................................................................19
4.2 Detailed Memory Information ....................................................................................................................20
5.0 Search Engine ................................................................................................................. 20
5.1 Search Engine Overview...........................................................................................................................20
5.2 Basic Flow .................................................................................................................................................20
5.3 Search, Learning, and Aging.....................................................................................................................21
5.3.1 MAC Search.....................................................................................................................................21
5.3.2 Learning...........................................................................................................................................21
5.3.3 Aging................................................................................................................................................21
5.3.4 Data Structure..................................................................................................................................21
6.0 Frame Engine................................................................................................................... 22
6.1 Data Forwarding Summary........................................................................................................................22
6.2 Frame Engine Details................................................................................................................................22
6.2.1 FCB Manager..................................................................................................................................22
6.2.2 Rx Interface.....................................................................................................................................22
6.2.3 RxDMA............................................................................................................................................22
6.2.4 TxQ Manager...................................................................................................................................22
6.3 Port Control ...............................................................................................................................................23
6.4 TxDMA.......................................................................................................................................................23
7.0 Quality of Service and Flow Control.............................................................................. 24
7.1 Model.........................................................................................................................................................24
7.2 Four QoS Configurations...........................................................................................................................25
7.3 Delay Bound..............................................................................................................................................25
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7.4 Strict Priority and Best Effort..................................................................................................................... 26
7.5 Weighted Fair Queuing ............................................................................................................................. 26
7.6 Shaper....................................................................................................................................................... 26
7.7 WRED Drop Threshold Management Support.......................................................................................... 27
7.8 Buffer Management................................................................................................................................... 27
7.8.1 Dropping When Buffers Are Scarce ................................................................................................ 28
7.9 Flow Control Basics .................................................................................................................................. 28
7.9.1 Unicast Flow Control ....................................................................................................................... 29
7.9.2 Multicast Flow Control ..................................................................................................................... 29
7.10 Mapping to IETF Diffserv Classes........................................................................................................... 30
8.0 Port Trunking ................................................................................................................... 31
8.1 Features and Restrictions ......................................................................................................................... 31
8.2 Unicast Packet Forwarding ...................................................................................................................... 31
8.3 Multicast Packet Forwarding.................................................................................................................... 31
8.4 Preventing Multicast Packets from Looping Back to the Source Trunk .................................................... 32
9.0 LED Interface.................................................................................................................... 32
9.1 Introduction ............................................................................................................................................... 32
9.2 Serial Mode............................................................................................................................................... 32
9.3 Parallel Mode ............................................................................................................................................ 33
9.4 LED Control Registers .............................................................................................................................. 33
10.0 Register Definition........................................................................................................ 35
10.1 Register Description................................................................................................................................ 35
10.2 Group 0 Address - MAC Ports Group ..................................................................................................... 40
10.2.1 ECR1Pn: Port N Control Register ................................................................................................. 40
10.2.2 ECR2Pn: Port N Control Register ................................................................................................. 41
10.2.3 ECRMISC1 - CPU Port Control Register MISC1........................................................................... 42
10.2.4 ECRMISC2 - CPU Port Control Register MISC2........................................................................... 43
10.2.5 GGControl 0- Extra GIGA Port Control.......................................................................................... 44
10.2.6 GGControl 1- Extra GIGA Port Control.......................................................................................... 44
10.2.7 GGControl 2- Extra GIGA Port Control.......................................................................................... 45
10.2.8 GGControl 3- Extra GIGA Port Control.......................................................................................... 45
10.3 Group 1 Address - VLAN Group ............................................................................................................. 45
10.3.1 AVTCL - VLAN Type Code Register Low...................................................................................... 45
10.3.2 AVTCH - VLAN Type Code Register High .................................................................................... 46
10.3.3 PVMAP00_0 - Port 00 Configuration Register 0 .......................................................................... 46
10.3.4 PVMAP00_1 - Port 00 Configuration Register 1 .......................................................................... 46
10.3.5 PVMAP00_2 - Port 00 Configuration Register 2 .......................................................................... 46
10.3.6 PVMAP00_3 - Port 00 Configuration Register 3 .......................................................................... 47
10.3.7 PVMODE...................................................................................................................................... 48
10.4 Group 2 Address - Port Trunking Group ................................................................................................. 48
10.4.1 TRUNK0 - Trunk group 0 Member (Managed Mode Only)............................................................ 48
10.4.2 TRUNK1 - Trunk group 1 Member (Managed Mode Only)............................................................ 48
10.4.3 TRUNK2- Trunk group 2 Member (Managed Mode Only)............................................................. 49
10.4.4 TRUNK3- Trunk group 3 Member (Managed Mode Only)............................................................. 49
10.4.5 TRUNK_HASH_MODE - Trunk hash mode .................................................................................. 49
10.4.6 TRUNK0_MODE - Trunk group 0 and 1 mode.............................................................................. 49
10.4.7 TRUNK0_HASH0 - Trunk group 0 hash result 0,1,2 destination port number .............................. 49
10.4.8 TRUNK0_HASH1 - Trunk group 0 hash result 2,3,4,5 destination port number ........................... 49
10.4.9 TRUNK0_HASH2 - Trunk group 0 hash result 5,6,7 destination port number .............................. 50
10.4.10 TRUNK0_HASH3 - Trunk group 0 hash result 8,9,10 destination port number .......................... 50
10.4.11 TRUNK0_HASH4 - Trunk group 0 hash result 10,11,12,13 destination port number ................. 50
10.4.12 TRUNK0_HASH5 - Trunk group 0 hash result 13,14,15 destination port number ...................... 50
10.4.13 TRUNK1_MODE - Trunk group 1 mode (Unmanaged Mode)..................................................... 50
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10.4.14 TRUNK1_HASH0 - Trunk group 1 hash result 0, 1, 2 destination port number...........................50
10.4.15 TRUNK1_HASH1 - Trunk group 1 hash result 2, 3, 4, 5 destination port number.......................50
10.4.16 TRUNK1_HASH2 - Trunk group 1 hash result 5, 6, 7 destination port number...........................50
10.4.17 TRUNK1_HASH3 - Trunk group 1 hash result 8, 9, 10 destination port number.........................50
10.4.18 TRUNK1_HASH4- Trunk group 1 hash result 11, 12, 13 destination port number......................51
10.4.19 TRUNK1_HASH5 - Trunk group 1 hash result 13, 14, 15 destination port number.....................51
10.4.20 TRUNK2_HASH0 - Trunk group 2 hash result 0, 1, 2 destination port number...........................51
10.4.21 TRUNK2_HASH1 - Trunk group 2 hash result 2, 3, 4, 5 destination port number.......................51
10.4.22 TRUNK2_HASH2 - Trunk group 2 hash result 5, 6, 7 destination port number...........................51
10.4.23 TRUNK2_HASH3 - Trunk group 2 hash result 8, 9, 10 destination port number.........................51
10.4.24 TRUNK2_HASH4 - Trunk group 2 hash result 10, 11, 12, 13 destination port number...............51
10.4.25 TRUNK2_HASH5 - Trunk group 2 hash result 13, 14, 15 destination port number.....................51
10.4.26 TRUNK3_HASH0 - Trunk group 3 hash result 0, 1, 2 destination port number...........................51
10.4.27 TRUNK3_HASH1 - Trunk group 3 hash result 2, 3, 4, 5 destination port number.......................51
10.4.28 TRUNK3_HASH2 - Trunk group 3 hash result 5, 6, 7 destination port number...........................52
10.4.29 TRUNK3_HASH3 - Trunk group 3 hash result 8, 9, 10 destination port number.........................52
10.4.30 TRUNK3_HASH4 - Trunk group 3 hash result 10, 11, 12, 13 destination port number...............52
10.4.31 TRUNK3_HASH5 - Trunk group 3 hash result 13, 14, 15 destination port number.....................52
10.4.32 Multicast Hash Registers .............................................................................................................52
10.4.33 Multicast_HASH00 - Multicast hash result0 mask byte [7:0] .......................................................52
10.4.34 Multicast_HASH01 - Multicast hash result1 mask byte [7:0] .......................................................52
10.4.35 Multicast_HASH02 - Multicast hash result2 mask byte [7:0] .......................................................52
10.4.36 Multicast_HASH03 - Multicast hash result3 mask byte [7:0] .......................................................52
10.4.37 Multicast_HASH04 - Multicast hash result4 mask byte [7:0] .......................................................53
10.4.38 Multicast_HASH05 - Multicast hash result5 mask byte [7:0] .......................................................53
10.4.39 Multicast_HASH06 - Multicast hash result6 mask byte [7:0] .......................................................53
10.4.40 Multicast_HASH07 - Multicast hash result7 mask byte [7:0] .......................................................53
10.4.41 Multicast_HASH08 - Multicast hash result8 mask byte [7:0] .......................................................53
10.4.42 Multicast_HASH09 - Multicast hash result9 mask byte [7:0] .......................................................53
10.4.43 Multicast_HASH10 - Multicast hash result10 mask byte [7:0] .....................................................53
10.4.44 Multicast_HASH11 - Multicast hash result11 mask byte [7:0] .....................................................54
10.4.45 Multicast_HASH12 - Multicast hash result12 mask byte [7:0] .....................................................54
10.4.46 Multicast_HASH13 - Multicast hash result13 mask byte [7:0] .....................................................54
10.4.47 Multicast_HASH14 - Multicast hash result14 mask byte [7:0] .....................................................54
10.4.48 Multicast_HASH15 - Multicast hash result15 mask byte [7:0] .....................................................54
10.4.49 Multicast_HASHML - Multicast hash bit[8] for result7-0...............................................................54
10.4.50 Multicast_HASHMH - Multicast hash BIT[8] for result 15-8 .........................................................54
10.5 Group 3 Address - CPU Port Configuration Group..................................................................................55
10.5.1 MAC0 - CPU Mac address byte 0..................................................................................................55
10.5.2 MAC1 - CPU Mac address byte 1..................................................................................................55
10.5.3 MAC2 - CPU Mac address byte 2..................................................................................................55
10.5.4 MAC3 - CPU Mac address byte 3..................................................................................................55
10.5.5 MAC4 - CPU Mac address byte 4..................................................................................................55
10.5.6 MAC5 - CPU Mac address byte 5..................................................................................................55
10.5.7 INT_MASK0 - Interrupt Mask 0......................................................................................................55
10.5.8 INT_MASK1 - Interrupt Mask 1......................................................................................................55
10.5.9 INT_STATUS0 - Masked Interrupt Status Register0 .....................................................................55
10.5.10 INT_STATUS1 - Masked Interrupt Status Register1 ...................................................................56
10.5.11 INTP_MASK0 - Interrupt Mask for MAC Port 0,1.........................................................................56
10.5.12 INTP_MASK1 - Interrupt Mask for MAC Port 2,3.........................................................................56
10.5.13 INTP_MASK4 - Interrupt Mask for MAC Port 4,5.........................................................................56
10.5.14 INTP_MASK5 - Interrupt Mask for MAC Port 6,7.........................................................................56
10.5.15 RQS - Receive Queue Select ......................................................................................................56
10.5.16 RQSS - Receive Queue Status....................................................................................................56
10.5.17 TX_AGE - Tx Queue Aging timer.................................................................................................56
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10.6 Group 4 Address - Search Engine Group ............................................................................................... 57
10.6.1 AGETIME_LOW - MAC address aging time Low .......................................................................... 57
10.6.2 AGETIME_HIGH -MAC address aging time High.......................................................................... 57
10.6.3 V_AGETIME - VLAN to Port aging time ........................................................................................ 57
10.6.4 SE_OPMODE - Search Engine Operation Mode .......................................................................... 57
10.6.5 SCAN - SCAN Control Register .................................................................................................... 58
10.7 Group 5 Address - Buffer Control/QOS Group........................................................................................ 58
10.7.1 FCBAT - FCB Aging Timer............................................................................................................ 58
10.7.2 QOSC - QOS Control .................................................................................................................... 58
10.7.3 FCR - Flooding Control Register ................................................................................................... 59
10.7.4 AVPML - VLAN Priority Map.......................................................................................................... 59
10.7.5 AVPMM - VLAN Priority Map......................................................................................................... 60
10.7.6 AVPMH - VLAN Priority Map......................................................................................................... 60
10.7.7 TOSPML - TOS Priority Map......................................................................................................... 60
10.7.8 TOSPMM - TOS Priority Map ........................................................................................................ 61
10.7.9 TOSPMH - TOS Priority Map ........................................................................................................ 61
10.7.10 AVDM - VLAN Discard Map ........................................................................................................ 61
10.7.11 TOSDML - TOS Discard Map...................................................................................................... 62
10.7.12 BMRC - Broadcast/Multicast Rate Control .................................................................................. 62
10.7.13 UCC - Unicast Congestion Control.............................................................................................. 63
10.7.14 MCC - Multicast Congestion Control ........................................................................................... 63
10.7.15 PRG - Port Reservation for Giga ports........................................................................................ 64
10.7.16 SFCB - Share FCB Size.............................................................................................................. 64
10.7.17 C2RS - Class 2 Reserved Size ................................................................................................... 65
10.7.18 C3RS - Class 3 Reserved Size ................................................................................................... 65
10.7.19 C4RS - Class 4 Reserved Size ................................................................................................... 65
10.7.20 C5RS - Class 5 Reserved Size ................................................................................................... 65
10.7.21 C6RS - Class 6 Reserved Size ................................................................................................... 66
10.7.22 C7RS - Class 7 Reserved Size ................................................................................................... 66
10.7.23 QOSC00 - BYTE_C2_G0 ............................................................................................................ 66
10.7.24 QOSC01 - BYTE_C3_G0 ............................................................................................................ 66
10.7.25 QOSC02 - BYTE_C4_G0 ............................................................................................................ 67
10.7.26 QOSC03 - BYTE_C5_G0 ............................................................................................................ 67
10.7.27 QOSC04 - BYTE_C6_G0 ............................................................................................................ 67
10.7.28 QOSC05 - BYTE_C7_G0 ............................................................................................................ 67
10.7.29 QOSC06 - BYTE_C2_G1 ............................................................................................................ 67
10.7.30 QOSC07 - BYTE_C3_G1 ........................................................................................................... 68
10.7.31 QOSC08 - BYTE_C4_G1 ........................................................................................................... 68
10.7.32 QOSC09 - BYTE_C5_G1 ........................................................................................................... 68
10.7.33 QOSC0A - BYTE_C6_G1........................................................................................................... 68
10.7.34 QOSC0B - BYTE_C7_G1........................................................................................................... 68
10.7.35 QOSC0C - BYTE_C2_G2 .......................................................................................................... 69
10.7.36 QOSC0D - BYTE_C3_G2 .......................................................................................................... 69
10.7.37 QOSC0E - BYTE_C4_G2........................................................................................................... 69
10.7.38 QOSC0F - BYTE_C5_G2........................................................................................................... 69
10.7.39 QOSC10 - BYTE_C6_G2 ............................................................................................................ 69
10.7.40 QOSC11 - BYTE_C7_G2 ............................................................................................................ 70
10.7.41 QOSC12 - BYTE_C2_G3 ........................................................................................................... 70
10.7.42 QOSC13 - BYTE_C3_G3 ............................................................................................................ 70
10.7.43 QOSC14 - BYTE_C4_G3 ............................................................................................................ 70
10.7.44 QOSC15 - BYTE_C5_G3 ............................................................................................................ 70
10.7.45 QOSC16 - BYTE_C6_G3 ........................................................................................................... 70
10.7.46 QOSC17 - BYTE_C7_G3 ............................................................................................................ 71
10.7.47 QOSC18 - BYTE_C2_G4 ........................................................................................................... 71
10.7.48 QOSC019 - BYTE_C3_G4 .......................................................................................................... 71
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10.7.49 QOSC1A - BYTE_C4_G4............................................................................................................71
10.7.50 QOSC1B - BYTE_C5_G4............................................................................................................71
10.7.51 QOSC1C - BYTE_C6_G4............................................................................................................71
10.7.52 QOSC1D- BYTE_C7_G4.............................................................................................................72
10.7.53 QOSC1E- BYTE_C2_G5.............................................................................................................72
10.7.54 QOSC1F - BYTE_C3_G5 ............................................................................................................72
10.7.55 QOSC20 - BYTE_C4_G5 ...........................................................................................................72
10.7.56 QOSC21 - BYTE_C5_G5 ............................................................................................................72
10.7.57 QOSC22 - BYTE_C6_G5 ............................................................................................................72
10.7.58 QOSC23 - BYTE_C7_G5 ............................................................................................................72
10.7.59 QOSC24 - BYTE_C2_G6 ............................................................................................................73
10.7.60 QOSC25 - BYTE_C3_G6 ............................................................................................................73
10.7.61 QOSC26 - BYTE_C4_G6 ............................................................................................................73
10.7.62 QOSC27 - BYTE_C5_G6 ............................................................................................................73
10.7.63 QOSC28 - BYTE_C6_G6 ............................................................................................................73
10.7.64 QOSC29 - BYTE_C7_G6 ............................................................................................................73
10.7.65 QOSC2A - BYTE_C2_G7............................................................................................................73
10.7.66 QOSC2B - BYTE_C3_G7............................................................................................................73
10.7.67 QOSC2C - BYTE_C4_G7...........................................................................................................74
10.7.68 QOSC2D - BYTE_C5_G7............................................................................................................74
10.7.69 QOSC2E - BYTE_C6_G7............................................................................................................74
10.7.70 QOSC2F - BYTE_C7_G7 ............................................................................................................74
10.7.71 QOSC30 - BYTE_C01 .................................................................................................................74
10.7.72 QOSC31 - BYTE_C02 .................................................................................................................74
10.7.73 QOSC32 - BYTE_C03 .................................................................................................................75
10.7.74 QOSC33 - CREDIT_C0_G0 ........................................................................................................75
10.7.75 QOSC34 - CREDIT_C1_G0 .......................................................................................................75
10.7.76 QOSC35 - CREDIT_C2_G0 ........................................................................................................76
10.7.77 QOSC36 - CREDIT_C3_G0 .......................................................................................................76
10.7.78 QOSC37 - CREDIT_C4_G0 ........................................................................................................76
10.7.79 QOSC38 - CREDIT_C5_G0 ........................................................................................................76
10.7.80 QOSC39- CREDIT_C6_G0 .........................................................................................................76
10.7.81 QOSC3A- CREDIT_C7_G0.........................................................................................................77
10.7.82 QOSC3B - CREDIT_C0_G1.......................................................................................................77
10.7.83 QOSC3C - CREDIT_C1_G1.......................................................................................................77
10.7.84 QOSC3D - CREDIT_C2_G1........................................................................................................78
10.7.85 QOSC3E - CREDIT_C3_G1........................................................................................................78
10.7.86 QOSC3F - CREDIT_C4_G1 ........................................................................................................78
10.7.87 QOSC40 - CREDIT_C5_G1 ........................................................................................................78
10.7.88 QOSC41- CREDIT_C6_G1 .........................................................................................................78
10.7.89 QOSC42- CREDIT_C7_G1 .........................................................................................................79
10.7.90 QOSC43 - CREDIT_C0_G2 .......................................................................................................79
10.7.91 QOSC44 - CREDIT_C1_G2 .......................................................................................................79
10.7.92 QOSC45 - CREDIT_C2_G2 ........................................................................................................80
10.7.93 QOSC46 - CREDIT_C3_G2 .......................................................................................................80
10.7.94 QOSC47 - CREDIT_C4_G2 ........................................................................................................80
10.7.95 QOSC48 - CREDIT_C5_G2 .......................................................................................................80
10.7.96 QOSC49- CREDIT_C6_G2 .........................................................................................................80
10.7.97 QOSC4A- CREDIT_C7_G2.........................................................................................................81
10.7.98 QOSC4B - CREDIT_C0_G3.......................................................................................................81
10.7.99 QOSC4 - CREDIT_C1_G3 ..........................................................................................................81
10.7.100 QOSC4D - CREDIT_C2_G3.....................................................................................................82
10.7.101 QOSC4E - CREDIT_C3_G3 ......................................................................................................82
10.7.102 QOSC4F - CREDIT_C4_G3 ......................................................................................................82
10.7.103 QOSC50 - CREDIT_C5_G3 ......................................................................................................82
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10.7.104 QOSC51- CREDIT_C6_G3 ....................................................................................................... 82
10.7.105 QOSC52- CREDIT_C7_G3 ....................................................................................................... 83
10.7.106 QOSC53 - CREDIT_C0_G4 ..................................................................................................... 83
10.7.107 QOSC54 - CREDIT_C1_G4 ...................................................................................................... 83
10.7.108 QOSC55 - CREDIT_C2_G4 ...................................................................................................... 83
10.7.109 QOSC56 - CREDIT_C3_G4 ...................................................................................................... 83
10.7.110 QOSC57 - CREDIT_C4_G4 ...................................................................................................... 83
10.7.111 QOSC58 - CREDIT_C5_G4 ...................................................................................................... 83
10.7.112 QOSC59- CREDIT_C6_G4 ....................................................................................................... 83
10.7.113 QOSC5A- CREDIT_C7_G4....................................................................................................... 84
10.7.114 QOSC5B - CREDIT_C0_G5..................................................................................................... 84
10.7.115 QOSC5C - CREDIT_C1_G5 ..................................................................................................... 84
10.7.116 QOSC5D - CREDIT_C2_G5 ..................................................................................................... 84
10.7.117 QOSC5E - CREDIT_C3_G5...................................................................................................... 84
10.7.118 QOSC5F - CREDIT_C4_G5..................................................................................................... 84
10.7.119 QOSC60 - CREDIT_C5_G5 ...................................................................................................... 84
10.7.120 QOSC61- CREDIT_C6_G5 ....................................................................................................... 84
10.7.121 QOSC62- CREDIT_C7_G5 ...................................................................................................... 85
10.7.122 QOSC63 - CREDIT_C0_G6 ..................................................................................................... 85
10.7.123 QOSC64 - CREDIT_C1_G6 ...................................................................................................... 85
10.7.124 QOSC65 - CREDIT_C2_G6 ...................................................................................................... 85
10.7.125 QOSC66 - CREDIT_C3_G6 ...................................................................................................... 85
10.7.126 QOSC67 - CREDIT_C4_G6 ...................................................................................................... 85
10.7.127 QOSC68 - CREDIT_C5_G6 ...................................................................................................... 85
10.7.128 QOSC69- CREDIT_C6_G6 ....................................................................................................... 85
10.7.129 QOSC6A- CREDIT_C7_G6....................................................................................................... 86
10.7.130 QOSC6B - CREDIT_C0_G7..................................................................................................... 86
10.7.131 QOSC6C - CREDIT_C1_G7 ..................................................................................................... 86
10.7.132 QOSC6D - CREDIT_C2_G7 ..................................................................................................... 86
10.7.133 QOSC6E - CREDIT_C3_G7...................................................................................................... 86
10.7.134 QOSC6F - CREDIT_C4_G7...................................................................................................... 86
10.7.135 QOSC70 - CREDIT_C5_G7 ...................................................................................................... 86
10.7.136 QOSC71- CREDIT_C6_G7 ....................................................................................................... 86
10.7.137 QOSC72- CREDIT_C7_G7 ....................................................................................................... 87
10.7.138 QOSC73 - TOKEN_RATE_G0 ................................................................................................. 87
10.7.139 QOSC74 - TOKEN_LIMIT_G0 .................................................................................................. 87
10.7.140 QOSC75 - TOKEN_RATE_G1 ................................................................................................. 87
10.7.141 QOSC76 - TOKEN_LIMIT_G1 .................................................................................................. 87
10.7.142 QOSC77 - TOKEN_RATE_G2.................................................................................................. 88
10.7.143 QOSC78 - TOKEN_LIMIT_G2 .................................................................................................. 88
10.7.144 QOSC79 - TOKEN_RATE_G3 ................................................................................................. 88
10.7.145 QOSC7A - TOKEN_LIMIT_G3.................................................................................................. 88
10.7.146 QOSC7B - TOKEN_RATE_G4................................................................................................. 88
10.7.147 QOSC7C - TOKEN_LIMIT_G4.................................................................................................. 89
10.7.148 QOSC7D - TOKEN_RATE_G5 ................................................................................................ 89
10.7.149 QOSC7E - TOKEN_LIMIT_G5.................................................................................................. 89
10.7.150 QOSC7F - TOKEN_RATE_G6................................................................................................. 89
10.7.151 QOSC80 - TOKEN_LIMIT_G6 .................................................................................................. 89
10.7.152 QOSC81 - TOKEN_RATE_G7 ................................................................................................. 89
10.7.153 QOSC82 - TOKEN_LIMIT_G7 .................................................................................................. 90
10.7.154 RDRC0 - WRED Rate Control 0................................................................................................ 90
10.7.155 RDRC1 - WRED Rate Control 1............................................................................................... 90
10.8 Group 6 Address - MISC Group.............................................................................................................. 91
10.8.1 MII_OP0 - MII Register Option 0 .................................................................................................. 91
10.8.2 MII_OP1 - MII Register Option 1 .................................................................................................. 91
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Table of Contents
10.8.3 FEN - Feature Register.................................................................................................................91
10.8.4 MIIC0 - MII Command Register 0 ..................................................................................................92
10.8.5 MIIC1 - MII Command Register 1 .................................................................................................92
10.8.6 MIIC2 - MII Command Register 2 .................................................................................................92
10.8.7 MIIC3 - MII Command Register 3 .................................................................................................93
10.8.8 MIID0 - MII Data Register 0 ..........................................................................................................93
10.8.9 MIID1 - MII Data Register 0 ...........................................................................................................93
10.8.10 LED Mode - LED Control ............................................................................................................94
10.8.11 DEVICE Mode.............................................................................................................................95
10.8.12 CHECKSUM - EEPROM Checksum...........................................................................................96
10.8.13 LED User ....................................................................................................................................96
10.8.14 LEDUSER0.................................................................................................................................96
10.8.15 LEDUSER1.................................................................................................................................96
10.8.16 LEDUSER2/LEDSIG2.................................................................................................................97
10.8.17 LEDUSER3/LEDSIG3.................................................................................................................97
10.8.18 LEDUSER4/LEDSIG4..................................................................................................................98
10.8.19 LEDUSER5/LEDSIG5.................................................................................................................99
10.8.20 LEDUSER6/LEDSIG6.................................................................................................................99
10.8.21 LEDUSER7/LEDSIG1_0...........................................................................................................100
10.8.22 MIINP0 - MII Next Page Data Register 0..................................................................................101
10.8.23 MIINP1 - MII Next Page Data Register 1...................................................................................101
10.9 Group F Address - CPU Access Group.................................................................................................101
10.9.1 GCR-Global Control Register ......................................................................................................101
10.9.2 DCR-Device Status and Signature Register................................................................................101
10.9.3 DCR01-Giga port status...............................................................................................................102
10.9.4 DCR23-Giga port status...............................................................................................................103
10.9.5 DCR45-Giga port status (useless in MVTX2801) ........................................................................103
10.9.6 DCR67-Giga port status (useless in MVTX2801) ........................................................................103
10.9.7 DPST - Device Port Status Register............................................................................................104
10.9.8 DTST - Data Read Back Register................................................................................................104
11.0 BGA and Ball Signal Description.............................................................................. 105
11.1 BGA Views ...........................................................................................................................................105
11.2 Power and Ground Distribution ............................................................................................................106
11.3 Ball- Signal Descriptions.......................................................................................................................107
11.4 Ball Signal Name..................................................................................................................................115
11.5 AC/DC Timing.......................................................................................................................................121
11.5.1 Absolute Maximum Ratings ........................................................................................................121
11.5.2 DC Electrical Characteristics ......................................................................................................121
11.5.3 Recommended Operation Conditions.........................................................................................121
11.6 Local Frame Buffer ZBT SRAM Memory Interface...............................................................................122
11.6.1 Local ZBT SRAM Memory Interface A........................................................................................122
11.7 Local Switch Database SBRAM Memory Interface ..............................................................................123
11.7.1 Local SBRAM Memory Interface.................................................................................................123
11.8 AC Characteristics................................................................................................................................124
11.8.1 Media Independent Interface ......................................................................................................124
11.8.2 Gigabit Media Independent Interface...........................................................................................125
11.8.3 PCS Interface..............................................................................................................................126
11.8.4 LED Interface..............................................................................................................................127
11.8.5 MDIO Input Setup and Hold Timing............................................................................................128
11.8.6 I2C Input Setup Timing.................................................................................................................128
11.8.7 Serial Interface Setup Timing......................................................................................................129
12.0 Mechanical Data ......................................................................................................... 130
12.1 Packaging Information..........................................................................................................................130
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Table of Contents
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List of Figures
Figure 1 - Chip Block Diagram ....................................................................................................i
Figure 2 - Data Transfer Format for I2C Interface .................................................................... 16
Figure 3 - Write Command...................................................................................................... 17
Figure 4 - Read Command...................................................................................................... 18
Figure 5 - SRAM Interface Block Diagram (DMAs for Gigabit Ports)...................................... 19
Figure 6 - Buffer Partition Scheme Used in the MVTX2801AG............................................... 28
Figure 7 - Timing diagram for serial mode in LED interface.................................................... 32
Figure 8 - Local Memory Interface - Input setup and hold timing.......................................... 122
Figure 9 - Local Memory Interface - Output valid delay timing.............................................. 122
Figure 10 - Local Memory Interface - Input setup and hold timing........................................ 123
Figure 11 - Local Memory Interface - Output valid delay timing............................................ 123
Figure 12 - AC Characteristics - Media Independent Interface ............................................. 124
Figure 13 - AC Characteristics - Media Independent Interface ............................................. 124
Figure 14 - AC Characteristics- GMII .................................................................................... 125
Figure 15 - AC Characteristics - Gigabit Media Independent Interface................................. 125
Figure 16 - AC Characteristics - PCS Interface..................................................................... 126
Figure 17 - AC Characteristics - PCS Interface..................................................................... 126
Figure 18 - AC Characteristics - LED Interface..................................................................... 127
Figure 19 - MDIO Input Setup and Hold Timing.................................................................... 128
Figure 20 - MDIO Output Delay Timing................................................................................. 128
Figure 21 - I2C Input Setup Timing ........................................................................................ 128
Figure 22 - I2C Output Delay Timing...................................................................................... 129
Figure 23 - Serial Interface Setup Timing.............................................................................. 129
Figure 24 - Serial Interface Output Delay Timing.................................................................. 129
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List of Tables
Table 1 - Two-dimensional World Traffic.................................................................................24
Table 2 - Four QoS configurations per port.............................................................................25
Table 3 - WRED Dropping Scheme ........................................................................................27
Table 4 - Mapping between MVTX2801AG and IETF Diffserv Classes for Gigabit Ports.......30
Table 5 - MVTX2801AG Features Enabling IETF Diffserv Standards ....................................30
Table 6 - MVTX2801AG Register Description.........................................................................35
Table 7 - Ball- Signal Descriptions ........................................................................................107
Table 8 - Ball Signal Name....................................................................................................115
Table 9 - Recommended Operation Conditions....................................................................121
Table 10 - AC Characteristics - Local frame buffer ZBT-SRAM Memory Interface A ...........122
Table 11 - AC Characteristics - Local Switch Database SBRAM Memory Interface.............123
Table 12 - AC Characteristics - Media Independent Interface ..............................................124
Table 13 - AC Characteristics - Gigabit Media Independent Interface..................................126
Table 14 - AC Characteristics - PCS Interface......................................................................127
Table 15 - AC Characteristics - LED Interface ......................................................................127
Table 16 - MDIO Timing........................................................................................................128
Table 17 - I2C Timing.............................................................................................................129
Table 18 - Serial Interface Timing .........................................................................................130
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1.0
1.1
Block Functionality
Frame Data Buffer (FDB) Interfaces
The FDB interface supports pipelined ZBT-SRAM memory at 133 MHz. To ensure a non-blocking switch, one
memory domain is required. Each domain has a 64-bit wide memory bus. At 133 MHz, the aggregate memory
bandwidth is 8.5 Gbps, which is enough to support 4 Gigabit ports at full wire speed switching. A patent pending
scheme is used to access the FDB memory. Each slot has one tick to read or write 8 bytes.
1.2
Switch Database (SDB) Interface
A pipelined synchronous burst SRAM (SBRAM) memory is used to store the switch database information including
MAC Table. Search Engine accesses the switch database via SDB interface. The SDB bus has 32-bit wide bus at
133MHz.
1.3
GMII/PCS MAC Module (GMAC)
The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface between
the Frame Engine (FE) and the external physical device (PHY). The MVTX2801AG has two interfaces, GMII or
PCS. The MAC of the MVTX2801AG meets the IEEE 802.3z specification and supports the MII interface. It is able
to operate 10M/100M/1G in Full Duplex mode with a back pressure/flow control mechanism. It has the options to
insert Source Address/CRC/VLAN ID to each frame. The GMII/PCS Module also supports hot plug detection.
1.4
Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent to
the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch
response from the search engine, the frame engine performs transmission scheduling based on the frame's priority.
The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.5
Search Engine
The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2) by
searching the database. It also performs MAC learning, priority assignment, and trunking functions.
1.6
LED Interface
The LED interface can be operated in a serial mode or a parallel mode. In the serial mode, the LED interface uses
3 pins for carrying 4 port status signals. In the parallel mode, the interface can drive LEDs by 8 status pins. The
LED port is shared with bootstrap pins. In order to avoid error when reading the bootstraps, a buffer must be used
to isolate the LED circuitry from the bootstrap pins during bootstrap cycle (the bootstrap pins are sampled at the
rising edge of the Reset).
1.7
Internal Memory
Several internal tables are required and are described as follows:
•
•
Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame
stored in the FDB, e.g. frame size, read/write pointer, transmission priority, etc.
MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the
external MAC Table.
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2.0
System Configuration
The MVTX2801AG can be configured by EEPROM (24C02 or compatible) via an I2C interface at boot time, or via
a synchronous serial interface during operation.
2.1
I2C Interface
The I2C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bi-directional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. The
figure below shows the data transfer format.
SLAVE
ADDRESS
DATA 1
(8 bits)
START
R/W ACK
ACK DATA 2 ACK DATA M ACK STOP
Figure 2 - Data Transfer Format for I2C Interface
2.1.1
Start Condition
Generated by the master, the MVTX2801AG. The bus is considered to be busy after the Start condition is generated.
The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period
of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I2C bus is free, both
lines are High.
2.1.2
Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.1.3
Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.1.4
Acknowledgment
Like all clock pulses, the master generates the acknowledgment-related clock pulse. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to
let the master generate the Stop condition.
2.1.5
Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB-first.
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2.1.6
Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition
occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
The I2C interface serves the function of configuring the MVTX2801AG at boot time. The master is the
MVTX2801AG, and the slave is the EEPROM memory.
2.2
Synchronous Serial Interface
The synchronous serial interface serves the function of configuring the MVTX2801AG not at boot time but via a PC.
The PC serves as master and the MVTX2801AG serves as slave. The protocol for the synchronous serial interface
is nearly identical to the I2C protocol. The main difference is that there is no acknowledgment bit after each byte of
data transferred.
The unmanaged MVTX2801AG uses a synchronous serial interface to program the internal registers. To reduce
the number of signals required, the register address, command and data are shifted in serially through the PS_DO
pin. PS_STROBE- pin is used as the shift clock. PS_DI- pin is used as data return path.
Each command consists of four parts.
•
•
•
•
START pulse
Register Address
Read or Write command
Data to be written or read back
Any command can be aborted in the middle by sending an ABORT pulse to the MVTX2801AG.
A START command is detected when PS_DO is sampled high at PS_STROBE - leading edge, and PS_DO is
sampled low when STROBE- falls.
An ABORT command is detected when PS_DO is sampled low at PS_STROBE - leading edge, and PS_DO is
sampled high when PS_STROBE - falls.
2.2.1
Write Command
PS-STROBE-
2 Extra clocks after last
transfer
A11
PS_DO
A2 ...
D0 D1 D2 D3 D4 D5 D6 D7
A9 A10
A0 A1
START
W
ADDRESS
COMMAND DATA
Figure 3 - Write Command
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Data Sheet
2.2.2
Read Command
PS_STROBE-
PS_DO
R
A0 A1 A2 ...
A9 A10 A11
START
ADDRESS
COMMAND
D0 D1
DATA
D7
D2 D3 D4 D5 D6
PS_DI
Figure 4 - Read Command
All registers in the MVTX2801AG can be modified through this synchronous serial interface.
3.0
3.1
Data Forwarding Protocol
Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available, because of advance buffer reservations.
The memory (ZBT-SRAM) interface is a 64-bit bus, connected to a ZBT-SRAM domain. The Receive DMA (RxDMA)
is responsible for multiplexing the data and the address. On a port's “turn,” the RxDMA will move 8 bytes (or up to
the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response queue
of the frame engine when done. Among other information, the search engine will have resolved the destination port
of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to
decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy
at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct
per-port-per-class TxQ. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames'
FCB's. There is one linked list for each transmission class for each port. There are 8 classes for each of the 4 Gigabit
ports - a total of 32 unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes for
a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for
another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the
head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling
algorithm.
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MVTX2801AG
As at the transmit end, each of the 4 ports has time slots devoted solely to reading data from memory at the address
calculated by port control. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the
address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated
TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates
among multiple buffer release requests.
The frame is transmitted from the TxFIFO to the line.
3.2
Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop
can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is
dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the
multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB
is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry
in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for
unicast frames). There are 4 multicast queues for each of the 4 Gigabit ports.
During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one
logical queue.
The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to
which the frame is destined.
4.0
4.1
Memory Interface
Overview
The figure below illustrates the first part of the ZBT-SRAM interface for the MVTX2801AG. As shown, a 64 bit bus
ZBT-SRAM bank A is used for Tx/RxDMA access. Because the clock frequency is 133 MHz, the total memory
bandwidth is 64-bits x 133 MHz = 8.5 Gbps, for frame data buffer (FDB) access.
ZBT-SRAM Bank A
TX DMA
0-1
TX DMA
2-3
RX DMA
0-1
RX DMA
2-3
Figure 5 - SRAM Interface Block Diagram (DMAs for Gigabit Ports)
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4.2
Detailed Memory Information
Because the memory bus is 64 bits wide, frames are broken into 8-byte granules, written to and read from each
memory access. In the worst case, a 1-byte-long EOF granule gets written to memory Bank. This means that a
7-byte segment of memory bus is idle. The scenario results in a maximum 7 bytes of waste per frame, which is
always acceptable because the interfame gap is 20 bytes.
5.0
5.1
Search Engine
Search Engine Overview
The MVTX2801AG search engine is optimized for high throughput searching, with enhanced features to support:
•
•
•
Up to 64K MAC addresses
4 groups of port trunking
Traffic classification into 8 transmission priorities, and 2 drop precedence levels
5.2
Basic Flow
Shortly after a frame enters the MVTX2801AG and is written to the Frame Data Buffer (FDB), the frame engine
generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of
the frame, which contain all the necessary information for the search engine to perform its task. When the search
engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that
queue for scheduling and forwarding.
In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch
request. Among the information extracted are the source and destination MAC addresses, the transmission and
discard priorities, whether the frame is unicast or multicast. Requests are sent to the external SRAM Switch
Database to locate the associated entries in the external MCT table.
When all the information has been collected from external SRAM, the search engine has to compare the MAC
address on the current entry with the MAC address for which it is searching. If it is not a match, the process is
repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal
to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address
unknown) or flooding (destination MAC address unknown).
If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number.
But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and
destination MAC addresses.
When all the information is compiled, the switch response is generated, as stated earlier.
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MVTX2801AG
5.3
Search, Learning, and Aging
5.3.1
MAC Search
The search block performs source MAC address and destination MAC address searching. As we indicated earlier,
if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or
the end of the list is reached.
In port based VLAN mode, a bitmap is used to determine whether the frame should be forwarded to the outgoing
port. The bitmap is not dynamic. Ports cannot enter and exit groups dynamically.
The MAC search block is also responsible for updating the source MAC address timestamp, used for aging.
5.3.2
Learning
The learning module learns new MAC addresses and performs port change operations on the MCT database. The
goal of learning is to update this database as the networking environment changes over time. Learning and port
change will be performed based on memory slot availability only.
5.3.3
Aging
Aging time is controlled by register 400h and 401h.
The aging module scans and ages MCT entries based on a programmable “age out” time interval. As we indicated
earlier, the search module updates the source MAC address and VLAN port association timestamps for each frame
it processes. When an entry is ready to be aged, the entry is removed from the table.
5.3.4
Data Structure
The MCT data structure is used for searching for MAC addresses. The structure is maintained by hardware in the
search engine. The database is essentially a hash table, with collisions resolved by chaining. The database is
partially external, and partially internal, as described earlier: the first MCT entry of each linked list is always located
in the external SRAM, and the subsequent MCTs are located internally.
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6.0
6.1
Frame Engine
Data Forwarding Summary
•
Enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is
moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
•
•
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast,
and its destination port or ports.
•
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon
receiving a Transmission Scheduling Request, the device will format an entry in the appropriate
Transmission Scheduling Queue (TxSch Q) or Queues. There are 8 TxSch Queues for each Gigabit port,
one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list
if unicast, or adding an entry to a physical queue if multicast.
•
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of
one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality
of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one
logical queue.
•
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of
the destination port.
6.2
Frame Engine Details
This section briefly describes the functions of each of the modules of the MVTX2801AG frame engine.
6.2.1 FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure.
The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be
determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging, and for linking
unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin
and the aging time is defined in register FCBAT.
6.2.2
Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch
request.
6.2.3
RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame
for use by the search engine when the switch request has been made.
6.2.4
TxQ Manager
First, the TxQ manager checks the per-class queue status and global Reserved resource situation, and using this
information, makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the
TxQ manager requests that the FCB manager link the unicast frame's FCB to the correct per-port-per-class TxQ. If
multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger
source port flow control for the incoming frame's source if that port is flow control enabled. Second, the TxQ manager
handles transmission scheduling; it schedules transmission among the queues representing different classes for a
port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port
control module.
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6.3
Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes
start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control
module requests that the buffer be released.
6.4
TxDMA
The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the
port control modules.
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7.0
7.1
Quality of Service and Flow Control
Model
Quality of service (QoS) is an all-encompassing term for which different people have different interpretations. In this
chapter, by quality of service assurances, we mean the allocation of chip resources so as to meet the latency and
bandwidth requirements associated with each traffic class. We do not presuppose anything about the offered traffic
pattern. If the traffic load is light, then ensuring quality of service is straightforward. But if the traffic load is heavy,
the MVTX2801AG must intelligently allocate resources so as to assure quality of service for high priority data.
We assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their
relative importance. The manager can then subdivide the applications into classes and set up a service contract with
each. The contract may consist of bandwidth or latency assurances per class. Sometimes it may even reflect an
estimate of the traffic mix offered to the switch, though this is not required.
The table below shows examples of QoS applications with eight transmission priorities, including best effort traffic
for which we provide no bandwidth or latency assurances.
Example
Assured
Bandwidth
(user defined)
Low Drop Subclass
(If class is oversubscribed,
these packets are the
last to be dropped.)
High Drop Subclass
(If class is oversubscribed,
these packets are the
first to be dropped.)
Class
Highest transmission
priorities, P7
Latency < 200 ms
300 Mbps
200 Mbps
125 Mbps
250 Mbps
80 Mbps
45 Mbps
Sample application:
control information
Highest transmission
priorities, P6
Latency < 200 ms
Sample applications:
phone calls;
circuit emulation
Sample application:
training video;
other multimedia
Middle transmission
priorities, P5
Latency < 400 ms
Sample application:
interactive activities
Sample application:
non-critical interactive activities
Middle transmission
priorities, P4
Latency < 800 ms
Sample application:
web business
Low transmission
priorities, P3
Latency < 1600 ms
Sample application:
file backups
Low transmission
priorities, P2
Sample application:
email
Sample application:
web research
Latency < 3200 ms
Best effort, P1-P0
TOTAL
-
Sample application: casual web browsing
1 Gbps
Table 1 - Two-dimensional World Traffic
It is possible that a class of traffic may attempt to monopolize system resources by sending data at a rate in excess
of the contractually assured bandwidth for that class. A well-behaved class offers traffic at a rate no greater than the
agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. A misbehaving
class is formed from an aggregation of misbehaving microflows. To achieve high link utilization, a misbehaving class
is allowed to use any idle bandwidth. However, the quality of service (QoS) received by well-behaved classes must
never suffer.
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As Table 1 illustrates, each traffic class may have its own distinct properties and applications. As shown, classes
may receive bandwidth assurances or latency bounds. In the example, P7, the highest transmission class, requires
that all frames be transmitted within 0.2 ms, and receives 30% of the 1 Gbps of bandwidth at that port.
Best-effort (P1-P0) traffic forms a lower tier of service that only receives bandwidth when none of the other classes
have any traffic to offer.
In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should not
lose packets. But poorly behaved users, users who send data at too high a rate, will encounter frame loss, and the
first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some
low-drop frames are dropped as well.
Table 1 shows that different types of applications may be placed in different boxes in the traffic table. For example,
web search may fit into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the category
of low-loss, low-latency traffic.
7.2
Four QoS Configurations
There are four basic pieces to QoS scheduling in the MVTX2801AG: strict priority (SP), delay bound, weighted fair
queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation, as shown
in Table 2.
P7
P6
P5
P4
P3
P2
P1
BE
BE
P0
Op1 (default) Delay Bound
Op2
Op3
Op4
SP
Delay Bound
WFQ
SP
WFQ
Table 2 - Four QoS configurations per port
The default configuration is six delay-bounded queues and two best-effort queues. The delay bounds per class are
0.16 ms for P7 and P6, 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. Best effort traffic is only
served when there is no delay-bounded traffic to be served. P1 has strict priority over P0.
We have a second configuration in which there are two strict priority queues, four delay bounded queues, and two
best effort queues. The delay bounds per class are 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms
for P2. If the user is to choose this configuration, it is important that P7-P6 (SP) traffic be either policed or implicitly
bounded (e.g. if the incoming SP traffic is very light and predictably patterned). Strict priority traffic, if not
admission-controlled at a prior stage to the MVTX2801AG, can have an adverse effect on all other classes'
performance. P7 and P6 are both SP classes, and P7 has strict priority over P6.
The third configuration contains two strict priority queues and six queues receiving a bandwidth partition via WFQ.
As in the second configuration, strict priority traffic needs to be carefully controlled.
In the fourth configuration, all queues are served using a WFQ service discipline
7.3
Delay Bound
In the absence of a sophisticated QoS server and signaling protocol, the MVTX2801AG may not be assured of the
mix of incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically
adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their
head-of-line (HOL) frames. As a result, we assure latency bounds for all admitted frames with high confidence, even
in the presence of system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards
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Data Sheet
frames at no detriment to well-behaved classes. Our algorithm also differentiates between high-drop and low-drop
traffic with a weighted random early drop (WRED) approach. Random early dropping prevents congestion by
randomly dropping a percentage of high-drop frames even before the chip's buffers are completely full, while still
largely sparing low-drop frames. This allows high-drop frames to be discarded early, as a sacrifice for future low-drop
frames. Finally, the delay bound algorithm also achieves bandwidth partitioning among classes.
7.4
Strict Priority and Best Effort
When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. Two
of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used for IETF
expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is important that
strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes.
When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other
classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for best
effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance.
However, in a typical network setting, much best effort traffic will indeed be transmitted, and with an adequate
degree of expediency.
Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best
effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the
MVTX2801AG, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping
to enforce quality of service (i.e. bandwidth or delay) does not apply to strict priority or best effort queues. We only
drop frames from best effort and strict priority queues when global buffer resources become scarce.
7.5
Weighted Fair Queuing
In some environments - for example, in an environment in which delay assurances are not required, but precise
bandwidth partitioning on small time scales is essential (WFQ may be preferable to a delay-bounded scheduling
discipline). The MVTX2801AG provides the user with a WFQ option with the understanding that delay assurances
cannot be provided if the incoming traffic pattern is uncontrolled. The user sets eight WFQ “weights” such that all
weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with error within 2%.
In WFQ mode, though we do not assure frame latency, the MVTX2801AG still retains a set of dropping rules that
helps to prevent congestion and trigger higher level protocol end-to-end flow control.
As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority
queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do
indeed drop frames from SP queues for global buffer management purposes. In addition, queues P1 and P0 are
treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a
WFQ scheduling perspective. What this means is that these particular queues are only affected by dropping when
the global buffer count becomes low.
7.6
Shaper
Although traffic shaping is not a primary function of the MVTX2801AG, the chip does implement a shaper for
expedited forwarding (EF). Our goal in shaping is to control the peak and average rate of traffic exiting the
MVTX2801AG. Shaping is limited to class P6 (the second highest priority). This means that class P6 will be the class
used for EF traffic. (By contrast, we assume class P7 will be used for control packets only.) If shaping is enabled for
P6, then P6 traffic must be scheduled using strict priority. With reference to Table 2, only the middle two QoS
configurations may be used.
Peak rate is set using a programmable whole number, no greater than 64 (register QOS-CREDIT_C6_Gn). For
example, if the setting is 32, then the peak rate for shaped traffic is 32/64 x 1000 Mbps = 500 Mbps. Average rate
is also a programmable whole number, no greater than 64, and no greater than the peak rate. For example, if the
setting is 16, then the average rate for shaped traffic is (16/64) x 1000 Mbps = 250 Mbps. As a consequence of the
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MVTX2801AG
above settings in our example, shaped traffic will exit the MVTX2801AG at a rate always less than 500 Mbps, and
averaging no greater than 250 Mbps.
Also, when shaping is enabled, it is possible for a P6 queue to explode in length if fed by a greedy source. The
reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if
the line is idle. Though we do have global resource management, we do nothing to prevent this situation locally.
We assume SP traffic is policed at a prior stage to the MVTX2801AG.
7.7
WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified
parameters. The following table summarizes the behavior of the WRED logic.
P7
P6
P5
P4
P3
P2
High Drop Low Drop
Level 1
N > 240
X%
Y%
0%
|P7| > A |P6| > B |P5| > C |P4| > D |P3| > E |P2| > F KB
KB KB KB KB KB
Level 2
N > 280
Z%
Level 3
N > 320
100%
100%
Table 3 - WRED Dropping Scheme
In the table, |Px| is the byte count in queue Px. The WRED logic has three drop levels, depending on the value of
N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals 16|P7|
+ 16|P6| + 8|P5| + 4|P4| + 2|P3| + |P2|. If WFQ scheduling is used, N equals |P7| + |P6| + |P5| + |P4| + |P3| + |P2|.
Each drop level has defined high-drop and low-drop percentages, which indicate the percentage of high-drop and
low-drop packets that will be dropped at that level. The X, Y, and Z percent parameters can be programmed using
the registers RDRC0 and RDRC1. Parameters A-F are the byte count thresholds for each priority queue, and are
also programmable. When using delay bound scheduling, the values selected for A-F also control the approximate
bandwidth partition among the traffic classes; see application note.
7.8
Buffer Management
Because the number of frame data buffer (FDB) slots is a scarce resource, and because we want to ensure that
one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we
introduce the concept of buffer management into the MVTX2801AG. Our buffer management scheme is designed
to divide the total buffer space into numerous reserved regions and one shared pool (see Figure 6).
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the MVTX2801AG, its destination port and class are as yet unknown, and so the decision to drop or not
needs to be temporarily postponed. This ensures that every frame can be received first before subjecting it to the
frame drop discipline after classifying.
Six reserved sections, one for each of the highest six priority classes, ensure a programmable number of FDB slots
per class. The lowest two classes do not receive any buffer reservation.
Another segment of the FDB reserves space for each of the 4 ports. These source port buffer reservations are
programmable. These 8 reserved regions make sure that no well-behaved source port can be blocked by another
misbehaving source port.
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In addition, there is a shared pool, which can store any type of frame. The registers related to the Buffer
Management logic are:
•
•
•
•
•
•
•
•
PRG- Port Reservation for Gigabit Ports
SFCB- Share FCB Size
C2RS- Class 2 Reserved Size
C3RS- Class 3 Reserved Size
C4RS- Class 4 Reserved Size
C5RS- Class 5 Reserved Size
C6RS- Class 6 Reserved Size
C7RS- Class 7 Reserved Size
Temporary
Reservation R
TMP
Per-Class Reservations
, R ... R
Shared Pool S
R
p7
p6
p2
Per-Source Reservations 8 . R
1G
Figure 6 - Buffer Partition Scheme Used in the MVTX2801AG
7.8.1
Dropping When Buffers Are Scarce
Summarizing the two examples of local dropping discussed earlier in this chapter:
•
•
If a queue is a delay-bounded queue, we have a multilevel WRED drop scheme, designed to control delay
and partition bandwidth in case of congestion.
If a queue is a WFQ-scheduled queue, we have a multilevel WRED drop scheme, designed to prevent
congestion.
In addition to these reasons for dropping, the MVTX2801AG also drops frames when global buffer space becomes
scarce. The function of buffer management is to ensure that such droppings cause as little blocking as possible.
7.9
Flow Control Basics
Because frame loss is unacceptable for some applications, the MVTX2801AG provides a flow control option. When
flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a
source port, sending a packet to this switch, to temporarily hold off.
While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When
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Data Sheet
MVTX2801AG
a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not,
are halted. A single packet destined for a congested output can block other packets destined for uncongested
outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high
confidence when flow control is enabled.
In the MVTX2801AG, each source port can independently have flow control enabled or disabled. For flow control
enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done so
that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports feed to
only one queue at the destination, the queue of lowest priority. What this means is that if flow control is enabled for
a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible
expense of minimum bandwidth or maximum delay assurances. In addition, these “downgraded” frames may only
use the shared pool or the per-source reserved pool in the FDB; frames from flow control enabled sources may not
use reserved FDB slots for the highest six classes (P2-P7).
The MVTX2801AG does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for
frames originating from flow control enabled ports. When this programmable option is active, it is possible that some
packets may be dropped, even though flow control is on. The reason is that intelligent packet dropping is a major
component of the MVTX2801AG's approach to ensuring bounded delay and minimum bandwidth for high priority
flows.
7.9.1
Unicast Flow Control
For unicast frames, flow control is triggered by source port resource availability. Recall that the MVTX2801AG's
buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed
number of a source port's reserved FDB slots have been used, then flow control Xoff is triggered. Xon is triggered
when a port is currently being flow controlled, and all of that port's reserved FDB slots have been released.
Note that the MVTX2801AG's per-source-port FDB reservations assure that a source port that sends a single frame
to a congested destination will not be flow controlled.
7.9.2
Multicast Flow Control
When port based Vlan is not used, a global buffer counter (64 packets) triggers flow control for multicast frames.
When the system exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when
the system returns below this threshold. MCC register programs the threshold. When port based Vlan is used, each
Vlan has a global buffer counter.
In addition, each source port has an 8-bit port map recording which port or ports of the multicast frame's fanout were
congested at the time Xoff was triggered. All ports are continuously monitored for congestion, and a port is identified
as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were originally
marked as congested in the port map have become uncongested, then Xon is triggered, and the 8-bit vector is reset
to zero.
The MVTX2801AG also provides the option of disabling VLAN multicast flow control.
Note: If port flow control is on, QoS performance will be affected. To determine the most efficient way to program,
please refer to the QoS Application Note.
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7.10
Mapping to IETF Diffserv Classes
The mapping between priority classes discussed in this chapter and elsewhere is shown below.
MVTX2801AG
P7
P6
P5
P4
P3
P2
P1
P0
IETF
NM
EF
AF0
AF1
AF2
AF3
BE0
BE1
Table 4 - Mapping between MVTX2801AG and IETF Diffserv Classes for Gigabit Ports
As the table illustrates, P7 is used solely for network management (NM) frames. P6 is used for expedited forwarding
service (EF). Classes P2 through P5 correspond to an assured forwarding (AF) group of size 4. Finally, P0 and P1
are two best effort (BE) classes.
Features of the MVTX2801AG that correspond to the requirements of their associated IETF classes are summarized
in the table below.
Network management (NM)
and Expedited forwarding (EF)
•
•
•
•
Global buffer reservation for NM and EF
Shaper for EF traffic
Option of strict priority scheduling
No dropping if admission controlled
Assured forwarding (AF)
•
•
Four AF classes
Programmable bandwidth partition, with option of
WFQ service
•
Option of delay-bounded service keeps delay
under fixed levels even if not
admission-controlled
•
•
Random early discard, with programmable levels
Global buffer reservation for each AF class
Best effort (BE)
•
•
Two BE classes
Service only when other queues are idle means
that QoS not adversely affected
•
•
Random early discard, with programmable levels
Traffic from flow control enabled ports
automatically classified as BE
Table 5 - MVTX2801AG Features Enabling IETF Diffserv Standards
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MVTX2801AG
8.0
8.1
Port Trunking
Features and Restrictions
A port group (i.e. trunk) can include up to 4 physical ports, but all of the ports in a group must be in the same
MVTX2801AG.
The MVTX2801AG provides several pre-assigned trunk group options, containing as many as 4 ports per group,
or alternatively, as many as 4 total groups.
Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address
and destination MAC address. The other options include source MAC address only, destination MAC address only.
Load distribution for multicast is performed similarly.
If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN
member map.
The MVTX2801AG also provides a safe fail-over mode for port trunking automatically. If one of the ports in the
trunking group goes down, the MVTX2801AG will automatically redistribute the traffic over to the remaining ports
in the trunk in unmanaged mode. In managed mode, the software can perform similar tasks.
8.2
Unicast Packet Forwarding
The search engine finds the destination MCT entry, and if the status field says that the destination address found
belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the source address
belongs to a trunk, then the source port's trunk membership register is checked to determine if the address has
moved.
A hash key is used to determine the appropriate forwarding port, based on some combination of the source and
destination MAC addresses for the current packet.
The search engine retrieves the VLAN member ports from the VLAN index table, which consists of 4K entries.
The search engine retrieves the VLAN member ports from the ingress port's VLAN map. Based on the destination
MAC address, the search engine determines the egress port from the MCT database. If the egress port is a member
of a trunk group, the packet can be distributed to the other members of that trunk group. The VLAN map is used to
check whether the egress port is a member of the VLAN, based on the ingress port. If it is a member, the packet is
forwarded otherwise it is discarded.
8.3
Multicast Packet Forwarding
For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the packet
based on the VLAN index and hash key.
Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port
trunking environment.
•
•
Determining one forwarding port per group.
For multicast packets, all but one port per group, the forwarding port, must be excluded.
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8.4
Preventing Multicast Packets from Looping Back to the Source Trunk
The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with
the source port. This is because, when we select the primary forwarding port for each group, we do not take the
source port into account. To prevent this, we simply apply one additional filter, so as to block that forwarding port for
this multicast packet.
9.0
9.1
LED Interface
Introduction
The MVTX2801AG LED block provides two interfaces: a serial output channel, and a parallel time-division interface.
The serial output channel provides port status information from the MVTX2801AG chip in a continuous serial stream.
This means that a low cost external device must be used to decode the serial data and to drive an LED array for
display.
By contrast, the parallel time-division interface supports a glueless LED module. Indeed, the parallel interface can
directly drive low-current LEDs without any extra logic. The pin LED_PM is used to select serial or parallel mode.
For some LED signals, the interface also provides a blinking option. Blinking may be enabled for LED signals TxD,
RxD, COL, and FC (to be described later). The pin LED_BLINK is used to enable blinking, and the blinking frequency
is around 160 ms.
9.2
Serial Mode
In serial mode, the following pins are utilized:
•
•
•
LED_SYNCO - a sync pulse that defines the boundary between status frames
LED_CLKO - the clock signal
LED_DO - a continuous serial stream of data for all status LEDs that repeats once every frame time
In each cycle (one frame of status information, or one sync pulse), 16x8 bits of data are transmitted on the LED_DO
signal. The sequence of transmission of data bits is as shown in the figure below:
LE_SYNCO
LE_DO
P0
P1
P2
P3
P4
P5
info info info info info info info info
P6
P7
U0
U1
U2
U3
U4
U5
U6
U7
LE_CLKO
0
1
2
3
4
5
6
7
FC
TxD
RxD
LNK
SP0
SP1
FDX
COL
Figure 7 - Timing diagram for serial mode in LED interface.
The status bits shown in here are flow control (FC), transmitting data (TxD), receiving data (RxD), link up (LNK),
speed (SP0 and SP1), full duplex (FDX), and collision (COL). Note that SP[1:0] is defined as 10 for 1 Gbps, 01 for
100 Mbps, and 00 for 10 Mbps.
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Also note that U0-U7 represent user-defined sub-frames in which additional status information may be embedded.
We will see later that the MVTX2801AG provides registers that can be written by the CPU to indicate this additional
status information as it becomes available.
9.3
Parallel Mode
In parallel mode, the following pins are utilized:
•
•
•
•
LED_PORT_SEL[3:0] - indicates which of the 4 Gigabit port status bytes is being read out
LED_PORT_SEL[7:4] - No use.
LED_PORT_SEL[9:8] - indicates which of the 2 user-defined status bytes is being read out
LED_BYTEOUT_[7:0] - provides 8 bits for 4 different port status indicators. Note that these bits are active
low.
By default, the system is in parallel mode. In parallel mode, the 10 status bytes are scanned in a continuous loop,
with one byte read out per clock cycle, and the appropriate port select bit asserted.
9.4
LED Control Registers
An LED Control Register can be used for programming the LED clock rate, sample hold time, and pattern in parallel
mode.
In addition, the MVTX2801AG provides 8 registers called LEDUSER[7:0] for user-defined status bytes. During
operation, the CPU can write values to these registers, which will be read out to the LED interface output (serial or
parallel). Only LEDUSER[1:0] are used in parallel mode. The content of the LEDUSER registers will be sent out by
the LED serial shift logic, or in parallel mode, a byte at a time.
Because in parallel mode there are only two user-defined registers, LEDUSER[7:2] is shared with LEDSIG[7:2].
For LEDSIG[j], where j = 2, 3, ..., 6, the corresponding register is used for programming the LED pin
LED_BYTEOUT_[j]. The format is as follows:
7
4
3
0
COL
FDX
SP1
SP0
COL
FDX
SP1
SP0
Bits [3:0]
Bits [7:4]
Signal polarity:
0: do not invert polarity (high true)
1: invert polarity
Signal select:
0: do not select
1: select the corresponding bit
For j = 2, 3, ..., 5, the value of LED_BYTEOUT_[j] equals the logical AND of all selected bits. For j = 6, the value is
equal to the logical OR. Therefore, the programmable LEDSIG[5:2] registers allow any conjunctive formula
including any of the 4 status bits (COL, FDX, SP1, SP0) or their negations to be sent to the LED_BYTEOUT_[5:2]
pins. Similarly, the programmable LEDSIG[6] register allows any disjunctive formula including any of the 4 status
bits or their negations to be sent to pin LED_BYTEOUT_[6].
LEDSIG[7] is used for programming both LED_BYTEOUT_[1] and LED_BYTEOUT_[0]. As we will see, it has other
functions as well. The format is as follows:
SEMICMF.019
33
MVTX2801AG
Data Sheet
7
4
3
0
GP
RxD
TxD
FC
P6
RxD
TxD
FC
Bits [7]
•
Global output polarity: this bit controls the output polarity of all LED_BYTEOUT_ and
LED_PORT_SEL pins. (Default 0)
- 0: do not invert polarity (LED_BYTEOUT_[7:0] are high activated; LED_PORT_SEL[9:0] are
low activated)
- 1: invert polarity (LED_BYTEOUT_[7:0] are low activated; LED_PORT_SEL[9:0] are high
activated)
Bits [6:4]
•
Signal select:
- 0: do not select
- 1: select the corresponding bit
•
•
The value of LED_BYTEOUT_[1] equals the logical OR of all selected bits. (Default
110)
Bit [3]
Polarity control of LED_BYTEOUT_[6]
(Default 0)
- 0: do not invert
- 1: invert
Bits [2:0]
•
•
Signal select:
- 0: do not select
- 1: select the corresponding bit
The value of LED_BYTEOUT_[0] equals the logical OR of all selected bits. (Default
001)
SEMICMF.019
34
Data Sheet
MVTX2801AG
10.0
Register Definition
Register Description
10.1
I2C
Addr
(Hex)
CPU
Addr
(Hex)
Register
Description
R/W
Default
Notes
0. ETHERNET Port Control Registers - Substitute [N] with Port number (0..7)
ECR1P”N”
Port Control Register 1 for Port N (N=0-7)
Port Control Register 2 for Port N (N=0-7)
Port Control Misc1
000 + 2N
001 + 2N
010
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
000+2N
001+2N
010
c0
00
c0
00
00
00
00
00
00
ECR2P”N”
ECRMISC1
ECRMISC2
Port Control Misc 2
011
011
GGCONTROL0
GGCONTROL1
GGCONTROL2
GGCONTROL3
ACTIVELINK
Extra Gigabit Port Control -port 0,1
Extra Gigabit Port Control -port 2,3
Extra Gigabit Port Control -port 4,5
Extra Gigabit Port Control -port 6,7
Active Link status port 7:0
012
N/A
013
N/A
014
N/A
015
N/A
016
N/A
1. VLAN Control Registers - Substitute [N] with Port number (0..8)
AVTCL
VLAN Type Code Register Low
100
R/W
R/W
R/W
R/W
R/W
R/W
R/W
012
00
81
ff
AVTCH
VLAN Type Code Register High
101
013
PVMAP”N”_0
PVMAP”N”_1
PVMAP”N”_2
PVMAP”N”_3
PVMODE
Port “N” Configuration Register 0 (N=0-8)
Port “N” Configuration Register 1 (N=0-8)
Port “N” Configuration Register 2 (N=0-8)
Port “N” Configuration Register 3 (N=0-8)
VLAN Operating Mode
102 + 4N
103 + 4N
104 + 4N
105 + 4N
126
014+4N
015+4N
016+4N
017+4N
038
ef
00
00
00
2. TRUNK Control Registers
TRUNK0
Trunk group 0 Member
Trunk group 1 Member
Trunk group 2 Member
Trunk group 3 Member
Single ring port map
Trunk ring port map
Trunk hash mode
200
201
202
203
204
205
206
207
208
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NA
NA
NA
NA
NA
NA
NA
039
NA
00
00
00
00
TRUNK1
TRUNK2
TRUNK3
SINGLE_RING
TRUNK_RING
TRUNK_HASH_MODE
TRUNK0_MODE
TRUNK0_HASH0
00
00
08
Trunk Group 0 Mode
Trunk Group 0 Hash 0, 1, 2 Destination
Port
TRUNK0_HASH1
TRUNK0_HASH2
Trunk Group 0 Hash 2, 3, 4, 5 Destination
Port
209
20A
R/W
R/W
NA
NA
82
20
Trunk Group 0 Hash 5, 6, 7 Destination
Port
Table 6 - MVTX2801AG Register Description
SEMICMF.019
35
MVTX2801AG
Data Sheet
CPU
Addr
(Hex)
I2C
Addr
(Hex)
Register
Description
R/W
Default
Notes
TRUNK0_HASH3
TRUNK0_HASH4
TRUNK0_HASH5
Trunk Group 0 Hash 8, 9, 10 Destination
Port
20B
R/W
R/W
R/W
NA
08
82
20
Trunk Group 0 Hash 10, 11, 12, 13
Destination Port
20C
20D
NA
NA
Trunk Group 0 Hash 13, 14, 15 Destination
Port
TRUNK1_MODE
TRUNK1_HASH0
Trunk Group 1 Mode
20E
20F
R/W
R/W
03A
NA
00
08
Trunk Group 1 Hash 0, 1, 2 Destination
Port
TRUNK1_HASH1
TRUNK1_HASH2
TRUNK1_HASH3
TRUNK1_HASH4
Trunk Group 1 Hash 2, 3, 4, 5 Destination
Port
210
211
212
213
R/W
R/W
R/W
R/W
NA
NA
NA
NA
82
20
08
82
Trunk Group 1 Hash 5, 6, 7 Destination
Port
Trunk Group 1 Hash 8, 9, 10 Destination
Port
Trunk Group 1 Hash 10, 11, 12, 13
Destination
TRUNK1_HASH5
TRUNK2_HASH0
Trunk Group 1 Hash 13, 14, 15 Destination 214
R/W
R/W
NA
NA
20
2c
Trunk Group 2 Hash 0, 1, 2 Destination
Port
215
216
217
218
219
21A
21B
21C
21D
21E
21F
220
TRUNK2_HASH1
TRUNK2_HASH2
TRUNK2_HASH3
TRUNK2_HASH4
TRUNK2_HASH5
TRUNK3_HASH0
TRUNK3_HASH1
TRUNK3_HASH2
TRUNK3_HASH3
TRUNK3_HASH4
TRUNK3_HASH5
Trunk Group 2 Hash 2, 3, 4, 5 Destination
Port
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
cb
b2
2c
cb
b2
2c
cb
b2
2c
Bc
b2
Trunk Group 2 Hash 5, 6, 7 Destination
Port
Trunk Group 2 Hash 8, 9, 10 Destination
Port
Trunk Group 2 Hash 10, 11, 12, 13
Destination Port
Trunk Group 2 Hash 13, 14, 15 Destination
Port
Trunk Group 3 Hash 0, 1, 2 Destination
Port
Trunk Group 3 Hash 2, 3, 4, 5 Destination
Port
Trunk Group 3 Hash 5, 6, 7 Destination
Port
Trunk Group 3 Hash 8, 9, 10 Destination
Port
Trunk Group 3 Hash 10, 11, 12, 13
Destination Port
Trunk Group 3 Hash 13, 14, 15 Destination
Port
Multicast_HASH00
Multicast_HASH01
Multicast hash result 0 mask bit[7:0]
Multicast hash result 1 mask bit[7:0]
221
222
R/W
R/W
NA
NA
ff
ff
Table 6 - MVTX2801AG Register Description (continued)
SEMICMF.019
36
Data Sheet
MVTX2801AG
I2C
Addr
(Hex)
CPU
Addr
(Hex)
Register
Description
R/W
Default
Notes
Multicast_HASH02
Multicast_HASH03
Multicast_HASH04
Multicast_HASH05
Multicast_HASH06
Multicast_HASH07
Multicast_HASH08
Multicast_HASH09
Multicast_HASH10
Multicast_HASH11
Multicast_HASH12
Multicast_HASH13
Multicast_HASH14
Multicast_HASH15
Multicast_HASHML
Multicast HASHMH
3. CPU Port Configuration
MAC0
Multicast hash result 2 mask bit[7:0]
Multicast hash result 3 mask bit[7:0]
Multicast hash result 4 mask bit[7:0]
Multicast hash result 5 mask bit[7:0]
Multicast hash result 6 mask bit[7:0]
Multicast hash result 7 mask bit[7:0]
Multicast hash result 8 mask bit[7:0]
Multicast hash result 9 mask bit[7:0]
Multicast hash result 10 mask bit[7:0]
Multicast hash result 11 mask bit[7:0]
Multicast hash result 12 mask bit[7:0]
Multicast hash result 13 mask bit[7:0]
Multicast hash result 14 mask bit[7:0]
Multicast hash result 15 mask bit[7:0]
Multicast hash bit[8] for result 7-0
Multicast hash bit[8] for result 15-8
223
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NA
ff
224
225
226
227
228
229
22A
22B
22C
22D
22E
22F
230
231
232
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
ff
ff
ff
ff
ff
ff
fff
ff
ff
ff
ff
ff
ff
ff
ff
CPU MAC Address byte 0
CPU MAC Address byte 1
CPU MAC Address byte 2
CPU MAC Address byte 3
CPU MAC Address byte 4
CPU MAC Address byte 5
Interrupt Mask 0
300
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
00
00
00
00
00
00
ff
MAC1
301
MAC2
302
MAC3
303
MAC4
304
MAC5
305
INT_MASK0
306
INT_MASK1
Interrupt Mask 1
307
ff
INT_MASK2
Interrupt Mask 2
308
ff
INT_MASK3
Interrupt Mask 3
309
ff
INT_STATUS0
INT_STATUS1
INTP_MASK”N”
Status of Masked Interrupt Register0
Status of Masked Interrupt Register1
30A
30B
30C-30F
RO
Interrupt Mask for MAC Port 2n, 2n+1
(n=0-3)
R/W
ff
RQS
Receive Queue Select
310
311
312
R/W
RO
NA
NA
03B
00
RQSS
TX_AGE
Receive Queue Status
Transmission Queue Aging Time
R/W
08
Table 6 - MVTX2801AG Register Description (continued)
SEMICMF.019
37
MVTX2801AG
Data Sheet
CPU
Addr
(Hex)
I2C
Addr
(Hex)
Register
Description
R/W
Default
Notes
4. Search Engine Configurations
AGETIME_LOW
AGETIME_HIGH
V_AGETIME
MAC Address Aging Time Low
MAC Address Aging Time High
VLAN to Port Aging Time
400
R/W
R/W
R/W
R/W
R/W
03C
2c
00
ff
401
402
403
404
03D
NA
NA
NA
SE_OPMODE
Search Engine operation mode
Scan Control Register
00
00
SCAN
5. Buffer Control and QOS Control
FCBAT
QOSC
FCR
FCB Aging Timer
500
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
03E
03F
040
041
042
043
044
045
046
047
048
049
04A
04B
04C
04D
04E
04F
050
051
052
053
054
055-084
NA
ff
QOS Control
501
00
08
88
c6
fa
Flooding Control Register
VLAN Priority Map Low
VLAN Priority Map Middle
VLAN Priority Map High
TOS Priority Map Low
TOS Priority Map Middle
TOS Priority Map High
VLAN Discard Map
502
AVPML
AVPMM
AVPMH
TOSPML
TOSPMM
TOSPMH
AVDM
TOSDML
BMRC
UCC
503
504
505
506
88
c6
fa
507
508
509
00
00
00
07
48
00
26
37
00
00
00
00
00
00
TOS Discard Map
50A
50B
50C
50D
50E
50F
510
Broadcast/Multicast Rate Control
Unicast Congestion Control
Multicast Congestion Control
Port Reservation for 10/100 Ports
Port Reservation for Giga Ports
Share FCB Size
MCC
PR100
PRG
SFCB
C2RS
Class 2 Reserved Size
Class 3 Reserved Size
Class 4 Reserved Size
Class 5 Reserved Size
Class 6 Reserved Size
Class 7 Reserved Size
QOS Control (N=0 - 2F)
QOS Control (N=30 - 82)
WRED Rate Control 0
WRED Rate Control 1
511
C3RS
512
C4RS
513
C5RS
514
C6RS
515
C7RS
516
QOSC”N”
QOSC”N”
RDRC0
RDRC1
517-546
547-599
59A
59B
085
086
8e
68
Table 6 - MVTX2801AG Register Description (continued)
SEMICMF.019
38
Data Sheet
MVTX2801AG
I2C
Addr
(Hex)
CPU
Addr
(Hex)
Register
Description
R/W
Default
Notes
6. MISC Configuration Register
MII_OP0
MII Register Option 0
600
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
0B1
00
00
10
00
00
00
00
00
00
38
00
00
00
00
80
33
32
20
40
61
MII_OP1
MII Register Option 1
601
602
603
604
605
606
607
608
609
60A
60B
60C
60D
60E
60F
610
611
612
613
0B2
0B3
N/A
N/A
N/A
N/A
N/A
N/A
0B4
0B5
0C5
0BB
0BC
0BD
0BE
0BF
0C0
0C1
0C2
FEN
Feature Registers
MIIC0
MII Command Register 0
MIIC1
MII Command Register 1
MIIC2
MII Command Register 2
MIIC3
MII Command Register 3
MIID0
MII Data Register 0
MIID1
MII Data Register 1
RO
LED
LED Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEVICE
Device id and test
CHECKSUM
LEDUSER0
LEDUSER1
LEDUSER2
LEDUSER3
LEDUSER4
LEDUSER5
LEDUSER6
LEDUSER7
EEPROM Checksum Register
LED User Define Register 0
LED User Define Register 1
LED User Define Reg. 2/LED_byte pin 2
LED User Define Reg. 3/LED_byte pin 3
LED User Define Reg. 4/LED_byte pin 4
LED User Define Reg. 5/LED_byte pin 5
LED User Define Reg. 6/LED_byte pin 6
LED User Define Reg. 7/LED_byte pin 1 &
0
MIINP0
MII NEXT PAGE DATA REGISTER0
MII NEXT PAGE DATA REGISTER1
614
615
R/W
R/W
0C3
0C4
00
00
MIINP1
E. Test Group Control
DTSRL
Test Register Low
E00
E01
E02
E03
E04
E05
E06
E07
E08
R/W
R/W
R/W
RO
N/A
N/A
N/A
N/A
N/A
N/A
0B6
0B7
0B8
00
01
00
DTSRM
DTSRH
Test Register Medium
Test Register High
TDRB0
TEST MUX read back register [7:0]
TEST MUX read back register [15:8]
Test Counter Register
MASK Timeout 0
TDRB1
RO
DTCR
R/W
R/W
R/W
R/W
00
00
00
00
MASK0
MASK1
MASK Timeout 1
MASK2
MASK Timeout 2
Table 6 - MVTX2801AG Register Description (continued)
SEMICMF.019
39
MVTX2801AG
Data Sheet
CPU
Addr
(Hex)
I2C
Addr
(Hex)
Register
Description
R/W
Default
Notes
MASK3
MASK Timeout 3
E09
R/W
R/W
0B9
00
00
MASK4
MASK Timeout 4
E0A
0BA
F. Device Configuration Register
GCR
Global Control Register
F00
F01
F02
F03
F04
F05
F06
F07
F08
F09
F0A
F0B
F0C
F0D
F0E
F0F
F10
FFF
R/W
RO
RO
RO
RO
RO
R/W
RO
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
N/A
N/A
NA
00
DCR
Device Status and Signature Register
Gigabit Port0 Port1 Status Register
Gigabit Port2 Port3 Status Register
Gigabit Port4 Port5 Status Register
Gigabit Port6 Port7 Status Register
Device Port Status Register
Data read back register
DCR01
DCR23
DCR45
DCR67
DPST
NA
NA
NA
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
00
DTST
PLLCR
LCLKCR
BCLKCR
BSTRRB0
BSTRRB1
BSTRRB2
BSTRRB3
BSTRRB4
BSTRRB5
DA
PLL Control Register
00
00
00
LCLK Control Register
BCLK Control Register
BOOT STRAP read back register 0
BOOT STRAP read back register 1
BOOT STRAP read back register 2
BOOT STRAP read back register 3
BOOT STRAP read back register 4
BOOT STRAP read back register 5
DA Register
da
Table 6 - MVTX2801AG Register Description (continued)
1. se = Search Engine
Note:
2. fe = Frame Engine
3. pgs = Port Group01, 23, 45, and 67
4. mc = MAC Control
5. tm = timer
10.2
Group 0 Address - MAC Ports Group
ECR1Pn: Port N Control Register
10.2.1
I2C Address h00+2n; Serial Interface Address: h000+2n (n=0 to 7) (For the 2600 it is different)
Accessed by serial interface and I2C (R/W)
SEMICMF.019
40
Data Sheet
MVTX2801AG
7
6
5
4
3
2
1
0
Sp State
A-FC
Port Mode
Bit [4:0]
Bit [4:3]
•
Port Mode (Default 2'b00)
- 00 - Automatic Enable Auto-Negotiation - This enables hardware state machine
for auto-negotiation.
- 01 - Limited Disable auto-Negotiation - This disables hardware for speed
auto-negotiation. Hardware Polls MII for link status.
- 10 - Link Down - Force link down (disable the port). Does not talk to PHY.
- 11 - Link Up - Does not talk to PHY. User ERC1 [2:0] for config.
- 1 - 10Mbps (Default 1'b0)
Bit [2]
- 0 - 100Mbps
•
Bit 2 is used only when the port is in MII (10/100) mode.
- 1 - Half Duplex (Do not use) (Default 1'b0)
- 0 - Full Duplex
Bit [1]
Bit [0]
- 1 - Flow Control Off (Default 1'b0)
- 0 - Flow Control On
•
•
When flow control is on:
In full duplex mode, the MAC transmitter sends Flow Control Frames when
necessary. The MAC receiver interprets and processes incoming flow
control frames. The Flow Control Frame Received counter is incremented
whenever a flow control frame is received.
•
•
When flow control is off:
In full duplex mode, the MAC transmitter does not send flow control frames.
The MAC receiver does not interpret or process the flow control frames. The
Flow Control Frame Receiver counter is not incremented.
Bit [5]
•
•
Asymmetric Flow Control Enable.
- 0 - Disable asymmetric flow control
- 1 - Enable asymmetric flow control
When this bit is set, and flow control is on (bit[0] = 0), don't send out a flow
control frame. But MAC Receiver interprets and process flow control
frames. (Default is 0)
- SS - Spanning tree state (802.1D spanning tree protocol). (Default 2'b11)
- 00 - Blocking: Frame is dropped
Bit [7:6]
- 01 - Listening: Frame is dropped
- 10 - Learning: Frame is dropped. Source MAC address is learned.
- 11 - Forwarding: Frame is forwarded. Source MAC address is learned.
10.2.2
ECR2Pn: Port N Control Register
I2C Address: 01+2n; Serial Interface Address:h001+2n (n=0to7)
Accessed by serial interface (R/W)
7
0
Security En
RTsel
DisL
Ftf
Futf
SEMICMF.019
41
MVTX2801AG
Data Sheet
Bit[0]:
Bit[1]:
Bit[2]:
•
•
•
Filter untagged frame (Default 0)
0: Disable
1: Enable - All untagged frames from this port are discarded or follow
security option when security is enable
•
•
•
Filter Tag frame (Default 0)
0: Disable
1: Enable - All tagged frames from this port are discarded or follow security
option when security is enable
•
•
•
Learning Disable (Default 0)
0: Learning is enabled on this port
1: Learning is disabled on this port
Bit[3]:
•
•
•
Reserved
Reserved
Bit [5:4:]
Bit[7:6]
Security Enable (Default 00). The MVTX2801AG checks the incoming data
for one of the following conditions:
•
•
If the source MAC address of the incoming packet is in the MAC table and is
defined as secure address but the ingress port is not the same as the port
associated with the MAC address in the MAC table.
A MAC address is defined as secure when its entry at MAC table has static
status and bit 0 is set to 1. MAC address bit 0 (the first bit transmitted)
indicates whether the address is unicast or multicast. As source addresses
are always unicast bit 0 is not used (always 0). MVTX2801 uses this bit to
define secure MAC addresses.
•
•
If the port is set as learning disable and the source MAC address of the
incoming packet is not defined in the MAC address table.
If the port is configured to filter untagged frames and an untagged frame
arrives or if the port is configured to filter tagged frames and a tagged frame
arrives.
•
If one of these three conditions occurs, the packet will be handled according
to one of the following specified options:
- 00 - Disable port security
- 01 - Enable port security. Port will be disabled when security violation is detected
- 10 - N/A
- 11 - N/A
10.2.3
ECRMISC1 - CPU Port Control Register MISC1
I2C Address h10, Serial Interface Address:h010
Access by serial interface and I2C (R/W)
7
5
0
SS State
Reserved
Bit [7:0]
•
Reserved
SEMICMF.019
42
Data Sheet
MVTX2801AG
10.2.4
ECRMISC2 - CPU Port Control Register MISC2
I2C Address h11, Serial Interface Address:h011
Access by serial interface and I2C (R/W)
7
0
Security En
RTsel
DisL
Ftf
Futf
Bit [7:0]
•
Reserved
SEMICMF.019
43
MVTX2801AG
Data Sheet
10.2.5
GGControl 0- Extra GIGA Port Control
Serial Interface Address:h012
Accessed by and serial interface (R/W)
7
5
4
1
0
DFC1
DI1
MII1
Rst1
DFC0
DI0
MII0
Rst0
Bit[0]:
Bit[1]:
•
•
Reset GIGA port 0 (Default is 0)
- 0: Normal operation
- 1: Reset Gigabit port 0.
GIGA port 0 use MII interface (10/100M) (Default is 0)
- 0: Gigabit port operation at 1000M mode
- 1: Gigabit port operation at 10/100M mode (MII)
Bit[2]:
Bit[3]:
Bit[4]:
•
•
•
Reserved -Must be '0' (Default 0)
Reserved - Must be '0'
Reset GIGA port 1 (Default 0)
- 0: Normal operation
- 1: Reset Gigabit port 1.
Bit[5]:
•
GIGA port 1 use MII interface (10/100M) (Default 0)
- 0: Gigabit port operation at 1000M mode
- 1: Gigabit port operation at 10/100M mode (MII)
Bit[6]:
Bit[7]:
•
•
Reserved - Must be '0' (Default 0)
Reserved - Must be '0'
10.2.6
GGControl 1- Extra GIGA Port Control
Serial Interface Address:h013
Accessed by CPU and serial interface (R/W)
7
5
4
1
0
DFC3
DI3
MII3
Rst3
DFC2
DI2
MII2
Rst2
Bit[0]:
Bit[1]:
•
•
Reset GIGA port 2 Default is 0
- 0: Normal operation
- 1: Reset Gigabit port 2
GIGA port 2 use MII interface (10/100M) Default is 0
- 0: Gigabit port operation at 1000M mode
- 1: Gigabit port operation at 10/100M mode (MII)
Bit[2]:
Bit[3]:
•
•
Reserved - Must be '0' (Default '0')
Reserved - Must be '0'
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Data Sheet
MVTX2801AG
Bit[4]:
•
•
Reset GIGA port 3 Default is 0
- 0: Normal operation
- 1: Reset Gigabit port 3.
Bit[5]:
GIGA port 3 use MII interface (10/100M) Default is 0
- 0: Gigabit port operation at 1000M mode
- 1: Gigabit port operation at 10/100M mode (MII)
Bit[6]:
Bit[7]:
•
•
Reserved - Must be '0' (Default '0')
Reserved - Must be '0'
10.2.7
GGControl 2- Extra GIGA Port Control
Serial Interface Address:h014
Accessed by CPU and serial interface (R/W)
7
5
4
1
0
Reserved
Bit[7:0]:
•
Reserve
10.2.8
GGControl 3- Extra GIGA Port Control
Serial Interface Address:h015
Accessed by CPU and serial interface (R/W)
7
5
4
1
0
Reserved
Bit[7:0]:
•
Reserve
10.3
Group 1 Address - VLAN Group
10.3.1
AVTCL - VLAN Type Code Register Low
I2C Address h12; Serial Interface Address:h100
Accessed by serial interface and I2C (R/W)
Bit[7:0]:
•
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00)
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Data Sheet
10.3.2
AVTCH - VLAN Type Code Register High
I2C Address h13; Serial Interface Address:h101
Accessed by serial interface and I2C (R/W)
Bit [7:0]
•
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81)
10.3.3
PVMAP00_0 - Port 00 Configuration Register 0
I2C Address h14, Serial Interface Address:h102)
Accessed by serial interface and I2C (R/W)
Port Based VLAN Mode
This register indicates the legal egress ports. Example: A “1” on bit 3 means that packets arriving on port 0 can be
sent to port 3. A “0” on bit 3 means that any packet destined to port 3 will be discarded.
Bit[3:0]:
Bit[7:4]:
•
•
VLAN Mask for ports 3 to 0 (Default F)
- 0 - Disable
- 1 - Enable
Reserve (Default F)
10.3.4
PVMAP00_1 - Port 00 Configuration Register 1
I2C Address h15, Serial Interface Address:h103
Accessed by serial interface and I2C (R/W)
Port Based VLAN Mode
Bit[0]:
•
•
VLAN Mask for ports 8 (Default 1'B1)
- 0 - Disable
- 1 - Enable
Bit[7:1]:
Reserved (Default is 7'B1111_111)
10.3.5
PVMAP00_2 - Port 00 Configuration Register 2
I2C Address h16, Serial Interface Address:h104
Accessed by serial interface and I2C (R/W)
This registered is unused
SEMICMF.019
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Data Sheet
MVTX2801AG
10.3.6
PVMAP00_3 - Port 00 Configuration Register 3
I2C Address h17, Serial Interface Address:h105
Accessed by serial interface and I2C (R/W)
Port Based Mode
7
6
5
3
2
1
0
FP en
Drop
Default TX priority
FNT
IF
Reserved
Bit [1:0]:
Bit [2]:
•
•
Reserved (Default 0)
Force untagout (Default 0)
- 0 Disable
- 1 Force untag output
All packets transmitted from this port are untagged. This register is used when this
port is connected to legacy equipment that does not support VLAN tagging.
Bit [5:3]:
•
Fixed Transmit priority. Used when bit[7] = 1 (Default 0)
- 000 Transmit Priority Level 0 (Lowest)
- 001 Transmit Priority Level 1
- 010 Transmit Priority Level 2
- 011 Transmit Priority Level 3
- 100 Transmit Priority Level 4
- 101 Transmit Priority Level 5
- 110 Transmit Priority Level 6
- 111 Transmit Priority Level 7 (Highest)
Bit [6]:
Bit [7]:
•
•
Fixed Discard priority (Default 0)
- 0 - Discard Priority Level 0 (Lowest)
- 1 - Discard Priority Level 7(Highest)
Enable Fix Priority (Default 0)
- 0 Disable fix priority. All frames are analysed. Transmit Priority and Drop Priority
are based on VLAN Tag, TOS or Logical Port.
- 1 Transmit Priority and Discard Priority are based on values programmed in bit
[6:3]
Port VLAN Map
PVMAP00_0,1,2,3 I2C Address h14,15,16,17; Serial Interface Address:h102,103,104,105)
See above format
PVMAP01_0,1,2,3 I2C Address h18,19,1A,1B; Serial Interface Address:h106,107,108,109)
See above format
PVMAP02_0,1,2,3 I2C Address h1C,1D,1E,1F; Serial Interface Address:h10A, 10B, 10C, 10D)
See above format
PVMAP03_0,1,2,3 I2C Address h20,21,22,23; Serial Interface Address:h10E, 10F, 110, 111)
See above format
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Data Sheet
PVMAP04_0,1,2,3 I2C Address h24,25,26,27; Serial Interface Address:h112, 113, 114, 115) (Reserved)
PVMAP05_0,1,2,3 I2C Address h28,29,2A,2B; Serial Interface Address:h116, 117, 118, 119) (Reserved)
PVMAP06_0,1,2,3 I2C Address h2C,2D,2E,2F; Serial Interface Address:h11A, 11B, 11C, 11D) (Reserved)
PVMAP07_0,1,2,3 I2C Address h30,31,32,33; Serial Interface Address:h11E, 11F, 120, 121) (Reserved)
PVMAP08_0,1,2,3 I2C Address h34,35,36,37; Serial Interface Address:h122, 123, 124, 125) (Reserved)
10.3.7
PVMODE
I2C Address: h038, Serial Interface Address:h126
Accessed by serial interface (R/W)
7
4
3
1
0
RO
MP
BPDU
DM Reserved
Vmod
Bit [0]:
Bit [4]:
•
•
Reserved
- Must be '0'
Disable MAC address 0
- 0: MAC address 0 is not leaned.
- 1: MAC address 0 is leaned.
Bit [5]:
•
Force BPDU as multicast frame (Default 0)
- 1: Enable. BPDU frames (frames with destination MAC address in the range of
01-80-C2 00-00-00 through 01-80-C2-00-00-0F) are forwarded as multicast
frames.
- 0: Disable. Drop frames in this range.
Bit [6]:
Bit [7]:
•
•
MAC/PORT
- 0: Single MAC address per system
- 1: Single MAC address per port
Reserved
10.4
Group 2 Address - Port Trunking Group
10.4.1
TRUNK0 - Trunk group 0 Member (Managed Mode Only)
Serial Interface Address:h200
Accessed by serial interface (R/W)
Bit [7:0] Reserved
10.4.2
TRUNK1 - Trunk group 1 Member (Managed Mode Only)
Serial Interface Address:h201
Accessed by serial interface (R/W)
Bit [7:0] Reserved
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Data Sheet
MVTX2801AG
10.4.3
TRUNK2- Trunk group 2 Member (Managed Mode Only)
Serial Interface Address:h202
Accessed by serial interface (R/W)
Bit [7:0] Reserved
10.4.4
TRUNK3- Trunk group 3 Member (Managed Mode Only)
Serial Interface Address:h203
Accessed by serial interface and I2C (R/W)
Bit [7:0] Reserved
10.4.5
TRUNK_HASH_MODE - Trunk hash mode
Serial Interface Address:h206
Accessed by serial interface (R/W)
Bit [7:0] Reserved
10.4.6
TRUNK0_MODE - Trunk group 0 and 1 mode
I2C Address: h039, Serial Interface Address:h207
Accessed by serial interface and I2C (R/W)
Port Selection in unmanaged mode. Trunk group 0 and trunk group 1 are enable accordingly to bit [1:0] when input
pin P_d[9] = 0 (external pull down).
7
0
Port sel
Bit [1:0]:
•
Port member selection for Trunk 0 and 1 in unmanaged mode (Default 2'b00)
- 00 - Only trunk group 0 is enable. Port 0 and 1 are used for trunk group0
- 01 - Only trunk group 0 is enable. Port 0,1 and 2 are used for trunk group0
- 10 - Only trunk group 0 is enable. Port 0,1,2 and 3 are used for trunk group0
- 11 - Trunk group 0 and 1 are enable. Port 0, 1 used for trunk group0, and port 2 and 3
are used for trunk group1
10.4.7
TRUNK0_HASH0 - Trunk group 0 hash result 0,1,2 destination port number
Serial Interface Address:h208
Reserved
10.4.8
TRUNK0_HASH1 - Trunk group 0 hash result 2,3,4,5 destination port number
Serial Interface Address:h209
Reserved
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Data Sheet
10.4.9
TRUNK0_HASH2 - Trunk group 0 hash result 5,6,7 destination port number
Serial Interface Address:h20A
Reserved
10.4.10
TRUNK0_HASH3 - Trunk group 0 hash result 8,9,10 destination port number
Serial Interface Address:h20B
Reserved
10.4.11
TRUNK0_HASH4 - Trunk group 0 hash result 10,11,12,13 destination port number
Serial Interface Address:h20C
Reserved
10.4.12
TRUNK0_HASH5 - Trunk group 0 hash result 13,14,15 destination port number
Serial Interface Address:h20D
Reserved
10.4.13
TRUNK1_MODE - Trunk group 1 mode (Unmanaged Mode)
I2C Address h03A; Serial Interface Address:20E
Accessed by serial interface and I2C (R/W)
Reserved
10.4.14
TRUNK1_HASH0 - Trunk group 1 hash result 0, 1, 2 destination port number
Serial Interface Address:h20F
Reserved
10.4.15
TRUNK1_HASH1 - Trunk group 1 hash result 2, 3, 4, 5 destination port number
Serial Interface Address:h210
Reserved
10.4.16
TRUNK1_HASH2 - Trunk group 1 hash result 5, 6, 7 destination port number
Serial Interface Address:h211
Reserved
10.4.17
TRUNK1_HASH3 - Trunk group 1 hash result 8, 9, 10 destination port number
Serial Interface Address:h212
Reserved
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Data Sheet
MVTX2801AG
10.4.18
TRUNK1_HASH4- Trunk group 1 hash result 11, 12, 13 destination port number
Serial Interface Address:h213
Reserved
10.4.19
TRUNK1_HASH5 - Trunk group 1 hash result 13, 14, 15 destination port number
Serial Interface Address:h214
Reserved
10.4.20
TRUNK2_HASH0 - Trunk group 2 hash result 0, 1, 2 destination port number
Serial Interface Address:h215
Reserved
10.4.21
TRUNK2_HASH1 - Trunk group 2 hash result 2, 3, 4, 5 destination port number
Serial Interface Address:h216
Reserved
10.4.22
TRUNK2_HASH2 - Trunk group 2 hash result 5, 6, 7 destination port number
Serial Interface Address:h217
Reserved
10.4.23
TRUNK2_HASH3 - Trunk group 2 hash result 8, 9, 10 destination port number
Serial Interface Address:h218
Reserved
10.4.24
number
TRUNK2_HASH4 - Trunk group 2 hash result 10, 11, 12, 13 destination port
Serial Interface Address:h219
Reserved
10.4.25
TRUNK2_HASH5 - Trunk group 2 hash result 13, 14, 15 destination port number
Serial Interface Address:h21A
Reserved
10.4.26
TRUNK3_HASH0 - Trunk group 3 hash result 0, 1, 2 destination port number
Serial Interface Address:h21B
Reserved
10.4.27
TRUNK3_HASH1 - Trunk group 3 hash result 2, 3, 4, 5 destination port number
Serial Interface Address:h21C
Reserved
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Data Sheet
10.4.28
TRUNK3_HASH2 - Trunk group 3 hash result 5, 6, 7 destination port number
Serial Interface Address:h21D
Reserved
10.4.29
TRUNK3_HASH3 - Trunk group 3 hash result 8, 9, 10 destination port number
Serial Interface Address:h21E
Reserved
10.4.30
number
TRUNK3_HASH4 - Trunk group 3 hash result 10, 11, 12, 13 destination port
Serial Interface Address:h21F
Reserved
10.4.31
TRUNK3_HASH5 - Trunk group 3 hash result 13, 14, 15 destination port number
Serial Interface Address:h220
Reserved
10.4.32
10.4.33
Multicast Hash Registers
Multicast_HASH00 - Multicast hash result0 mask byte [7:0]
Serial Interface Address:h221
Accessed by serial interface (R/W)
Reserved
10.4.34
Multicast_HASH01 - Multicast hash result1 mask byte [7:0]
Serial Interface Address:h222
Accessed by serial interface (R/W)
Reserved
10.4.35
Multicast_HASH02 - Multicast hash result2 mask byte [7:0]
Serial Interface Address:h223
Accessed by serial interface (R/W)
Reserved
10.4.36
Multicast_HASH03 - Multicast hash result3 mask byte [7:0]
Serial Interface Address:h224
Accessed by serial interface (R/W)
Reserved
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Data Sheet
MVTX2801AG
10.4.37
Multicast_HASH04 - Multicast hash result4 mask byte [7:0]
Serial Interface Address:h225
Accessed by serial interface (R/W)
Reserved
10.4.38
Multicast_HASH05 - Multicast hash result5 mask byte [7:0]
Serial Interface Address:h226
Accessed by serial interface (R/W)
Reserved
10.4.39
Multicast_HASH06 - Multicast hash result6 mask byte [7:0]
Serial Interface Address:h227
Accessed by serial interface (R/W)
Reserved
10.4.40
Multicast_HASH07 - Multicast hash result7 mask byte [7:0]
Serial Interface Address:h228
Accessed by serial interface (R/W)
Reserved
10.4.41
Multicast_HASH08 - Multicast hash result8 mask byte [7:0]
Serial Interface Address:h229
Accessed by serial interface (R/W)
Reserved
10.4.42
Multicast_HASH09 - Multicast hash result9 mask byte [7:0]
Serial Interface Address:h22A
Accessed by serial interface (R/W)
Reserved
10.4.43
Multicast_HASH10 - Multicast hash result10 mask byte [7:0]
Serial Interface Address:h22B
Accessed by serial interface (R/W)
Reserved
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Data Sheet
10.4.44
Multicast_HASH11 - Multicast hash result11 mask byte [7:0]
Serial Interface Address:h22C
Accessed by serial interface (R/W)
Reserved
10.4.45
Multicast_HASH12 - Multicast hash result12 mask byte [7:0]
Serial Interface Address:h22D
Accessed by serial interface (R/W)
Reserved
10.4.46
Multicast_HASH13 - Multicast hash result13 mask byte [7:0]
Serial Interface Address:h22E
Accessed by serial interface (R/W)
Reserved
10.4.47
Multicast_HASH14 - Multicast hash result14 mask byte [7:0]
Serial Interface Address:h22F
Accessed by serial interface (R/W)
Reserved
10.4.48
Multicast_HASH15 - Multicast hash result15 mask byte [7:0]
Serial Interface Address:h230
Accessed by serial interface (R/W)
Reserved
10.4.49
Multicast_HASHML - Multicast hash bit[8] for result7-0
Serial Interface Address:h231
Accessed by serial interface (R/W)
Reserved
10.4.50
Multicast_HASHMH - Multicast hash BIT[8] for result 15-8
Serial Interface Address:h232
Accessed by serial interface (R/W)
Reserved
SEMICMF.019
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Data Sheet
MVTX2801AG
10.5
Group 3 Address - CPU Port Configuration Group
10.5.1
MAC0 - CPU Mac address byte 0
Serial Interface Address:h300
Reserved
10.5.2
MAC1 - CPU Mac address byte 1
Serial Interface Address:h301
Reserved
10.5.3
MAC2 - CPU Mac address byte 2
Serial Interface Address:h302
Reserved
10.5.4
MAC3 - CPU Mac address byte 3
Serial Interface Address:h303
Reserved
10.5.5
MAC4 - CPU Mac address byte 4
Serial Interface Address:h304
Reserved
10.5.6
MAC5 - CPU Mac address byte 5
Serial Interface Address:h305
Reserved
10.5.7
INT_MASK0 - Interrupt Mask 0
Serial Interface Address:h306
Reserved
10.5.8
INT_MASK1 - Interrupt Mask 1
Serial Interface Address:h307
Reserved
10.5.9
INT_STATUS0 - Masked Interrupt Status Register0
Serial Interface Address:h30A
Reserved
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MVTX2801AG
Data Sheet
10.5.10
INT_STATUS1 - Masked Interrupt Status Register1
Serial Interface Address:h30B
Reserved
10.5.11
INTP_MASK0 - Interrupt Mask for MAC Port 0,1
Serial Interface Address:h30C
Reserved
10.5.12
INTP_MASK1 - Interrupt Mask for MAC Port 2,3
Serial Interface Address:h30D
Reserved
10.5.13
INTP_MASK4 - Interrupt Mask for MAC Port 4,5
Serial Interface Address:h30E
Reserved
10.5.14
INTP_MASK5 - Interrupt Mask for MAC Port 6,7
Serial Interface Address:h30F
Reserved
10.5.15
RQS - Receive Queue Select
Serial Interface Address:h310
Reserved
10.5.16
RQSS - Receive Queue Status
Serial Interface Address:h311
Reserved
10.5.17
TX_AGE - Tx Queue Aging timer
I2C Address: h03B;Serial Interface Address:h312
Accessed by serial interface and I2C (R/W)
7
5
0
Tx Queue Agent
Bit[4:0]:
Bit[5]:
•
•
•
Unit of 100ms (Default 8). Disable transmission queue aging if value is zero.
Must be set to '0'
Reserved
Bit[7:6]:
SEMICMF.019
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Data Sheet
MVTX2801AG
10.6
Group 4 Address - Search Engine Group
10.6.1
AGETIME_LOW - MAC address aging time Low
I2C Address h03C; Serial Interface Address:h400
Accessed by serial interface and I2C (R/W)
Bit [7:0] Low byte of the MAC address aging timer. (Default 2c)
Mac address aging is enable/disable by boot strap T_d[9].
10.6.2
AGETIME_HIGH -MAC address aging time High
I2C Address h03D; Serial Interface Address h401
Accessed by serial interface and I2C (R/W)
Bit [7:0]: High byte of the MAC address aging timer. (Default 00)
Aging time is based on the following equation:
{AGETIME_TIME,AGETIME_LOW} X (# of MAC entries X100µsec)
Note: the number of entries= 66K when T_d[5] is pull down (SRAM memory size = 512K) and 34K when T_d[5] is
pull up (SRAM memory size = 256K).
10.6.3
V_AGETIME - VLAN to Port aging time
Serial Interface Address h402
Reserved
10.6.4
SE_OPMODE - Search Engine Operation Mode
Serial Interface Address:h403
Accessed by CPU (R/W)
7
6
5
4
3
2
1
0
SL
DMS
DA
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
•
•
•
•
•
•
•
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Disable MCT speed-up aging (Default 0)
- 1 - Disable speed-up aging when MCT resource is low.
- 0 - Enable speed-up aging when MCT resource is low.
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Data Sheet
Bit [7]:
•
Slow Learning (Default 0)
- 1- Enable slow learning. Learning is temporary disabled when search demand is
high
- 0 - Learning is performed independent of search demand
10.6.5
SCAN - SCAN Control Register
Serial interface Address h404
Reserved
10.7
Group 5 Address - Buffer Control/QOS Group
10.7.1
FCBAT - FCB Aging Timer
I2C Address h03E; Serial Interface Address:h500
7
0
FCBAT
Bit [7:0]:
•
•
FCB Aging time. Unit of 1ms. (Default FF)
FCBAT define the aging time out interval of FCB handle
10.7.2
QOSC - QOS Control
I2C Address h03F; Serial Interface Address:h501
Accessed by serial interface and I2C (R/W)
7
0
Tos-d
Tos-p
VF1c
fb
Bit [0]:
Bit [4]:
•
•
QoS frame lost is OK. Priority will be available for flow control enabled
source only when this bit is set (Default 0)
Per VLAN (Port based) Multicast Flow Control (Default 0)
- 0 - Disable
- 1 - Enable
Bit [5]:
Bit [6]:
•
•
Reserved
Select TOS bits for Priority (Default 0)
- 0 - Use TOS [4:2] bits to map the transmit priority
- 1 - Use TOS [5:3] bits to map the transmit priority
Bit [7]:
•
select TOS bits for Drop (Default 0)
- 0 - Use TOS [4:2] bits to map the drop priority
- 1 - Use TOS [5:3] bits to map the drop priority
SEMICMF.019
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Data Sheet
MVTX2801AG
10.7.3
FCR - Flooding Control Register
I2C Address h040; Serial Interface Address:h502
Accessed by serial interface and I2C (R/W)
7
0
Tos
TimeBase
U2MR
Bit [3:0]:
Bit [6:4]:
•
•
U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits
[6:4]. This is used to limit the amount of flooding traffic. The value in U2MR
specifies how many packets are allowed to flood within the time specified by
bit [6:4]. To disable this function, program U2MR to 0.
(Default = 4'h8)
TimeBase: (Default = 000)
- 000 = 10us
- 001 = 20us
- 010 = 40us
- 011 = 80us
- 100 = 160us
- 101 = 320us
- 110 = 640us
- 111 = 10us, same as 000.
Bit [7]:
•
Select VLAN tag or TOS field (IP packets) to be preferentially picked to map
transmit priority and drop priority (Default = 0).
- 0 - Select VLAN tag priority field over TOS field
- 1 - Select TOS field over VLAN tag priority field
10.7.4
AVPML - VLAN Priority Map
I2C Address h041; Serial Interface Address:h503
Accessed by serial interface and I2C (R/W)
7
0
Registers AVPML, AVPMM, and AVPMH allow the eight VLAN priorities to map into eight internal level transmit
priorities. Under the internal transmit priority, “seven” is the highest priority where as “zero” is the lowest. This
feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7
into bit 2:0 of the AVPML register would map packet VLAN priority) into internal transmit priority 7. The new priority
is used only inside the 2801. When the packet goes out it carries the original priority.
Bit [2:0]:
Bit [5:3]:
Bit [7:6]:
•
•
•
Mapped priority of 0 (Default 000)
Mapped priority of 1 (Default 001)
Mapped priority of 2 (Default 10)
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Data Sheet
10.7.5
AVPMM - VLAN Priority Map
I2C Address h042, Serial Interface Address:h504
Accessed by serial interface and I2C (R/W)
7
0
Map VLAN priority into eight level transmit priorities:
Bit [0]:
•
•
•
•
Mapped priority of 2 (Default 0)
Mapped priority of 3 (Default 011)
Mapped priority of 4 (Default 100)
Mapped priority of 5 (Default 1)
Bit [3:1]:
Bit [6:4]:
Bit [7]:
10.7.6
AVPMH - VLAN Priority Map
I2C Address h043, Serial Interface Address:h505
Accessed by serial interface and I2C (R/W)
7
0
Map VLAN priority into eight level transmit priorities:
Bit [1:0]:
Bit [4:2]:
Bit [7:5]:
•
•
•
Mapped priority of 5 (Default 10)
Mapped priority of 6 (Default 110)
Mapped priority of 7 (Default 111)
10.7.7
TOSPML - TOS Priority Map
I2C Address h044, Serial Interface Address:h506
Accessed by serial interface and I2C (R/W)
7
0
Map TOS field in IP packet into four level transmit priorities
Bit [2:0]:
Bit [5:3]:
Bit [7:6]:
•
•
•
Mapped priority when TOS is 0 (Default 000)
Mapped priority when TOS is 1 (Default 001)
Mapped priority when TOS is 2 (Default 10)
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Data Sheet
MVTX2801AG
10.7.8
TOSPMM - TOS Priority Map
I2C Address h045, Serial Interface Address:h507
Accessed by serial interface and I2C (R/W)
7
0
Map TOS field in IP packet into four level transmit priorities
Bit [0]:
•
•
•
•
Mapped priority when TOS is 2 (Default 0)
Mapped priority when TOS is 3 (Default 011)
Mapped priority when TOS is 4 (Default 100)
Mapped priority when TOS is 5 (Default 1)
Bit [3:1]:
Bit [6:4]:
Bit [7]:
10.7.9
TOSPMH - TOS Priority Map
I2C Address h046, Serial Interface Address:h508
Accessed by serial interface and I2C (R/W)
7
0
Map TOS field in IP packet into four level transmit priorities:
Bit [1:0]:
Bit [4:2]:
Bit [7:5]:
•
•
•
Mapped priority when TOS is 5 (Default 01)
Mapped priority when TOS is 6 (Default 110)
Mapped priority when TOS is 7 (Default 111)
10.7.10
AVDM - VLAN Discard Map
I2C Address h047, Serial Interface Address:h509
Accessed by serial interface and I2C (R/W)
7
0
Map VLAN priority into frame discard when low priority buffer usage is above threshold. Frames with high discard
(drop) priority will be discarded (dropped) before frames with low drop priority.
- 0 - Low discard priority
- 1 - High discard priority
SEMICMF.019
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MVTX2801AG
Data Sheet
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
Frame discard priority for frames with VLAN transmit priority 0 (Default 0)
Frame discard priority for frames with VLAN transmit priority 1 (Default 0)
Frame discard priority for frames with VLAN transmit priority 2 (Default 0)
Frame discard priority for frames with VLAN transmit priority 3 (Default 0)
Frame discard priority for frames with VLAN transmit priority 4 (Default 0)
Frame discard priority for frames with VLAN transmit priority 5 (Default 0)
Frame discard priority for frames with VLAN transmit priority 6 (Default 0)
Frame discard priority for frames with VLAN transmit priority 7 (Default 0)
10.7.11
TOSDML - TOS Discard Map
I2C Address h048, Serial Interface Address:h50A
Accessed by serial interface and I2C (R/W)
7
0
Map TOS into frame discard when low priority buffer usage is above threshold
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
Frame discard priority for frames with TOS transmit priority 0 (Default 0)
Frame discard priority for frames with TOS transmit priority 1 (Default 0)
Frame discard priority for frames with TOS transmit priority 2 (Default 0)
Frame discard priority for frames with TOS transmit priority 3 (Default 0)
Frame discard priority for frames with TOS transmit priority 4 (Default 0)
Frame discard priority for frames with TOS transmit priority 5 (Default 0)
Frame discard priority for frames with TOS transmit priority 6 (Default 0)
Frame discard priority for frames with TOS transmit priority 7 (Default 0)
10.7.12
BMRC - Broadcast/Multicast Rate Control
I2C Address h049, Serial Interface Address:h50B
Accessed by serial interface and I2C (R/W)
7
0
Broadcast Rate
Multicast Rate
This broadcast and multicast rate defines for each port the number of incoming packet allowed to be forwarded
within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program
the field to 0.
SEMICMF.019
62
Data Sheet
MVTX2801AG
Bit [3:0]:
•
•
Multicast Rate Control Number of multicast packets allowed within the time
defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0).
Bit [7:4]:
Broadcast Rate Control Number of broadcast packets allowed within the time
defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0)
10.7.13
UCC - Unicast Congestion Control
I2C Address h04A, Serial Interface Address:h50C
Accessed by serial interface and I2C (R/W)
7
0
Unicast congest threshold
Bit [7:0]:
•
Number of frame count. Used for best effort dropping at B% when
destination port's best effort queue reaches UCC threshold and shared pool
is all in use. Granularity 16 frame. (Default: h07)
10.7.14
MCC - Multicast Congestion Control
I2C Address h0B7, Serial Interface Address:h50D
Accessed by serial interface and I2C (R/W)
7
0
FC reaction prd
Multicast congest threshold
Bit [3:0]:
•
In multiples of two. Used for triggering MC flow control when destination
port's best effort queue reaches MCC threshold. (Default 5'h08)
Bit [4]:
•
•
Must be 0
Bit [7:5]:
Flow control reaction period. ([7:5] 4)+3 usec (Default 3'h2).
SEMICMF.019
63
MVTX2801AG
Data Sheet
10.7.15
PRG - Port Reservation for Giga ports
I2C Address h0B9, Serial Interface Address:h50F
Accessed by serial interface and I2C (R/W)
7
0
Buffer low thd
Per source buffer Reservation
Bit [3:0]:
•
Per source buffer reservation. Define the space in the FDB reserved for
each port. Expressed in multiples of 16 packets. For each packet 1536
bytes are reserved in the memory.
Default: 4'hA for 4MB memory
4'h6 for 2MB memory
4'h3 for 1MB memory
Bits [7:4]:
•
Expressed in multiples of 16 packets. Threshold for dropping all best effort
frames when destination port best effort queues reach UCC threshold and
shared pool is all used and source port reservation is at or below the
PRG[7:4] level. Also the threshold for initiating UC flow control.
Default: 4'h6 for 4MB memory
4'h2 for 2MB memory
4'h1 for 1MB memory
FCB Reservation
10.7.16
SFCB - Share FCB Size
I2C Address h04E), Serial Interface Address:h510
Accessed by serial interface and I2C (R/W)
7
0
Shared buffer size
Bits [7:0]:
•
Expressed in multiples of 8. Buffer reservation for shared pool.
- (Default 4G & 4M = 8'd62)
- (Default 4G & 2M = 8'd20)
- (Default 4G & 1M = 8'd08)
- (Default 8G & 4M = 8'd150)
- (Default 8G & 2M = 8'd55)
- (Default 8G & 1M = 8'd25)
SEMICMF.019
64
Data Sheet
MVTX2801AG
10.7.17
C2RS - Class 2 Reserved Size
I2C Address h04F, Serial Interface Address:h511
Accessed by serial interface and I2C (R/W)
7
0
Class 2 FCB Reservation
Bits [7:0]:
•
Buffer reservation for class 2 (third lowest priority). Granularity 2.
(Default 8'h00)
10.7.18
C3RS - Class 3 Reserved Size
I2C Address h050, Serial Interface Address:h512
Accessed by serial interface and I2C (R/W)
7
0
Class 3 FCB Reservation
Bits [7:0]:
•
Buffer reservation for class 3. Granularity 2. (Default 8'h00)
10.7.19 C4RS - Class 4 Reserved Size
I2C Address h051, Serial Interface Address:h513
Accessed by serial interface and I2C (R/W)
7
0
Class 4 FCB Reservation
Bits [7:0]:
•
Buffer reservation for class 4. Granularity 2. (Default 8'h00)
10.7.20 C5RS - Class 5 Reserved Size
I2C Address h052; Serial Interface Address:h514
Accessed by serial interface and I2C (R/W)
7
0
Class 5 FCB Reservation
Bits [7:0]:
•
Buffer reservation for class 5. Granularity 2. (Default 8'h00)
SEMICMF.019
65
MVTX2801AG
Data Sheet
10.7.21
C6RS - Class 6 Reserved Size
I2C Address h053; Serial Interface Address:h515
Accessed by serial interface and I2C (R/W)
7
0
Class 6 FCB Reservation
Bits [7:0]:
•
Buffer reservation for class 6 (second highest priority). Granularity 2.
(Default 8'h00)
10.7.22
C7RS - Class 7 Reserved Size
I2C Address h054; Serial Interface Address:h516
Accessed by serial interface and I2C (R/W)‘
7
0
Class 7 FCB Reservation
Bits [7:0]:
•
Buffer reservation for class 7 (highest priority). Granularity 2.
(Default 8'h00)
Classes Byte Gigabit Port 0
10.7.23
QOSC00 - BYTE_C2_G0
I2C Address h055, Serial Interface Address:h517
Bits [7:0]:
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
10.7.24
QOSC01 - BYTE_C3_G0
I2C Address h056, Serial Interface Address:h518
Bits [7:0]:
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
SEMICMF.019
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Data Sheet
MVTX2801AG
10.7.25
QOSC02 - BYTE_C4_G0
I2C Address h057, Serial Interface Address:h519
Bits [7:0]:
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
10.7.26
QOSC03 - BYTE_C5_G0
I2C Address h058, Serial Interface Address:h51A
Bits [7:0]:
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
10.7.27
QOSC04 - BYTE_C6_G0
I2C Address h059, Serial Interface Address:h51B
Bits [7:0]:
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
10.7.28
QOSC05 - BYTE_C7_G0
I2C Address h05A, Serial Interface Address:h51C
Bits [7:0]:
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
QOSC00 through QOSC05 represent the values F-A in Table 3 for Gigabit port 0. They are per-queue byte
thresholds for weighted random early drop (WRED). QOSC05 represents A, and QOSC00 represents F.
Classes Byte Gigabit Port 1
10.7.29
QOSC06 - BYTE_C2_G1
I2C Address h05B, Serial Interface Address:h51D
Bits [7:0]:
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
SEMICMF.019
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MVTX2801AG
Data Sheet
10.7.30
QOSC07 - BYTE_C3_G1
I2C Address h05C, Serial Interface Address:h51E
Bits [7:0]
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.31
QOSC08 - BYTE_C4_G1
I2C Address h05D, Serial Interface Address:h51F
Bits [7:0]:
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024byte/unit when WFQ is used)
10.7.32
QOSC09 - BYTE_C5_G1
I2C Address h05E, Serial Interface Address:h520
Bits [7:0]:
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.33
QOSC0A - BYTE_C6_G1
I2C Address h05F, Serial Interface Address:h521
Bits [7:0]:
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.34
QOSC0B - BYTE_C7_G1
I2C Address h060, Serial Interface Address:h522
Bits [7:0]:
•
Byte count threshold for C7 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC06 through QOSC0B represent the values F-A in Table 3. They are per-queue byte thresholds for random
early drop. QOSC0B represents A, and QOSC06 represents F.
SEMICMF.019
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Data Sheet
MVTX2801AG
Classes Byte Gigabit Port 2
10.7.35
QOSC0C - BYTE_C2_G2
I2C Address h061, Serial Interface Address:h523
Bits [7:0]:
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.36
QOSC0D - BYTE_C3_G2
I2C Address h062, Serial Interface Address:h524
Bits [7:0]:
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.37
QOSC0E - BYTE_C4_G2
I2C Address h063, Serial Interface Address:h525
Bits [7:0]:
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.38
QOSC0F - BYTE_C5_G2
I2C Address h064, Serial Interface Address:h526
Bits [7:0]:
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.39
QOSC10 - BYTE_C6_G2
I2C Address h065, Serial Interface Address:h527
Bits [7:0]:
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
SEMICMF.019
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MVTX2801AG
Data Sheet
10.7.40
QOSC11 - BYTE_C7_G2
I2C Address h066, Serial Interface Address:h528
Bits [7:0]:
•
Byte count threshold for C7 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC0C through QOSC11 represent the values F-A in Table 3 for Gigabit port 2. They are per-queue byte
thresholds for random early drop. QOSC11 represents A, and QOSC0C represents F.
Classes Byte Gigabit Port 3
10.7.41
QOSC12 - BYTE_C2_G3
I2C Address h067, Serial Interface Address:h529
Bits [7:0]:
•
Byte count threshold for C2 queue WRED (Default 8'h28)
(1024 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.42
QOSC13 - BYTE_C3_G3
I2C Address h068, Serial Interface Address:h52A
Bits [7:0]:
•
Byte count threshold for C3 queue WRED (Default 8'h28)
(512 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.43
QOSC14 - BYTE_C4_G3
I2C Address h069, Serial Interface Address:h52B
Bits [7:0]:
•
Byte count threshold for C4 queue WRED (Default 8'h28)
(256 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.44
QOSC15 - BYTE_C5_G3
I2C Address h06A, Serial Interface Address:h52C
Bits [7:0]:
•
Byte count threshold for C5 queue WRED (Default 8'h28)
(128 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
10.7.45
QOSC16 - BYTE_C6_G3
I2C Address h06B, Serial Interface Address:h52D
Bits [7:0]:
•
Byte count threshold for C6 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
SEMICMF.019
70
Data Sheet
MVTX2801AG
10.7.46
QOSC17 - BYTE_C7_G3
I2C Address h06C, Serial Interface Address:h52E
Bits [7:0]:
•
Byte count threshold for C7 queue WRED (Default 8'h50)
(64 byte/unit when Delay Bound is used)
(1024 byte/unit when WFQ is used)
QOSC12 through QOSC17 represent the values F-A in Table 3 for Gigabit port 3. They are per-queue byte
thresholds for random early drop. QOSC17 represents A, and QOSC12 represents F.
Classes Byte Gigabit Port 4 (Useless in MVTX2801)
10.7.47
QOSC18 - BYTE_C2_G4
I2C Address h06D, Serial Interface Address:h52F
Bits [7:0]:
•
Reserved
10.7.48
QOSC019 - BYTE_C3_G4
I2C Address h06E, Serial Interface Address:h530
Bits [7:0]:
•
Reserved
10.7.49
QOSC1A - BYTE_C4_G4
I2C Address h06F, Serial Interface Address:h531
Bits [7:0]:
•
Reserved
10.7.50
QOSC1B - BYTE_C5_G4
I2C Address h070, Serial Interface Address:h532
Bits [7:0]:
•
Reserved
10.7.51
QOSC1C - BYTE_C6_G4
I2C Address h071, Serial Interface Address:h533
Bits [7:0]:
•
Reserved
SEMICMF.019
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MVTX2801AG
Data Sheet
10.7.52
QOSC1D- BYTE_C7_G4
I2C Address h072, Serial Interface Address:h534
Bits [7:0]:
•
Reserved
QOSC18 through QOSC1D are useless in MVTX2801.
Classes Byte Gigabit Port 5 (useless in MVTX2801)
10.7.53
QOSC1E- BYTE_C2_G5
I2C Address h073, Serial Interface Address:h535
Bits [7:0]:
•
Reserved
10.7.54
QOSC1F - BYTE_C3_G5
I2C Address h074, Serial Interface Address:h536
Bits [7:0]:
•
Reserved
10.7.55
QOSC20 - BYTE_C4_G5
I2C Address h075, Serial Interface Address:h537
Bits [7:0]:
•
Reserved
10.7.56
QOSC21 - BYTE_C5_G5
I2C Address h076, Serial Interface Address:h538
Bits [7:0]:
•
Reserved
10.7.57
QOSC22 - BYTE_C6_G5
I2C Address h077, Serial Interface Address:h539
Bits [7:0]:
•
Reserved
10.7.58
QOSC23 - BYTE_C7_G5
I2C Address h078, Serial Interface Address:h53A
Bits [7:0]:
•
Reserved
QOSC1E through QOSC23 are useless in MVTX2801.
SEMICMF.019
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Data Sheet
MVTX2801AG
Classes Byte Gigabit Port 6 (useless in MVTX2801)
10.7.59
QOSC24 - BYTE_C2_G6
I2C Address h079, Serial Interface Address:h53B
Bits [7:0]:
•
Reserved
10.7.60
QOSC25 - BYTE_C3_G6
I2C Address h07A, Serial Interface Address:h53C
Bits [7:0]:
•
Reserved
10.7.61
QOSC26 - BYTE_C4_G6
I2C Address h07B, Serial Interface Address:h53D
Bits [7:0]:
•
Reserved
10.7.62
QOSC27 - BYTE_C5_G6
I2C Address h07C, Serial Interface Address:h53E
Bits [7:0]:
•
Reserved
10.7.63
QOSC28 - BYTE_C6_G6
I2C Address h07D, Serial Interface Address:h53F
Bits [7:0]:
•
Reserved
10.7.64
QOSC29 - BYTE_C7_G6
I2C Address h07E, Serial Interface Address:h540
Bits [7:0]:
•
Reserved
QOSC24 through QOSC29 are useless in MVTX2801.
Classes Byte Gigabit Port 7 (useless in MVTX2801)
10.7.65
QOSC2A - BYTE_C2_G7
I2C Address h07F, Serial Interface Address:h541
Bits [7:0]:
•
Reserved
10.7.66
QOSC2B - BYTE_C3_G7
I2C Address h080, Serial Interface Address:h542
Bits [7:0]:
•
Reserved
SEMICMF.019
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MVTX2801AG
Data Sheet
10.7.67
QOSC2C - BYTE_C4_G7
I2C Address h081, Serial Interface Address:h543
Bits [7:0]:
•
Reserved
10.7.68
QOSC2D - BYTE_C5_G7
I2C Address h082, Serial Interface Address:h544
Bits [7:0]:
•
Reserved
10.7.69
QOSC2E - BYTE_C6_G7
I2C Address h083, Serial Interface Address:h545
Bits [7:0]:
•
Reserved
10.7.70
QOSC2F - BYTE_C7_G7
I2C Address h084, Serial Interface Address:h546
Bits [7:0]:
•
Reserved
QOSC00 through QOSC05 are useless in MVTX2801.
Classes Byte Limit CPU
10.7.71
QOSC30 - BYTE_C01
Serial Interface Address:h547
Bits [7:0]:
•
Reserved
10.7.72
QOSC31 - BYTE_C02
Serial Interface Address:h548
Bits [7:0]:
•
Reserved
SEMICMF.019
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Data Sheet
MVTX2801AG
10.7.73
QOSC32 - BYTE_C03
Serial Interface Address:h549
Bits [7:0]:
•
Reserved
Classes WFQ Credit Set 0
10.7.74
QOSC33 - CREDIT_C0_G0
Serial Interface Address:h54A
Bits [5:0]:
Bits [7:6]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Priority type. Define one of the four QoS mode of operation for port 0 (Default 2'00)
- 00: Option 1
- 01: Option 2
- 10: Option 3
- 11: Option 4
See table below:
Queue P7
P6
P5
P4
P3
P2
P1
BE
BE
P0
Option 1 Bit [7:6] = 2'B00 DELAY BOUND
Option 2 Bit [7:6] = 2'B01
Option 3 Bit [7:6] = 2'B10
Option 4 Bit [7:6] = 2'B11
Credit for WFQ - Bit [5:0]
SP
DELAY BOUND
WFQ
SP
WFQ
W7
W6
W5
W4
W3
W2
W1
W0
10.7.75
QOSC34 - CREDIT_C1_G0
Serial Interface Address:h54B
Bits [7]:
Bits [6]:
•
•
•
Flow control allow during WFQ scheme. (Default 1'b1)
0 = Not support QoS when the Source port Flow control status is on.
1= Always support QoS)
Flow control BE Queue only. (Default 1'b1)
0= DO NOT send any frames if the XOFF is on.
1= the P7-P2 frames can be sent even the XOFF is ON
Bits [5:0]
Fc_allow
W1 - Credit register. (Default 4'h04)
Fc_be_only
Lost_ok
Egress- for dest fc_status Ingress- for src fc status
0
0
0
Go to BE Queue if (Src FC or Des FC on)
otherwise Normal
0
0
1
Go to BE Queue if (Dest FC on) otherwise
Normal
SEMICMF.019
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MVTX2801AG
Data Sheet
1
0
0
(WFQ only) Go to BE Queue if (Src FC on)
otherwise BAD
1
0
1
1
1
0
1
(WFQ only) Always Normal
Go to BE Queue if (Src FC on)
Always Normal
X
X
10.7.76
QOSC35 - CREDIT_C2_G0
Serial Interface Address:h54C
Bits [5:0]
Bits [7:6]:
•
•
W2 - Credit register. (Default 4'h04)
Reserved
10.7.77
QOSC36 - CREDIT_C3_G0
Serial Interface Address:h54D
Bits [5:0]
Bits [7:6]:
•
•
W3 - Credit register. (Default 4'h04)
Reserved
10.7.78
QOSC37 - CREDIT_C4_G0
Serial Interface Address:h54E
Bits [5:0]
Bits [7:6]:
•
•
W4 - Credit register. (Default 4'h04)
Reserved
10.7.79
QOSC38 - CREDIT_C5_G0
Serial Interface Address:h54F
Bits [5:0]
Bits [7:6]:
•
•
W5 - Credit register. (Default 5'h8)
Reserved
10.7.80
QOSC39- CREDIT_C6_G0
Serial Interface Address:h550
Bits [5:0]
Bits [7:6]:
•
•
W6 - Credit register. (Default 5'h8)
Reserved
SEMICMF.019
76
Data Sheet
MVTX2801AG
10.7.81
QOSC3A- CREDIT_C7_G0
Serial Interface Address:h551
Bits [5:0]
Bits [7:6]:
•
•
W7 - Credit register. (Default 5'h10)
Reserved
QOSC33 through QOSC3Arepresents the set of WFQ parameters (see section 7.5) for Gigabit port 0. The
granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC33 corresponds to W0, and QOSC3A
corresponds to W7.
Classes WFQ Credit Port G1
10.7.82
QOSC3B - CREDIT_C0_G1
Serial Interface Address:h552
Bits [5:0]:
Bits [7:6]:
•
W0 - Credit register for WFQ. (Default 6'h04)
Priority type. Define one of the four QoS mode of operation for port 1 (Default 2'00)
- 00: Option 1
- 01: Option 2
- 10: Option 3
- 11: Option 4
See table below:
Queue P7
P6
P5
P4
P3
P2
P1
BE
BE
P0
Option 1 Bit [7:6] = 2'B00 DELAY BOUND
Option 2 Bit [7:6] = 2'B01 SP
Option 3 Bit [7:6] = 2'B10 SP
Option 4 Bit [7:6] = 2'B11 WFQ
DELAY BOUND
WFQ
Credit for WFQ - Bit [5:0]
W7
W6
W5
W4
W3
W2
W1
W0
10.7.83
QOSC3C - CREDIT_C1_G1
Serial Interface Address:h54B
Bits [7]:
Bits [6]:
Bits [5:0]
•
•
•
Flow control allow during WFQ scheme. (Default 1'b1)
0 = Not support QoS when the Source port Flow control status is on.
1= Always support QoS)
Flow control BE Queue only. (Default 1'b1)
0= DO NOT send any frames if the XOFF is on.
1= the P7-P2 frames can be sent even the XOFF is ON
W1 - Credit register. (Default 4'h04)
SEMICMF.019
77
MVTX2801AG
Data Sheet
Fc_allow
Fc_be_only
Lost_ok
Egress- for dest fc_status Ingress- for src
fc status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise
Normal
0
1
0
0
1
0
Go to BE Queue if (Dest FC on) otherwise Normal
(WFQ only) Go to BE Queue if (Src FC on) otherwise
BAD
1
X
X
0
1
1
1
0
1
(WFQ only) Always Normal
Go to BE Queue if (Src FC on)
Always Normal
10.7.84
QOSC3D - CREDIT_C2_G1
Serial Interface Address:h553
Bits [5:0]
Bits [7:6]:
•
•
W2 - Credit register. (Default 4'h04)
Reserved
10.7.85
QOSC3E - CREDIT_C3_G1
Serial Interface Address:h554
Bits [5:0]
Bits [7:6]:
•
•
W3 - Credit register. (Default 4'h04)
Reserved
10.7.86
QOSC3F - CREDIT_C4_G1
Serial Interface Address:h555
Bits [5:0]
Bits [7:6]:
•
•
W4 - Credit register. (Default 4'h04)
Reserved
10.7.87
QOSC40 - CREDIT_C5_G1
Serial Interface Address:h556
Bits [5:0]
Bits [7:6]:
•
•
W5 - Credit register. (Default 5'h8)
Reserved
10.7.88
QOSC41- CREDIT_C6_G1
Serial Interface Address:h557
Bits [5:0]
Bits [7:6]:
•
•
W6 - Credit register. (Default 5'h8)
Reserved
SEMICMF.019
78
Data Sheet
MVTX2801AG
10.7.89
QOSC42- CREDIT_C7_G1
Serial Interface Address:h558
Bits [5:0]
Bits [7:6]:
•
•
W7 - Credit register. (Default 5'h10)
Reserved
QOSC3B through QOSC42 represents the set of WFQ parameters (see section 7.5) for Gigabit port 1. The
granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC3B corresponds to W0, and QOSC42
corresponds to W7.
Classes WFQ Credit Port G2
10.7.90
QOSC43 - CREDIT_C0_G2
Serial Interface Address:h55A
Bits [5:0]:
Bits [7:6]:
•
•
W0 - Credit register for WFQ. (Default 6'h04)
Priority type. Define one of the four QoS mode of operation for port 2 (Default 2'00)
- 00: Option 1
- 01: Option 2
- 10: Option 3
- 11: Option 4
See table below:
Queue P7
P6
P5
P4
P3
P2
P1
BE
BE
P0
Option 1 Bit [7:6] = 2'B00
Option 2 Bit [7:6] = 2'B01
Option 3 Bit [7:6] = 2'B10
Option 4 Bit [7:6] = 2'B11
Credit for WFQ - Bit [5:0]
DELAY BOUND
SP
DELAY BOUND
WFQ
SP
WFQ
W7
W6
W5
W4
W3
W2
W1
W0
10.7.91
QOSC44 - CREDIT_C1_G2
Serial Interface Address:h55B
Bits [7]:
Bits [6]:
Bits [5:0]
•
•
•
Flow control allow during WFQ scheme. (Default 1'b1)
0 = Not support QoS when the Source port Flow control status is on.
1= Always support QoS)
Flow control BE Queue only. (Default 1'b1)
0= DO NOT send any frames if the XOFF is on.
1= the P7-P2 frames can be sent even the XOFF is ON
W1 - Credit register. (Default 4'h04)
SEMICMF.019
79
MVTX2801AG
Data Sheet
Fc_allow
Fc_be_only
Lost_ok
Egress- for dest fc_status Ingress- for src
fc status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise
Normal
0
1
0
0
1
0
Go to BE Queue if (Dest FC on) otherwise Normal
(WFQ only) Go to BE Queue if (Src FC on) otherwise
BAD
x
0
1
(WFQ only)
Always Normal
X
X
1
1
0
1
Go to BE Queue if (Src FC on)
Always Normal
10.7.92
QOSC45 - CREDIT_C2_G2
Serial Interface Address:h55C
Bits [5:0]
Bits [7:6]:
•
•
W2 - Credit register. (Default 4'h04)
Reserved
10.7.93
QOSC46 - CREDIT_C3_G2
Serial Interface Address:h55D
Bits [5:0]
Bits [7:6]:
•
•
W3 - Credit register. (Default 4'h04)
Reserved
10.7.94
QOSC47 - CREDIT_C4_G2
Serial Interface Address:h55E
Bits [5:0]
Bits [7:6]:
•
•
W4 - Credit register. (Default 4'h04)
Reserved
10.7.95
QOSC48 - CREDIT_C5_G2
Serial Interface Address:h55F
Bits [5:0]
Bits [7:6]:
•
•
W5 - Credit register. (Default 5'h8)
Reserved
10.7.96
QOSC49- CREDIT_C6_G2
Serial Interface Address:h560
Bits [5:0]
Bits [7:6]:
•
•
W6 - Credit register. (Default 5'h8)
Reserved
SEMICMF.019
80
Data Sheet
MVTX2801AG
10.7.97
QOSC4A- CREDIT_C7_G2
Serial Interface Address:h561
Bits [5:0]
Bits [7:6]:
•
•
W7 - Credit register. (Default 5'h10)
Reserved
QOSC43 through QOSC4Arepresents the set of WFQ parameters (see section 7.5) for Gigabit port 2. The
granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC43 corresponds to W0, and QOSC4A
corresponds to W7.
Classes WFQ Credit Port G3
10.7.98
QOSC4B - CREDIT_C0_G3
Serial Interface Address:h562
Bits [5:0]:
Bits [7:6]:
•
•
W0 - Credit register for WFQ. (Default 6'h04)
Priority type. Define one of the four QoS mode of operation for port 3
(Default 2'00)
- 00: Option 1
- 01: Option 2
- 10: Option 3
- 11: Option 4
See table below:
Queue P7 P6 P5 P4 P3 P2 P1 P0
Option 1 Bit [7:6] = 2'B00
Option 2 Bit [7:6] = 2'B01
Option 3 Bit [7:6] = 2'B10
Option 4 Bit [7:6] = 2'B11
Credit for WFQ - Bit [5:0]
DELAY BOUND
BE
BE
SP
DELAY BOUND
WFQ
SP
WFQ
W7 W6 W5 W4 W3 W2 W1 W0
10.7.99
QOSC4 - CREDIT_C1_G3
Serial Interface Address:h563
Bits [7]:
Bits [6]:
Bits [5:0]
•
•
•
Flow control allow during WFQ scheme. (Default 1'b1)
0 = Not support QoS when the Source port Flow control status is on.
1= Always support QoS)
Flow control BE Queue only. (Default 1'b1)
(0= DO NOT send any frames if the XOFF is on.
(1= the P7-P2 frames can be sent even the XOFF is ON)
W1 - Credit register. (Default 4'h04)
SEMICMF.019
81
MVTX2801AG
Data Sheet
Fc_allow
Fc_be_only
Lost_ok
Egress- for dest fc_status Ingress- for
src fc status
0
0
0
Go to BE Queue if (Src FC or Des FC on) otherwise
Normal
0
1
0
0
1
0
Go to BE Queue if (Dest FC on) otherwise Normal
(WFQ only) Go to BE Queue if (Src FC on) otherwise
BAD
1
0
1
1
0
(WFQ only) Always Normal
Go to BE Queue if (Src FC on)
Always Normal
X
X
1
1
10.7.100
QOSC4D - CREDIT_C2_G3
Serial Interface Address:h564
Bits [5:0]
Bits [7:6]:
•
•
W2 - Credit register. (Default 4'h04)
Reserved
10.7.101
QOSC4E - CREDIT_C3_G3
Serial Interface Address:h565
Bits [5:0]
Bits [7:6]:
•
•
W3 - Credit register. (Default 4'h04)
Reserved
10.7.102
QOSC4F - CREDIT_C4_G3
Serial Interface Address:h566
Bits [5:0]
Bits [7:6]:
•
•
W4 - Credit register. (Default 4'h04)
Reserved
10.7.103
QOSC50 - CREDIT_C5_G3
Serial Interface Address:h567
Bits [5:0]
Bits [7:6]:
•
•
W5 - Credit register. (Default 5'h8)
Reserved
10.7.104
QOSC51- CREDIT_C6_G3
Serial Interface Address:h568
Bits [5:0]
Bits [7:6]:
•
•
W6 - Credit register. (Default 5'h8)
Reserved
SEMICMF.019
82
Data Sheet
MVTX2801AG
10.7.105
QOSC52- CREDIT_C7_G3
Serial Interface Address:h569
Bits [5:0]
Bits [7:6]:
•
•
W7 - Credit register. (Default 5'h10)
Reserved
QOSC4B through QOSC52 represents the set of WFQ parameters (see section 7.5) for Gigabit port 3. The
granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC4B corresponds to W0, and QOSC52
corresponds to W7.
Classes WFQ Credit Port G4 (useless in MVTX2801)
10.7.106
QOSC53 - CREDIT_C0_G4
Serial Interface Address:h56A
Bits [7:0]:
•
Reserved
10.7.107
QOSC54 - CREDIT_C1_G4
Serial Interface Address:h56B
Bits [7:0]:
•
Reserved
10.7.108
QOSC55 - CREDIT_C2_G4
Serial Interface Address:h56C
Bits [7:0]
•
Reserved
10.7.109
QOSC56 - CREDIT_C3_G4
Serial Interface Address:h56D
Bits [7:0]
•
Reserved
10.7.110
QOSC57 - CREDIT_C4_G4
Serial Interface Address:h56E
Bits [7:0]
•
Reserved
10.7.111
QOSC58 - CREDIT_C5_G4
Serial Interface Address:h56F
Bits [7:0]
•
Reserved
10.7.112
QOSC59- CREDIT_C6_G4
Serial Interface Address:h570
Bits [7:0]
•
Reserved
SEMICMF.019
83
MVTX2801AG
Data Sheet
10.7.113
QOSC5A- CREDIT_C7_G4
Serial Interface Address:h571
Bits [7:0]
•
Reserved
QOSC53 through QOSC5A are useless in MVTX2801.
Classes WFQ Credit Port G5 (useless in MVTX2801)
10.7.114
QOSC5B - CREDIT_C0_G5
Serial Interface Address:h572
Bits [7:0]:
•
Reserved
10.7.115
QOSC5C - CREDIT_C1_G5
Serial Interface Address:h573
Bits [7:0]:
•
Reserved
10.7.116
QOSC5D - CREDIT_C2_G5
Serial Interface Address:h574
Bits [7:0]
•
Reserved
10.7.117
QOSC5E - CREDIT_C3_G5
Serial Interface Address:h575
Bits [7:0]
•
Reserve
10.7.118
QOSC5F - CREDIT_C4_G5
Serial Interface Address:h576
Bits [7:0]
•
Reserved
10.7.119
QOSC60 - CREDIT_C5_G5
Serial Interface Address:h577
Bits [7:0]
•
Reserved
10.7.120
QOSC61- CREDIT_C6_G5
Serial Interface Address:h578
Bits [7:0]
•
Reserved
SEMICMF.019
84
Data Sheet
MVTX2801AG
10.7.121
QOSC62- CREDIT_C7_G5
Serial Interface Address:h579
Bits [7:0] Reserved
•
QOSC5B through QOSC62 are useless.
Classes WFQ Credit Port G6 (useless in MVTX2801)
10.7.122
QOSC63 - CREDIT_C0_G6
Serial Interface Address:h57A
Bits [7:0]:
•
Reserved
10.7.123
QOSC64 - CREDIT_C1_G6
Serial Interface Address:h57B
Bits [7:0]:
•
Reserved
10.7.124
QOSC65 - CREDIT_C2_G6
Serial Interface Address:h57C
Bits [7:0]
•
Reserved
10.7.125
QOSC66 - CREDIT_C3_G6
Serial Interface Address:h57D
Bits [7:0]
•
Reserved
10.7.126
QOSC67 - CREDIT_C4_G6
Serial Interface Address:h57E
Bits [7:0]
•
Reserved
10.7.127
QOSC68 - CREDIT_C5_G6
Serial Interface Address:h57F
Bits [7:0]
•
Reserved
10.7.128
QOSC69- CREDIT_C6_G6
Serial Interface Address:h580
Bits [7:0]
•
Reserved
SEMICMF.019
85
MVTX2801AG
Data Sheet
10.7.129
QOSC6A- CREDIT_C7_G6
Serial Interface Address:h581
Bits [7:0]
•
Reserved
QOSC63 through QOSC6A are useless in MVTX2801
Classes WFQ Credit Port G7 (useless in MVTX2801)
10.7.130
QOSC6B - CREDIT_C0_G7
Serial Interface Address:h582
Bits [7:0]:
•
Reserved
10.7.131
QOSC6C - CREDIT_C1_G7
Serial Interface Address:h583
Bits [7:0]:
•
Reserved
10.7.132
QOSC6D - CREDIT_C2_G7
Serial Interface Address:h584
Bits [7:0]
•
Reserved
10.7.133
QOSC6E - CREDIT_C3_G7
Serial Interface Address:h585
Bits [7:0]
•
Reserved
10.7.134
QOSC6F - CREDIT_C4_G7
Serial Interface Address:h586
Bits [7:0]
•
Reserved
10.7.135
QOSC70 - CREDIT_C5_G7
Serial Interface Address:h587
Bits [7:0]
•
Reserved
10.7.136
QOSC71- CREDIT_C6_G7
Serial Interface Address:h588
Bits [7:0]
•
Reserved
SEMICMF.019
86
Data Sheet
MVTX2801AG
10.7.137
QOSC72- CREDIT_C7_G7
Serial Interface Address:h589
Bits [5:0]
•
Reserved
QOSC6B through QOSC72 are useless in MVTX2801
Class 6 Shaper Control Port G0
10.7.138
QOSC73 - TOKEN_RATE_G0
Serial Interface Address:h58A
Bits [7:0]
•
Bytes allow to transmit every frame time (0.512usec) when regulated by
Shaper logic. (Default: 8'h08)
10.7.139
QOSC74 - TOKEN_LIMIT_G0
Serial Interface Address:h58B
Bits [7:0]
•
Bytes allow to continue transmit out when regulated by Shaper logic.
(16byte/unit) (Default: 8'hC0)
QOSC73 and QOSC74 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC73 is an
integer less than 64, with granularity 1. QOSC74 is the programmed maximum value of the counter (maximum burst
size). This value is expressed in multiples of 16. QOSC73 and QOSC74 apply to Gigabit port 0. Register
QOSC39-CREDIT_C6_G0 programs the peak rate. See QoS application note for more information.
Class 6 Shaper Control Port G1
10.7.140
QOSC75 - TOKEN_RATE_G1
Serial Interface Address:h58C
Bits [7:0]
•
Bytes allow to transmit every frame time (0.512usec) when regulated by
Shaper logic. (Default: 8'h08)
10.7.141
QOSC76 - TOKEN_LIMIT_G1
Serial Interface Address:h58D
Bits [7:0]
•
Bytes allow to continue transmit out when regulated by Shaper logic.
(16byte/unit) (Default: 8'hC0)
QOSC75 and QOSC76 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC75 is an
integer less than 64, with granularity 1. QOSC76 is the programmed maximum value of the counter (maximum burst
size). This value is expressed in multiples of 16. QOSC75 and QOSC76 apply to Gigabit port 1. Register
QOSC41-CREDIT_C6_G1 programs the peak rate. See QoS application note for more information.
SEMICMF.019
87
MVTX2801AG
Data Sheet
Class 6 Shaper Control Port G2
10.7.142
QOSC77 - TOKEN_RATE_G2
Serial Interface Address:h58E
Bits [7:0]
•
Bytes allow to transmit every frame time (0.512usec) when regulated by
Shaper logic. (Default: 8'h08)
10.7.143
QOSC78 - TOKEN_LIMIT_G2
Serial Interface Address:h58F
Bits [7:0]
•
Bytes allow to continue transmit out when regulated by Shaper logic.
(16byte/unit) (Default: 8'hC0)
QOSC77 and QOSC78 correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC77 is an
integer less than 64, with granularity 1. QOSC78 is the programmed maximum value of the counter (maximum burst
size). This value is expressed in multiples of 16. QOSC77 and QOSC78 apply to Gigabit port 2. Register
QOSC49-CREDIT_C6_G2 programs the peak rate. See QoS application note for more information.
Class 6 Shaper Control Port G3
10.7.144
QOSC79 - TOKEN_RATE_G3
Serial Interface Address:h590
Bits [7:0]
•
Bytes allow to transmit every frame time (0.512usec) when regulated by
Shaper logic. (Default: 8'h08)
10.7.145
QOSC7A - TOKEN_LIMIT_G3
Serial Interface Address:h591
Bits [7:0]
•
Bytes allow to continue transmit out when regulated by Shaper logic.
(16byte/unit) (Default: 8'hC0)
QOSC79 and QOSC7A correspond to parameters from section 7.6 on the shaper for EF traffic. QOSC79 is an
integer less than 64, with granularity 1. QOSC7A is the programmed maximum value of the counter (maximum burst
size). This value is expressed in multiples of 16. QOSC79 and QOSC7A apply to Gigabit port 3. Register
QOSC51-CREDIT_C6_G3 programs the peak rate. See QoS application note for more information.
Class 6 Shaper Control Port G4 (useless in MVTX2801)
10.7.146
QOSC7B - TOKEN_RATE_G4
Serial Interface Address:h592
Bits [7:0]
•
Reserved
SEMICMF.019
88
Data Sheet
MVTX2801AG
10.7.147
QOSC7C - TOKEN_LIMIT_G4
Serial Interface Address:h593
Bits [7:0]
•
Reserved
QOSC7B and QOSC7C are useless in MVTX2801
Class 6 Shaper Control Port G5 (useless in MVTX2801)
10.7.148
QOSC7D - TOKEN_RATE_G5
Serial Interface Address:h594
Bits [7:0]
•
Reserved
10.7.149
QOSC7E - TOKEN_LIMIT_G5
Serial Interface Address:h595
Bits [7:0]
•
Reserved
QOSC7D and QOSC7E are useless in MVTX2801.
Class 6 Shaper Control Port G6 (useless in MVTX2801)
10.7.150
QOSC7F - TOKEN_RATE_G6
Serial Interface Address:h596
Bits [7:0]
•
Reserved
10.7.151
QOSC80 - TOKEN_LIMIT_G6
Serial Interface Address:h597
Bits [7:0]
•
Reserved
QOSC7F and QOSC80 are useless in MVTX2801.
Class 6 Shaper Control Port G7 useless in MVTX2801
10.7.152
QOSC81 - TOKEN_RATE_G7
Serial Interface Address:h598
Bits [7:0]
•
Reserved
SEMICMF.019
89
MVTX2801AG
Data Sheet
10.7.153
QOSC82 - TOKEN_LIMIT_G7
Serial Interface Address:h599
Bits [7:0]
QOSC81 and QOSC82 are useless in MVTX2801
10.7.154 RDRC0 - WRED Rate Control 0
•
Reserved
I2C Address 085, Serial Interface Address:h59A
Accessed by Serial Interface and I2C (R/W)
7
0
X Rate
Y Rate
Bits [7:4]:
Bits[3:0]:
•
•
Corresponds to the percentage X% in Chapter 7. Used for random early
drop. Granularity 6.25%. (Default: 4'h8)
Corresponds to the percentage Y% in Chapter 7. Used for random early
drop. Granularity 6.25%.(Default: 4'hE)
10.7.155
RDRC1 - WRED Rate Control 1
I2C Address 086, Serial Interface Address:h59B
Accessed by Serial Interface and I2C (R/W)
7
0
Z Rate
B Rate
Bits [7:4]:
Bits[3:0]:
•
•
Corresponds to the percentage Z% in Chapter 7. Used for random early
drop. Granularity 6.25%.%. (Default: 4'h6)
Corresponds to the best effort frame drop percentage B%, when shared
pool is all in use and destination port best effort queue reaches UCC. Used
for random early drop. Granularity 6.25%.%. (Default: 4'h8)
SEMICMF.019
90
Data Sheet
MVTX2801AG
10.8
Group 6 Address - MISC Group
10.8.1
MII_OP0 - MII Register Option 0
I2C Address h0B1, Serial Interface Address:h600
Accessed by serial interface and I2C (R/W)
7
6
5
4
0
Hfc
1prst
NP
Vendor Spc. Reg Addr
Bit [7]:
•
Half duplex flow control no default enable (Do not use half duplex mode)
- 0 = Half duplex flow control always enable
- 1 = Half duplex flow control by negotiation
Bit[6]:
Bit [5]
•
•
Link partner reset auto-negotiate disable
Next page enable
- 1: enable
- 0: disable
Bit[4:0]:
•
Vendor specified link status register address (null value means don't use it)
(Default 00)
10.8.2
MII_OP1 - MII Register Option 1
I2C Address 0B2, Serial Interface Address:h601
Accessed by serial interface and I2C (R/W)
7
4
3
0
Speed bit location
Duplex bit location
Bits[3:0]:
Bits [7:4]:
•
•
Duplex bit location in vendor specified register
Speed bit location in vendor specified register (Default 00)
10.8.3
FEN - Feature Register
I2C Address h0B3, Serial Interface Address:h602
Accessed by serial interface and I2C (R/W)
7
0
DML
MII
Rp
IP Mul
V-Sp
DS
RC
SC
Bits [0]:
Bits[1]:
•
•
Reserved
Reserved
SEMICMF.019
91
MVTX2801AG
Data Sheet
Bit [2]:
•
Support DS EF Code. (Default 0)
- 0 - Disable
- 1 - Enable (all ports)
•
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for
110 and drop is set for 0.
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
•
•
•
Reserved
Reserved
Reserved
- 0: Enable MII Management State Machine (Default 0)
- 1: Disable MII Management State Machine
- 0: Enable using MCT Link List structure
- 1: Disable using MCT Link List structure
Bit [7]:
10.8.4
MIIC0 - MII Command Register 0
Serial Interface Address:h603
Accessed by serial interface (R/W)
Bit [7:0] MII Data [7:0]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then
program MII command.
10.8.5
MIIC1 - MII Command Register 1
Serial Interface Address:h604
Accessed by serial interface (R/W)
Bit [7:0]
•
MII Data [15:8]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
10.8.6
MIIC2 - MII Command Register 2
Serial Interface Address:h605
Accessed by serial interface (R/W)
7
0
MII OP
Register address
Bits [4:0]:
Bit [6:5]
•
•
REG_AD - Register PHY Address
OP - Operation code “10” for read command and “01” for write command
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
SEMICMF.019
92
Data Sheet
MVTX2801AG
10.8.7
MIIC3 - MII Command Register 3
Serial Interface Address:h606
Accessed by serial interface (R/W)
7
0
Rdy
Valid
PHY address
Bits [4:0]:
•
•
•
PHY_AD - 5 Bit PHY Address
Bit [6]
Bit [7]
VALID - Data Valid from PHY (Read Only)
RDY - Data is returned from PHY (Ready Only)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
10.8.8
MIID0 - MII Data Register 0
Serial Interface Address:h607
Accessed by serial interface (RO)
Bit [7:0]
•
MII Data [7:0]
10.8.9
MIID1 - MII Data Register 0
Serial Interface Address:h608
Accessed by serial interface (RO)
Bit [7:0]
•
MII Data [15:8]
SEMICMF.019
93
MVTX2801AG
Data Sheet
10.8.10
LED Mode - LED Control
I2C Address:h0B4; Serial Interface Address:h609
Accessed by serial interface and I2C (R/W)
7
0
lpbk
Elpbk
Clock rate
Hold Time
Se
Bit[1:0]
Bit[3:2]
•
•
Sample hold time (Default 2'b00)
2'b00- 8 msec
2'b01- 16 msec
2'b10- 32 msec
2'b11- 64 msec
LED clock speed (serial mode) (Default 2'b10)
2'b00- sclk/128
2'b01- sclk/256
2'b10- sclk/1024
2'b11- sclk/2048
LED clock speed (parallel mode) (Default 2'b10)
2'b00- sclk/1024
2'b01- sclk/4096
2'b10- sclk/2048
2'b11- sclk/8192
Bit[5:4]
LED indicator out pattern (Default 2'b11)
2'b00- Normal output, LED signals go straight out, no logical combination
2'b01- 4 bi-color LED mode
2'b10- 3 bi-color LED mode
2'b11- programmable mode
Normal mode:
LED_BYTEOUT_[7]:Collision (COL)
LED_BYTEOUT_[6]:Full duplex (FDX)
LED_BYTEOUT_[5]:Speed[1] (SP1)
LED_BYTEOUT_[4]:Speed[0] (SP0)
LED_BYTEOUT_[3]:Link (LNK)
LED_BYTEOUT_[2]:Rx (RXD)
LED_BYTEOUT_[1]:Tx (TXD)
SEMICMF.019
94
Data Sheet
MVTX2801AG
Bit[5:4]
cont’d
LED_BYTEOUT_[0]:Flow Control (FC) 4 bi-color LED mode
LED_BYTEOUT_[7]:COL
LED_BYTEOUT_[6]:1000FDX
LED_BYTEOUT_[5]:1000HDX
LED_BYTEOUT_[4]:100FDX
LED_BYTEOUT_[3]:100HDX
LED_BYTEOUT_[2]:10FDX
LED_BYTEOUT_[1]:10HDX
LED_BYTEOUT_[0]:ACT
Note: All output qualified by Link signal
3 bi-color LED mode:
LED_BYTEOUT_[7]:COL
LED_BYTEOUT_[6]:LNK
LED_BYTEOUT_[5]:FC
LED_BYTEOUT_[4]:SPD1000
LED_BYTEOUT_[3]:SPD100 LED_BYTEOUT_[2]:FDX
LED_BYTEOUT_[1]:HDX
LED_BYTEOUT_[0]:ACT
Note: All output qualified by Link signal
Programmable mode:
LED_BYTEOUT_[7]:Link
LED_BYTEOUT_[6:0]:Defined by the LEDSIG6 ~ LEDSIG0 programmable
registers.
Note: All output qualified by Link signal
Reserved. Must be '0'
Bit[6]:
Bit[7]:
•
•
Enable internal loop back. When this bit is set to '1' all ports work in internal
loop back mode. For normal operation must be '0'.
10.8.11
DEVICE Mode
I2C Address h0B5; Serial Interface Address:h60a
Accessed by serial interface and I2C (R/W)
7
3
2
0
Device ID
Bit[2:0]:
Bit [7:3]:
•
•
Reserved
DEVICE ID (Default 0). This is for stacking operation. This is the stack ID
for loop topology.
SEMICMF.019
95
MVTX2801AG
Data Sheet
10.8.12
CHECKSUM - EEPROM Checksum
I2C Address h0C5, Serial Interface Address:h60B
Accessed by serial interface and I2C (R/W)
Bit [7:0]:
•
•
(Default 00)
Before requesting that the MVTX2801AG updates the EEPROM device, the
correct checksum needs to be calculated and written into this checksum
register. The checksum formula is:
FF
S
i2C register = 0
i = 0
After booting cycle the MVTX2801AG calculates the checksum. If the checksum is
not zeroed the MVTX2801AG does not start.
10.8.13
10.8.14
LED User
LEDUSER0
I2C Address h0BB, Serial Interface Address:h60C
Accessed by serial interface and I2C (R/W)
7
0
LED USER0
Bit [7:0]:
•
(Default 00)
Content will send out by LED serial logic
10.8.15
LEDUSER1
I2C Address h0BC, Serial Interface Address:h60D
Accessed by serial interface and I2C (R/W)
7
0
LED USER1
Bit [7:0]:
•
(Default 00)
Content will send out by LED serial logic
SEMICMF.019
96
Data Sheet
MVTX2801AG
10.8.16
LEDUSER2/LEDSIG2
I2C Address h0BD, Serial Interface Address:h60E
Accessed by serial interface and I2C (R/W)
In serial mode:
7
0
LED USER2
Bit [7:0]:
•
(Default 00)
Content will be sent out by LED serial shift logic
In parallel mode: this register is used for programming the LED pin - led_byteout_[2]
7
4
3
0
COL
FDX
SP1
SP0
COL
FDX
SP1
SP0
Bit [3:0]:
Bit [7:4]
(Default 4'H0)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
(Default 4'H8)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[2] = AND (all selected bits)
10.8.17
LEDUSER3/LEDSIG3
I2C Address:h0BE, Serial Interface Address:h60F
Access by CPU, serial interface (R/W)
In serial mode:
7
0
LED USER3
Bit [7:0]:
•
(Default 8'H33)
Content will be sent out by LED serial shift logic.
SEMICMF.019
97
MVTX2801AG
Data Sheet
In parallel mode: this register is used for programming the LED pin - led_byteout_[3]
7
4
3
0
COL
FDX
SP1
SP0
COL
FDX
SP1
SP0
Bit [3:0]:
(Default 4'H3)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
Bit [7:4]
(Default 4'H3)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[3] = AND (all selected bits)
LEDUSER4/LEDSIG4
10.8.18
I2C Address:h0BF, Serial Interface Address:h610
Access by CPU, serial interface (R/W)
7
0
LED USER4
Bit [7:0]
(Default 8'H32)
Content will be sent out by LED serial shift logic.
In parallel mode: this register is used for programming the LED pin - led_byteout_[4]
7
4
3
0
COL
FDX
SP1
SP0
COL
FDX
SP1
SP0
Bit [3:0]
Bit [7:4]
(Default 4'H2)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
(Default 4'H3)
Signal Select
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[4] = AND (all selected bits)
SEMICMF.019
98
Data Sheet
MVTX2801AG
10.8.19
LEDUSER5/LEDSIG5
I2C Address:h0C0, Serial Interface Address:h611
Access by CPU, serial interface (R/W)
7
0
LED USER5
Bit [7:0]
(Default 8'H20)
Content will be sent out by LED serial shift logic.
In parallel mode: this register is used for programming the LED pin - led_byteout_[5]
7
4
3
0
COL
FDX
SP1
SP0
COL
FDX
SP1
SP0
Bit [3:0]
Bit [7:4]
(Default 4'H0)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
(Default 4'H2)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[5] = AND (all selected bits)
10.8.20
LEDUSER6/LEDSIG6
I2C Address:h0C1, Serial Interface Address:h612
Access by CPU, serial interface (R/W)
7
0
LED USER6
Bit [7:0]
(Default 8'H40)
Content will be sent out by LED serial shift logic.
In parallel mode: this register is used for programming the LED pin - led_byteout_[6]
7
4
3
0
COL
FDX
SP1
SP0
COL
FDX
SP1
SP0
Bit [3:0]
(Default 4'B0000)
Signal polarity:
0: not invert polarity (high true)
1: invert polarity
SEMICMF.019
99
MVTX2801AG
Data Sheet
Bit [7:4]
(Default 4'b0100)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[6] = AND (all selected bits), or the
polarity of led_byteout_[6] is controlled by LEDSIG1_0[3]
10.8.21
LEDUSER7/LEDSIG1_0
I2C Address:h0C2, Serial Interface Address:h613
Access by CPU, serial interface (R/W)
7
0
LED USER7
Bit [7:0]
(Default 8'H61)
Content will be sent out by LED serial shift logic.
In parallel mode: this register is used for programming the LED pin - led_byteout_[2]
7
4
3
0
GP
RX
TX
FC
P6
RX
TX
FC
Bit [7]
(Default 1'B0)
Global output polarity: this bit controls the output polarity of all led_byteout_ and
led_port_sel pins.
0: no invert polarity - (led_byteout_[7:0] are high activated, led_port_sel[9:0]
are low activated)
1: invert polarity - (led_byteout_[7:0] are low activated, led_port_sel[9:0] are
high activated)
Bit [6:4]
(Default 3'B110)
Signal Select
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[6] = OR (all selected bits)
Bit[3]
(Default 1'B0)
Polarity control of led_byteout_[6]
0: not invert
1: invert
Bit [2:0]
(Default 3'b001)
Signal Select:
0: not select
1: select the corresponding bit
When bits get selected, the led_byteout_[0] = OR (all selected bits)
SEMICMF.019
100
Data Sheet
MVTX2801AG
10.8.22
MIINP0 - MII Next Page Data Register 0
I2C Address:h0C3, Serial Interface Address:h614
Access by CPU and serial interface only (R/W)
Bit [7:0]
MII next page Data [7:0]
10.8.23
MIINP1 - MII Next Page Data Register 1
I2C Address:h0C4, Serial Interface Address:h615
Access by CPU and serial interface only (R/W)
Bit [7:0]
MII next page Data [15:8]
10.9
Group F Address - CPU Access Group
GCR-Global Control Register
10.9.1
Serial Interface Address: hF00
Accessed by serial interface. (R/W)
7
0
Init
Reset
Bist
SR
SC
Bit [0]:
Bit[1]:
Bit[2]:
•
•
Store configuration (Default = 0)
Write '1' followed by '0' to store configuration into external EEPROM
•
•
Store configuration and reset (Default = 0)
Write '1' to store configuration into external EEPROM and reset chip
•
•
Start BIST (Default = 0)
Write '1' followed by '0' to start the device's built-in self-test. The result is
found in the DCR register.
Bit[3]:
•
•
Soft Reset (Default = 0)
Write '1' to reset the chip
Bit[4]:
•
•
Reserved
Reserved
Bit[5:7]:
10.9.2
DCR-Device Status and Signature Register
Serial Interface Address: hF01
Accessed by serial interface. (RO)
7
0
Revision
Signature
RE
BinP
BR
BW
SEMICMF.019
101
MVTX2801AG
Data Sheet
Bit [0]:
Bit[1]:
Bit[2]:
Bit[3]:
Bit[5:4]:
1 - Busy writing configuration to I2C
0 - Not Busy writing configuration to I2C
1 - Busy reading configuration from I2C
0 - Not Busy reading configuration from I2C
1 - BIST in progress
0 - BIST not running
1 - RAM Error
0 - RAM OK
Device Signature
00 - 4 Ports Device, non-management mode
01 - 8 Ports Device, non-management mode
10 - 4 Ports Device, management mode possible (need to install CPU)
11 - 8 Ports Device, management mode possible (need to install CPU)
Bit [7:6]:
Revision
10.9.3
DCR01-Giga port status
Serial Interface Address: hF02
Accessed by serial interface. (RO)
7
3
2
1
0
CIC
GIGA1
GIGA0
Bit [1:0]:
Bit[3:2]
Bit [7]
Giga port 0 strap option
00 - 100Mb MII mode
01 - Invalid
10 - GMII
11 - PCS
Giga port 1 strap option
00 - 100Mb MII mode
01 - Invalid
10 - GMII
11 - PCS
Chip initialization completed
Note: DCR01[7], DCR23[7], DCR45[7] and DCR67[7] have the same function.
SEMICMF.019
102
Data Sheet
MVTX2801AG
10.9.4
DCR23-Giga port status
Serial Interface Address: hF03
Accessed by CPU and serial interface. (RO)
7
3
2
1
0
CIC
GIGA3
GIGA2
Bit [1:0]:
Bit[3:2]
Bit [7]
Giga port 2 strap option
00 - 100Mb MII mode
01 - Invalid
10 - GMII
11 - PCS
Giga port 3 strap option
00 - 100Mb MII mode
01 - Invalid
10 - GMII
11 - PCS
Chip initialization completed
10.9.5
DCR45-Giga port status (useless in MVTX2801)
Serial Interface Address: hF04
Accessed by CPU and serial interface. (RO)
7
3
2
1
0
Reserved
10.9.6
DCR67-Giga port status (useless in MVTX2801)
Serial Interface Address: hF05
Accessed by CPU and serial interface. (RO)
7
3
2
1
0
Reserved
SEMICMF.019
103
MVTX2801AG
Data Sheet
10.9.7
DPST - Device Port Status Register
Serial Interface Address:hF06
Accessed by CPU and serial interface (R/W)
Bit[2:0]:
Read back index register. This is used for selecting what to read back from DTST.
(Default 00)
3'B000 - Port 0 Operating mode and Negotiation status
3'B001 - Port 1 Operating mode and Negotiation status
3'B010 - Port 2 Operating mode and Negotiation status
3'B011 - Port 3 Operating mode and Negotiation status
3'B100 - Reserved
3'B101 - Reserved
3'B110 - Reserved
3'B111 - Reserved
10.9.8
DTST - Data Read Back Register
Serial Interface Address: hF07
Accessed by CPU and serial interface (RO)
7
0
MD InfoDet SigDet Giga Inkdn FE Fdpx Fc_en
This register provides various internal information as selected in DPST bit[2:0]
Bit[0]:
Bit[1]:
Bit[2]:
Bit[3]:
Bit[4]:
Bit[5]:
Bit[6]:
Bit[7]:
Flow control enabled
Full duplex port
Fast ethernet port (if not giga)
Link is down
GIGA port
Signal detect (when PCS interface mode)
Pipe signal detected (pipe mode only)
Module detected (for hot swap purpose)
SEMICMF.019
104
Data Sheet
MVTX2801AG
11.0
11.1
BGA and Ball Signal Description
BGA Views
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC NC NC NC NC NC NC NC NC NC NC NC
NC NC NC NC NC
A
B
C
D
E
AVD NC9 SCA
N_EN
S_CL
K
B_A[1B_A[1B_A[7B_A[2B_OEB_D[ B_D[ NC4 NC3
6] 2] 27] 26]
D
]
]
#
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
DEV_ LA_D NC7
CF[0] [0]
B_A[1B_A[1B_A[8B_A[3B_W B_D[ DEV_ NC5 B_D[25
7] 3] E# 30] CFG[
]
]
]
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
LA_D LA_C LA_D NC6
[1] LK [3]
B_A[1B_A[1B_A[1B_A[5B_A[4B_D[ AVD B_CL B_D[22
8]
4]
1]
]
]
28]
D
K
]
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
LA_D LA_D LA_D NC8
[2] [5] [9]
B_A[9B_A[1B_AD NC2 B_D[ B_D[ B_D[ B_D[21
]
0] SC# 29] 24] 18]
]
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
LA_D LA_D LA_D LA_D AGN
[8] [7] [6] [4]
LB_A[B_A[1B_A[6B_D[ AGN B_D[ B_D[ B_D[ B_D[ B_D[14
20] 5]
D
]
31]
D
17] 23] 19] 16]
]
F
G
H
J
LA_D LA_D LA_D LA_D LA_D VSS VSS
[10] [11] [12] [13] [14]
VDD VDD
VD33 VD33 VD33 VSS VSS VD33 VD33 VD33
VDD VDD
VSS VSS NC1 B_D[ B_D[ B_D[ B_D[12
9] 10] 11]
]
LA_D LA_D LA_D LA_D LA_D VDD
VDD B_D[ B_D[ B_D[ B_D[ B_D[7]
LA_D LA_D LA_D LA_D LA_D
B_D[ B_D[ P_IN B_D[ B_D[2]
LA_D LA_D LA_D LA_D LA_D VDD
[23] [25] [26] [27] [31]
VDD B_D[ P_A[1P_A[2P_W P_RD#
13] E#
]
]
K
L
LA_D LA_D LA_C LA_D LA_D VDD
[28] [30] S0# [37] [33]
VDD B_D[ P_D[ P_D[ P_D[ P_D[13
5] 15] 11] 12]
]
LA_C LA_R LA_D LA_D LA_D
S1# W# [32] [46] [41]
P_CS P_D[ P_D[ P_D[ P_D[10
14] 7] 8]
#
]
M
LA_D LA_D LA_D LA_D LA_D VD33
[34] [35] [36] [53] [48]
VD33 P_A[ B_D[ P_D[ P_D[ P_D[5]
0] 0] 3] 4]
N
P
LA_D LA_D LA_D LA_D LA_D VD33
[38] [40] [42] [61] [56]
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VD33 P_D[ P_D[ P_D[ P_D[ P_D[2]
6] 9] 0] 1]
LA_D LA_D LA_D LA_A[LA_D VD33
VD33 T_D[ T_D[1T_D[1T_D[1T_D[14
15] 1] 2] 3]
[43] [44] [45] 4]
[39]
]
R
T
LA_D LA_D LA_D LA_D LA_D VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS T_D[ T_D[5T_D[7T_D[8T_D[9]
LA_D LA_D LA_D LA_D LA_A VSS
[58] [57] [55] [54] [7]
VSS T_D[ T_D[4T_D[2T_D[1T_D[0]
6]
]
]
]
U
V
LA_D LA_D LA_D LA_D LA_A VD33
[63] [62] [60] [59] [11]
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VD33 S_RST_D[3TMO TMO RESO
T# DE[1] DE[0] UT#
]
LA_A[LA_A[LA_A[LA_A[LA_A VD33
VD33 NC[7] G7_RLESY LE_C LE_DO
X_ER NO# LK0
6]
5]
3]
14] [18]
W
Y
LA_A[LA_A[LA_A[LA_A[G0_T VD33
10] 9] 8] 20] XD[1]
VD33 NC[3] NC[1] G7_RNC[6] NC[5]
X_DV
LA_A[LA_A[LA_A[G0_CG0_T
NC[6] G7_T NC[4] NC[2] NC[0]
A A
A B
LA_A[LA_A[LA_A[GRE G0_T VDD
19] 17] 16] FC[0] XD[7]
VDD NC[0] NC[3] G7_CG7_RMIITX
OL XCLK CK[7]
MIITXG0_T G0_T G0_T G0_T VDD
CK[0] XD[2] XD[0] XCLK X_ER
VDD NC[7] G7_T NC[7] NC[5] NC[4]
X_ER
A C
A D
A E
G0_RG0_T G0_T G0_RG0_R
NC[2] NC[4] NC[2] NC[1] G7_CR
G0_RG0_T G0_CG0_T G0_R VSS
XD[0] X_EN OL XD[6] X_DV
VDD NC[0] NC G7_T NC NC
XCLK
G0_RG0_R G0_RG0_RG1_T VSS VDD
VDD VDD
VD33 VD33 VD33 VSS VSS VD33 VD33 VD33
VDD VDD
VSS VSS NC[7] NC[6] NC[5] NC[3] NC[1]
A F
A G
G0_RG0_R GRE G1_RG1_RG1_R G2_T G2_T G2_RG2_R G2_RG3_T G3_T G3_C G3_RG3_RIND_ G3_R G3_RNC[3] NC[1] NC[4] NC[2] NC[4] NC NC[5] NC NC[6] NC NC
XD[7] X_ER FC[1] XD[2] XD[5] XD[7] XD[0] XD[7] XD[2] XD[4] XD[5] XD[1] XD[6] OL XD[3] XD[6] CM XD[4] X_ER
G1_T G1_T G1C G1_T G2_T G1_R G2_T G2_T G2_RG2_R G2_RG2_RG3_T G3_R G3_RG3_RNC M_M NC[1] NC[5] NC[6] NC[7] NC NC[5] MIITXNC[1] NC[3] NC[4] NC NC[5]
XD[1] XCLK RS/L XD[7] XCLKXD[4] XD[4] XD[3] XD[3] XCLK XD[7] X_ER X_EN XD[0] XD[5] XD[7]
DIO
CK[5]
A H
AJ
G1_T G1_T MIITXG1_RG1_RG2C MIITXG2_T G2_RG2_R G3_T G3_T G3_T G3_R G3_RG3_RNC NC[4] NC[6] NC NC NC NC NC[3] NC NC[3] NC[6] NC[1] NC[2] NC
XD[2] XD[3] CK[1] XD[0] XCLKRS/L CK[2] X_EN XD[1] X_DV XCLKXD[3] XD[5] XCLK XD[2] X_DV
G1_T G1_T G1_T G1_CG1_RGRE G2_T G2_T G2_RG2_R GRE G3_T MIITXG3_T G3_RM_M NC[0] NC[5] NC[7] NC[0] NC NC NC[0] NC[6] NC[0] NC NC[4] NC NC NC[0]
XD[5] XD[4] X_ER OL XD[6] FC[2] XD[2] XD[6] XD[0] XD[6] FC[3] XD[2] CK[3] X_ER XD[1] DC
A K
G1_T G1_T G1_RG1_RG1_RG1_R G2_T G2_T G2_T G2_C G3_CG3_T G3_T G3_T CM_ G4C NC[2] MIITXNC NC[2] NC[3] NC NC[1] NC[7] NC[2] NC NC[7] NC MIITXNC
XD[6] X_EN XD[1] XD[3] X_DVX_ER XD[1] XD[5] X_EROL RS/L XD[0] XD[4] XD[7] CLK RS/L
CK[4]
CK[6]
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SEMICMF.019
105
MVTX2801AG
Data Sheet
11.2
Power and Ground Distribution
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC
NC NC NC NC NC NC NC NC NC NC NC
NC NC NC NC NC
AAVDD NC9 SCA
N_EN
S_CL
K
B_A[ B_A[ B_A[ B_A[ B_OEB_D[ B_D[ NC4 NC3
16] 12] 7] 2] 27] 26]
#
NC
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
BDEV_CLA_D NC7
B_A[ B_A[ B_A[ B_A[ B_W B_D[ DEV_ NC5 B_D[
17] 13] 8] 3] E# 30] CFG[ 25]
F[0]
CLA_D[1LA_C LA_D NC6
LK [3]
DLA_D[2LA_D LA_D NC8
[5] [9]
ELA_D[8LA_D LA_D LA_D[ AGN
[7] [6] 4]
FLA_D[1LA_D LA_D LA_D[ LA_D VSS VSS
0] [11] [12] 13] [14]
GLA_D[1LA_D LA_D LA_D[ LA_D VDD
[0]
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
B_A[ B_A[ B_A[ B_A[ B_A[ B_D[ AVD B_CL B_D[
18] 14] 11] 5] 4] 28] 22]
]
D
K
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
B_A[ B_A[ B_AD NC2 B_D[ B_D[ B_D[ B_D[
9] 10] SC# 29] 24] 18] 21]
]
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
LB_A B_A[ B_A[ B_D[ AGN B_D[ B_D[ B_D[ B_D[ B_D[
[20] 15] 6]
]
D
31]
VSS VSS NC1 B_D[ B_D[ B_D[ B_D[
9] 10] 11] 12]
VDD B_D[ B_D[ B_D[ B_D[ B_D[
20] 4] 3] 6] 7]
B_D[ B_D[ P_IN B_D[ B_D[
15] 8] T# 1] 2]
VDD B_D[ P_A[ P_A[ P_W P_RD
13] 1] 2] E#
VDD B_D[ P_D[ P_D[ P_D[ P_D[
5] 15] 11] 12] 13]
P_CS P_D[ P_D[ P_D[ P_D[
14] 7] 8] 10]
VD33 P_A[ B_D[ P_D[ P_D[ P_D[
0] 0] 3] 4] 5]
VD33 P_D[ P_D[ P_D[ P_D[ P_D[
6] 9] 0] 1] 2]
D
17] 23] 19] 16] 14]
VDD VDD
VD33 VD33 VD33 VSS VSS VD33 VD33 VD33
VDD VDD
5] [16] [19] 18] [17]
HLA_D[2LA_D LA_D LA_D[ LA_D
0] [21] [22] 29] [24]
JLA_D[2LA_D LA_D LA_D[ LA_D VDD
3] [25] [26] 27] [31]
#
KLA_D[2LA_D LA_C LA_D[ LA_D VDD
8] [30] S0# 37] [33]
LLA_CS LA_R LA_D LA_D[ LA_D
1# W# [32] 46] [41]
#
MLA_D[3LA_D LA_D LA_D[ LA_D VD33
4] [35] [36] 53] [48]
NLA_D[3LA_D LA_D LA_D[ LA_D VD33
8] [40] [42] 61] [56]
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
PLA_D[4LA_D LA_D LA_A[ LA_D VD33
3] [44] [45] 4] [39]
VD33 T_D[ T_D[ T_D[ T_D[ T_D[
15] 11] 12] 13] 14]
RLA_D[4LA_D LA_D LA_D[ LA_D VSS
9] [50] [51] 52] [47]
VSS T_D[ T_D[ T_D[ T_D[ T_D[
10] 5]
VSS T_D[ T_D[ T_D[ T_D[ T_D[
6] 4] 2] 1] 0]
VD33 S_RS T_D[ TMO TMO RES
T# 3] DE[1] DE[0] OUT#
VD33 NC[7] G7_R LESY LE_C LE_D
7]
8]
9]
TLA_D[5LA_D LA_D LA_D[ LA_A VSS
8] [57] [55] 54] [7]
ULA_D[6LA_D LA_D LA_D[ LA_A VD33
3] [62] [60] 59] [11]
VLA_A[6 LA_A LA_A LA_A[ LA_A VD33
[5] [3] 14] [18]
]
X_ER NO# LK0
O
W LA_A[1 LA_A LA_A LA_A[ G0_T VD33
0] [9] [8] 20] XD[1]
VD33 NC[3] NC[1] G7_R NC[6] NC[5]
X_DV
YLA_A[1 LA_A LA_A G0_C G0_T
5] [13] [12] RS/L XD[4]
NC[6] G7_T NC[4] NC[2] NC[0]
X_EN
AALA_A[1 LA_A LA_A GREF G0_T VDD
9] [17] [16] C[0] XD[7]
VDD NC[0] NC[3] G7_C G7_R MIITX
OL XCLK CK[7]
ABMIITX G0_T G0_T G0_T G0_T VDD
CK[0] XD[2] XD[0] XCLK X_ER
VDD NC[7] G7_T NC[7] NC[5] NC[4]
X_ER
ACG0_RXG0_T G0_T G0_R G0_R
NC[2] NC[4] NC[2] NC[1] G7_C
RS/L
CLK
XD[5] XD[3] XD[2] XD[6]
ADG0_RXG0_T G0_C G0_T G0_R VSS
D[0] X_EN OL XD[6] X_DV
VDD NC[0] NC G7_T NC NC
XCLK
AEG0_RXG0_R G0_R G0_R G1_T VSS VDD
D[5] XD[4] XD[3] XD[1] XD[0]
VDD VDD
VD33 VD33 VD33 VSS VSS VD33 VD33 VD33
VDD VDD
VSS VSS NC[7] NC[6] NC[5] NC[3] NC[1]
AFG0_RXG0_R GRE G1_R G1_R G1_R G2_T G2_T G2_R G2_R G2_R G3_T G3_T G3_C G3_R G3_R IND_ G3_R G3_R NC[3] NC[1] NC[4] NC[2] NC[4] NC NC[5] NC NC[6] NC NC
D[7] X_ER FC[1] XD[2] XD[5] XD[7] XD[0] XD[7] XD[2] XD[4] XD[5] XD[1] XD[6] OL XD[3] XD[6] CM XD[4] X_ER
AGG1_TX G1_T G1C G1_T G2_T G1_R G2_T G2_T G2_R G2_R G2_R G2_R G3_T G3_R G3_R G3_R NC M_M NC[1] NC[5] NC[6] NC[7] NC NC[5] MIITX NC[1] NC[3] NC[4] NC NC[5]
D[1] XCLK RS/L XD[7] XCLK XD[4] XD[4] XD[3] XD[3] XCLK XD[7] X_ER X_EN XD[0] XD[5] XD[7] DIO CK[5]
AHG1_TX G1_T MIITXG1_R G1_R G2C MIITX G2_T G2_R G2_R G3_T G3_T G3_T G3_R G3_R G3_R NC NC[4] NC[6] NC NC NC NC NC[3] NC NC[3] NC[6] NC[1] NC[2] NC
D[2] XD[3] CK[1] XD[0] XCLK RS/L CK[2] X_EN XD[1] X_DV XCLK XD[3] XD[5] XCLK XD[2] X_DV
AJG1_TX G1_T G1_T G1_C G1_R GRE G2_T G2_T G2_R G2_R GRE G3_T MIITX G3_T G3_R M_M NC[0] NC[5] NC[7] NC[0] NC NC NC[0] NC[6] NC[0] NC NC[4] NC NC NC[0]
D[5] XD[4] X_ER OL XD[6] FC[2] XD[2] XD[6] XD[0] XD[6] FC[3] XD[2] CK[3] X_ER XD[1] DC
AKG1_TX G1_T G1_R G1_R G1_R G1_R G2_T G2_T G2_T G2_C G3_C G3_T G3_T G3_T CM_ G4C NC[2] MIITX NC NC[2] NC[3] NC NC[1] NC[7] NC[2] NC NC[7] NC MIITXNC
D[6]
X_EN XD[1] XD[3] X_DV X_ER XD[1] XD[5] X_ER OL RS/L XD[0] XD[4] XD[7] CLK RS/L
CK[4]
CK[6]
SEMICMF.019
106
Data Sheet
MVTX2801AG
11.3
Ball- Signal Descriptions
All pins are CMOS type; all Input pins are 5 Volt tolerance, and all Output pins are 3.3 CMOS drive.
Ball No(s)
Symbol
P_DATA[15:11]
I/O
Description
K27, L27, K30, K29, K28
L30
I/O-TS with pull up
I/O - TS with pull up
Not used - leave unconnected
P_DATA[10]
P_DATA[9]
P_DATA[8:0]
Trunk enable
External pull up or unconnected-
disable trunk group 0 and 1
External pull down - enable trunk group
0 and 1
See register TRUNK0_MODE for port
selection and trunk enable.
N27
I/O - TS with pull up
Trunk enable
External pull up or unconnected -
disable trunk group 2 and 3
External pull down - enable trunk group
2 and 3
See register TRUNK1_MODE for port
selection and trunk enable.
L29, L28, N26, M30, M29,
M28, N30, N29, N28
I/O - TS with pull up
Bootstrap function - See bootstrap
section
J28
P_A[2]
Input
Not used - leave unconnected
Not used - leave unconnected
H28
P_INT#
Output
2
2
I C Interface (0) Note: In unmanaged mode, Use I C and Serial control interface to configure the system
2
J27
SCL
SDA
Output
I C Data Clock
2
M26
I/O-TS with pull up
I C Data I/O
Serial Control Interface
J29
PS_STROBE
PS_DO
Input with weak internal pull
up
Serial Strobe Pin
L26
Input with weak internal pull
up
Serial Data Input
J30
PS_DI (AUTOFD)
Output with pull up
Serial Data Output (AutoFD)
Frame Buffer Interface
U1, U2, N4, U3, U4, T1, T2, LA_D[63:0]
N5, T3, T4, M4, R4, R3,
I/O-TS with pull up
Frame Bank A- Data Bit [63:0]
R2, R1, M5, R5, L4, P3,
P2, P1, N3, L5, N2, P5, N1,
K4, M3, M2, M1, K5, L3,
J5, K2, H4, K1, J4, J3, J2,
H5, J1, H3, H2, H1, G3,
G4, G5, G2, G1, F5, F4,
F3, F2, F1, D3, E1, E2, E3,
D2., E4, C3, D1, C1, B2
AA1, V5, AA2, AA3, Y1,
V4, Y2, Y3, U5, W1, W2,
W3, T5, V1, V2, P4, V3
LA_A[19:3]
Output
Frame Bank A - Address Bit [19:3]
W4
C2
K3
LA_A[20]
LA_CLK
LA_CS0#
Output with pull up
Output
Frame Bank A - Address Bit [20]
Frame Bank A Clock Input
Output with pull up
Frame Bank A Low Portion Chip
Selection
L1
L2
LA_CS1#
LA_RW#
Output with pull up
Frame Bank A High Portion Chip
Selection
Output with pull up
Frame Bank A Read/Write
Table 7 - Ball- Signal Descriptions
SEMICMF.019
107
MVTX2801AG
Data Sheet
Ball No(s)
Symbol
I/O
Description
D18, B18, C18, A17, E17,
B17, C17, E16, D17, B16,
E15, C16, D16, D15, E14,
C15, B15, E13, A15, D14,
C14, D13, B14, A14, C13,
E12, B13, A13, D12, C12,
B12, A12, A11, E10, C10,
B10, E9, A10, D11, D10,
D8, D9, C9, B9, A9, C8,
B8, A8, C7, E7, D7, B7, E8,
A7, D6, C6, E6, B6, A6, A5,
B5, C5, B4,A4
NC
I/O-TS with pull up.
No Connect
D22, D20, E20, D21, A21,
D19, B21, C21, A20, B20,
E19, C20, A19, B19, E18,
C19, A18
NC
Output
F
LB_A[20]
NC
Output with pull up
Output
Bootstrap Pin
D5
B11
NC
Output with pull up
Output with pull up
Output with pull up
E11
NC
C11
NC
Switch Database Interface
E24,B27, D27, C27, A27,
A28, B30, D28, E27, C30,
D30, G26, E28, D29, E26,
E29, H26, E30, J26, F30,
F29, F28, F27, H27, G30,
G29, K26, G27, G28, H30,
H29, M27
B_D[31:0]
I/O-TS with pull up
Switch Database Domain
- Data Bit [31:0]
C22, B22, A22, E22, C23,
B23, A23, C24, D24, D23,
B24, A24, E23, C25, C26,
B25, A25
B_A[18:2]
B_CLK
Output
Switch Database Address (512K)
- Address Bit [18:2]
C29
D25
Output
Switch Database Clock Input
B_ADSC#
Output with pull up
Switch Database Address Status
Control
B26
B_WE#
B_OE#
Output with pull up
Output with pull up
Switch Database Write Chip Select
Switch Database Read Chip Select
A26
MII Management Interface
AJ16
M_MDC
M_MDIO
Output
MII Management Data Clock -
(common for all MII Ports [3:0])
AG18
I/O-TS with pull up
MII Management Data I/O -
(common for all MII Ports -[3:0]))
2.5Mhz
GMII / MII Interface (193) Gigabit Ethernet Access Port
AJ11, AJ6, AF3,AA4
AD29, AK30, AJ22, AG17
AK15
GREF_CLK [3:0]
NC
Input w/ pull up
Gigabit Reference Clock
CM_CLK
IND/CM
Input w/ pull up
Input w/ pull up
Common Clock shared by port G[3:0]
AF17
1: select GREF_CLK[3:0] as clock 0:
select CM_CLK as clock for all ports
AJ13, AH7, AH3, AB1
MII TX CLK[3:0]
Input w/ pull up
AA30, AK29, AG25, AK18, NC
Table 7 - Ball- Signal Descriptions (continued)
SEMICMF.019
108
Data Sheet
MVTX2801AG
Ball No(s)
Symbol
I/O
Input w/ pull up
Description
AG16, AF16, AG15, AF18, G3_RXD[7:0]
AF15, AH15, AJ15, AG14
G[3:0] port - Receive Data Bit [7:0]
AG11, AJ10, AF11, AF10,
AG9, AF9, AH9, AJ9
G2_RXD[7:0]
AF6, AJ5, AF5, AG6, AK4, G1_RXD[7:0]
AF4, AK3, AH4
AF1, AC5, AE1, AE2, AE3, G0_RXD[7:0]
AC4, AE4, AD1
V26, W29, W30, Y28, W26, NC
Y29, W27, Y30
AB26, AE27, AE28, AC27,
AE29, AC26, AE30, AD26
AK27, AH27, AF26, AJ27,
AH26, AK25, AG26, AJ25
AG22, AG21, AG20, AF22,
AK21, AK20, AF21, AJ20
AH16, AH10, AK5, AD5
W28, AD30, AK28, AH22,
AF19, AG12, AK6, AF2
V27, AD27, AJ28, AH23,
AK11, AH6, AG3, Y4
G[3:0]_RX_DV
Input w/ pull down
Input w/ pull up
Input w/ pull down
Input w/ pull up
Input w/ pull up
Output
G[3:0]port - Receive Data Valid
G[3:0]port - Receive Error
G[3:0]_RX_ER
NC
G[3:0]_CRS/LINK
G[3:0]port - Carrier Sense
AC30, AJ29, AG23, AK16, NC
AF14, AK10, AJ4, AD3
AA28, AF29, AJ26, AJ21,
AH14, AG10, AH5, AC1
G[3:0]_COL
G[3:0]port - Collision Detected
G[3:0]port - Receive Clock
G[3:0]port - Transmit Data Bit [7:0]
NC
G[3:0]_RXCLK
AA29, AF27, AK26, AH21, NC
AK14, AF13, AH13, AK13, G3_TXD[7:0]
AH12, AJ12, AF12, AK12
AF8, AJ8, AK8, AG7, AG8, G2_TXD[7:0]
AJ7, AK7, AF7
AG4, AK1, AJ1, AJ2, AH2, G1_TXD[7:0]
AH1, AG1, AE5
AA5, AD4, AC2, Y5, AC3,
AB2, W5, AB3
G0_TXD[7:0]
AB28, Y26, AB29, AB30, NC
AA27, AC28, AC29, AA26
AE26, AF28, AG30, AG28,
AG27, AH29, AH28, AJ30
AK24, AJ24, AG24, AF24,
AH24, AF23, AK23, AJ23
AJ19, AH19, AJ18, AH18,
AF20, AK17, AG19, AJ17
AG13, AH8, AK2, AD2
Y27, AG29, AH25, AK19,
AJ14, AK9, AJ3, AB5
G[3:0]_TX_EN
Output w/ pull up
Output w/ pull up
Output
G[3:0]port - Transmit Data Enable
G[3:0]port - Transmit Error
NC
G[3:0]_TX_ER
NC
AB27, AF30, AF25, AH20,
AH11, AG5, AG2, AB4
G[3:0]_ TXCLK
G[3:0]port - Gigabit Transmit Clock
AD28, AH30, AK22, AH17, NC
Table 7 - Ball- Signal Descriptions (continued)
SEMICMF.019
109
MVTX2801AG
Data Sheet
Ball No(s)
Symbol
I/O
Description
PMA Interface (193) Gigabit Ethernet Access Port (PCS)
AJ11, AJ6, AF3,AA4 GREF_CLK [3:0]
AD29, AK30, AJ22, AG17, NC
Input w/ pull up
Gigabit Reference Clock
AK15
AF17
CM_CLK
IND/CM
Input w/ pull up
Input w/ pull up
Common Clock shared by port G[3:0]
1: select GREF_CLK[3:0] as clock
0: select CM_CLK as clock for all port
AG16, AF16, AG15, AF18, G3_RXD[7:0]
AF15, AH15, AJ15, AG14
Input w/ pull up
G[3:0]port - PMA Receive Data Bit [7:0]
AG11, AJ10, AF11, AF10, G2_RXD[7:0]
AG9, AF9, AH9, AJ9
AF6, AJ5, AF5, AG6, AK4, G1_RXD[7:0]
AF4, AK3, AH4
AF1, AC5, AE1, AE2, AE3, G0_RXD[7:0]
AC4, AE4, AD1
V26, W29, W30, Y28, W26, NC
Y29, W27, Y30
AB26, AE27, AE28, AC27,
AE29, AC26, AE30, AD26
AK27, AH27, AF26, AJ27,
AH26, AK25, AG26, AJ25
AG22, AG21, AG20, AF22,
AK21, AK20, AF21, AJ20
AH16, AH10, AK5, AD5
W28, AD30, AK28, AH22,
AF19, AG12, AK6, AF2
V27, AD27, AJ28, AH23,
AF14, AK10, AJ4, AD3
AA28, AF29, AJ26, AJ21,
AH14, AG10, AH5, AC1
G[3:0]_RX_D[8]
NC
Input w/ pull down
Input w/ pull up
Input w/ pull up
Input w/ pull up
Output
G[3:0]port - PMA Receive Data Bit [8]
G[3:0]port - PMA Receive Data Bit [9]
G[3:0]port - PMA Receive Clock 1
G[3:0]port - PMA Receive Clock 0
G[3:0]port - PMA Transmit Data Bit [7:0]
G[3:0]_RX_D[9]
NC
G[3:0]_RXCLK1
NC
G[3:0]_RXCLK0
AA29, AF27, AK26, AH21, NC
AK14, AF13, AH13, AK13, G3_TXD[7:0]
AH12, AJ12, AF12, AK12
AF8, AJ8, AK8, AG7, AG8, G2_TXD[7:0]
AJ7, AK7, AF7
AG4, AK1, AJ1, AJ2, AH2, G1_TXD[7:0]
AH1, AG1, AE5
AA5, AD4, AC2, Y5, AC3,
AB2, W5, AB3
G0_TXD[7:0]
AB28, Y26, AB29, AB30, NC
AA27, AC28, AC29, AA26
AE26, AF28, AG30, AG28,
AG27, AH29, AH28, AJ30
AK24, AJ24, AG24, AF24,
AH24, AF23, AK23, AJ23
AJ19, AH19, AJ18, AH18,
AF20, AK17, AG19, AJ17
AG13, AH8, AK2, AD2
G[3:0]_TXD[8]
NC
Output w/ pull up
G[3:0]port - PMA Transmit Data Bit [8]
Y27, AG29, AH25, AK19,
Table 7 - Ball- Signal Descriptions (continued)
SEMICMF.019
110
Data Sheet
MVTX2801AG
Ball No(s)
Symbol
G[3:0]_TX_D[9]
I/O
Description
AJ14, AK9, AJ3, AB5
AB27, AF30, AF25, AH20,
AH11, AG5, AG2, AB4
Output w/ pull up
G[3:0]port - PMA Transmit Data Bit [9]
NC
G[3:0]_ TXCLK
Output
G[3:0]port - PMA Gigabit Transmit
Clock
AD28, AH30, AK22, AH17, NC
Test Facility (3)
U29
U28
A3
T_MODE0
I/O-TS with pull up
Test - Set upon Reset, and provides
NAND Tree test output during test
mode
Use external Pull up for normal
operation
T_MODE1
SCAN_EN
I/O-TS with pull up
Input with pull down
Test - Set upon Reset, and provides
NAND Tree test output during test
mode.
Use external Pull up for normal
operation
Enable test mode
For normal operation leave it
unconnected
LED Interface (serial and parallel)
R28, T26, R27, T27, U27,
T28, T29, T30
T_D[7:0]/ LE_PD[7:0]
Output
Output
While resetting, T_D[7,0] are in input
mode and are used as strapping pins.
Internal pull up
LE_PD - Parallel Led data [7:0]
P27, R26, R30, R29
P26, P30, P29, P28,
T_D[11:8]/ LE_PT[3:0]
While resetting, T_D[11:8] are in input
mode and are used as strapping pins.
Internal pull up
LED_PR[3:0] - Parallel Led port
selection [3:0]
T_D[15:12]/ LE_PT[7:4]
LE_CLK0/ LE_PT[8]
Output
While resetting, T_D[15:12] are in input
mode and are used as strapping pins.
Internal pull up
LED_PR[7:4] - No Meaning
V29
V30
Output
Output
LE_CLK0 - LED Serial Interface Output
Clock
LE_PT[8] - Parallel Led port sel [8]
LED_BLINK/ LE_DO/
LE_PT[9]
While resetting, LED-BLINK is in input
mode and is used as strapping pin.
1: No Blink,
0: Blink. Internal pull up.
LE_DO - LED Serial Data Output
Stream
LE_PT[9] - Parallel Led port sel [9]
V28
LED_PM/ LE_SYNCO#
Output with pull up
While resetting, LED_PM is in input
mode and is used as strapping pin.
Internal pull up.
1: Enable parallel interface,
0: enable serial interface.
LE_SYNCO# - LED Output Data
Stream Envelop
System Clock, Power, and Ground Pins
A16
U26
U30
S_CLK
Input
System Clock at 133 MHz
Reset Input
S_RST#
RESOUT#
Input - ST
Output
Reset PHY
Table 7 - Ball- Signal Descriptions (continued)
SEMICMF.019
111
MVTX2801AG
Data Sheet
Ball No(s)
Symbol
DEV_CFG[0]
I/O
Description
B1
Input w/ pull down
Input w/ pull down
Power core
Not used
Not used
B28
DEV_CFG[1]
VDD
AE7, AE9, F10, F21, F22,
F9, G25, G6, J25, J6, K25,
K6, AA25, AA6, AB25,
AB6, AD25, AE10, AE21,
AE22
+2.5 Volt DC Supply
V14, V15, V16, V17, V18, VSS
F16, F24, F25, F6, F7, N13,
N14, N15, N16, N17, N18,
P13, P14, P15, P16, P17,
P18, R13, R14, R15, R16,
R17, R18, R25, R6, T13,
T14, T15, T16, T17, T18,
T25, T6, U13, U14, U15,
U16, U17, U18, V13, AD6,
AE15, AE16, AE24, AE25,
AE6, F15
Ground
Ground
A1, C28
E5, E25
AVDD
AVSS
Power
Analog DC Supply
Analog Ground
Ground
Power I/O
AE12, AE13, AE14, AE17, VDD33
AE18, AE19, F12, F13,
F14, F17, F18, F19, M25,
M6, N25, N6, P25, P6,
U25, U6, V25, V6, W25,
W6
+3.3 Volt DC Supply
Bootstrap Pins (Default= pull up, 1= pull up 0= pull down)
AD2
G0_TX_EN
Default: PCS
Giga0
Mode: G0_TXEN G0_TXER
0
0
1
1
0
MII
Invalid
1
0
1
GMII
PCS
AB5
AK2
G0_TX_ER
G1_TX_EN
Default: PCS
Default: PCS
Giga1
Mode: G1_TXEN G1_TXER
0
0
1
1
0
1
0
1
MII
Invalid
GMII
PCS
AJ3
G1_TXER
Default: PCS
Default: PCS
AH8
G2_TX_EN
Giga2
Mode: G0_TXEN G0_TXER
0
0
1
1
0
1
0
1
MII
Invalid
GMII
PCS
AK9
G2_TX_ER
G3_TX_EN
Default: PCS
Default: PCS
AG13
Giga3
Mode: G0_TXEN G0_TXER
0
0
1
1
0
1
0
1
MII
Invalid
GMII
PCS
AJ14
G3_TX_ER
Default: PCS
Table 7 - Ball- Signal Descriptions (continued)
SEMICMF.019
112
Data Sheet
MVTX2801AG
Ball No(s)
Symbol
I/O
Description
After reset T_d[15:0] are used by the LED interface
T30
T29
T_d[0]
T_d[1]
1
1
Giga link active status 0 - active low 1 -
active high
Power saving
0 - No power saving
1 - Power saving
Stop MAC clock if no MAC activity.
T28
U27
T_d[2]
T_d[3]
1
1
- Must be 0 (Use external pull down)
Hot plug port module detection enable
0 - module detection enable
1 - module detection disable
T27
R27
T_d[4]
T_d[5]
1
1
- Must be 0 (Use external pull down)
SRAM memory size
0 - 512K SRAM
1 - 256K SRAM
T26
T_d[6]
1
CPU Port mode
0 - 8 bit cpu data bus
1 - 16 bit cpu data bus
R28
T_d[7]
1
FDB memory depth
1- one memory layer
0 - two memory layers
W4, E21
La_a[20], Lb_a[20]
11
FDB memory size
11 - 2M per bank = 4M total
10 - 1M per bank = 2M total
0x - 512K per bank = 1M total
R29
R30
R26
P27
T_d[8]
1
1
1
1
EEPROM installed
0 - EEPROM is installed
1 - EEPROM is not installed
T_d[9]
MCT Aging enable
0 - MCT aging disable
1 - MCT aging enable
T_d[10]
T_d[11]
FCB handle aging enable
0 - FCB handle aging disable
1 - FCB handle aging enable
Timeout reset enable
0 - timeout reset disable
1 - timeout reset enable Issue reset if
any state machine did not go back to
idle for 5sec.
P28
P29
T_d[12]
T_d[13]
1
1
Speed-up test
0 - enable test speed up. DO NOT
USE.
1 - disable test speed up
Enable debounce for strobe signal
0 - disable debounce on strobe signal
using 1msec clock - DO NOT USE.
1 - enable debounce on strobe signal
P30
P26
T_d[14]
T_d[15]
1
1
CPU installed
0 - CPU installed.
1 - CPU is not installed.
External RAM test 0 - Perform the
infinite loop of ZBT RAM BIST. Debug
test only 1 - Regular operation.
Table 7 - Ball- Signal Descriptions (continued)
SEMICMF.019
113
MVTX2801AG
Data Sheet
Ball No(s)
Symbol
I/O
Description
N30, N29, N28
P_d[2:0]
111
ZBT RAM la_clk turning
3'b000 - control by reg. LCLKCR[2:0]
3'b001 - delay by method # 0
3'b010 - delay by method # 1
3'b011 - delay by method # 2
3'b100 - delay by method # 3
3'b101 - delay by method # 4
3'b110 - delay by method # 5
3'b111 - delay by method # 6
- USE THIS METHOD
M30, M29, M28
L29, L28, N26
P_d[5:3]
P_d[8:6]
111
111
No Use
SBRAM b_clk turning3'b000 - control by
BCLKCR[2:0]
3'b001 - delay by method # 0
3'b010 - delay by method # 1
3'b011 - delay by method # 2
3'b100 - delay by method # 3
3'b101 - delay by method # 4
3'b110 - delay by method # 5
3'b111 - delay by method # 6
- USE THIS METHOD
Table 7 - Ball- Signal Descriptions (continued)
Notes:
# =
Active low signal
Input signal
Input =
In-ST =
Output =
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Out-OD=
I/O-TS =
I/O-OD =
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
SEMICMF.019
114
Data Sheet
11.4
MVTX2801AG
Ball Signal Name
Ball No.
Signal Name
Ball No.
M1
Signal Name
LA_D[34]
Ball No.
Y2
Signal Name
A1
B1
B2
C2
C1
D1
C3
E4
D2
E3
E2
E1
D3
F1
F2
F3
F4
F5
G1
G2
G5
G4
G3
H1
H2
H3
J1
AVDD
LA_A[13]
DEV_CFG[0]
LA_D[0]
M2
M3
K4
N1
P5
N2
L5
LA_D[35]
LA_D[36]
LA_D[37]
LA_D[38]
LA_D[39]
LA_D[40]
LA_D[41]
LA_D[42]
LA_D[43]
LA_D[44]
LA_D[45]
LA_D[46]
LA_D[47]
LA_D[48]
LA_D[49]
LA_D[50]
LA_D[51]
LA_D[52]
LA_D[53]
LA_D[54]
LA_D[55]
LA_D[56]
LA_D[57]
LA_D[58]
LA_D[59]
LA_D[60]
LA_D[61]
LA_D[62]
LA_D[63]
LA_A[3]
V4
LA_A[14]
Y1
LA_A[15]
LA_CLK
LA_D[1]
AA3
AA2
V5
LA_A[16]
LA_A[17]
LA_D[2]
LA_A[18]
LA_D[3]
AA1
W4
LA_A[19]
LA_D[4]
LA_A[20]
LA_D[5]
N3
P1
P2
P3
L4
Y4
G0_CRS/LINK
GREF_CLK[0]
G0_TXCLK
G0_TXD[0]
G0_TXD[1]
G0_TXD[2]
MII_TX_CLK[0]
G0_TXD[3]
G0_TXD[4]
G0_TXD[5]
G0_RXCLK
G0_COL
LA_D[6]
AA4
AB4
AB3
W5
LA_D[7]
LA_D[8]
LA_D[9]
LA_D[10]
LA_D[11]
LA_D[12]
LA_D[13]
LA_D[14]
LA_D[15]
LA_D[16]
LA_D[17]
LA_D[18]
LA_D[19]
LA_D[20]
LA_D[21]
LA_D[22]
LA_D[23]
LA_D[24]
LA_D[25]
LA_D[26]
LA_D[27]
LA_D[28]
LA_D[29]
LA_D[30]
R5
M5
R1
R2
R3
R4
M4
T4
T3
N5
T2
T1
U4
U3
N4
U2
U1
V3
P4
V2
V1
AB2
AB1
AC3
Y5
AC2
AC1
AD3
AD4
AA5
AD2
AB5
AD1
AE4
AC4
AE3
AE2
AE1
AC5
AF1
AD5
AF2
G0_TXD[6]
G0_TXD[7]
G0_TX_EN
G0_TX_ER
G0_RXD[0]
G0_RXD[1]
G0_RXD[2]
G0_RXD[3]
G0_RXD[4]
G0_RXD[5]
G0_RXD[6]
G0_RXD[7]
G0_RX_DV
G0_RX_ER
H5
J2
J3
J4
K1
H4
K2
LA_A[4]
LA_A[5]
LA_A[6]
Table 8 - Ball Signal Name
SEMICMF.019
115
MVTX2801AG
Data Sheet
Ball No.
Signal Name
Ball No.
T5
Signal Name
LA_A[7]
Ball No.
AF3
Signal Name
J5
LA_D[31]
GREF_CLK[1]
K3
LA_CS0#
W3
LA_A[8]
AG2
G1_TXCLK
L1
LA_CS1#
W2
LA_A[9]
AG3
G1_CRS/LINK
L2
LA_RW#
W1
LA_A[10]
AE5
G1_TXD[0]
G1_TXD[1]
G1_TXD[2]
NC
L3
LA_D[32]
U5
LA_A[11]
AG1
K5
LA_D[33]
Y3
LA_A[12]
AH1
AH2
AJ2
AJ1
AK1
AG4
AK2
AH3
AJ3
AH4
AK3
AF4
AK4
AH5
AJ4
AG6
AF5
AJ5
AF6
AK5
AK6
AJ6
AG5
AH6
AF7
AK7
AJ7
AG8
AG7
AH7
G1_TXD[3]
G1_TXD[4]
G1_TXD[5]
G1_TXD[6]
G1_TXD[7]
G1_TX_EN
MII_TX_CLK[1]
G1_TX_ER
G1_RXD[0]
G1_RXD[1]
G1_RXD[2]
G1_RXD[3]
G1_RXCLK
G1_COL
AG10
AK10
AJ10
AG11
AH10
AG12
AK11
AJ11
AH11
AK12
AF12
AJ12
AH12
AK13
AJ13
AH13
AF13
AK14
AG13
AJ14
AH14
AF14
AG14
AK15
AF17
AJ15
AH15
AF15
AF18
G2_RXCLK
G2_COL
AG19
AK17
AF20
AH18
AJ18
AK18
AH19
AJ19
AK19
AH20
AJ20
AF21
AK20
AH21
AJ21
AK21
AF22
AG20
AG21
AG22
AH22
AJ22
AK22
AH23
AG23
AJ23
AK23
AF23
AH24
NC
G2_RXD[6]
G2_RXD[7]
G2_RX_DV
G2_RX_ER
G3_CRS/LINK
GREF_CLK[3]
G3_TXCLK
G3_TXD[0]
G3_TXD[1]
G3_TXD[2]
G3_TXD[3]
G3_TXD[4]
MII_TX_CLK[3]
G3_TXD[5]
G3_TXD[6]
G3_TXD[7]
G3_TX_EN
G3_TX_ER
G3_RXCLK
G3_COL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G1_RXD[4]
G1_RXD[5]
G1_RXD[6]
G1_RXD[7]
G1_RX_DV
G1_RX_ER
GREF_CLK[2]
G2_TXCLK
G2_CRS/LINK
G2_TXD[0]
G2_TXD[1]
G2_TXD[2]
G2_TXD[3]
G2_TXD[4]
MII_TX_CLK[2]
NC
NC
NC
NC
NC
NC
NC
NC
G3_RXD[0]
CM_CLK
NC
NC
IND_CM
NC
G3_RXD[1]
G3_RXD[2]
G3_RXD[3]
G3_RXD[4]
NC
NC
NC
NC
Table 8 - Ball Signal Name (continued)
SEMICMF.019
116
Data Sheet
MVTX2801AG
Ball No.
Signal Name
G2_TXD[5]
Ball No.
AG15
Signal Name
G3_RXD[5]
Ball No.
AF24
Signal Name
AK8
NC
AJ8
G2_TXD[6]
AF16
AG16
AH16
AF19
AJ16
AG18
AK16
AG17
AH17
AJ17
AA27
AB30
AB29
Y26
G3_RXD[6]
G3_RXD[7]
G3_RX_DV
G3_RX_ER
M_MDC
M_MDIO
NC
AG24
AJ24
AK24
AG25
AH25
AF25
AJ25
AG26
AK25
AK26
P29
NC
AF8
G2_TXD[7]
NC
AH8
G2_TX_EN
NC
AK9
G2_TX_ER
NC
AJ9
G2_RXD[0]
NC
AH9
G2_RXD[1]
NC
AF9
G2_RXD[2]
G2_RXD[3]
G2_RXD[4]
G2_RXD[5]
NC
NC
AG9
NC
NC
AF10
AF11
AJ26
AH26
AJ27
AF26
AH27
AK27
AK28
AJ28
AJ29
AK29
AK30
AJ30
AH28
AH29
AG27
AG28
AH30
AG30
AF28
AE26
AG29
AF27
AF29
AF30
NC
NC
NC
NC
NC
T_D[13]
T_D[14]
T_D[15]
P_D[0]
P_D[1]
P_D[2]
P_D[3]
P_D[4]
P_D[5]
P_D[6]
P_D[7]
P_D[8]
P_D[9]
P_D[10]
P_D[11]
P_D[12]
P_D[13]
P_D[14]
P_D[15]
P_A[0]
P_A[1]
P_A[2]
P_WE#
P_RD#
NC
NC
P30
NC
NC
P26
NC
NC
N28
N29
N30
M28
M29
M30
N26
L28
NC
AB28
Y27
NC
NC
NC
NC
AB27
AA30
AA29
AA28
Y30
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
W27
Y29
NC
L29
NC
NC
N27
L30
NC
W26
Y28
NC
NC
NC
K28
NC
W30
W29
V26
NC
K29
NC
NC
K30
NC
NC
L27
NC
W28
V27
NC
K27
NC
NC
M26
J27
NC
V30
LE_DO
LE_CLK0
LE_SYNCO#
S_RST#
NC
V29
J28
NC
V28
J29
NC
U26
J30
Table 8 - Ball Signal Name (continued)
SEMICMF.019
117
MVTX2801AG
Data Sheet
Ball No.
AD26
Signal Name
Ball No.
U30
Signal Name
RESOUT#
Ball No.
L26
Signal Name
NC
P_CS#
AE30
AC26
AE29
AC27
AE28
AE27
AB26
AD30
AD29
AD27
AD28
AC30
AA26
AC29
AC28
E30
NC
U29
U28
T30
T29
T28
U27
T27
R27
T26
R28
R29
R30
R26
P27
P28
A23
B23
C23
E22
A22
B22
C22
E21
D22
D20
E20
D21
A21
D19
B21
C21
A20
B20
E19
T_MODE[0]
T_MODE[1]
T_D[0]
T_D[1]
T_D[2]
T_D[3]
T_D[4]
T_D[5]
T_D[6]
T_D[7]
T_D[8]
T_D[9]
T_D[10]
T_D[11]
T_D[12]
B_A[12]
B_A[13]
B_A[14]
B_A[15]
B_A[16]
B_A[17]
B_A[18]
LB_A[20]
NC
H28
M27
H29
H30
G28
G27
K26
G29
G30
H27
F27
F28
F29
F30
J26
P_INT#
B_D[0]
B_D[1]
B_D[2]
B_D[3]
B_D[4]
B_D[5]
B_D[6]
B_D[7]
B_D[8]
B_D[9]
B_D[10]
B_D[11]
B_D[12]
B_D[13]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B_D[14]
B_D[15]
B_D[16]
B_D[17]
B_D[18]
B_D[19]
B_D[20]
B_D[21]
B_D[22]
B_D[23]
B_CLK
B_D[24]
B_D[25]
NC1
E14
C15
B15
E13
A15
D14
C14
D13
B14
A14
C13
E12
B13
A13
D12
C12
B12
A12
C11
H26
NC
E29
NC
E26
NC
D29
NC
E28
NC
G26
NC
D30
NC
C30
NC
E27
NC
NC
C29
NC
NC
D28
NC
NC
B30
NC
NC
F26
NC
NC
D26
NC2
NC
NC
A30
NC3
NC
NC
A29
NC4
NC
NC
B29
NC5
NC
NC
E25
AGND
NC
NC
Table 8 - Ball Signal Name (continued)
SEMICMF.019
118
Data Sheet
MVTX2801AG
Ball No.
Signal Name
DEV_CFG[1]
Ball No.
C20
Signal Name
Ball No.
E11
Signal Name
B28
C28
A28
A27
C27
D27
B27
E24
D25
B26
A26
A25
B25
C26
C25
E23
A24
B24
D23
D24
C24
B7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AVDD
B_D[26]
B_D[27]
B_D[28]
B_D[29]
B_D[30]
B_D[31]
B_ADSC#
B_WE#
B_OE#
B_A[2]
B_A[3]
B_A[4]
B_A[5]
B_A[6]
B_A[7]
B_A[8]
B_A[9]
B_A[10]
B_A[11]
NC
A19
B19
E18
C19
A18
D18
B18
C18
A17
E17
B17
C17
E16
D17
A16
B16
E15
C16
D16
D15
P15
P16
P17
P18
R13
R14
R15
R16
R17
R18
R25
R6
B11
A11
E10
C10
B10
E9
NC
NC
NC
NC
NC
NC
A10
D11
D10
D8
NC
NC
NC
NC
D9
NC
C9
NC
B9
NC
A9
NC
S_CLK
NC
C8
NC
B8
NC
NC
A8
NC
NC
C7
NC
NC
E7
NC
NC
D7
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE7
AE9
F10
F21
F22
F9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VD33
VD33
E8
NC
A7
NC
D6
NC
C6
NC
E6
NC
B6
NC
G25
G6
A6
NC
A5
NC
J25
J6
B5
NC
C5
NC
K25
K6
B4
NC
D5
NC
T13
T14
AE12
AE13
A4
NC
Table 8 - Ball Signal Name (continued)
SEMICMF.019
119
MVTX2801AG
Data Sheet
Ball No.
A3
Signal Name
Ball No.
T15
Signal Name
Ball No.
AE14
Signal Name
SCAN_EN
AGND
NC6
NC7
NC8
NC9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
VD33
E5
T16
AE17
AE18
AE19
F12
F13
F14
F17
F18
F19
M25
M6
C4
T17
B3
T18
D4
T25
A2
T6
AD6
AE15
AE16
AE24
AE25
AE6
F15
F16
F24
F25
F6
U13
U14
U15
U16
U17
U18
V13
V14
V15
V16
V17
V18
AA25
AA6
AB25
AB6
AD25
AE10
AE21
AE22
N25
N6
P25
P6
U25
U6
F7
N13
N14
N15
N16
N17
N18
P13
P14
V25
V6
W25
W6
Table 8 - Ball Signal Name (continued)
SEMICMF.019
120
Data Sheet
MVTX2801AG
11.5
AC/DC Timing
11.5.1
Absolute Maximum Ratings
Storage Temperature
-65oC to +150oC
-40oC to +85oC
+3.0 V to +3.6 V
Operating Temperature
Supply Voltage VDD33 with Respect to VSS
Supply Voltage VDD with Respect to VSS
Voltage on Input Pins
+2.38 V to +2.75 V
-0.5 V to (VDD33 + 3.3 V)
Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for
extended periods may affect device reliability. Functionality at or above these limits is not implied.
11.5.2
DC Electrical Characteristics
VDD33 = 3.0 V to 3.6 V (3.3v +/- 10%)
VDD = 2.5V +10% - 5%
TAMBIENT = -40oC to +85oC
11.5.3
Recommended Operation Conditions
Preliminary
Symbol
Parameter Description
Unit
Min
Type
133
Max
fosc
IDD1
Frequency of Operation
MHz
mA
Supply Current - @ 133 MHz
(VDD33 = 3.3V)
680
850
IDD2
Supply Current - @ 133 MHz
(VDD = 2.5V)
1300
1500
mA
VOH
Output High Voltage (CMOS)
VDD33 - 0.5
V
VOL
Output Low Voltage (CMOS)
0.5
V
VIH-TTL
VIL-TTL
IIH-5VT
Input High Voltage (TTL 5V tolerant)
Input Low Voltage (TTL 5V tolerant)
VDD33 x 70%
VDD33 + 2.0
VDD33 x 30%
10
V
V
Input Leakage Current (0.1 V < VIN
VDD33)
<
mA
IIL-5VT
Output Leakage Current
(0.1 V < VOUT < VDD33)
mA
CIN
Input Capacitance
Output Capacitance
I/O Capacitance
5
5
7
pF
pF
pF
COUT
CI/O
Table 9 - Recommended Operation Conditions
SEMICMF.019
121
MVTX2801AG
Data Sheet
11.6
Local Frame Buffer ZBT SRAM Memory Interface
11.6.1
Local ZBT SRAM Memory Interface A
LA_CLK
L1
L2
LA_D[63:0]
Figure 8 - Local Memory Interface - Input setup and hold timing
LA_CLK
L3-max
L3-min
LA_D[63:0]
L4-max
L4-min
LA_A[20:3]
L6-max
L6-min
LA_CS[1,0]#
L9-max
L9-min
LA_RW#
Figure 9 - Local Memory Interface - Output valid delay timing
(SCLK= 133MHz)
Parameter
Symbol
Min (ns)
Max (ns)
Note:
L1
L2
L3
L4
L6
L9
LA_D[63:0] input set-up time
LA_D[63:0] input hold time
LA_D[63:0] output valid delay
LA_A[20:3] output valid delay
LA_CS[1:0]# output valid delay
LA_WE# output valid delay
2.5
1
3
5
5
5
5
CL = 25pf
CL = 30pf
CL = 30pf
CL = 25pf
3
3
3
Table 10 - AC Characteristics - Local frame buffer ZBT-SRAM Memory Interface A
SEMICMF.019
122
Data Sheet
MVTX2801AG
11.7
Local Switch Database SBRAM Memory Interface
11.7.1
Local SBRAM Memory Interface
B_CLK
L1
L2
B_D[31:0]
Figure 10 - Local Memory Interface - Input setup and hold timing
B_CLK
L3-max
L3-min
B_D[31:0]
L4-max
L4-min
B_A[18:2]
L6-max
L6-min
B_ADSC#
L10-max
L10-min
B_WE#
L11-max
L11-min
B_OE#
Figure 11 - Local Memory Interface - Output valid delay timing
(SCLK= 133MHz)
Symbol
Parameter
Min (ns)
2.5
Max (ns)
Note:
L1
B_D[31:0] input set-up time
B_D[31:0] input hold time
B_D[31:0] output valid delay
B_A[18:2] output valid delay
B_ADSC# output valid delay
B_WE# output valid delay
B_OE# output valid delay
L2
1
3
3
3
3
3
L3
5
CL = 25pf
CL = 30pf
CL = 30pf
CL = 25pf
CL = 25pf
L4
5
5
5
4
L6
L10
L11
Table 11 - AC Characteristics - Local Switch Database SBRAM Memory Interface
SEMICMF.019
123
MVTX2801AG
Data Sheet
11.8
AC Characteristics
11.8.1
Media Independent Interface
MII_TXCLK[3:0]
M6-max
M6-min
G[3:0]_TXEN
M7-max
M7-min
G[3:0] _TXD[3:0]
Figure 12 - AC Characteristics - Media Independent Interface
G[3:0]_RXCLK
M2
G[3:0]_RXD[3:0]
M3
M4
G[3:0]_CRS_DV
M5
Figure 13 - AC Characteristics - Media Independent Interface
(MII_TXCLK & G_RXCLK = 25MHz)
Symbol Parameter
Min (ns)
Max (ns)
Note:
M2
M3
M4
M5
M6
M7
G[3:0]_RXD[3:0] Input Setup Time
G[3:0]_RXD[3:0] Input Hold Time
G[3:0]_CRS_DV Input Setup Time
G[3:0]_CRS_DV Input Hold Time
G[3:0]_TXEN Output Delay Time
G[3:0]_TXD[3:0] Output Delay Time
4
1
4
1
3
3
11
11
CL = 20 pF
CL = 20 pF
Table 12 - AC Characteristics - Media Independent Interface
SEMICMF.019
124
Data Sheet
MVTX2801AG
11.8.2
Gigabit Media Independent Interface
G[3:0]_TXCLK
G[3:0]_TXD[7:0]
G[3:0]_TX_EN
G[3:0]_TX_ER
G12-max
G12-min
G13-max
G13-min
G14-max
G14-min
Figure 14 - AC Characteristics- GMII
G[3:0]_RXCLK
G1
G3
G5
G7
G2
G4
G[3:0]_RXD[7:0]
G[3:0]_RX_DV
G[3:0]_RX_ER
G[3:0]_RX_CRS
G6
G8
Figure 15 - AC Characteristics - Gigabit Media Independent Interface
SEMICMF.019
125
MVTX2801AG
Data Sheet
(G_RCLK & G_REFCLK = 125MHz)
Min (ns) Max (ns)
Symbol
Parameter
Note:
G1
G[3:0]_RXD[7:0] Input Setup Times
G[3:0]_RXD[7:0] Input Hold Times
G[3:0]_RX_DV Input Setup Times
G[3:0]_RX_DV Input Hold Times
G[3:0]_RX_ER Input Setup Times
G[3:0]_RX_ER Input Hold Times
G[3:0]_CRS Input Setup Times
G[3:0]_CRS Input Hold Times
2
1
2
1
2
1
2
1
1
1
1
G2
G3
G4
G5
G6
G7
G8
G12
G13
G14
G[3:0]_TXD[7:0] Output Delay Times
G[3:0]_TX_EN Output Delay Times
G[3:0]_TX_ER Output Delay Times
5
5
5
CL = 20pf
CL = 20pf
CL = 20pf
Table 13 - AC Characteristics - Gigabit Media Independent Interface
11.8.3
PCS Interface
G[3:0]_TXCLK
G30-max
G30-min
G[3:0]_TXD[9:0]
Figure 16 - AC Characteristics - PCS Interface
G[3:0]_RXCLK1
G[3:0]_RXCLK
G[3:0]_RXD[9:0]
G[3:0]_RX_CRS
Figure 17 - AC Characteristics - PCS Interface
SEMICMF.019
126
Data Sheet
MVTX2801AG
(G_RCLK & G_REFCLK =
125MHz)
Min (ns)
2
Symbol
Parameter
Max (ns)
Note:
G21
G[3:0]_RXD[9:0] Input Setup Times ref to
G_RXCLK
G22
G23
G24
G[3:0]_RXD[9:0] Input Hold Times ref to
G_RXCLK
1
2
1
G[3:0]_RXD[9:0] Input Setup Times ref to
G_RXCLK1
G[3:0]_RXD[9:0] Input Hold Times ref to
G_RXCLK1
G25
G26
G30
G[3:0]_CRS Input Setup Times
G[3:0]_CRS Input Hold Times
G[3:0]_TXD[9:0] Output Delay Times
2
1
1
5
CL = 20pf
Table 14 - AC Characteristics - PCS Interface
11.8.4
LED Interface
LED_CLK
LE5-max
LE5-min
LED_SYN
LE6-max
LE6-min
LED_BIT
Figure 18 - AC Characteristics - LED Interface
Variable FREQ.
Symbol Parameter
Min (ns)
Max (ns)
Note:
LE5
LE6
LED_SYN Output Valid Delay
LED_BIT Output Valid Delay
1
1
7
7
CL = 30pf
CL = 30pf
Table 15 - AC Characteristics - LED Interface
SEMICMF.019
127
MVTX2801AG
Data Sheet
11.8.5
MDIO Input Setup and Hold Timing
MDC
D1
D2
MDIO
Figure 19 - MDIO Input Setup and Hold Timing
MDC
D3-max
D3-min
MDIO
Figure 20 - MDIO Output Delay Timing
1MHz
Symbol Parameter
Min (ns) Max (ns) Note:
D1
D2
D3
MDIO input setup time
MDIO input hold time
MDIO output delay time
10
2
1
20
CL = 50pf
Table 16 - MDIO Timing
2
11.8.6
I C Input Setup Timing
SCL
SDA
S1
S2
Figure 21 - I2C Input Setup Timing
SEMICMF.019
128
Data Sheet
MVTX2801AG
SCL
SDA
S3-max
S3-min
Figure 22 - I2C Output Delay Timing
500KHz
Symbol
S1
Parameter
Min (ns)
Max (ns)
Note:
SDA input setup time
SDA input hold time
SDA output delay time
20
1
S2
S3
1
20
CL = 30pf
Open Drain Output. Low to High transistor is controlled by external pullup resistor.
Table 17 - I2C Timing
11.8.7
Serial Interface Setup Timing
STROBE
D4
D5
D1
D1
D2
D2
PS_DI
Figure 23 - Serial Interface Setup Timing
STROBE
D3-max
D3-min
PS_DO
Figure 24 - Serial Interface Output Delay Timing
SEMICMF.019
129
MVTX2801AG
Data Sheet
Note:
(SCLK =133 MHz)
Min (ns)
Symbol
Parameter
Max (ns)
D1
D2
D3
D4
D5
PS_DI setup time
PS_DI hold time
20
10
PS_DO output delay time
Strobe low time
1
50
CL = 100pf
5ms
5ms
Strobe high time
Table 18 - Serial Interface Timing
12.0
12.1
Mechanical Data
Packaging Information
596 PIN BGA Packaging Diagram. 40 x 40 mm
SEMICMF.019
130
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
MVTX2802AG
DATACOM, LAN SWITCHING CIRCUIT, PBGA596, 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
MICROSEMI
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