MVTX2604AG [ZARLINK]
Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch; 网管24端口10/100兆+ 2端口1 Gb以太网交换机
| 型号： | MVTX2604AG |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| 文件： | 总173页 (文件大小：1994K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MVTX2604
Managed 24-Port 10/100 Mb + 2 Port 1 Gb
Ethernet Switch
Data Sheet
February 2004
Features
•
Integrated Single-Chip 10/100/1000 Mbps
Ordering Information
Ethernet Switch
•
24 10/100 Mbps Autosensing, Fast Ethernet
Ports with RMII or Serial Interface (7WS). Each
port can independently use one of the two
interfaces
MVTX2604AG
553 Pin HSBGA
-40°C to 85°C
•
•
•
2 Gigabit Ports with GMII, PCS, 10/100 and
•
Provides port based and ID tagged VLAN
support (IEEE 802.1Q), up to 255 VLANs
Supports IP Multicast with IGMP snooping
stacking (2 G per port) interface options per port
Stacking port supports hot swap in managed
•
•
configuration
Supports spanning tree with CPU, on per port or
Supports 8/16-bit CPU interface in managed
mode
per VLAN basis
Packet Filtering and Port Security
•
•
•
Serial interface in unmanaged mode
• Static address filtering for source and/or destination
MAC
• Static MAC address not subject to aging
Supports two Frame Buffer Memory domains with
SRAM at 100 MHz
•
Supports memory size 2 MB, or 4 MB
•
Secure mode freezes MAC address learning
• For 24 + 2, two SRAM domains (2 MB or 4 MB) are
required.
Each port may independently use this mode
•
•
•
Full Duplex Ethernet IEEE 802.3x Flow Control
Backpressure flow control for Half Duplex ports
• For 24 + 2 stacking (2 G per stacking port), two ZBT
domains (2 MB or 4 MB) are required
Supports Ethernet multicasting and broadcasting
•
•
•
•
Applies centralized shared memory architecture
Up to 64 K MAC addresses
and flooding control
•
Supports per-system option to enable flow
control for best effort frames even on QoS-
enabled ports
Maximum throughput is 6.4 Gbps non-blocking
High performance packet forwarding (19.047 M
packets per second) at full wire speed
Frame Data Buffer A
SRAM (1 M / 2 M)
Frame Data Buffer B
SRAM (1 M / 2 M)
FDB Interface
LED
Search
Engine
MCT
Link
Frame Engine
FCB
GMII/
PCS
Port
24
GMII/
24 x 10 / 100
Management
Module
16-bit
PCS
Port
25
RMII
Parallel /
Ports 0 - 23
Serial
Figure 1 - MVTX2604 System Block Diagram
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
MVTX2604
Data Sheet
•
Traffic Classification
• 4 transmission priorities for Fast Ethernet ports with 2 dropping levels
• Classification based on:
- Port based priority
- VLAN Priority field in VLAN tagged frame
- DS/TOS field in IP packet
- UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
The precedence of the above classifications is programmable
QoS Support
•
•
• Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and
WFQ service disciplines
• Provides 2 levels of dropping precedence with WRED mechanism
• User controls the WRED thresholds
• Buffer management: per class and per port buffer reservations
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID
•
•
•
•
3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10/100 ports, with up to 4 10/100
ports per group
Load sharing among trunked ports can be based on source MAC and/or destination MAC. The Gigabit
trunking group has one more option, based on source port
Port Mirroring to any two ports of 0-23 in managed mode or to a dedicated mirroring port or port 23 in
unmanaged mode
Full set of LED signals provided by a serial interface, or 6 LED signals dedicated to Gigabit port status only
(without serial interface)
•
•
Built-in MIB statistics counters
Recognizes Simple Bandwidth Management (SBM) and Resource Reservation Protocol (RSVP) packets
and forwards to CPU
•
•
•
•
•
Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports
Built-in reset logic triggered by system malfunction
Built-in self test for internal and external SRAM
2
I C EEPROM for configuration
553 BGA package
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Description
The MVTX2604 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 24 ports at 10/100 Mbps, 2 ports at 1000 Mbps and a CPU interface for managed and unmanaged switch
applications. The Gigabit ports can also support 10/100 M and 2 G stacking modes.
The chip supports up to 64 K MAC addresses and up to 255 port-based Virtual LANs (VLANs). The centralized
shared memory architecture permits a very high performance packet forwarding rate at up to 9.524 M packets per
second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching.
Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate
bandwidth of 12.8 Gbps to support full wire speed on all ports simultaneously. In the 24+2 stacking (2 G per
stacking port) configuration, 2 ZBT domains are needed.
With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the
MVTX2604 provides powerful QoS functions for various multimedia and mission-critical applications. The chip
provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is
assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged
frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The MVTX2604 recognizes a total of
16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).
The MVTX2604 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports,
and the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load
sharing can be used to group ports between interlinked switches to increase the effective network bandwidth.
In half-duplex mode all ports support backpressure flow control to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The MVTX2604 also supports a per-
system option to enable flow control for best effort frames, even on QoS-enabled ports.
The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to
SERDES chips. The PCS can be bypassed to provide a GMII interface.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are
collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface.
SNMP Management frames can be received and transmitted via the CPU interface creating a complete network
management solution.
The MVTX2604 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are
capable of directly interfacing to LVTTL levels. The MVTX2604 is packaged in a 553-pin Ball Grid Array package.
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Table of Contents
1.0 Bock Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1 Frame Data Buffer (FDB) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 GMII/PCS MAC Module (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Physical Coding Sublayer (PCS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4 10/100 MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5 CPU Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Management Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.7 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.8 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.9 LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.10 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.0 System Configuration (Stand-alone and Stacking) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Register Configuration, Frame Transmission, and Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.2 Rx/Tx of Standard Ethernet Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.3 Control Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 Unmanaged Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6.2 Read Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7 Stacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.0 MVTX2604 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Frame Forwarding To and From CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.0 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 ZBT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 Detailed Memory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Search, Learning, and Aging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.4 VLAN Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 MAC Address Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.5 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6 Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.7 Port and Tag Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.7.1 Port-Based VLAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Table of Contents
5.7.2 Tag-Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.8 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.3 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4 TxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1 Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 Four QoS Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3 Delay Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4 Strict Priority and Best Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6 Shaper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.7 Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.8 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.9 Buffer Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.9.1 Dropping When Buffers Are Scarce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.10 MVTX2604 Flow Control Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.10.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.10.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.11 Mapping to IETF Diffserv Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.4 Unmanaged Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.0 Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 Port Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 Setting Registers for Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.0 TBI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1 TBI Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.0 GPSI (7WS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.1 GPSI connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.2 SCAN LINK and SCAN COL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.0 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.1 LED Interface Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.2 Port Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.3 LED Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13.0 Hardware Statistics Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
13.2 IEEE 802.3 HUB Management (RFC 1516) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.2.1.1 Readablectet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.2.1.3 FCSErrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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13.2.1.5 FrameTooLongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.2.1.6 ShortEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.2.1.7 Runts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2.1.8 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2.1.9 LateEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2.1.10 VeryLongEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2.1.11 DataRateMisatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2.1.12 AutoPartitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.2.1.13 TotalErrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.3 IEEE – 802.1 Bridge Management (RFC 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3.1.1 InFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3.1.2 OutFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3.1.3 InDiscards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3.1.4 DelayExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3.1.5 MtuExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.4 RMON – Ethernet Statistic Group (RFC 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.4.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.4.1.1 Drop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.4.1.2 Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.4.1.3 BroadcastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.4.1.4 MulticastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.4.1.5 CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4.1.6 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4.1.7 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4.1.8 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4.1.9 Jabbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
13.4.1.10 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.4.1.11 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.0 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.1 MVTX2604 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.2.2 INDEX_REG1 (only needed for 8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.2.3 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.2.4 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.2.5 COMMAND&STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.2.6 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14.2.7 Control Command Frame Buffer1 Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14.2.8 Control Command Frame Buffer2 Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14.3 Indirectly Accessed registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14.4 Group 0 Address MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14.4.1 ECR1Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
14.4.2 ECR2Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.4.3 GGControl – Extra GIGA Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.5 Group 1 Address VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.5.1 AVTCL – VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.5.2 AVTCH – VLAN Type Code Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.5.3 PVMAP00_0 – Port 00 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.5.4 PVMAP00_1 – Port 00 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.5.5 PVMAP00_2 – Port 00 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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14.5.6 PVMAP00_3 – Port 00 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.6 Port Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.6.1 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.6.2 PVROUTE 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.6.3 PVROUTE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.6.4 PVROUTE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.6.5 PVROUTE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.6.6 PVROUTE4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.6.7 PVROUTE5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.6.8 PVROUTE6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.6.9 PVROUTE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.7 Group 2 Address Port Trunking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.7.1 TRUNK0_L – Trunk group 0 Low (Managed mode only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.7.2 TRUNK0_M – Trunk group 0 Medium (Managed mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.7.3 TRUNK0_H – Trunk group 0 High (Managed mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.7.4 TRUNK0_MODE– Trunk group 0 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.7.5 TRUNK0_HASH0 – Trunk group 0 hash result 0 destination port number . . . . . . . . . . . . . . . . . . 78
14.7.6 TRUNK0_HASH1 – Trunk group 0 hash result 1 destination port number . . . . . . . . . . . . . . . . . . 78
14.7.7 TRUNK0_HASH2 – Trunk group 0 hash result 2 destination port number . . . . . . . . . . . . . . . . . . 78
14.7.8 TRUNK0_HASH3 – Trunk group 0 hash result 3 destination port number . . . . . . . . . . . . . . . . . . 79
14.7.9 TRUNK1_L – Trunk group 1 Low (Managed mode only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.7.10 TRUNK1_M – Trunk group 1 Medium (Managed mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.7.11 TRUNK1_H – Trunk group 1 High (Managed mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.7.12 TRUNK1_MODE – Trunk group 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.7.13 TRUNK1_HASH0 – Trunk group 1 hash result 0 destination port number . . . . . . . . . . . . . . . . . 80
14.7.14 TRUNK1_HASH1 – Trunk group 1 hash result 1 destination port number . . . . . . . . . . . . . . . . . 80
14.7.15 TRUNK1_HASH2 – Trunk group 1 hash result 2 destination port number . . . . . . . . . . . . . . . . . 80
14.7.16 TRUNK1_HASH3 – Trunk group 1 hash result 3 destination port number . . . . . . . . . . . . . . . . . 80
14.7.17 TRUNK2_MODE – Trunk group 2 mode (Gigabit ports 1 and 2). . . . . . . . . . . . . . . . . . . . . . . . . 80
14.7.18 TRUNK2_HASH0 – Trunk group 2 hash result 0 destination port number . . . . . . . . . . . . . . . . . 81
14.7.19 TRUNK2_HASH1 – Trunk group 2 hash result 1 destination port number . . . . . . . . . . . . . . . . . 81
14.7.20 Multicast Hash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
14.7.20.1 Multicast_HASH0-1 – Multicast hash result 0 mask byte 1. . . . . . . . . . . . . . . . . . . . . . . . 82
14.7.20.2 Multicast_HASH0-2 – Multicast hash result 0 mask byte 2. . . . . . . . . . . . . . . . . . . . . . . . 82
14.7.20.3 Multicast_HASH0-3 – Multicast hash result 0 mask byte 3. . . . . . . . . . . . . . . . . . . . . . . . 82
14.7.20.4 Multicast_HASH1-0 – Multicast hash result 1 mask byte 0. . . . . . . . . . . . . . . . . . . . . . . . 82
14.7.20.5 Multicast_HASH1-1 – Multicast hash result 1 mask byte 1. . . . . . . . . . . . . . . . . . . . . . . . 82
14.7.20.6 Multicast_HASH1-2 – Multicast hash result 1 mask byte 2. . . . . . . . . . . . . . . . . . . . . . . . 82
14.7.20.7 Multicast_HASH1-3 – Multicast hash result 1 mask byte 3. . . . . . . . . . . . . . . . . . . . . . . . 82
14.7.20.8 Multicast_HASH2-0 – Multicast hash result 2 mask byte 0. . . . . . . . . . . . . . . . . . . . . . . . 83
14.7.20.9 Multicast_HASH2-1 – Multicast hash result 2 mask byte 1. . . . . . . . . . . . . . . . . . . . . . . . 83
14.7.20.10 Multicast_HASH2-2 – Multicast hash result 2 mask byte 2. . . . . . . . . . . . . . . . . . . . . . . 83
14.7.20.11 Multicast_HASH2-3 – Multicast hash result 2 mask byte 3. . . . . . . . . . . . . . . . . . . . . . . 83
14.7.20.12 Multicast_HASH3-0 – Multicast hash result 3 mask byte 0. . . . . . . . . . . . . . . . . . . . . . . 83
14.7.20.13 Multicast_HASH3-1 – Multicast hash result 3 mask byte 1. . . . . . . . . . . . . . . . . . . . . . . 83
14.7.20.14 Multicast_HASH3-2 – Multicast hash result 3 mask byte 2. . . . . . . . . . . . . . . . . . . . . . . 83
14.7.20.15 Multicast_HASH3-3 – Multicast hash result 3 mask byte 3. . . . . . . . . . . . . . . . . . . . . . . 84
14.8 Group 3 Address CPU Port Configuration Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.8.1 MAC0 – CPU Mac address byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.8.2 MAC1 – CPU Mac address byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.8.3 MAC2 – CPU Mac address byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.8.4 MAC3 – CPU Mac address byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Table of Contents
14.8.5 MAC4 – CPU Mac address byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.8.6 MAC5 – CPU Mac address byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.8.7 INT_MASK0 – Interrupt Mask 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.8.8 INTP_MASK0 – Interrupt Mask for MAC Port 0,1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
14.8.9 INTP_MASK1 – Interrupt Mask for MAC Port 2,3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.10 INTP_MASK2 – Interrupt Mask for MAC Port 4,5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.11 INTP_MASK3 – Interrupt Mask for MAC Port 6,7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.12 INTP_MASK4 – Interrupt Mask for MAC Port 8,9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.13 INTP_MASK5 – Interrupt Mask for MAC Port 10,11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.14 INTP_MASK6 – Interrupt Mask for MAC Port 12,13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.15 INTP_MASK7 – Interrupt Mask for MAC Port 14,15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.16 INTP_MASK8 – Interrupt Mask for MAC Port 16,17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.17 NTP_MASK9 – Interrupt Mask for MAC Port 18,19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
14.8.18 INTP_MASK10 – Interrupt Mask for MAC Port 20,21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14.8.19 INTP_MASK11 – Interrupt Mask for MAC Port 22,23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14.8.20 INTP_MASK12 – Interrupt Mask for MAC Port G1,G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14.8.21 RQS – Receive Queue Select CPU Address:h323). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
14.8.22 RQSS – Receive Queue Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.8.23 TX_AGE – Tx Queue Aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.9 Group 4 Address Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.9.1 AGETIME_LOW – MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.9.2 AGETIME_HIGH –MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
14.9.3 V_AGETIME – VLAN to Port aging time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.9.4 SE_OPMODE – Search Engine Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14.9.5 SCAN – SCAN Control Register (default 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.10 Group 5 Address Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.10.1 FCBAT – FCB Aging Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
14.10.2 QOSC – QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
14.10.3 FCR – Flooding Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
14.10.4 AVPML – VLAN Tag Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.10.5 AVPMM – VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.10.6 AVPMH – VLAN Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.10.7 TOSPML – TOS Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14.10.8 TOSPMM – TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14.10.9 TOSPMH – TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14.10.10 AVDM – VLAN Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
14.10.11 TOSDML – TOS Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.10.12 BMRC - Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.10.13 UCC – Unicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.10.14 MCC – Multicast Congestion Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.10.15 PR100 – Port Reservation for 10/100 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.10.16 PRG – Port Reservation for Giga ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.10.17 SFCB – Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.10.18 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.10.19 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.10.20 C4RS – Class 4 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.10.21 C5RS – Class 5 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.10.22 C6RS – Class 6 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.10.23 C7RS – Class 7 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.10.24 QOSCn - Classes Byte Limit Set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.10.25 Classes Byte Limit Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
14.10.26 Classes Byte Limit Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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14.10.27 Classes Byte Limit Set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14.10.28 Classes Byte Limit Giga Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14.10.29 Classes Byte Limit Giga Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
14.10.30 Classes WFQ Credit Set 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14.10.31 Classes WFQ Credit Set 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14.10.32 Classes WFQ Credit Set 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14.10.33 Classes WFQ Credit Set 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14.10.34 Classes WFQ Credit Port G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14.10.35 Classes WFQ Credit Port G2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
14.10.36 Class 6 Shaper Control Port G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
14.10.37 Class 6 Shaper Control Port G2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
14.10.38 RDRC0 – WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14.10.39 RDRC1 – WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14.10.40 User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14.10.40.1 USER_PORT0_(0~7) – User Define Logical Port (0~7) . . . . . . . . . . . . . . . . . . . . . . . . 105
14.10.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority . . . . . . . . . . 105
14.10.40.3 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority . . . . . . . . . . 106
14.10.40.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority . . . . . . . . . . 106
14.10.40.5 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority . . . . . . . . . . 106
14.10.40.6 USER_PORT_ENABLE[7:0] – User Define Logic 7 to 0 Port Enables . . . . . . . . . . . . . 106
14.10.40.7 WELL_KNOWN_PORT[1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . 106
14.10.40.8 WELL_KNOWN_PORT[3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . 107
14.10.40.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . 107
14.10.40.10 WELL_KNOWN_PORT [7:6] PRIORITY- Well Known Logic Port 7 and 6 Priority . . . 107
14.10.40.11 WELL KNOWN_PORT_ENABLE [7:0] – Well Known Logic 7 to 0 Port Enables . . . . 108
14.10.40.12 RLOWL – User Define Range Low Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.10.40.13 RLOWH – User Define Range Low Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.10.40.14 RHIGHL – User Define Range High Bit 7:0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.10.40.15 RHIGHH – User Define Range High Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.10.40.16 RPRIORITY – User Define Range Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.10.41 CPUQOSC123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.11 Group 6 Address MISC Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.11.1 MII_OP0 – MII Register Option 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.11.2 MII_OP1 – MII Register Option 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
14.11.3 FEN – Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
14.11.4 MIIC0 – MII Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
14.11.5 MIIC1 – MII Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
14.11.6 MIIC2 – MII Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.11.7 MIIC3 – MII Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.11.8 MIID0 – MII Data Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.11.9 MIID1 – MII Data Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.11.10 LED Mode – LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.11.11 DEVICE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.11.12 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
14.12 Group 7 Address Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.12.1 MIRROR1_SRC - Port Mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.12.2 MIRROR1_DEST – Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.12.3 MIRROR2_SRC – Port Mirror source port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
14.12.4 MIRROR2_DEST – Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.13 Group F Address CPU Access Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.13.1 GCR-Global Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
14.13.2 DCR-Device Status and Signature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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14.3.13 DCR1-Giga port status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
14.3.14 DPST – Device Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
14.3.15 DTST – Data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.3.16 DA – DA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.4 TBI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.4.1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14.4.2 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
14.4.3 Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.4.4 Link Partner Ability Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.4.5 Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.4.6 Extended Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
15.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
15.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
15.1.1 Encapsulated view in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
15.1.2 Encapsulated view in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
15.2 Ball – Signal Descriptions in Managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
15.2.1 Ball Signal Descriptions in Managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
15.2.2 Ball – Signal Descriptions in Unmanaged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
15.3 Ball – Signal Name in Unmanaged Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.4 Ball – Signal Name in Managed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
15.5 AC/DC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.5.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.5.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15.5.4 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
15.5.5 Typical CPU Timing Diagram for a CPU Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
15.5.6 Typical CPU Timing Diagram for a CPU Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.6 Local Frame Buffer SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.6.1 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
15.7 Local Switch Database SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
15.7.1 Local SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
15.8 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
15.8.1 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
15.8.2 Gigabit Media Independent Interface - Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
15.8.3 Ten Bit Interface - Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
15.8.4 Gigabit Media Independent Interface - Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
15.8.5 Ten Bit Interface - Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.8.6 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
15.8.7 SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
15.9 MDIO Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
15.9.1 I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
15.9.2 Serial Interface Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
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MVTX2604
Data Sheet
List of Figures
Figure 1 - MVTX2604 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Overview of the MVTX2604 CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3 - Data Transfer Format for I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4 - MVTX2604 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only) . . . . . . . . . . . . . . . . . . . . 24
Figure 5 - Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 6 - Memory Configuration For: 2 Banks, 1 Layer, 2 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7 - Memory Configuration For: 2 Banks, 2 Layers, 4 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9 - Memory Configuration For: 2 Banks, 2 Layers, 4 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11 - Buffer Partition Scheme Used to Implement MVTX2604 AG Buffer Management . . . . . . . . . . . . . . . 41
Figure 12 - TBI Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 13 - GPSI (7WS) Mode Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 14 - SCAN LINK and SCAN COLLISON Status Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 15 - Timing Diagram of LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 16 - Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 17 - Typical CPU Timing Diagram for a CPU Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 18 - Typical CPU Timing Diagram for a CPU Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 19 - Local Memory Interface – Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 20 - Local Memory Interface - Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 21 - Local Memory Interface – Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 22 - Local Memory Interface - Output Valid Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 23 - AC Characteristics – Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 24 - AC Characteristics – Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 25 - AC Characteristics- GMII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 26 - AC Characteristics – Gigabit Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 27 - Gigabit TBI Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 28 - Gigabit TBI Interface Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 29 - AC Characteristics- GMII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 30 - AC Characteristics – Gigabit Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 31 - Gigabit TBI Interface Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 32 - Gigabit TBI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 33 - AC Characteristics – LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 34 - SCANLINK SCANCOL Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 35 - SCANLINK, SCANCOL Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 36 - MDIO Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 37 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 38 - I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 39 - I2C Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 40 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 41 - Serial Interface Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
List of Tables
Table 1 - VLAN Index Mapping Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 2 - LAN Index Port Association Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 3 - PVMAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4 - Supported Memory Configurations (SBRAM Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5 - Supported Memory Configurations (ZBT Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6 - Options for Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7 - Two-dimensional World Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8 - Four QoS Configurations for a 10/100 Mbps Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9 - Four QoS Configurations for a Gigabit Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10 - WRED Drop Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11 - Mapping between MVTX2604 and IETF Diffserv Classes for Gigabit Ports . . . . . . . . . . . . . . . . . . . . . 43
Table 12 - Mapping between MVTX2604 and IETF Diffserv Classes for 10/100 Ports . . . . . . . . . . . . . . . . . . . . . 43
Table 13 - MVTX2604 Features Enabling IETF Diffserv Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 14 - Reset & Bootstrap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 15 - AC Characteristics – Local Frame Buffer SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 16 - AC Characteristics – Local Switch Database SBRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . 163
Table 17 - AC Characteristics – Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 18 - AC Characteristics – Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 19 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 20 - Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 21 - AC Characteristics – Gigabit Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 22 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 23 - Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 24 - AC Characteristics – LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 25 - SCANLINK, SCANCOL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 26 - MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 27 - I2C Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 28 - Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
1.0 Bock Functionality
1.1 Frame Data Buffer (FDB) Interfaces
The FDB interface supports pipelined synchronous burst SRAM (SBRAM) memory at 100 MHz. To ensure a non-
blocking switch two memory domains are required. Each domain has a 64 bit wide memory bus. At 100 MHz, the
aggregate memory bandwidth is 12.8 Gbps which is enough to support 24 10/100 Mbps and 2 Gigabit ports at full
wire speed switching. For 24 + 2 stacking application, pipelined ZBT-SRAM memory running at 125 MHz is
required.
The Switching Database is also located in the external SRAM; it is used for storing MAC addresses and their
physical port number. It is duplicated and stored in both memory domains. Therefore, when the system updates the
contents of the switching database it has to write the entry to both domains at the same time.
1.2 GMII/PCS MAC Module (GMAC)
The GMII/PCS Media Access Control (MAC) module provides the necessary buffers and control interface between
the Frame Engine (FE) and the external physical device (PHY).
The MVTX2604 GMAC implements both GMII and MII interface, which offers a simple migration from 10/100 to 1 G.
The GMAC of the MVTX2604 meets the IEEE 802.3Z specification. It is able to operate in 10 M/100 M either Half or
Full Duplex mode with a back pressure/flow control mechanism or in 1G Full duplex mode with flow control
mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. PHY
addresses for GMAC are 01h and 02h.
For fiber optics media, the MVTX2604 implements the Physical Code Sublayer (PCS) interface. The PCS includes
an 8B10B encoder and decoder, auto-negotiation and Ten Bit Interface (TBI)
1.3 Physical Coding Sublayer (PCS) Interface
For the MVTX2604, the 1000BASE-X PCS Interface is designed internally and may be utilized in the absence of a
GMII. The PCS incorporates all the functions required by the GMII to include encoding (decoding) 8B GMII data to
(from) 8B/10B TBI format for PHY communication and generating Collision Detect (COL) signals for half-duplex
mode. It also manages the Auto negotiation process by informing the management entity that the PHY is ready for
communications. The on-chip TBI may be disabled if TBI exists within the Gigabit PHY. The TBI interface provides
a uniform interface for all 1000 Mbps PHY implementations.
The PCS comprises the PCS Transmit, Synchronization, PCS Receive and Auto negotiation processes for
1000BASE-X.
The PCS Transmit process sends the TBI signals TXD [9:0] to the physical medium and generates the GMII
Collision Detect (COL) signal based on whether a reception is occurring simultaneously with transmission.
Additionally, the Transmit process generates an internal “transmitting” flag and monitors Auto negotiation to
determine whether to transmit data or to reconfigure the link.
The PCS Synchronization process determines whether or not the receive channel is operational.
The PCS Receive process generates RXD [7:0] on the GMII from the TBI data [9:0], and the internal “receiving” flag
for use by the Transmit processes.
The PCS Auto negotiation process allows the MVTX2604 to exchange configuration information between two
devices that share a link segment and to automatically configure the link for the appropriate speed of operation for
both devices.
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MVTX2604
Data Sheet
1.4 10/100 MAC Module (RMAC)
The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame
Engine (FE) and the external physical device (PHY). The MVTX2604 has two interfaces, RMII or Serial (only for
10 M). The 10/100 MAC of the MVTX2604 device meets the IEEE 802.3 specification. It is able to operate in either
Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit
upon collision for up to 16 total transmissions. The PHY addresses for 24 10/100 MAC are from 08h to 1Fh.
1.5 CPU Interface Module
One extra port is dedicated to the CPU via the CPU interface module. The CPU interface utilizes a 16/8-bit bus in
2
managed mode (Bootstrap pin TSTOUT6 makes the selection). It also supports a serial and an I C interface, which
provides an easy way to configure the system if unmanaged.
1.6 Management Module
The CPU can send a control frame to access or configure the internal network management database. The
Management Module decodes the control frame and executes the functions requested by the CPU.
1.7 Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame
arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request which is sent to
the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch
response from the search engine, the frame engine performs transmission scheduling based on the frame’s priority.
The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
1.8 Search Engine
The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2) or
IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority
assignment and trunking functions.
1.9 LED Interface
The LED interface provides a serial interface for carrying 24 + 2 port status signals. It can also provide direct status
pins (6) for the two Gigabit ports.
1.10 Internal Memory
Several internal tables are required and are described as follows:
•
•
•
Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame
stored in the FDB, e.g., frame size, read/write pointer, transmission priority, etc.
Network Management (NM) Database - The NM database contains the information in the statistics counters
and MIB.
MAC address Control Table (MCT) Link Table - The MCT Link Table stores the linked list of MCT entries that
have collisions in the external MAC Table.
Note that the external MAC table is located in the external SRAM Memory.
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MVTX2604
2.0 System Configuration (Stand-alone and Stacking)
2.1 Management and Configuration
Data Sheet
Two modes are supported in the MVTX2604: managed and unmanaged. In managed mode, the MVTX2604 uses
an 8 or 16 bit CPU interface very similar to the Industry Standard Architecture (ISA) specification. In unmanaged
2
mode, the MVTX2604 has no CPU but can be configured by EEPROM using an I C interface at bootup, or via a
synchronous serial interface otherwise.
2.2 Managed Mode
In managed mode, the MVTX2604 uses an 8 or 16 bit CPU interface very similar to the ISA bus. The MVTX2604
CPU interface provides for easy and effective management of the switching system. Figure 2 provides an overview
of the CPU interface.
INDEX REG 1
(Addr = 001)
INDEX REG 0
(Addr = 000)
FRAME DATA REG
(Addr = 011)
CONFIG
CONTROL
BLOCK REG
DATA REG
(Addr = 010)
8/16 bit internal
data bus
8 bit internal
data bus
8/16 bit internal
data bus
16 bit internal
address bus
CPU
FRAME
TRANSMIT
FIFO
CONTROL
COMMAND
FRAME
CONTROL
CPU
FRAME
RECEIVE
FIFO
INTERNAL
COMMAND
FRAME
CONFIGURE
REGISTERS
RECEIVE
FIFO
TRANSMIT
FIFO
1 AND 2
SYNOCHRONOUS
SERIAL
INTERFACE
Figure 2 - Overview of the MVTX2604 CPU Interface
2.3 Register Configuration, Frame Transmission, and Frame Reception
2.3.1 Register Configuration
The MVTX2604 has many programmable parameters, covering such functions as QoS weights, VLAN control and
port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters.
The parameters are contained in 8-bit configuration registers. The MVTX2604 allows indirect access to these
registers, as follows:
•
If operating in 8 bits-interface mode, two “index” registers (addresses 000 and 001) need to be written to
indicate the desired 8-bit register address. In 16-bit mode, only one register (address 000) needs to be
written for the desired 16-bit register address.
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
•
•
To indirectly configure the register addressed by the two index registers, a “configure data” register (address
010) must be written with the desired 8-bit data.
Similarly, to read the value in the register addressed by the two index registers, the “configure data” register
can now simply be read.
In summary, access to the many internal registers is carried out simply by directly accessing only three registers –
two registers to indicate the address of the desired parameter, and one register to read or write a value. Of course,
because there is only one bus master, there can never be any conflict between reading and writing the
configuration registers.
2.3.2 Rx/Tx of Standard Ethernet Frames
The CPU interface is also responsible for receiving and transmitting standard Ethernet frames to and from the CPU.
To transmit a frame from the CPU:
•
The CPU writes a “data frame” register (address 011) with the data it wants to transmit (minimum 64 bytes).
After writing all the data, it then writes the frame size, destination port number and frame status.
•
The MVTX2604 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact
that the frame originated from the CPU.
To receive a frame into the CPU:
•
•
The CPU receives an interrupt when an Ethernet frame is available to be received.
Frame information arrives first in the data frame register. This includes source port number, frame size and
VLAN tag.
•
The actual data follows the frame information. The CPU uses the frame size information to read the frame
out.
In summary, receiving and transmitting frames to and from the CPU is a simple process that uses one direct access
register only.
2.3.3 Control Frames
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle
special “Control frames,” generated by the MVTX2604 and sent to the CPU. These proprietary frames are related
to such tasks as statistics collection, MAC address learning and aging etc. All Control frames are up to 40 bytes
long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that
the register accessed is the “Control frame data” register (address 111).
Specifically, there are eight types of control frames generated by the CPU and sent to the MVTX2604:
•
•
•
•
•
•
•
•
Memory read request
Memory write request
Learn MAC address
Delete MAC address
Search MAC address
Learn IP Multicast address
Delete IP Multicast address
Search IP Multicast address
Note: Memory read and write requests by the CPU may include VLAN table, spanning tree, statistic counters and
similar updates.
In addition, there are nine types of Control frames generated by the MVTX2604 and sent to the CPU:
•
Interrupt CPU when statistics counter rolls over
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Data Sheet
•
•
•
•
•
•
•
•
Response to memory read request from CPU
Learn MAC address
Delete MAC address
Delete IP Multicast address
New VLAN port
Age out VLAN port
Response to search MAC address request from CPU
Response to search IP Multicast address request from CPU
The format of the Control Frame is described in the processor interface application note.
2.4 Unmanaged Mode
2
In unmanaged mode, the MVTX2604 can be configured by EEPROM (24C02 or compatible) via an I C interface at
boot time, or via a synchronous serial interface during operation.
2.5 I2C Interface
2
The I C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer.
Figure 3 depicts the data transfer format.
START
SLAVE ADDRESS
R/W
ACK
DATA 1 (8 bits)
ACK
DATA 2
ACK
DATA M
ACK
STOP
2
Figure 3 - Data Transfer Format for I C Interface
2.5.1 Start Condition
Generated by the master (in our case, the MVTX2604). The bus is considered to be busy after the Start condition is
generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line.
Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High
2
period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I C bus is
free, both lines are High.
2.5.2 Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the
EEPROM. The first seven bits of the first data byte make up the slave address.
2.5.3 Data Direction
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master
transmitter sets this bit to W; a master receiver sets this bit to R.
2.5.4 Acknowledgment
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter
releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the
SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An
acknowledgment pulse follows every byte transfer.
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If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the
transfer.
If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let
the master generate the Stop condition.
2.5.5 Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an
acknowledge bit. Data is transferred MSB first.
2.5.6 Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition
occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
2
The I C interface serves the function of configuring the MVTX2604 at boot time. The master is the MVTX2604 and
the slave is the EEPROM memory.
2.6 Synchronous Serial Interface
The synchronous serial interface serves the function of configuring the MVTX2604, not at boot time, but via a PC.
The PC serves as master and the MVTX2604 serves as slave. The protocol for the synchronous serial interface is
2
nearly identical to the I C protocol. The main difference is that there is no acknowledgment bit after each byte of
data transferred.
The unmanaged MVTX2604 uses a synchronous serial interface to program the internal registers. To reduce the
number of signals required, the register address, command and data are shifted in serially through the D0 pin.
STROBE- pin is used as the shift clock. AUTOFD- pin is used as data return path.
Each command consists of four parts.
•
•
•
•
START pulse
Register Address
Read or Write command
Data to be written or read back
Any command can be aborted in the middle by sending a ABORT pulse to the MVTX2600AG.
A START command is detected when D0 is sampled high when STROBE- rise and D0 is sampled low when
STROBE- fall.
An ABORT command is detected when D0 is sampled low when STROBE- rise and D0 is sampled high when
STROBE- fall.
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Data Sheet
2.6.1 Write Command
STROBE-
2 extra clock cycles after
lasttraloftl
nsfer
D0
A0 A1
A
2
... A9 A10 A11
D0 D1 D2 D3 D4 D5 D6 D7
W
START
ADDRESS
COMMAND
DATA
2.6.2 Read Command
STROBE-
R
COMMAND
D0 D1
A0 A1 A2
...
A9 A10 A11
D0
START
ADDRESS
DATA
D4
D7
D5 D6
AUTOFD-
D2 D3
All registers in MVTX2600AG can be modified through this synchronous serial interface.
2.7 Stacking
The MVTX2604 supports expanded port count by providing stacking capabilities. The Gigabit port is used as the
link between boxes, and each Gigabit port can be accelerated to 2 Gpbs if desired (in conjunction with ZBT memory
domains at 125 MHz). If both Gigabit ports are used for this purpose, this provides a total of 4 Gbps of bandwidth
between devices.
In addition to a standard back-to-back configuration of devices, the MVTX2604 also provides more powerful
stacking alternatives:
•
Unidirectional ring configuration. Up to 32 devices. Devices are connected by one Gigabit link, which can be
accelerated to 2 Gbps, if desired. Flow control cannot be enabled in this configuration, because of the
inherent inefficiency in sending flow control messages upstream in a unidirectional ring.
Bidirectional ring configuration. Up to 32 devices. Devices are connected by two Gigabit links, forming two
rings, one clockwise and one counter clockwise. The total outgoing bandwidth can be as much as 4 Gbps.
Flow control may be enabled in this configuration. The outgoing direction of a packet (clockwise or counter
clockwise) is selected using a hash key for load distribution. The hash key can be a function of source MAC
address, destination MAC address, both MAC addresses, or source port. This configuration provides fault-
tolerance when one of the stacking links fail.
•
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Data Sheet
. . .
MVTX2600
MVTX2600
MVTX2600
•
Cascade Stacking configuration. Up to 32 devices. Devices are connected to form a list configuration.
Devices are connected by two Gigabit links, except the two devices at both ends, where one Gigabit port is
used as an uplink port. Flow control may be enabled in this configuration.
. . .
MVTX2600
MVTX2600
MVTX2600
3.0 MVTX2604 Data Forwarding Protocol
3.1 Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available because of advance buffer reservations.
The memory (SRAM) interface consists of two 64-bit buses, connected to two SRAM banks, A and B. The Receive
DMA (RxDMA) is responsible for multiplexing the data and the address. On a port’s “turn,” the RxDMA will move 8
bytes (or up to the end-of-frame) from the port’s associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response
queue of the frame engine when done. Among other information, the search engine will have resolved the
destination port of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to
decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy
at the destination. If the frame is not dropped, then the TxQ manager links the frame’s FCB to the correct per-port-
per-class TxQ. Unicast TxQ’s are linked lists of transmission jobs, represented by their associated frames’ FCB’s.
There is one linked list for each transmission class for each port. There are 4 transmission classes for each of the
24 10/100 ports and 8 classes for each of the two Gigabit ports – a total of 112 unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a
port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for
another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among
the head-of-line (HOL) frames from the per-class queues for that port using a Zarlink Semiconductor scheduling
algorithm.
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The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port’s turn, the
TxDMA will move 8 bytes (or up to the EOF) from memory into the port’s associated TxFIFO. After reading the EOF,
the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release
requests.
The frame is transmitted from the TxFIFO to the line.
3.2 Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop
can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is
dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of
the multicast packet’s destinations. If so, then the frame is dropped at some destinations but not others and the
FCB is not released.
If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast
queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames).
There are 2 multicast queues for each of the 24 10/100 ports. The queue with higher priority has room for 32 entries
and the queue with lower priority has room for 64 entries. There are 4 multicast queues for each of the two Gigabit
ports. The size of the queues are: 32 entries (higher priority queue), 32 entries, 32 entries and 64 entries (lower
priority queue). There is one multicast queue for every two priority classes. For the 10/100 ports to map the 8
transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the gigabit ports to map the 8 transmit
priorities into 4 multicast queues, the LSB are discarded.
During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one
logical queue. The older head of line of the two queues is forwarded first.
The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to
which the frame is destined.
3.3 Frame Forwarding To and From CPU
Frame forwarding from the CPU port to a regular transmission port is nearly the same as forwarding between
transmission ports. The only difference is that the physical destination port must be indicated in addition to the
destination MAC address.
Frame forwarding to the CPU port is nearly the same as forwarding to a regular transmission port. The only
difference is in frame scheduling. Instead of using the patent-pending Zarlink Semiconductor scheduling algorithms,
scheduling for the CPU port is simply based on strict priority. That is, a frame in a high priority queue will always be
transmitted before a frame in a lower priority queue. There are four output queues to the CPU and one receive
queue.
4.0 Memory Interface
4.1 Overview
The MVTX2604 provides two 64-bit wide SRAM banks, SRAM Bank A and SRAM Bank B with a 64-bit bus
connected to each. Each DMA can read and write from both bank A and bank B. The following figure provides an
overview of the MVTX2604 SRAM banks.
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MVTX2604
Data Sheet
SRAM
SRAM
TX DMA
0-7
TX DMA
8-15
TX DMA
16-23
RX DMA
0-7
RX DMA
8-15
RX DMA
16-23
Figure 4 - MVTX2604 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only)
4.2 ZBT Support
The MVTX2604 supports Zero Bus Turnaround (ZBT). ZBT is a synchronous SRAM architecture that is optimized
for networking and telecommunications applications. It can significantly increase the switch’s internal bandwidth
when compared to standard Pipeline SyncBurst SRAM.
The ZBT architecture is optimized for switching and other applications with highly random READs and WRITEs.
ZBT SRAMs eliminate all idle cycles when turning the data bus around from a WRITE operation to a READ
operation (or vice versa). This feature results in dramatic performance improvements in systems that have such
traffic patterns (that is, frequent and random read and write access to the SRAM).
Please refer to the ZBT Application Note for further details.
4.3 Detailed Memory Information
Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from
memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B and so on
in alternating fashion. When reading frames from memory, the same procedure is followed, first from A, then from B
and so on.
The reading and writing from alternating memory banks can be performed with minimal waste of memory
bandwidth. What’s the worst case? For any speed port, in the worst case, a 1-byte-long EOF granule gets written
to Bank A. This means that a 7-byte segment of Bank A bandwidth is idle, and furthermore, the next 8-byte
segment of Bank B bandwidth is idle, because the first 8 bytes of the next frame will be written to Bank A, not B.
This scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the
interframe gap is 20 bytes.
The CPU management port gets treated like any other port, reading and writing to alternating memory banks
starting with Bank A. The VLAN Index Mapping Table and Mac Address Table are duplicated in Bank A and B.
When the CPU writes an entry to the VLAN Index Mapping Table it has to write the same data in bank A and bank
B. Search engine data is written to both banks in parallel. In this way, a search engine read operation can be
performed by either bank at any time without a problem.
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MVTX2604
Data Sheet
4.4 Memory Requirements
To speed up searching and decrease memory latency, the external MAC address database is duplicated in both
memory banks. To support 64 K MAC address, 4 MB memory is required. When VLAN support is enabled, 512
entries of the MAC address table are used for storing the VLAN ID at VLAN Index Mapping Table.
Up to 2 K Ethernet frame buffers are supported and they will use 3 MB of memory. Each frame uses 1536 bytes.
The maximum system memory requirement is 4 MB. If less memory is desired, the configuration can scale down.
Memory Configuration
Bank A
1 M
Bank B
1 M
Tag based VLAN
Frame Buffer
1 K
Max MAC Address
Disable
Enable
Disable
Enable
32 K
1 M
2 M
2 M
1 M
2 M
2 M
1 K
2 K
2 K
31.5 K
64 K
63.5 K
Memory Map
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Data Sheet
5.0 Search Engine
5.1 Search Engine Overview
The MVTX2604 search engine is optimized for high throughput searching, with enhanced features to support:
•
•
•
•
•
•
•
•
•
Up to 64 K MAC addresses
Up to 255 VLAN and IP Multicast groups
3 groups of port trunking (1 for the two Gigabit ports and 2 others)
Traffic classification into 4 (or 8 for Gigabit) transmission priorities and 2 drop precedence levels
Packet filtering
Security
IP Multicast
Flooding, Broadcast, Multicast Storm Control
MAC address learning and aging
5.2 Basic Flow
Shortly after a frame enters the MVTX2604 and is written to the Frame Data Buffer (FDB), the frame engine
generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of
the frame, which contain all the necessary information for the search engine to perform its task. When the search
engine is done, it writes to the Switch Response Queue and the frame engine uses the information provided in that
queue for scheduling and forwarding.
In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch
request. Among the information extracted are the source and destination MAC addresses, the transmission and
discard priorities, whether the frame is unicast or multicast and VLAN ID. Requests are sent to the external SRAM
to locate the associated entries in the external hash table.
When all the information has been collected from external SRAM, the search engine has to compare the MAC
address on the current entry with the MAC address for which it is searching. If it is not a match, the process is
repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to
the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address
unknown) or flooding (destination MAC address unknown).
In addition, VLAN information is used to select the correct set of destination ports for the frame (for multicast), or to
verify that the frame’s destination port is associated with the VLAN (for unicast).
If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port
number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the
source and destination MAC addresses.
When all the information is compiled, the switch response is generated, as stated earlier. The search engine also
interacts with the CPU with regard to learning and aging.
5.3 Search, Learning, and Aging
5.3.1 MAC Search
The search block performs source MAC address and destination MAC address (or destination IP address for IP
multicast) searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be
examined and so on until a match is found or the end of the list is reached.
In tag based VLAN mode, if the frame is unicast, and the destination port is not a member of the correct VLAN, then
the frame is dropped; otherwise, the frame is forwarded. If the frame is multicast, this same table is used to indicate
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Data Sheet
all the ports to which the frame will be forwarded. Moreover, if port trunking is enabled, this block selects the
destination port (among those in the trunk group).
In port based VLAN mode, a bitmap is used to determine whether the frame should be forwarded to the outgoing
port. The main difference in this mode is that the bitmap is not dynamic. Ports cannot enter and exit groups
because of real-time learning made by a CPU.
The MAC search block is also responsible for updating the source MAC address timestamp and the VLAN port
association timestamp, used for aging.
5.3.2 Learning
The learning module learns new MAC addresses and performs port change operations on the MCT database. The
goal of learning is to update this database as the networking environment changes over time.
When CPU reporting is enabled, learning and port change will be performed when the CPU request queue has
room, and a memory slot is available, and a “Learn MAC Address” message is sent to the CPU. When fast learning
mode is enabled, learning and port change will be performed when memory slot is available and a latter “Learn
MAC Address” message is sent to the CPU when CPU queue has room.
When CPU reporting is disabled, learning and port change will be performed based on memory slot availability only.
In tag based VLAN mode, if the source port is not a member of a classified VLAN a “New VLAN Port” message is
sent to the CPU. The CPU can decide whether or not the source port can be added to the VLAN.
5.3.3 Aging
Aging time is controlled by register 400h and 401h.
The aging module scans and ages MCT entries based on a programmable “age out” time interval. As we indicated
earlier, the search module updates the source MAC address and VLAN port association timestamps for each frame
it processes. When an entry is ready to be aged, the entry is removed from the table and a “Delete MAC Address”
message is sent to inform the CPU.
Supported MAC entry types are: dynamic, static, source filter, destination filter, IP multicast, source and destination
filter and secure MAC address. Only dynamic entries can be aged; all others are static. The MAC entry type is
stored in the “status” field of the MCT data structure.
5.3.4 VLAN Table
The table below provides a mapping from VLAN ID to VLAN index. It is maintained by system software and is
checked by the hardware search engine for every incoming frame. This table has 4 K entries and is stored in
external SRAM. It is organized as 512 × 8 entries (total of 4 K VLAN indexes) as shown. Each VLAN index is 8 bits.
VIX7
…
VIX6
…
VIX5
…
VIX4
…
VIX3
…
VIX2
…
VIX1
…
VIX0
…
…
…
…
…
…
…
…
…
VIX4095
VIX4094
VIX4093
VIX4092
VIX4091
VIX4090
VIX4089
VIX4088
Table 1 - VLAN Index Mapping Table
Each VIX represents the mapping result from the associated VLAN ID (VLANID = 0x004 is mapped to VIX4).
Unused VLAN ID’s have their corresponding VIX programmed to hexadecimal 00. Used VLAN ID’s have their
corresponding VIX programmed to hexadecimal 01 through FF. In other words, 255 VLAN’s are supported. The VIX
value is a pointer to the entries in the VLAN Index port association table (internal memory).
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Data Sheet
The VLAN Index port association table is used by both software and hardware. It contains 256 entries. Each entry
has 27 fields, such that each field represents the port status of that particular VLAN.
Port
Bit
0
Not Used G1
63 to 54 53 52
G0
CPU P23
49 48 47 46
P22
……
P3
P2
P1
3
P0
1
51 50
45 44
7 6
5 4
2
0
E
N
T
R
I
E
S
1
:
:
255
Table 2 - LAN Index Port Association Table
Each entry has 64 bits. Each port has a VLAN status field with the following two bits values:
• 00: Port not a member of VLAN
• 01: Port is a member of VLAN, and is subject to aging (Do not use. Used by the aging module)
• 10: Port is a member of VLAN, and is subject to aging
• 11: Port is a member of VLAN, and is not subject to aging
Note: The VLAN aging time is controlled by register 402h.
5.4 MAC Address Filtering
The MVTX2604's implementation of intelligent traffic switching provides filters for source and destination MAC
addresses. This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and
broadcast traffic.
MAC address filtering allows the MVTX2604 to block an incoming packet to an interface when it sees a specified
MAC address in either the source address or destination address of the incoming packet. For example, if your
network is congested because of high utilization from a MAC address you can filter all traffic transmitted from that
address and restore network flow while you troubleshoot the problem.
5.5 Quality of Service
Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over
various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by
some real-time and interactive traffic) and improved loss characteristics.
Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate
traffic, a service level known as “best effort” attempts to get all the packets to their intended destinations with
minimum delay; however, there are no guarantees. In a congested network or when a low-performance
switch/router is overloaded, “best effort” becomes unsuitable for delay-sensitive traffic and mission-critical data
transmission.
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The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and
multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously
plagued such “best effort” networking systems. QoS provides Ethernet networks with the breakthrough technology
to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth.
Extensive core QoS mechanisms are built into the MVTX2604 architecture to ensure policy enforcement and
buffering of the ingress port, as well as weighted fair-queue(WFQ) scheduling at the egress port.
In the MVTX2604, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly.
The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is
provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which
the frames and packets belong. For example, the overall service given to frames and packets in the premium class
will be better than that given to the standard class; the premium class is expected to experience lower loss rate or
delay.
The MVTX2604 supports the following QoS techniques:
•
•
•
In a port-based setup, any station connected to the same physical port of the switch will have the same
transmit priority.
In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be
mapped to different queues in the switch to provide QoS.
In a TOS/DS-based set up, TOS stands for “Type of Service” that may include “minimize delay,” “maximize
throughput,” or “maximize reliability.” Network nodes may select routing paths or forwarding behaviours that
are suitably engineered to satisfy the service request.
•
In a logical port-based set up, a logical port provides the application information of the packet. Certain
applications are more sensitive to delays than others; using logical ports to classify packets can help speed
up delay sensitive applications, such as VoIP.
5.6 Priority Classification Rule
Figure 5 shows the MVTX2604 priority classification rule.
Yes
Use Default Port Settings
Fix Port Priority ?
No
Yes
TOS Precedence over VLAN?
(FCR Register, Bit 7)
Use Default Port Settings
No
No
No
No
IP Frame ?
IP
VLAN Tag ?
Yes
Yes
Use Logical Port
Yes
Use Logical Port
Yes
No
Use TOS
Use VLAN Priority
Figure 5 - Priority Classification Rule
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Data Sheet
5.7 Port and Tag Based VLAN
The MVTX2604 supports two models for determining and controlling how a packet gets assigned to a VLAN: port
priority and tag -based VLAN.
5.7.1 Port-Based VLAN
An administrator can use the PVMAP Registers to configure the MVTX2604 for port-based VLAN (see “Registration
Definition” on page 42). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the
Engineering VLAN and ports 7-9 to the Administrative VLAN. The MVTX2604 determines the VLAN membership of
each packet by noting the port on which it arrives. From there, the MVTX2604 determines which outgoing port(s)
is/are eligible to transmit each packet or whether the packet should be discarded.
Destination Port Numbers Bit Map
Port Registers
26
0
…
2
1
1
1
0
0
Register for Port #0
PVMAP00_0[7:0] to PVMAP00_3[2:0]
Register for Port #1
0
0
1
0
0
0
1
0
PVMAP01_0[7:0] to PVMAP01_3[2:0]
Register for Port #2
PVMAP02_0[7:0] to PVMAP02_3[2:0]
…
Register for Port #26
0
0
0
0
PVMAP26_0[7:0] to PVMAP26_3[2:0]
Table 3 - PVMAP Register
For example, in the above table, a "1" denotes that an outgoing port is eligible to receive a packet from an incoming
port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port.
In this example:
Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2.
Data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2.
Data packets received at port #2 are NOT eligible to be sent to ports 0 and 1.
5.7.2 Tag-Based VLAN
The MVTX2604 supports the IEEE 802.1q specification for “tagging” frames. The specification defines a way to
coordinate VLANs across multiple switches. In the specification, an additional 4-octet header (or “tag”) is inserted in
a frame after the source MAC address and before the frame type. 12 bits of the tag are used to define the VLAN ID.
Packets are then switched through the network with each MVTX2604 simply swapping the incoming tag for an
appropriate forwarding tag rather than processing each packet's contents to determine the path. This approach
minimizes the processing needed once the packet enters the tag-switched network. In addition, coordinating VLAN
IDs across multiple switches enables VLANs to extend to multiple switches.
Up to 255 VLANs are supported in the MVTX2604. The 4 K VLANs specified in the IEEE 802.1q are mapped to 255
VLAN indexes. The mapping is made by the VLAN index mapping table. Based on the VLAN index (VIXn), the
source and destination port membership is checked against the content in the VLAN Index Port association table. If
the destination port is a member of the VLAN, the packet is forwarded; otherwise it is discarded. If the source port is
not a member, a “New VLAN Port” message is sent to the CPU. A filter can be applied to discard the packet if the
source port is not a member of the VLAN.
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5.8 Memory Configurations
The MVTX2604 supports the following memory configurations. Pipeline SBRAM modes support 1 M and 2 M per
bank configurations, while ZBT mode supports 4 M configurations, 2 M per domain (bank). For detail connection
information, please reference the memory application note.
Configuration
1 M per bank
2 M per bank
Connections
(Bootstrap pin
TSTOUT7 = open)
(Bootstrap pin
TSTOUT7 = pull down)
Single Layer
Two 128 K x 32 SRAM/bank
or
One 128 K x 64 SRAM/bank
Two 256 K x 32 SRAM/bank Connect 0E# and WE#
(Bootstrap pin
TSTOUT13 = open)
Double Layer
(Bootstrap pin
TSTOUT13 = pull
down)
NA
Four 128 K x 32
SRAM/bank
or
Connect 0E0# and
WE0#
Connect 0E1# and
Two 128 K x 64 SRAM/bank WE1#
Table 4 - Supported Memory Configurations (SBRAM Mode)
Configuration
2 M per bank
Connections
Single Layer
Two 256 K x 32 ZBT SRAM/bank
Connect ADS# to Layer 0 chipselect
(Bootstrap pin
or One 256 K x 64 ZBT SRAM/bank pin
TSTOUT13 = open)
Double Layer
Four 128 K x 32 ZBT SRAM/bank
Connect ADS# to Layer 0 chipselect
(Bootstrap pin
or Two 128 K x 64 ZBT SRAM/bank pin
TSTOUT13 = pull down)
and 0E# to Layer 1 chipselect pin
Table 5 - Supported Memory Configurations (ZBT Mode)
Frame data Buffer
Only Bank A
Bank A and Bank B
Bank A and Bank B
1 M
2 M
1 M/bank
(SBRAM)
2 M/bank
1 M/bank
2 M/bank
(SBRAM)
(SBRAM)
(SBRAM)
(ZBT SRAM)
(ZBT SRAM)
MVTX2601
MVTX2602
MVTX2603
X
X
X
X
X
X
X
MVTX2603
X
X
X
X
(Gigabit ports
in 2giga mode)
MVTX2604
X
MVTX2604
(Gigabit ports
in 2giga mode)
Table 6 - Options for Memory Configuration
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Bank B (1 M One Layer)
Bank A (1 M One Layer)
Data LB_D[63:32]
Data LA_D[63:32]
Data LB_D[31:0]
Data LA_D[31:0]
SRAM
Memory
128 K
SRAM
Memory
128 K
Memory
128 K
32 bits
Memory
128 K
32 bits
32 bits
32 bits
Address LB_A[19:3]
Address LA_A[19:3]
Bootstraps: TSTOUT7 = Open, TSTOUT13 = Open, TSTOUT4 = Open
Figure 6 - Memory Configuration For: 2 Banks, 1 Layer, 2 MB Total
Bank A (2 M Two Layers)
Bank B (2 M Two Layers)
Data LA_D[63:32]
Data LB_D[63:32]
Data LA_D[31:0]
Data LB_D[31:0]
SRAM
Memory
128 K
SRAM
Memory
128 K
SRAM
Memory
128 K
SRAM
Memory
128 K
32 bits
32 bits
32 bits
32 bits
SRAM
Memory
128 K
SRAM
Memory
128 K
SRAM
Memory
128 K
SRAM
Memory
128 K
32 bits
32 bits
32 bits
32 bits
Address LA_A[19:3]
Address LB_A[19:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Pull Down, TSTOUT4 = Open
Figure 7 - Memory Configuration For: 2 Banks, 2 Layers, 4 MB Total
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Bank B (2 M One Layer)
Bank A (2 M One Layer)
Data LB_D[63:32]
Data LA_D[63:32]
Data LB_D[31:0]
Data LA_D[31:0]
SRAM
Memory
256 K
SRAM
Memory
256 K
Memory
256 K
32 bits
Memory
256 K
32 bits
32 bits
32 bits
Address LB_A[20:3]
Address LA_A[20:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open
Figure 8 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB
Bank A (2 M Two Layers)
Bank B (2 M Two Layers)
Data LA_D[63:32]
Data LB_D[63:32]
Data LA_D[31:0]
Data LB_D[31:0]
ZBT
Memory
128 K
ZBT
Memory
128 K
ZBT
Memory
128 K
ZBT
Memory
128 K
32 bits
32 bits
32 bits
32 bits
ZBT
Memory
128 K
ZBT
Memory
128 K
ZBT
Memory
128 K
ZBT
Memory
128 K
32 bits
32 bits
32 bits
32 bits
Address LA_A[19:3]
Address LB_A[19:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Pull Down, TSTOUT4 = Open
Figure 9 - Memory Configuration For: 2 Banks, 2 Layers, 4 MB Total
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Data Sheet
Bank B (2 M One Layer)
Bank A (2 M One Layer)
Data LB_D[63:32]
Data LA_D[63:32]
Data LB_D[31:0]
Data LA_D[31:0]
ZBT
ZBT
ZBT
Memory
256 K
ZBT
Memory
256 K
Memory
Memory
256 K
32 bits
256 K
32 bits
32 bits
32 bits
Address LB_A[20:3]
Address LA_A[20:3]
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open
Figure 10 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB
6.0 Frame Engine
6.1 Data Forwarding Summary
When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB.
Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast and its
destination port or ports. A VLAN table lookup is performed as well.
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a
Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling
Queue (TxSch Q) or Queues. There are 4 TxSch Q for each 10/100 port (and 8 per Gigabit port), one for each
priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast or adding
an entry to a physical queue if multicast.
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of
the TxSch Qs, according to the transmission scheduling algorithm (to ensure per-class quality of service). The
unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The older
HOL between the two queues goes first. For 10/100 ports multicast queue 0 is associated with unicast queue 0 and
multicast queue 1 is associated with unicast queue 2. For Gigabit ports multicast queue 0 is associated with unicast
queue 0, multicast queue 1 with unicast queue 2, multicast queue 2 with unicast queue 4 and multicast queue 3
with unicast queue 6.
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the
destination port.
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6.2 Frame Engine Details
This section briefly describes the functions of each of the modules of the MVTX2604 frame engine.
6.2.1 FCB Manager
The FCB manager allocates FCB handles to incoming frames and releases FCB handles upon frame departure.
The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be
determined by referring to Chapter 7. In addition, the FCB manager is responsible for buffer aging and for linking
unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin
and the aging time is defined in register FCBAT.
6.2.2 Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch
request.
6.2.3 RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each
frame for use by the search engine when the switch request has been made.
6.2.4 TxQ Manager
First, the TxQ manager checks the per-class queue status and global reserved resource situation and using this
information makes the frame dropping decision after receiving a switch response. If the decision is not to drop, the
TxQ manager requests that the FCB manager link the unicast frame’s FCB to the correct per-port-per-class TxQ. If
multicast, the TxQ manager writes to the multicast queue for that port and class. The TxQ manager can also trigger
source port flow control for the incoming frame’s source if that port is flow control enabled. Second, the TxQ
manager handles transmission scheduling; it schedules transmission among the queues representing different
classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to
the correct port control module.
6.3 Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes
start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control
module requests that the buffer be released.
6.4 TxDMA
The TxDMA multiplexes data and address from port control and arbitrates among buffer release requests from the
port control modules.
7.0 Quality of Service and Flow Control
7.1 Model
Quality of service is an all-encompassing term for which different people have different interpretations. In general,
the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also
assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager
knows his applications, such as voice, file transfer, or web browsing and their relative importance. The manager
can then subdivide the applications into classes and set up a service contract with each. The contract may consist
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Data Sheet
of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to
the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic
is policed or shaped we may be able to provide additional assurances about our switch’s performance.
Table 7 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form
a fourth class with no bandwidth or latency assurances. Gigabit ports actually have eight total transmission
priorities.
Goals
TotalAssured
Bandwidth (user
defined)
Low Drop Probability
(low-drop)
High Drop Probability
(high-drop)
Highest transmission
priority, P3
50 Mbps
Apps: phone calls,
circuit emulation.
Latency: < 1 ms.
Drop: No drop if P3 not
oversubscribed.
Apps: training video.
Latency: < 1 ms.
Drop: No drop if P3 not
oversubscribed; first P3 to drop
otherwise.
Middle transmission
priority, P2
37.5 Mbps
Apps: interactive apps,
Web business.
Apps: non-critical interactive
apps.
Latency: < 4-5 ms.
Drop: No drop if P2 not
oversubscribed.
Latency: < 4-5 ms.
Drop: No drop if P2 not
oversubscribed; firstP2 to drop
otherwise.
Low transmission
priority, P1
12.5 Mbps
100 Mbps
Apps: emails, file
backups.
Apps: casual web browsing.
Latency: < 16 ms desired, but
not critical.
Latency: < 16 ms
desired, but not critical.
Drop: No drop if P1 not
oversubscribed.
Drop: No drop if P1 not
oversubscribed; first to drop
otherwise.
Total
Table 7 - Two-dimensional World Traffic
A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a
rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-
upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link
utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade the
quality of service (QoS) received by well-behaved classes.
As Table 7 illustrates, the six traffic types may each have their own distinct properties and applications. As shown,
classes may receive bandwidth assurances or latency bounds. In the table, P3, the highest transmission class,
requires that all frames be transmitted within 1 ms,and receives 50% of the 100 Mbps of bandwidth at that port.
Best-effort (P0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any
traffic to offer. It is also possible to add a fourth class that has strict priority over the other three; if this class has
even one frame to transmit, then it goes first. In the MVTX2604, each 10/100 Mbps port will support four total
classes and each 1000 Mbps port will support eight classes. We will discuss the various modes of scheduling these
classes in the next section.
In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely
lose packets. But poorly behaved users – users who send frames at too high a rate – will encounter frame loss and
the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some
low-drop frames are dropped and then all frames in the worst case.
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Table 7 shows that different types of applications may be placed in different boxes in the traffic table. For example,
casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the
category of low-loss, low-latency traffic.
7.2 Four QoS Configurations
There are four basic pieces to QoS scheduling in the MVTX2604: strict priority (SP), delay bound, weighted fair
queuing (WFQ), and best effort (BE). Using these four pieces, there are four different modes of operation as shown
in the tables below. For 10/100 Mbps ports, the following registers select these modes:
QOSC24 [7:6]_CREDIT_C00
QOSC28 [7:6]_CREDIT_C10
QOSC32 [7:6]_CREDIT_C20
QOSC36 [7:6]_CREDIT_C30
P3
P2
P1
P0
BE
BE
Delay Bound
Op1 (default)
Op2
SP
Delay Bound
WFQ
SP
Op3
WFQ
Op4
Table 8 - Four QoS Configurations for a 10/100 Mbps Port
QOSC40 [7:6] and QOSC48 [7:6] select these modes for the first and second gigabit ports, respectively.
P6
P5
P4
P3
P2
P1
P0
P7
Delay Bound
BE
BE
Op1 (default)
Op2
SP
Delay Bound
WFQ
SP
Op3
WFQ
Op4
Table 9 - Four QoS Configurations for a Gigabit Port
The default configuration for a 10/100 Mbps port is three delay-bounded queues and one best-effort queue. The
delay bounds per class are 0,8 ms for P3, 3.2 ms for P2, and 12.8 ms for P1. For a 1 Gbps port, we have a default
of six delay-bounded queues and two best-effort queues. The delay bounds for a 1 Gbps port are 0.16 ms for P7
and P6, 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. Best effort traffic is only served when
there is no delay-bounded traffic to be served. For a 1 Gbps port, where there are two best-effort queues, P1 has
strict priority over P0.
We have a second configuration for a 10/100 Mbps port in which there is one strict priority queue, two delay
bounded queues and one best effort queue. The delay bounds per class are 3.2 ms for P2 and 12.8 ms for P1. If
the user is to choose this configuration, it is important that P3 (SP) traffic be either policed or implicitly bounded
(e.g., if the incoming P3 traffic is very light and predictably patterned). Strict priority traffic, if not admission-
controlled at a prior stage to the MVTX2604 can have an adverse effect on all other classes’ performance. For a
1 Gbps port, P7 and P6 are both SP classes and P7 has strict priority over P6. In this case, the delay bounds per
class are 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2.
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The third configuration for a 10/100 Mbps port contains one strict priority queue and three queues receiving a
bandwidth partition via WFQ. As in the second configuration, strict priority traffic needs to be carefully controlled. In
the fourth configuration, all queues are served using a WFQ service discipline.
7.3 Delay Bound
In the absence of a sophisticated QoS server and signaling protocol, the MVTX2604 may not know the mix of
incoming traffic ahead of time. To cope with this uncertainty, our delay assurance algorithm dynamically adjusts its
scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (HOL)
frames. As a result, we assure latency bounds for all admitted frames with high confidence, even in the presence of
system-wide congestion. Our algorithm identifies misbehaving classes and intelligently discards frames at no
detriment to well-behaved classes. Our algorithm also differentiates between high-drop and low-drop traffic with a
weighted random early drop (WRED) approach. Random early dropping prevents congestion by randomly dropping
a percentage of high-drop frames even before the chip’s buffers are completely full, while still largely sparing low-
drop frames. This allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. Finally,
the delay bound algorithm also achieves bandwidth partitioning among classes.
7.4 Strict Priority and Best Effort
When strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. Two
of our four QoS configurations include strict priority queues. The goal is for strict priority classes to be used for IETF
expedited forwarding (EF), where performance guarantees are required. As we have indicated, it is important that
strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes.
When best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other
classes have any traffic to offer. Two of our four QoS configurations include best effort queues. The goal is for best
effort classes to be used for non-essential traffic, because we provide no assurances about best effort performance.
However, in a typical network setting, much best effort traffic will indeed be transmitted and with an adequate
degree of expediency.
Because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best
effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the
MVTX2604, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to
enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best
effort and strict priority queues when global buffer resources become scarce.
7.5 Weighted Fair Queuing
In some environments – for example, in an environment in which delay assurances are not required, but precise
bandwidth partitioning on small time scales is essential, WFQ may be preferable to a delay-bounded scheduling
discipline. The MVTX2604 provides the user with a WFQ option with the understanding that delay assurances can
not be provided if the incoming traffic pattern is uncontrolled. The user sets four WFQ “weights” (eight for Gigabit
ports) such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with
error within 2%.
In WFQ mode, though we do not assure frame latency, the MVTX2604 still retains a set of dropping rules that helps
to prevent congestion and trigger higher level protocol end-to-end flow control.
As before, when strict priority is combined with WFQ, we do not have special dropping rules for the strict priority
queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. However, we do
indeed drop frames from SP queues for global buffer management purposes. In addition, queue P0 for a 10/100
port (and queues P0 and P1 for a Gigabit port) are treated as best effort from a dropping perspective, though they
still are assured a percentage of bandwidth from a WFQ scheduling perspective. What this means is that these
particular queues are only affected by dropping when the global buffer count becomes low.
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7.6 Shaper
Although traffic shaping is not a primary function of the MVTX2604, the chip does implement a shaper for expedited
forwarding (EF). Our goal in shaping is to control the peak and average rate of traffic exiting the MVTX2604.
Shaping is limited to the two Gigabit ports only, and only to class P6 (the second highest priority). This means that
class P6 will be the class used for EF traffic. If shaping is enabled for P6, then P6 traffic must be scheduled using
strict priority. With reference to Table 7, only the middle two QoS configurations may be used.
Peak rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then the
peak rate for shaped traffic is 32/64 * 1000 Mbps = 500 Mbps. Average rate is also a programmable whole number,
no greater than 64 and no greater than the peak rate. For example, if the setting is 16, then the average rate for
shaped traffic is 16/64 * 1000 Mbps = 250 Mbps. As a consequence of the above settings in our example, shaped
traffic will exit the MVTX2604 at a rate always less than 500 Mbps and averaging no greater than 250 Mbps. See
Programming QoS Register application note for more information.
Also, when shaping is enabled, it is possible for a P6 queue to explode in length if fed by a greedy source. The
reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if
the line is idle. Though we do have global resource management, we do nothing to prevent this situation locally. We
assume SP traffic is policed at a prior stage to the MVTX2604.
7.7 Rate Control
The MVTX2604 provides a rate control function on its 10/100 ports. This rate control function applies to the
outgoing traffic aggregate on each 10/100 port. It provides a way of reducing the outgoing average rate below full
wire speed. Note that the rate control function does not shape or manipulate any particular traffic class.
Furthermore, though the average rate of the port can be controlled with this function, the peak rate will still be full
line rate.
Two principal parameters are used to control the average rate for a 10/100 port. A port’s rate is controlled by
allowing, on average, M bytes to be transmitted every N microseconds. Both of these values are programmable.
The user can program the number of bytes in 8-byte increments and the time may be set in units of 10 ms.
The value of M/N will, of course, equal the average data rate of the outgoing traffic aggregate on the given 10/100
port. Although there are many (M,N) pairs that will provide the same average data rate performance, the smaller the
time interval N, the “smoother” the output pattern will appear.
In addition to controlling the average data rate on a 10/100 port, the rate control function also manages the
maximum burst size at wire speed. The maximum burst size can be considered the memory of the rate control
mechanism; if the line has been idle for a long time, to what extent can the port “make up for lost time” by
transmitting a large burst? This value is also programmable, measured in 8-byte increments.
Example: Suppose that the user wants to restrict Fast Ethernet port P’s average departure rate to 32 Mbps – 32%
of line rate – when the average is taken over a period of 10 ms. In an interval of 10 ms, exactly 40000 bytes can be
transmitted at an average rate of 32 Mbps.
So how do we set the parameters? The rate control parameters are contained in an internal RAM block accessible
through the CPU port (See Programming QoS Registers application note and Processor interface application note).
The data format is shown below.
63:40
0
39:32
31:16
15:0
Time interval
Maximum burst size
Number of bytes
As we indicated earlier, the number of bytes is measured in 8-byte increments, so the 16-bit field “Number of bytes”
should be set to 40000/8, or 5000. In addition, the time interval has to be indicated in units of 10 ms. Though we
want the average data rate on port P to be 32 Mbps when measured over an interval of 10 ms, we can also adjust
the maximum number of bytes that can be transmitted at full line rate in any single burst. Suppose we wish this limit
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Data Sheet
to be 12 kilobytes. The number of bytes is measured in 8-byte increments, so the 16-bit field “Maximum burst size”
is set to 12000/8, or 1500.
7.8 WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified
parameters. The following table summarizes the behavior of the WRED logic.
In KB (kilobytes)
P3
P2
P1
High Drop
Low Drop
Level 1
X%
0%
N ≥ 120
P3 ≥ AKB
P2 ≥ BKB
P1 ≥ CKB
Level 2
Y%
Z%
N ≥ 140
Level 3
100%
100%
N ≥ 160
Table 10 - WRED Drop Thresholds
Px is the total byte count, in the priority queue x. The WRED logic has three drop levels, depending on the value of
N, which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals
P3*16+P2*4+P1. If using WFQ scheduling, N equals P3+P2+P1. Each drop level from one to three has defined
high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can
be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. In Level 3, all packets are
dropped if the bytes in each priority queue exceed the threshold. Parameters A, B, C are the byte count thresholds
for each priority queue. They can be programmed by the QOS control register (refer to the register group 5). See
Programming QoS Registers application note for more information.
7.9 Buffer Management
Because the number of FDB slots is a scarce resource and because we want to ensure that one misbehaving
source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept
of buffer management into the MVTX2604. Our buffer management scheme is designed to divide the total buffer
space into numerous reserved regions and one shared pool as shown in Figure 11 on page 41.
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores
frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first
enters the MVTX2604, its destination port and class are as yet unknown, and so the decision to drop or not needs
to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the
frame drop discipline after classifying.
Six reserved sections, one for each of the first six priority classes, ensure a programmable number of FDB slots per
class. The lowest two classes do not receive any buffer reservation. Furthermore, even for 10/100 Mbps ports, a
frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only
four transmission scheduling queues for 10/100 Mbps ports, but as far as buffer usage is concerned there are still
eight distinguishable classes.
Another segment of the FDB reserves space for each of the 27 ports — 26 ports for Ethernet and one CPU port
(port number 24). Two parameters can be set, one for the source port reservation for 10/100 Mbps ports and CPU
port, and one for the source port reservation for 1 Gbps ports. These 27 reserved regions make sure that no well-
behaved source port can be blocked by another misbehaving source port.
In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in
the six priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the
shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port.
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The following registers define the size of each section of the Frame data Buffer:
PR100- Port Reservation for 10/100 Ports
PRG- Port Reservation for Giga Ports
SFCB- Share FCB Size
C2RS- Class 2 Reserve Size
C3RS- Class 3 Reserve Size
C4RS- Class 4 Reserve Size
C5RS- Class 5 Reserve Size
C6RS- Class 6 Reserve Size
C7RS- Class 7 Reserve Size
temporary
reservation
shared pool
S
per-class
reservation
per-source
reservations
per-source
reservations
(2 G)
(24 10/100 M, CPU)
Figure 11 - Buffer Partition Scheme Used to Implement MVTX2604 AG Buffer Management
7.9.1 Dropping When Buffers Are Scarce
Summarizing the two examples of local dropping discussed earlier in this chapter:
If a queue is a delay-bounded queue we have a multi-level WRED drop scheme designed to control delay and
partition bandwidth in case of congestion.
If a queue is a WFQ-scheduled queue we have a multi-level WRED drop scheme designed to prevent congestion.
In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The
function of buffer management is to make sure that such dropping causes as little blocking as possible.
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
7.10 MVTX2604 Flow Control Basics
Because frame loss is unacceptable for some applications, the MVTX2604 provides a flow control option. When
flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a
source port that is sending a packet to this switch, to temporarily hold off.
While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When
a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not,
are halted. A single packet destined for a congested output can block other packets destined for uncongested
outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high
confidence when flow control is enabled.
In the MVTX2604, each source port can independently have flow control enabled or disabled. For flow control
enabled ports, by default all frames are treated as lowest priority during transmission scheduling. This is done so
that those frames are not exposed to the WRED Dropping scheme. Frames from flow control enabled ports feed to
only one queue at the destination, the queue of lowest priority. This means that if flow control is enabled for a given
source port then we can guarantee that no packets originating from that port will be lost but at the possible expense
of minimum bandwidth or maximum delay assurances. In addition, these “downgraded” frames may only use the
shared pool or the per-source reserved pool in the FDB; frames from flow control enabled sources may not use
reserved FDB slots for the highest six classes (P2-P7).
The MVTX2604 does provide a system-wide option of permitting normal QoS scheduling (and buffer use) for
frames originating from flow control enabled ports. When this programmable option is active, it is possible that
some packets may be dropped even though flow control is on. The reason is that intelligent packet dropping is a
major component of the MVTX2604’s approach to ensuring bounded delay and minimum bandwidth for high priority
flows.
7.10.1 Unicast Flow Control
For unicast frames, flow control is triggered by source port resource availability. Recall that the MVTX2604’s buffer
management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a
source port’s reserved FDB slots have been used then flow control Xoff is triggered.
Xon is triggered when a port is currently being flow controlled and all of that port’s reserved FDB slots have been
released.
Note that the MVTX2604’s per-source-port FDB reservations assure that a source port that sends a single frame to
a congested destination will not be flow controlled.
7.10.2 Multicast Flow Control
In unmanaged mode, flow control for multicast frames is triggered by a global buffer counter. When the system
exceeds a programmable threshold of multicast packets Xoff is triggered. Xon is triggered when the system returns
below this threshold.
In managed mode, per-VLAN flow control is used for multicast frames. In this case, flow control is triggered by
congestion at the destination. How so? The MVTX2604 checks each destination to which a multicast packet is
headed. For each destination port, the occupancy of the lowest-priority transmission multicast queue (measured in
number of frames) is compared against a programmable congestion threshold. If congestion is detected at even
one of the packet’s destinations then Xoff is triggered.
In addition, each source port has a 26-bit port map recording which port or ports of the multicast frame’s fanout
were congested at the time Xoff was triggered. All ports are continuously monitored for congestion and a port is
identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were
originally marked as congested in the port map have become uncongested, then Xon is triggered and the 26-bit
vector is reset to zero.
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
The MVTX2604 also provides the option of disabling VLAN multicast flow control.
Note: If per-Port flow control is on, QoS performance will be affected.
7.11 Mapping to IETF Diffserv Classes
The mapping between priority classes discussed in this chapter and elsewhere is shown below.
P7
P6
EF
P5
P4
P3
P2
P1
P0
VTX
NM
AF0
AF1
AF2
AF3
BE0
BE1
IETF
Table 11 - Mapping between MVTX2604 and IETF Diffserv Classes for Gigabit Ports
As the table illustrates, P7 is used solely for network management (NM) frames. P6 is used for expedited
forwarding service (EF). Classes P2 through P5 correspond to an assured forwarding (AF) group of size 4. Finally,
P0 and P1 are two best effort (BE) classes.
For 10/100 Mbps ports, the classes of Table 12 are merged in pairs—one class corresponding to NM+EF, two AF
classes, and a single BE class.
P3
P2
P1
P0
VTX
NM+EF
AF0 AF1
BE0
IETF
Table 12 - Mapping between MVTX2604 and IETF Diffserv Classes for 10/100 Ports
Features of the MVTX2604 that correspond to the requirements of their associated IETF classes are summarized in
the table below.
Network management (NM) and
Expedited forwarding (EF)
Global buffer reservation for NM and EF
Shaper for EF traffic on 1 Gbps ports
Option of strict priority scheduling
No dropping if admission controlled
Assured forwarding (AF)
Four AF classes for 1 Gbps ports
Programmable bandwidth partition, with option of
WFQ service
Option of delay-bounded service keeps delay
under fixed levels even if not admission-
controlled
Random early discard, with programmable levels
Global buffer reservation for each AF class
Best effort (BE)
Two BE classes for 1 Gbps ports
Service only when other queues are idle means
that QoS not adversely affected
Random early discard, with programmable levels
Traffic from flow control enabled ports
automatically classified as BE
Table 13 - MVTX2604 Features Enabling IETF Diffserv Standards
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
8.0 Port Trunking
8.1 Features and Restrictions
A port group (i.e., trunk) can include up to 4 physical ports but when using stack all of the ports in a group must be
in the same MVTX2604.
The two Gigabit ports may also be trunked together. There are three trunk groups total including the option to trunk
Gigabit ports.
Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address
and destination MAC address. Three other options include source MAC address only, destination MAC address
only and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly.
If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN
member map.
The MVTX2604 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking
group goes down, the MVTX2604 will automatically redistribute the traffic over to the remaining ports in the trunk in
unmanaged mode. In managed mode, the software can perform similar tasks.
8.2 Unicast Packet Forwarding
The search engine finds the destination MCT entry, and if the status field says that the destination port found
belongs to a trunk, then the group number is retrieved instead of the port number. In addition, if the source address
belongs to a trunk then the source port’s trunk membership register is checked.
A hash key, based on some combination of the source and destination MAC addresses for the current packet
selects the appropriate forwarding port as specified in the Trunk_Hash registers.
8.3 Multicast Packet Forwarding
For multicast packet forwarding, the device must determine the proper set of ports from which to transmit the
packet based on the VLAN index and hash key.
Two functions are required in order to distribute multicast packets to the appropriate destination ports in a port
trunking environment.
Determining one forwarding port per group. For multicast packets, all but one port per group, the forwarding port
must be excluded.
Preventing the multicast packet from looping back to the source trunk.
The search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with
the source port. This is because, when we select the primary forwarding port for each group we do not take the
source port into account. To prevent this, we simply apply one additional filter so as to block that forwarding port for
this multicast packet.
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
8.4 Unmanaged Trunking
In unmanaged mode, 3 trunk groups are supported. Groups 0 and 1 can trunk up to 4 10/100 ports. Group 2 can
trunk 2 Gigabit ports. The supported combinations are shown in the following table.
Group 0
Port 0
Port 1
Port 2
Port 3
9
9
9
9
9
9
9
9
9
Select via trunk0_mode register
Group 1
Group 2
Port 4
9
Port 5
Port 6
Port 7
9
9
9
9
9
Select via trunk1_mode register
Port 25(Giga 0)
Port 26 (Giga 1)
9
9
In unmanaged mode, the trunks are individually enabled/disabled by controlling pin trunk0,1,2.
9.0 Port Mirroring
9.1 Port Mirroring Features
The received or transmitted data of any 10/100 port in the MVTX2604 chip can be “mirrored” to any other port. We
support two such mirrored source-destination pairs. A mirror port can not also serve as a data port.
Please refer to the Port Mirroring Application note for further details.
9.2 Setting Registers for Port Mirroring
MIRROR1_SRC: Sets the source port for the first port mirroring pair. Bits [4:0] select the source port to be mirrored.
An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between
ingress (Rx) or egress (Tx) data.
MIRROR1_DEST: Sets the destination port for the first port mirroring pair. Bits [4:0] select the destination port to be
mirrored. The default is port 23.
MIRROR2_SRC: Sets the source port for the second port mirroring pair. Bits [4:0] select the source port to be
mirrored. An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select
between ingress (Rx) or egress (Tx) data.
MIRROR2_DEST: Sets the destination port for the second port mirroring pair. Bits [4:0] select the destination port to
be mirrored. The default is port 0.
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
10.0 TBI Interface
10.1 TBI Connection
The TBI interface can be used for 1000 Mbps fiber operation. In this mode, the MVTX2604 is connected to the
Serdes as shown in Figure 12. There are two TBI interfaces in the MVTX2604 devices. To enable to TBI function,
the corresponding TXEN and TXER pins need to be boot strapped. See Ball – Signal Description for details.
M25/26_TXD[9:0]
T[9:0]
REFCLK
M25/26_TXCLK
MVTX2604
SERDES
R[9:0]
RBC0
M25/26_RXD[9:0]
M25/26_RXCLK
M25/26_COL
RBC1
Figure 12 - TBI Connection
11.0 GPSI (7WS) Interface
11.1 GPSI connection
The 10/100 RMII ethernet port can function in GPSI (7WS) mode when the corresponding TXEN pin is strapped low
with a 1K pull down resistor. In this mode, the TXD[0], TXD[1], RXD[0] and RXD[1] serve as TX data, TX clock, RX
data and RX clock respectively. The link status and collision from the PHY are multiplexed and shifted into the
switch device through external glue logic. The duplex of the port can be controlled by programming the ECR
register.
The GPSI interface can be operated in port based VLAN mode only.
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
crs
rxd
CRS_DV
RXD[0]
RXD[1]
TXD[1]
rx_clk
tx_clk
txd
link0
col0
Port 0
Ethernet
PHY
TXD[0]
TXEN
txen
link1
link2
col1
col2
260X
link23
col23
Port 23
Ethernet
PHY
Link
Serializer
(CPLD)
Collision
Serializer
(CPLD)
Figure 13 - GPSI (7WS) Mode Connection Diagram
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
11.2SCAN LINK and SCAN COL interface
An external CPLD logic is required to take the link signals and collision signals from the GPSI PHYs and shift them
into the switch device. The switch device will drive out a signature to indicate the start of the sequence. After that,
the CPLD should shift in the link and collision status of the PHYS as shown in the figure. The extra link status
indicates the polarity of the link signal. One indicates the polarity of the link signal is active high.
scan_clk
scan_link/
scan_col
25 cycles for link/
24 cycles for col
Drived by MVTX260x
Drived by VTX260x
Drived by CPLD
Drived by CPLD
Total 32 cycles period
Figure 14 - SCAN LINK and SCAN COLLISON Status Diagram
12.0 LED Interface
12.1 LED Interface Introduction
A serial output channel provides port status information from the MVTX2604 chips. It requires three additional pins.
LED_CLK at 12.5 MHz
LED_SYN a sync pulse that defines the boundary between status frames
LED_DATA a continuous serial stream of data for all status LEDs that repeats once every frame time
A non-serial interface is also allowed, but in this case, only the Gigabit ports will have status LEDs.
A low cost external device (44 pin PAL) is used to decode the serial data and to drive an LED array for display. This
device can be customized for different needs.
12.2 Port Status
In the VTX2604, each port has 8 status indicators, each represented by a single bit. The 8 LED status indicators
are:
Bit 0: Flow control
Bit 1:Transmit data
Bit 2: Receive data
Bit 3: Activity (where activity includes either transmission or reception of data)
Bit 4: Link up
Bit 5: Speed (1= 100 Mb/s; 0= 10 Mb/s)
Bit 6: Full-duplex
Bit 7: Collision
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MVTX2604
Data Sheet
Eight clocks are required to cycle through the eight status bits for each port.
When the LED_SYN pulse is asserted, the LED interface will present 256 LED clock cycles with the clock cycles
providing information for the following ports.
Port 0 (10/100): cycles #0 to cycle #7
Port 1 (10/100): cycles#8 to cycle #15
Port 2 (10/100): cycle #16 to cycle #23
...
Port 22 (10/100): cycle #176 to cycle #183
Port 23 (10/100): cycle #184 to cycle #191
Port 24 (Gigabit 1): cycle #192 to cycle #199
Port 25 (Gigabit 2): cycle #200 to cycle #207
Byte 26 (additional status): cycle #208 to cycle #215
Byte 27 (additional status): cycle #216 to cycle #223
Cycles #224 to 256 present data with a value of zero.
The first two bits of byte 26 provides the speed information for the Gigabit ports while the remainder of byte 26 and
byte 27 provides bist status.
26[0]: G0 port (1= port 24 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on
speed bit of Port 24)
26[1]: G1 port (1= port 25 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on
speed bit of Port 25)
26[2]: initialization done
26[3]: initialization start
26[4]: checksum ok
26[5]: link_init_complete
26[6]: bist_fail
26[7]: ram_error
27[0]: bist_in_process
27[1]: bist_done
12.3 LED Interface Timing Diagram
The signal from the MVTX2604 to the LED decoder is shown in Figure 15.
Figure 15 - Timing Diagram of LED Interface
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
13.0 Hardware Statistics Counter
13.1 Hardware Statistics Counters List
MVTX2604 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these
counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over the
CPU is interrupted so that long-term statistics may be kept. The MAC detects all statistics except for the delay
exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager). The
following is the wrapped signal sent to the CPU through the command block.
31
30
2
6
2
5
0
Status Wrapped Signal
Bytes Sent (D)
B[0]
0-d
1-L
1-U
2-I
Unicast Frame Sent
B[1]
Frame Send Fail
B[2]
Flow Control Frames Sent
Non-Unicast Frames Sent
Bytes Received (Good and Bad) (D)
Frames Received (Good and Bad) (D)
Total Bytes Received (D)
B[3]
B[4]
2-u
3-d
4-d
5-d
6-L
6-U
7-l
B[5]
B[6]
B[7]
Total Frames Received
B[8]
Flow Control Frames Received
Multicast Frames Received
Broadcast Frames Received
Frames with Length of 64 Bytes
Jabber Frames
B9]
B[10]
B[11]
B[12]
B[13]
B[14]
B[15]
B[16]
B[17]
B[18]
B[19]
B[20]
B[21]
B[22]
B[23]
7-u
8-L
8-U
9-L
9-U
A-l
Frames with Length Between 65-127 Bytes
Oversize Frames
Frames with Length Between 128-255 Bytes
A-u
B-l
Frames with Length Between 256-511 Bytes
Frames with Length Between 512-1023 Bytes
Frames with Length Between 1024-1528 Bytes
B-u
C-l
Fragments
Alignment Error
Undersize Frames
CRC
C-U1
C-U
D-l
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Short Event
Collision
B[24]
B[25]
B[26]
B[27]
B[28]
B[29]
B[30]
D-u
E-l
Drop
E-u
F-l
Filtering Counter
Delay Exceed Discard Counter
Late Collision
F-U1
F-U
Link Status Change
Current link status
B[31]
Notation: X-Y
Address in the contain memory
Size and bits for the counter
X:
Y:
D Word counter
d:
L:
U:
24 bits counter bit[23:0]
8 bits counter bit[31:24]
8 bits counter bit[23:16]
16 bits counter bit[15:0]
16 bits counter bit[31:16]
U1:
l:
u:
13.2 IEEE 802.3 HUB Management (RFC 1516)
13.2.1 Event Counters
13.2.1.1 Readablectet
Counts number of bytes (i.e. octets) contained in good valid frames received.
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
No FCS (i.e. checksum) error
No collisions
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MVTX2604
Data Sheet
13.2.1.2 ReadableFrame
Counts number of good valid frames received.
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
No FCS error
No collisions
13.2.1.3 FCSErrors
Counts number of valid frames received with bad FCS.
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
No framing error
No collisions
13.2.1.4 AlignmentErrors
Counts number of valid frames received with bad alignment (not byte-aligned).
Frame size:
> 64 bytes,
< 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
No framing error
No collisions
13.2.1.5 FrameTooLongs
Counts number of frames received with size exceeding the maximum allowable frame size.
Frame size:
> 64 bytes,
> 1522 bytes if VLAN Tagged;
1518 bytes if not VLAN Tagged
FCS error:
don’t care
don’t care
Framing error:
No collisions
13.2.1.6 ShortEvents
Counts number of frames received with size less than the length of a short event.
Frame size:
FCS error:
< 10 bytes
don’t care
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MVTX2604
Data Sheet
Framing error:
No collisions
don’t care
13.2.1.7 Runts
Counts number of frames received with size under 64 bytes, but greater than the length of a short event.
Frame size:
FCS error:
> 10 bytes,
don’t care
don’t care
< 64 bytes
Framing error:
No collisions
13.2.1.8 Collisions
Counts number of collision events.
Frame size:
any size
13.2.1.9 LateEvents
Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes).
Frame size:
any size
Events are also counted by collision counter
13.2.1.10
VeryLongEvents
Counts number of frames received with size larger than Jabber Lockup Protection Timer (TW3).
Frame size: > Jabber
13.2.1.11
DataRateMisatches
For repeaters or HUB application only.
13.2.1.12 AutoPartitions
For repeaters or HUB application only.
13.2.1.13 TotalErrors
Sum of the following errors:
FCS errors
Alignment errors
Frame too long
Short events
Late events
Very long events
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MVTX2604
13.3 IEEE – 802.1 Bridge Management (RFC 1286)
13.3.1 Event Counters
Data Sheet
13.3.1.1 InFrames
Counts number of frames received by this port or segment.
Note: A frame received by this port is only counted by this counter if and only if it is for a protocol being processed
by the local bridge function.
13.3.1.2 OutFrames
Counts number of frames transmitted by this port.
Note: A frame transmitted by this port is only counted by this counter if and only if it is for a protocol being
processed by the local bridge function.
13.3.1.3 InDiscards
Counts number of valid frames received which were discarded (i.e. filtered) by the forwarding process.
13.3.1.4 DelayExceededDiscards
Counts number of frames discarded due to excessive transmit delay through the bridge.
13.3.1.5 MtuExceededDiscards
Counts number of frames discarded due to excessive size.
13.4 RMON – Ethernet Statistic Group (RFC 1757)
13.4.1 Event Counters
13.4.1.1 Drop Events
Counts number of times a packet is dropped, because of lack of available resources. DOES NOT include all packet
dropping -- for example, random early drop for quality of service support.
13.4.1.2 Octets
Counts the total number of octets (i.e. bytes) in any frames received.
13.4.1.3 BroadcastPkts
Counts the number of good frames received and forwarded with broadcast address.
Does not include non-broadcast multicast frames.
13.4.1.4 MulticastPkts
Counts the number of good frames received and forwarded with multicast address.
Does not include broadcast frames.
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MVTX2604
Data Sheet
13.4.1.5 CRCAlignErrors
Frame size:
> 64 bytes,
< 1522 bytes if VLAN tag (1518 if no VLAN)
No collisions:
Counts number of frames received with FCS or alignment errors
13.4.1.6 UndersizePkts
Counts number of frames received with size less than 64 bytes.
Frame size:
< 64 bytes,
No FCS error
No framing error
No collisions
13.4.1.7 OversizePkts
Counts number of frames received with size exceeding the maximum allowable frame size.
Frame size:
FCS error
1522 bytes if VLAN tag (1518 bytes if no VLAN)
don’t care
don’t care
Framing error
No collisions
13.4.1.8 Fragments
Counts number of frames received with size less than 64 bytes and with bad FCS.
Frame size:
Framing error
No collisions
< 64 bytes
don’t care
13.4.1.9 Jabbers
Counts number of frames received with size exceeding maximum frame size and with bad FCS.
Frame size:
Framing error
No collisions
> 1522 bytes if VLAN tag (1518 bytes if no VLAN)
don’t care
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MVTX2604
Data Sheet
13.4.1.10 Collisions
Counts number of collision events detected.
Only a best estimate since collisions can only be detected while in transmit mode, but not while in receive mode.
Frame size: any size
13.4.1.11 Packet Count for Different Size Groups
Six different size groups – one counter for each:
Pkts64Octets
for any packet with size = 64 bytes
Pkts65to127Octets
Pkts128to255Octets
Pkts256to511Octets
for any packet with size from 65 bytes to 127 bytes
for any packet with size from 128 bytes to 255 bytes
for any packet with size from 256 bytes to 511 bytes
Pkts512to1023Octets for any packet with size from 512 bytes to 1023 bytes
Pkts1024to1518Octets for any packet with size from 1024 bytes to 1518 bytes
Counts both good and bad packets.
13.5 Miscellaneous Counters
In addition to the statistics groups defined in previous sections, the MVTX2604 has other statistics counters for its
own purposes. We have two counters for flow control – one counting the number of flow control frames received,
and another counting the number of flow control frames sent. We also have two counters, one for unicast frames
sent and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we
have a counter called “frame send fail.” This keeps track of FIFO under-runs, late collisions and collisions that have
occurred 16 times.
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Data Sheet
14.0 Register Definition
14.1 MVTX2604 Register Description
2
Default
Notes
CPU Addr
(Hex)
I C Addr
Register
Description
R/W
(Hex)
0. ETHERNET Port Control Registers Substitute [N] with Port number (0..1A)
ECR1P”N”
ECR2P”N”
GGC
Port Control Register 1 for Port N
Port Control Register 2 for Port N
Extra GIGA bit control register
0000 + 2 x N
001 + 2 x N
036
R/W 000-01A
R/W 01B-035
R/W NA
020
000
000
1. VLAN Control Registers Substitute [N] with Port number (0..1A)
AVTCL
VLAN Type Code Register Low
VLAN Type Code Register High
Port “N” Configuration Register 0
Port “N” Configuration Register 1
Port “N” Configuration Register 2
Port “N” Configuration Register 3
VLAN Operating Mode
100
R/W 036
000
081
0FF
0FF
0FF
007
000
000
AVTCH
101
R/W 037
PVMAP”N”_0
PVMAP”N”_1
PVMAP”N”_2
PVMAP”N”_3
PVMODE
102 + 4N
103 + 4N
104 + 4N
105 + 4N
170
R/W 038-052
R/W 053-06D
R/W 06E-088
R/W 089-0A3
R/W 0A4
PVROUTE7-0
VLAN Router Group Enable
171-178
R/W NA
2. TRUNK Control Registers
TRUNK0_L
TRUNK0_M
TRUNK0_H
Trunk Group 0 Low
200
201
202
203
R/W NA
R/W NA
R/W NA
R/W 0A5
000
000
000
003
Trunk Group 0 Medium
Trunk Group 0 High
Trunk Group 0 Mode
TRUNK0_
MODE
TRUNK0_
HASH0
Trunk Group 0 Hash 0 Destination 204
Port
R/W NA
R/W NA
R/W NA
R/W NA
000
001
002
003
TRUNK0_
HASH1
Trunk Group 0 Hash 1 Destination 205
Port
TRUNK0_
HASH2
Trunk Group 0 Hash 2 Destination 206
Port
TRUNK0_
HASH3
Trunk Group 0 Hash 3 Destination 207
Port
TRUNK1_L
TRUNK1_M
Trunk Group 1 Low
208
209
R/W NA
R/W NA
000
000
Trunk Group 1 Medium
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Data Sheet
2
Default
Notes
CPU Addr
(Hex)
I C Addr
Register
Description
R/W
(Hex)
TRUNK1_H
Trunk Group 1 High
Trunk Group 1 Mode
20A
20B
R/W NA
R/W 0A6
000
003
TRUNK1_
MODE
TRUNK1_
HASH0
Trunk Group 1 Hash 0 Destination 20C
Port
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
004
005
006
007
003
019
01A
0FF
0FF
0FF
0FF
0FF
0FF
0FF
0FF
0FF
0FF
TRUNK1_
HASH1
Trunk Group 1 Hash 1 Destination 20D
Port
TRUNK1_
HASH2
Trunk Group 1 Hash 2 Destination 20E
Port
TRUNK1_
HASH3
Trunk Group 1 Hash 3 Destination 20F
Port
TRUNK2_
MODE
Trunk Group 2 Mode
210
TRUNK2_
HASH0
Trunk Group 2 Hash 0 Destination 211
Port
TRUNK2_
HASH1
Trunk Group 2 Hash 1 Destination 212
Port
Multicast_
HASH0-0
Multicast hash result 0 mask byte
0
220
221
222
223
224
225
226
227
228
229
Multicast_
HASH0-1
Multicast hash result 0 mask byte
1
Multicast_
HASH0-2
Multicast hash result 0 mask byte
2
Multicast_
HASH0-3
Multicast hash result 0 mask byte
3
Multicast_
HASH1-0
Multicast hash result 1 mask byte
0
Multicast_
HASH1-1
Multicast hash result 1 mask byte
1
Multicast_
HASH1-2
Multicast hash result 1 mask byte
2
Multicast_
HASH1-3
Multicast hash result 1 mask byte
3
Multicast_
HASH2-0
Multicast hash result 2 mask byte
0
Multicast_
HASH2-1
Multicast hash result 2 mask byte
1
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MVTX2604
Data Sheet
2
Default
Notes
CPU Addr
(Hex)
I C Addr
Register
Description
R/W
(Hex)
Multicast_
Multicast hash result 2 mask byte
2
22A
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
0FF
0FF
0FF
0FF
0FF
0FF
HASH2-2
Multicast_
HASH2-3
Multicast hash result 2 mask byte
3
22B
Multicast_
HASH3-0
Multicast hash result 3 mask byte
0
22C
22D
22E
22F
Multicast_
HASH3-1
Multicast hash result 3 mask byte
1
Multicast_
HASH3-2
Multicast hash result 3 mask byte
2
Multicast_
HASH3-3
Multicast hash result 3 mask byte
3
3. CPU Port Configuration
MAC0
CPU MAC Address byte 0
300
301
302
303
304
305
306
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
R/W NA
000
000
000
000
000
000
000
000
MAC1
CPU MAC Address byte 1
CPU MAC Address byte 2
CPU MAC Address byte 3
CPU MAC Address byte 4
CPU MAC Address byte 5
Interrupt Mask 0
MAC2
MAC3
MAC4
MAC5
INT_MASK0
INTP_MASK”N” Interrupt Mask for MAC Port 2N,
2N+1
310+N (310 - R/W NA
313)
RQS
Receive Queue Select
323
324
325
R/W NA
RO NA
000
N/A
008
RQSS
TX_AGE
Receive Queue Status
Transmission Queue Aging Time
R/W 0A7
4. Search Engine Configurations
AGETIME_LOW MAC Address Aging Time Low
400
401
R/W 0A8
R/W 0A9
2M:05C/
4M:02E
AGETIME_
HIGH
MAC Address Aging Time High
000
V_AGETIME
SE_OPMODE
SCAN
VLAN to Port Aging Time
Search Engine Operating Mode
Scan control register
402
403
404
R/W NA
R/W NA
R/W NA
0FF
000
000
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Data Sheet
2
Default
Notes
CPU Addr
(Hex)
I C Addr
Register
Description
R/W
(Hex)
5. Buffer Control and QOS Control
FCBAT
QOSC
FCB Aging Timer
500
501
502
503
504
505
506
507
508
509
50A
50B
R/W 0AA
R/W 0AB
R/W 0AC
R/W 0AD
R/W 0AE
R/W 0AF
R/W 0B0
R/W 0B1
R/W 0B2
R/W 0B3
R/W 0B4
R/W 0B5
R/W 0B6
0FF
000
008
000
000
000
000
000
000
000
000
000
QOS Control
FCR
Flooding Control Register
VLAN Priority Map Low
VLAN Priority Map Middle
VLAN Priority Map High
TOS Priority Map Low
TOS Priority Map Middle
TOS Priority Map High
VLAN Discard Map
AVPML
AVPMM
AVPMH
TOSPML
TOSPMM
TOSPMH
AVDM
TOSDML
BMRC
TOS Discard Map
Broadcast/Multicast Rate Control
Unicast Congestion Control
UCC
50C
2M:008/
4M:010
MCC
Multicast Congestion Control
50D
R/W 0B7
R/W 0B8
050
PR100
Port Reservation for 10/100 Ports 50E
2M:024/
4M:036
PRG
Port Reservation for Giga Ports
Share FCB Size
50F
510
R/W 0B9
R/W 0BA
2M:035/
4M:058
SFCB
2M:014/
4M:064
C2RS
C3RS
C4RS
C5RS
C6RS
C7RS
QOSC”N”
Class 2 Reserve Size
Class 3 Reserve Size
Class 4 Reserve Size
Class 5 Reserve Size
Class 6 Reserve Size
Class 7 Reserve Size
QOS Control (N=0 - 5)
QOS Control (N=6 - 11)
511
R/W 0BB
R/W 0BC
R/W 0BD
R/W 0BE
R/W 0BF
R/W 0C0
R/W 0C1-0C6
R/W NA
000
000
000
000
000
000
000
000
512
513
514
515
516
517- 51C
51D- 522
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Data Sheet
2
Default
Notes
CPU Addr
I C Addr
Register
Description
R/W
(Hex)
523- 52E
52F- 552
553
(Hex)
QOS Control (N=12 - 23)
QOS Control (N=24 - 59)
WRED Drop Rate Control 0
WRED Drop Rate Control 1
R/W 0C7-0D2
R/W NA
000
000
08F
088
RDRC0
R/W 0FB
R/W 0FC
RDRC1
554
USER_
User Define Logical Port “N” Low
(N=0-7)
580 + 2N
R/W 0D6-0DD 000
PORT”N”_LOW
USER_
User Define Logical Port “N” High 581 + 2N
R/W 0DE-0E5
R/W 0E6
000
000
PORT”N”_HIGH
USER_
User Define Logic Port 1 and 0
Priority
590
591
592
593
PORT1:0_
PRIORITY
USER_
User Define Logic Port 3 and 2
Priority
R/W 0E7
R/W 0E8
R/W 0E9
000
000
000
PORT3:2_
PRIORITY
USER_
User Define Logic Port 5 and 4
Priority
PORT5:4_
PRIORITY
USER_
User Define Logic Port 7 and 6
Priority
PORT7:6_PRI
ORITY
USER_PORT_
ENABLE
User Define Logic Port Enable
594
595
596
597
598
R/W 0EA
R/W 0EB
R/W 0EC
R/W 0ED
R/W 0EE
000
000
000
000
000
WLPP10
WLPP32
WLPP54
WLPP76
Well known Logic Port Priority for
1 and 0
Well known Logic Port Priority for
3 and 2
Well known Logic Port Priority for
5 and 4
Well-known Logic Port Priority for
7 & 6
WLPE
Well known Logic Port Enable
User Define Range Low Bit7:0
User Define Range Low Bit 15:8
User Define Range High Bit 7:0
User Define Range High Bit 15:8
User Define Range Priority
599
59A
59B
59C
59D
59E
R/W 0EF
R/W 0F4
R/W 0F5
R/W 0D3
R/W 0D4
R/W 0D5
000
000
000
000
000
000
RLOWL
RLOWH
RHIGHL
RHIGHH
RPRIORITY
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Data Sheet
2
Default
Notes
CPU Addr
I C Addr
Register
Description
R/W
(Hex)
(Hex)
CPUQOSC1~3
Byte limit for TxQ on CPU port
5A0-5A2
R/W NA
000
6. MISC Configuration Registers
MII_OP0
MII_OP1
FEN
MII Register Option 0
600
601
602
603
604
605
606
607
608
609
60A
60B
R/W 0F0
R/W 0F1
R/W 0F2
R/W N/A
R/W N/A
R/W N/A
R/W N/A
000
000
010
000
000
000
000
N/A
N/A
000
000
000
MII Register Option 1
Feature Registers
MIIC0
MIIC1
MIIC2
MIIC3
MIID0
MIID1
LED
MII Command Register 0
MII Command Register 1
MII Command Register 2
MII Command Register 3
MII Data Register 0
RO
RO
N/A
N/A
MII Data Register 1
LED Control Register
Device id and test
R/W 0F3
R/W N/A
R/W 0FF
DEVICE
SUM
EEPROM Checksum Register
7. Port Mirroring Controls
MIRROR1_SRC Port Mirror 1 Source Port
700
701
R/W N/A
R/W N/A
07F
017
MIRROR1_
DEST
Port Mirror 1 Destination Port
MIRROR2_SRC Port Mirror 2 Source Port
702
703
R/W N/A
R/W N/A
0FF
000
MIRROR2_
DEST
Port Mirror 2 Destination Port
F. Device Configuration Register
GCR
DCR
Global Control Register
F00
F01
R/W N/A
000
N/A
Device Status and Signature
Register
RO
N/A
DCR1
DPST
DTST
DA
Giga Port status
F02
F03
F04
FFF
RO
N/A
N/A
000
N/A
DA
Device Port Status Register
Data read back register
DA Register
R/W N/A
RO
RO
N/A
N/A
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MVTX2604
Data Sheet
14.2 Directly Accessed Registers
14.2.1 INDEX_REG0
•
•
Address bits [7:0] for indirectly accessed register addresses
Address = 0 (write only)
14.2.2 INDEX_REG1 (only needed for 8-bit mode)
•
•
Address bits [15:8] for indirectly accessed register addresses
Address = 1 (write only)
14.2.3 DATA_FRAME_REG
•
•
Data of indirectly accessed registers. (8 bits)
Address = 2 (read/write)
14.2.4 CONTROL_FRAME_REG
•
•
•
CPU transmit/receive switch frames. (8/16 bits)
Address = 3 (read/write)
Format:
- Send frame from CPU: In sequence)
Frame Data (size should be in multiple of 8-byte)
8-byte of Frame status (Frame size, Destination port #, Frame O.K. status)
- CPU Received frame: In sequence)
8-byte of Frame status (Frame size, Source port #, VLAN tag)
Frame Data
14.2.5 COMMAND&STATUS Register
•
•
•
CPU interface commands (write) and status
Address = 4 (read/write)
When the CPU writes to this register
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
•
•
•
•
Set Control Frame Receive buffer ready after CPU writes a complete frame
into the buffer. This bit is self-cleared.
Set Control Frame Transmit buffer1 ready after CPU reads out a complete
frame from the buffer. This bit is self-cleared.
Set Control Frame Transmit buffer2 ready after CPU reads out a complete
frame from the buffer. This bit is self-cleared.
Set this bit to indicate CPU received a whole frame (transmit FIFO frame
receive done), and flushed the rest of frame fragment. This bit will be self-
cleared.
Bit [4]:
•
Set this bit to indicate that the following Write to the Receive FIFO is the last
one (EOF). This bit will be self-cleared.
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MVTX2604
Data Sheet
Bit [5]:
•
Set this bit to re-start the data that is sent from the CPU to Receive FIFO
(re-align). This feature can be used for software debug. For normal
operation must be '0'.
Bit [6]:
Bit [7]:
•
•
Do not use. Must be '0'
Reserved
When the CPU reads this register:
Bit [0]:
Bit [1]:
Bit [2]:
•
•
•
Control Frame receive buffer ready, CPU can write a new frame
• 1 – CPU can write a new control command 1
• 0 – CPU has to wait until this bit is 1 to write a new control command 1
Control Frame transmit buffer1 ready for CPU to read
• 1 – CPU can read a new control command 1
• 0 – CPU has to wait until this bit is 1 to read a new control command
Control Frame transmit buffer2 ready for CPU to read
• 1 – CPU can read a new control command 1
• 0 – CPU has to wait until this bit is 1 to read a new control command
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
Transmit FIFO has data for CPU to read (TXFIFO_RDY)
Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK)
Transmit FIFO End Of Frame (TXFIFO_EOF)
Reserve
Reserve
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
14.2.6 Interrupt Register
•
•
•
Interrupt sources (8 bits)
Address = 5 (read only)
When CPU reads this register
Bit [0]:
Bit [1]:
•
•
CPU frame interrupt
Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU
to read
Bit [2]:
•
Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU
to read
Bit [3]:
Bit [4]:
Bit [7:5]:
•
•
•
Gigabit port A interrupt
Gigabit port B interrupt
Reserve
Note: This register is not self-cleared. After reading CPU has to clear the bit writing 0 to it.
14.2.7 Control Command Frame Buffer1 Access Register
•
•
•
Address = 6 (read/write)
When CPU writes to this register, data is written to the Control Command Frame Receive Buffer
When CPU reads this register, data is read from the Control Command Frame Transmit Buffer1
14.2.8 Control Command Frame Buffer2 Access Register
•
•
Address = 7 (read only)
When CPU reads this register, data is read from the Control Command Frame Transmit Buffer1
14.3 Indirectly Accessed registers
14.4 Group 0 Address MAC Ports Group
14.4.1 ECR1Pn: Port N Control Register
2
I C Address 000 - 01A; CPU Address:0000+2xN (N = port number)
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
4
2
1
0
3
Sp State
A-FC Port Mode
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Bit [0]
1 - Flow Control Off
0 - Flow Control On
•
•
When Flow Control On:
In half duplex mode the MAC transmitter applies back pressure for flow
control.
•
In full duplex mode the MAC transmitter sends Flow Control frames when
necessary. The MAC receiver interprets and processes incoming flow
control frames. The Flow Control Frame Received counter is incremented
whenever a flow control is received.
•
•
When Flow Control off:
In half duplex mode the MAC Transmitter does not assert flow control by
sending flow control frames or jamming collision.
•
In full duplex mode the Mac transmitter does not send flow control frames.
The MAC receiver does not interpret or process the flow control frames. The
Flow Control Frame Received counter is not incremented.
Bit [1]
1 - Half Duplex - Only in 10/100 mode
0 - Full Duplex
Bit [2]
1 - 10 Mbps
0 - 100 Mbps
Bit [4:3]
00 – Automatic Enable Auto Neg. - This enables hardware state machine
for auto-negotiation.
01 - Limited Disable auto Neg. This disables hardware for speed auto-nego-
tiation. Hardware Poll MII for link status.
10 - Link Down. Force link down (disable the port).
11 - Link Up. The configuration in ECR1[2:0] is used for (speed/half
duplex/full duplex/flow control) setup.
Bit [5]
•
Asymmetric Flow Control Enable.
0 – Disable asymmetric flow control
01 – Enable Asymmetric flow control
•
•
When this bit is set, and flow control is on (bit[0] = 0), don’t send out a flow
control frame. But MAC receiver interprets and processes flow control
frames.
Bit [7:6]
SS - Spanning tree state (802.1D spanning tree protocol) Default is 11.
00 – Blocking: Frame is dropped
01 - Listening:
10 - Learning:
Frame is dropped
Frame is dropped. Source MAC address is learned.
11 - Forwarding: Frame is forwarded. Source MAC address is learned.
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MVTX2604
Data Sheet
14.4.2 ECR2Pn: Port N Control Register
2
I C Address: 01B-035; CPU Address:0001+2xN (N = port number)
Accessed by CPU and serial interface (R/W)
7
6
5
4
3
2
1
0
Security En
QoS Sel
Reserve DisL
Ftf
Futf
Bit [0]:
Bit [1]:
Bit [2]:
•
Filter untagged frame (Default 0)
• 0: Disable
• 1: All untagged frames from this port are discarded or follow security option when
security is enable
•
Filter Tag frame (Default 0)
• 0: Disable
• 1: All tagged frames from this port are discarded or follow security option when
security is enable
•
•
Learning Disable (Default 0)
• 1 Learning is disabled on this port
• 0 Learning is enabled on this port
Bit [3]:
Must be ‘1’
Bit [5:4:]
•
•
•
QOS mode selection (Default 00)
Determines which of the 4 sets of QoS settings is used for 10/100 ports.
Note that there are 4 sets of per-queue byte thresholds, and 4 sets of WFQ
ratios programmed. These bits select among the 4 choices for each 10/100
port. Refer to QOS Application Note.
• 00: select class byte limit set 0 and classes WFQ credit set 0
• 01: select class byte limit set 1 and classes WFQ credit set 1
• 10: select class byte limit set 2 and classes WFQ credit set 2
• 11: select class byte limit set 3 and classes WFQ credit set 3
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MVTX2604
Data Sheet
Bit[7:6]
•
Security Enable (Default 00). The MVTX2604 checks the incoming data for
one of the following conditions:
1. If the source MAC address of the incoming packet is in the MAC table
and is defined as secure address but the ingress port is not the same as the
port associated with the MAC address in the MAC table.
A MAC address is defined as secure when its entry at MAC table has static
status and bit 0 is set to 1. MAC address bit 0 (the first bit transmitted) indi-
cates whether the address is unicast or multicast. As source addresses are
always unicast bit 0 is not used (always 0). MVTX2600 uses this bit to
define secure MAC addresses.
2. If the port is set as learning disable and the source MAC address of the
incoming packet is not defined in the MAC address table.
3. If the port is configured to filter untagged frames and an untagged frame
arrives or if the port is configured to filter tagged frames and a tagged frame
arrives.
If one of these three conditions occurs the packet will be handled according
to one of the following specified options:
•
CPU installed
• 00 – Disable port security
• 01 – Discard violating packets
• 10 – Send packet to CPU and destination port
• 11 – Send packet to CPU only
14.4.3 GGControl – Extra GIGA Port Control
CPU Address:h036
Accessed by CPU and serial interface (R/W)
7
6
5
4
3
2
1
0
DF
DI
MiiB
RstA
DF
DI
MiiA RstA
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
•
•
•
•
Reset GIGA port A
• 0: Normal operation (default)
• 1: Reset Gigabit port A. Normally used when a new Phy is connected (Hot swap).
GIGA port A use MII interface (10/100M)
• 0: Gigabit port operations at 1000 mode (default)
• 1: Gigabit port operations at 10/100 mode
Device information insertion enable for Gigabit port A
• 0: Disable preamble stack device ID insertion (default).
• 1: Insert stack device ID into the preamble (must be enabled for ring mode).
GIGA port A direct flow control (MAC to MAC connection). The MVTX2604
supports direct flow control mechanism; the flow control frame is therefore
not sent through the Gigabit port data path.
• 0: Direct flow control disabled (default)
• 1: Direct flow control enabled
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Data Sheet
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
Reset GIGA port B
• 0: Normal operation (default)
• 1: Reset Gigabit port B
GIGA port B use MII interface (10/100M)
• 0: Gigabit port operates at 1000 mode (default)
• 1: Gigabit port operates at 10/100 mode
Device information attach enable for Gigabit port B
• 0: Disable preamble stack device ID insertion (default)
• 1: Insert stack device ID into the preamble (must be enabled for ring mode).
GIGA port B direct flow control (MAC to MAC connection). MVTX2604
supports direct flow control mechanism; the flow control frame is therefore
not sent through the Gigabit port data path.
• 0: Direct flow control disabled (default)
• 1: Direct flow control enabled
14.5 Group 1 Address VLAN Group
14.5.1 AVTCL – VLAN Type Code Register Low
2
I C Address 036; CPU Address:h100
2
Accessed by CPU, serial interface and I C (R/W)
Bit [7:0]:
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 00)
14.5.2 AVTCH – VLAN Type Code Register High
2
I C Address 037; CPU Address:h101
2
Accessed by CPU, serial interface and I C (R/W)
Bit [7:0]:
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 81)
14.5.3 PVMAP00_0 – Port 00 Configuration Register 0
2
I C Address 038, CPU Address:h102
2
Accessed by CPU, serial interface and I C (R/W)
In Port Based VLAN Mode
Bit [7:0]:
VLAN Mask for ports 7 to 0 (Default FF)
This register indicates the legal egress ports. A “1” on bit 7 means that the packet can be sent to port 7. A
“0” on bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1,
2 and 3 to form a 27 bit mask to all egress ports.
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Data Sheet
In Tag based VLAN Mode
Bit [7:0]:
PVID [7:0] (Default is FF)
This is the default VLAN tag. It works with configuration register PVMAP00_1 [7:5] [3:0] to form a default
VLAN tag. If the received packet is untagged, then the packet is classified with the default VLAN tag. If the
received packet has a VLAN ID of 0, then PVID is used to replace the packet’s VLAN ID.
14.5.4 PVMAP00_1 – Port 00 Configuration Register 1
2
I C Address h53, CPU Address:h103
2
Accessed by CPU, serial interface and I C (R/W)
In Port based VLAN Mode
Bit [7:0]:
VLAN Mask for ports 15 to 8 (Default is FF)
In Tag based VLAN Mode
7
5
4
3
0
Unitag Port Priority Ultrust PVID
Bit [3:0]:
Bit [4]:
PVID [11:8] (Default is F)
•
Untrusted Port. (Default is 1)
This register is used to change the VLAN priority field of a packet to a prede-
termined priority.
• 1 : VLAN priority field is changed to Bit[7:5] at ingress port
• 0 : Keep VLAN priority field
Bit [7:5]:
•
Untag Port Priority (Default 7)
14.5.5 PVMAP00_2 – Port 00 Configuration Register 2
2
I C Address h6E, CPU Address:h104
2
Accessed by CPU, serial interface and I C (R/W)
In Port Based VLAN Mode
Bit [7:0]:
•
VLAN Mask for ports 23 to 16 (Default FF)
In Tag based VLAN Mode
This registered is unused
14.5.6 PVMAP00_3 – Port 00 Configuration Register 3
2
I C Address h89, CPU Address:h105
2
Accessed by CPU, serial interface and I C (R/W)
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In Port Based VLAN Mode
7
6
5
3
2
0
FP
en
Drop
Default
priority
tx VLAN Mask
Bit [2:0]:
Bit [5:3]:
VLAN Mask for ports 26 to 24 (Default 7). Port 24 is the CPU port
Default Transmit priority. Used when Bit [7] = 1 (Default 0)
• 000 Transmit Priority Level 0 (Lowest)
• 001 Transmit Priority Level 1
• 010 Transmit Priority Level 2
• 011 Transmit Priority Level 3
• 100 Transmit Priority Level 4
• 101 Transmit Priority Level 5
• 110 Transmit Priority Level 6
• 111 Transmit Priority Level 7 (Highest)
Bit [6]:
Bit [7]:
Default Discard priority. Used when Bit[7]=1 (Default 0)
• 0 - Discard Priority Level 0 (Lowest)
• 1 - Discard Priority Level 1(Highest)
Enable Fix Priority (Default 0)
• 0 Disable fix priority. All frames are analyzed. Transmit Priority and Discard
Priority are based on VLAN Tag, TOS or Logical Port.
• 1 Transmit Priority and Discard Priority are based on values programmed in bit
[6:3]
In Tag-based VLAN Mode
Bit [0]:
Bit [1]:
•
Not used
Ingress Filter Enable (Default 1)
• 0 Disable Ingress Filter. Packets with VLAN not belonging to source
port are forwarded, if destination port belongs to the VLAN. Symmetric
VLAN.
• 1 Enable Ingress Filter. Packets with VLAN not belonging to source port
are filtered. Asymmetric VLAN.
Bit [2]:
Force untag out (VLAN tagging is based on 802.1q rule) (Default 1).
• 0 Disable (Default)
• 1 Force untagged output
All packets transmitted from this port are untagged. This register is used
when this port is connected to legacy equipment that does not support
VLAN tagging.
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Bit [5:3]:
Default Transmit priority. Used when Bit [7] = 1 (Default 0)
• 000 Transmit Priority Level 0 (Lowest)
• 001 Transmit Priority Level 1
• 010 Transmit Priority Level 2
• 011 Transmit Priority Level 3
• 100 Transmit Priority Level 4
• 101 Transmit Priority Level 5
• 110 Transmit Priority Level 6
• 111 Transmit Priority Level 7 (Highest)
Bit [6]:
Bit [7]:
Default Discard priority Used when Bit [7] =1 (Default 0)
• 0 - Discard Priority Level 0 (Lowest)
• 1 Discard Priority Level 1 (Highest)
Enable Fix Priority (Default 0)
• 0 Disable fix priority. All frames are analyzed. Transmit Priority and
Discard Priority are based on VLAN Tag, TOS or Logical Port.
• 1 Transmit Priority and Discard Priority are based on values
programmed in bit [6:3]
14.6 Port Configuration Registers
2
PVMAP01_0,1,2,3 I C Address h39,54,6F,8A; CPU Address:h106,107,108,109)
2
PVMAP02_0,1,2,3 I C Address h3A,55,70,8B; CPU Address:h10A, 10B, 10C, 10D)
2
PVMAP03_0,1,2,3 I C Address h3B,56,71,8C; CPU Address:h10E, 10F, 110, 111)
2
PVMAP04_0,1,2,3 I C Address h3C,57,72,8D; CPU Address:h112, 113, 114, 115)
2
PVMAP05_0,1,2,3 I C Address h3D,58,73,8E; CPU Address:h116, 117, 118, 119)
2
PVMAP06_0,1,2,3 I C Address h3E,59,74,8F; CPU Address:h11A, 11B, 11C, 11D)
2
PVMAP07_0,1,2,3 I C Address h3F,5A,75,90; CPU Address:h11E, 11F, 120, 121)
2
PVMAP08_0,1,2,3 I C Address h40,5B,76,91; CPU Address:h122, 123, 124, 125)
2
PVMAP09_0,1,2,3 I C Address h41,5C,77,92; CPU Address:h126, 127, 128, 129)
2
PVMAP10_0,1,2,3 I C Address h42,5D,78,93; CPU Address:h12A, 12B, 12C, 12D)
2
PVMAP11_0,1,2,3 I C Address h43,5E,79,94; CPU Address:h12E, 12F, 130, 131)
2
PVMAP12_0,1,2,3 I C Address h44,5F,7A,95; CPU Address:h132, 133, 134, 135)
2
PVMAP13_0,1,2,3 I C Address h45,60,7B,96; CPU Address:h136, 137, 138, 139)
2
PVMAP14_0,1,2,3 I C Address h46,61,7C,97; CPU Address:h13A, h13B, 13C, 13D)
2
PVMAP15_0,1,2,3 I C Address h47,62,7D,98; CPU Address:h13E, 13F, 140, 141)
2
PVMAP16_0,1,2,3 I C Address h48,63,7E,99; CPU Address:h142, 143, 144, 145)
2
PVMAP17_0,1,2,3 I C Address h49,64,7F,9A; CPU Address:h146, 147, 148, 149)
2
PVMAP18_0,1,2,3 I C Address h4A,65,80,9B; CPU Address:h14A, 14B, 14C, 14D)
2
PVMAP19_0,1,2,3 I C Address h4B,66,81,9C; CPU Address:h14E, 14F, 150, 151)
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2
PVMAP20_0,1,2,3 I C Address h4C,67,82,9D; CPU Address:h152, 153, 154, 155)
2
PVMAP21_0,1,2,3 I C Address h4D,68,83,9E; CPU Address:h156, 157, 158, 159)
2
PVMAP22_0,1,2,3 I C Address h4E,69,84,9F; CPU Address:h15A, 15B, 15C, 15D)
2
PVMAP23_0,1,2,3 I C Address h4F,6A,85,A0; CPU Address:h15E, 15F, 160, 161)
2
PVMAP24_0,1,2,3 I C Address h50,6B,86,A1; CPU Address:h162, 163, 164, 165) (CPU port)
2
PVMAP25_0,1,2,3 I C Address h51,6C,87,A2; CPU Address:h166, 167, 168, 169) (Giagabit port 1)
2
PVMAP26_0,1,2,3 I C Address h52,6D,88,A3; CPU Address:h16A, 16B, 16C, 16D) (Gigabit port 2)
14.6.1 PVMODE
2
I C Address: h0A4, CPU Address:h170
Accessed by CPU, serial interface (R/W)
7
6
5
4
3
2
1
0
MAC05
MMA STP SM0 rPCS
DF
SL
Vmod
Bit [0]:
•
•
•
VLAN Mode (Default = 0)
• 1 Tag based VLAN Mode
• 0 Port based VLAN Mode
Bit [1]:
Bit [2]:
Slow learning (Default = 0)
Same function as SE_OP MODE bit 7. Either bit can enable the function;
both need to be turned off to disable the feature.
Disable dropping of frames with destination MAC addresses
0180C2000001 to 0180C200000F (Default = 0)
• 0: Drop all frames in this range
• 1: Disable dropping of frames in this range
Bit [3]:
Bit [4]:
Bit [5]:
•
•
•
Disable Reset PCS (Default = 0)
• 0: Enable reset PCS. PCS FIFO will be reset when received a PCS symbol error.
• 1: Disable reset PCS
Support MAC address 0 (Default = 0)
• 0: MAC address 0 is not learned.
• 1: MAC address 0 is learned.
Disable IEEE multicast control frame (0180C2000000 to 0180C20000FF)
to CPU in managed mode (Default = 0)
• 0: Packet is forwarded to CPU
• 1: Packet is forwarded as multicast
Bit [6]:
•
Multiple MAC addresses (Default = 0)
• 0: Single MAC address is assigned to CPU. Registers MAC0 to MAC5 are used
to program the CPU MAC address.
• 1: One block of 32 MAC addresses are assigned to CPU. The block is defined in
an increase way from the MAC address programmed in registers MAC0 to
MAC5.
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Bit [7]:
•
Disable registers MAC 5 – 0 (CPU MAC address) in comparison with
Ethernet frame destination MAC address. When disable, unicast frames
are not forward to CPU. (Default = 0)
• 1: Disable
• 0: Enable
14.6.2 PVROUTE 0
Registers PVROUTE0 to PVROUTE7 allows the VLAN Index to be assigned an address of a router group. This
feature is useful during IP Multicast mode when data is being sent to the VLAN group and no member of the group
registers. By assigning a router group the VLAN group always has a default address to handle the multicast traffic.
CPU Address:h171
Accessed by CPU, serial interface (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
VLAN Index 8’hC0 has router group and the router group is VLAN Index 8’h40
VLAN Index 8’hC1 has router group and the router group is VLAN Index 8’h41
VLAN Index 8’hC2 has router group and the router group is VLAN Index 8’h42
VLAN Index 8’hC3 has router group and the router group is VLAN Index 8’h43
VLAN Index 8’hC4 has router group and the router group is VLAN Index 8’h44
VLAN Index 8’hC5 has router group and the router group is VLAN Index 8’h45
VLAN Index 8’hC6 has router group and the router group is VLAN Index 8’h46
VLAN Index 8’hC7 has router group and the router group is VLAN Index 8’h47
14.6.3 PVROUTE1
CPU Address:h172
Accessed by CPU, serial interface (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
VLAN Index 8’hC8 has router group and the router group is VLAN Index 8’h48
VLAN Index 8’hC9 has router group and the router group is VLAN Index 8’h48
VLAN Index 8’hCA has router group and the router group is VLAN Index 8’h4A
VLAN Index 8’hCB has router group and the router group is VLAN Index 8’h4B
VLAN Index 8’hCC has router group and the router group is VLAN Index 8’h4C
VLAN Index 8’hCD has router group and the router group is VLAN Index 8’h4D
VLAN Index 8’hCE has router group and the router group is VLAN Index 8’h4E
VLAN Index 8’hCF has router group and the router group is VLAN Index 8’h4F
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14.6.4 PVROUTE2
CPU Address:h173
Accessed by CPU, serial interface (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
VLAN Index 8’hD0 has router group and the router group is VLAN Index 8’h50
VLAN Index 8’hD1 has router group and the router group is VLAN Index 8’h51
VLAN Index 8’hD2 has router group and the router group is VLAN Index 8’h52
VLAN Index 8’hD3 has router group and the router group is VLAN Index 8’h53
VLAN Index 8’hD4 has router group and the router group is VLAN Index 8’h54
VLAN Index 8’hD5 has router group and the router group is VLAN Index 8’h55
VLAN Index 8’hD6 has router group and the router group is VLAN Index 8’h56
VLAN Index 8’hD7 has router group and the router group is VLAN Index 8’h57
14.6.5 PVROUTE3
CPU Address:h174
Accessed by CPU, serial interface (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
VLAN Index 8’hD8 has router group and the router group is VLAN Index 8’h58
VLAN Index 8’hD9 has router group and the router group is VLAN Index 8’h59
VLAN Index 8’hDA has router group and the router group is VLAN Index 8’h5A
VLAN Index 8’hDB has router group and the router group is VLAN Index 8’h5B
VLAN Index 8’hDC has router group and the router group is VLAN Index 8’h5C
VLAN Index 8’hDD has router group and the router group is VLAN Index 8’h5D
VLAN Index 8’hDE has router group and the router group is VLAN Index 8’h5E
VLAN Index 8’hDF has router group and the router group is VLAN Index 8’h5F
14.6.6 PVROUTE4
CPU Address:h175
Accessed by CPU, serial interface (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
VLAN Index 8’hE0 has router group and the router group is VLAN Index 8’h60
VLAN Index 8’hE1 has router group and the router group is VLAN Index 8’h61
VLAN Index 8’hE2 has router group and the router group is VLAN Index 8’h62
VLAN Index 8’hE3 has router group and the router group is VLAN Index 8’h63
VLAN Index 8’hE4 has router group and the router group is VLAN Index 8’h64
VLAN Index 8’hE5 has router group and the router group is VLAN Index 8’h65
VLAN Index 8’hE6 has router group and the router group is VLAN Index 8’h66
VLAN Index 8’hE7 has router group and the router group is VLAN Index 8’h67
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14.6.7 PVROUTE5
CPU Address:h176
Accessed by CPU, serial interface (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
VLAN Index 8’hE8 has router group and the router group is VLAN Index 8’h68
VLAN Index 8’hE9 has router group and the router group is VLAN Index 8’h69
VLAN Index 8’hEA has router group and the router group is VLAN Index 8’h6A
VLAN Index 8’hEB has router group and the router group is VLAN Index 8’h6B
VLAN Index 8’hEC has router group and the router group is VLAN Index 8’h6C
VLAN Index 8’hED has router group and the router group is VLAN Index 8’h6D
VLAN Index 8’hEE has router group and the router group is VLAN Index 8’h6E
VLAN Index 8’hEF has router group and the router group is VLAN Index 8’h6F
14.6.8 PVROUTE6
CPU Address:h177
Accessed by CPU, serial interface (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
•
•
•
•
•
•
•
•
VLAN Index 8’hF0 has router group and the router group is VLAN Index 8’h70
VLAN Index 8’hF1 has router group and the router group is VLAN Index 8’h71
VLAN Index 8’hF2 has router group and the router group is VLAN Index 8’h72
VLAN Index 8’hF3 has router group and the router group is VLAN Index 8’h73
VLAN Index 8’hF4 has router group and the router group is VLAN Index 8’h74
VLAN Index 8’hF5 has router group and the router group is VLAN Index 8’h75
VLAN Index 8’hF6 has router group and the router group is VLAN Index 8’h76
VLAN Index 8’hF7 has router group and the router group is VLAN Index 8’h77
14.6.9 PVROUTE7
CPU Address:h178
Accessed by CPU, serial interface (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
•
•
•
•
•
VLAN Index 8’hF8 has router group and the router group is VLAN Index 8’h78
VLAN Index 8’hF9 has router group and the router group is VLAN Index 8’h79
VLAN Index 8’hFA has router group and the router group is VLAN Index 8’h7A
VLAN Index 8’hFB has router group and the router group is VLAN Index 8’h7B
VLAN Index 8’hFC has router group and the router group is VLAN Index
8’h7C
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Bit [5]:
•
VLAN Index 8’hFD has router group and the router group is VLAN Index
8’h7D
Bit [6]:
Bit [7]:
•
•
VLAN Index 8’hFE has router group and the router group is VLAN Index 8’h7E
VLAN Index 8’hFF has router group and the router group is VLAN Index 8’h7F
14.7 Group 2 Address Port Trunking Groups
Trunk Group 0 - Up to four 10/100 ports can be selected for trunk group 0.
14.7.1 TRUNK0_L – Trunk group 0 Low (Managed mode only)
CPU Address:h200
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port7-0 bit map of trunk 0. (Default 00)
14.7.2 TRUNK0_M – Trunk group 0 Medium (Managed mode only)
CPU Address:h201
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port15-8 bit map of trunk 0. (Default 00)
14.7.3 TRUNK0_H – Trunk group 0 High (Managed mode only)
CPU Address:h202
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port23-16 bit map of trunk 0. (Default 00)
TRUNK0_H, TRUNK0_M, and TRUNK0_L provide a trunk map for trunk0. If ports 0 and 2 are to be trunked
together bit 0 and bit 2 of TRUNK0_L are set to 1. All others are clear at “0” to indicate that they are not part of
trunk 0. Up to 4 ports can be selected for trunk group 0.
B
i
B B
B
i
B
i
B
i
i
i
t
t
t
t
t
t
7
0 7
0
7
0
TRUNK0_H
TRUNK0_M
TRUNK0_L
P
o
r
P
o
r
P
o
r
P
P
o
r
P
o
r
o
r
t
t
t
t
t
t
23
16 15
8
7
0
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14.7.4 TRUNK0_MODE– Trunk group 0 mode
2
I C Address h0A5; CPU Address:203
2
Accessed by CPU, serial interface and I C (R/W)
7
4
3
2
1
0
Hash
Port
Select
Select
Bit [1:0]:
•
•
Port selection in unmanaged mode. Input pin TRUNK0 enable/disable
trunk group 0 in unmanaged mode.
00 Reserved
01 Port 0 and 1 are used for trunk0
10 Port 0,1 and 2 are used for trunk0
11 Port 0,1,2 and 3 are used for trunk0
Bit [3:2]
Hash Select. The Hash selected is valid for Trunk 0, 1 and 2. (Default
00)
00 Use Source and Destination Mac Address for hashing
01 Use Source Mac Address for hashing
10 Use Destination Mac Address for hashing
11 Use source destination MAC address and ingress physical port
number for hashing
14.7.5 TRUNK0_HASH0 – Trunk group 0 hash result 0 destination port number
CPU Address:h204
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 0 destination port number (Default 00)
14.7.6 TRUNK0_HASH1 – Trunk group 0 hash result 1 destination port number
CPU Address:h205
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 1 destination port number (Default 01)
14.7.7 TRUNK0_HASH2 – Trunk group 0 hash result 2 destination port number
CPU Address:h206
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 2 destination port number (Default 02)
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14.7.8 TRUNK0_HASH3 – Trunk group 0 hash result 3 destination port number
CPU Address:h207
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 3 destination port number (Default 03)
Trunk Group 1 - Up to four 10/100 ports can be selected for trunk group 1.
14.7.9 TRUNK1_L – Trunk group 1 Low (Managed mode only)
Port selection for trunk group 1.
CPU Address:h208
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port7-0 bit map of trunk 1. (Default 00)
14.7.10 TRUNK1_M – Trunk group 1 Medium (Managed mode only)
CPU Address:h209
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port15-8 bit map of trunk 1. (Default 00)
14.7.11 TRUNK1_H – Trunk group 1 High (Managed mode only)
CPU Address:h20A
Accessed by CPU, serial interface (R/W)
Bit [7:0] Port23-16 bit map of trunk 1. (Default 00)
14.7.12 TRUNK1_MODE – Trunk group 1 mode
2
I C Address h0A6; CPU Address:20B
2
Accessed by CPU, serial interface and I C (R/W)
7
2
1
0
Port Select
Bit [1:0]:
•
Port selection in unmanaged mode. Input pin TRUNK1
enable/disable trunk group 1 in unmanaged mode.
• 00 Reserved
• 01 Port 4 and 5 are used for trunk1
• 10 Reserved
• 11 Port 4,5,6 and 7 are used for trunk1
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14.7.13 TRUNK1_HASH0 – Trunk group 1 hash result 0 destination port number
•
•
•
CPU Address:h20C
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 0 destination port number (Default 04)
14.7.14 TRUNK1_HASH1 – Trunk group 1 hash result 1 destination port number
CPU Address:h20D
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 1 destination port number (Default 05)
14.7.15 TRUNK1_HASH2 – Trunk group 1 hash result 2 destination port number
CPU Address:h20E
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 1 destination port number (Default 06)
14.7.16 TRUNK1_HASH3 – Trunk group 1 hash result 3 destination port number
CPU Address:h20F
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 1 destination port number (Default 07)
Trunk Group 2
14.7.17 TRUNK2_MODE – Trunk group 2 mode (Gigabit ports 1 and 2)
CPU Address:210
Accessed by CPU, serial interface (R/W)
7
6
4
3
0
Ring/trunk Mode
Reserved
Bit [3:0]
Bit [6:4]
000 Normal
001 Trunk Mode. Enable Trunk group for Gigabit port 1 and 2 in
managed mode. In unmanaged mode Trunk 2 is enable/disable
using input pin TRUNK2.
• 010 Single Ring with G1
• 100 Single Ring with G2
• 111 Dual Ring Mode
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14.7.18 TRUNK2_HASH0 – Trunk group 2 hash result 0 destination port number
CPU Address:h211
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 0 destination port number (Default 0x19)
0x19 = Gigabit port 1
0x1A = Gigabit port 2
14.7.19 TRUNK2_HASH1 – Trunk group 2 hash result 1 destination port number
CPU Address:h211
Accessed by CPU, serial interface (R/W)
Bit [4:0]
Hash result 1 destination port number (Default 0x1A)
0x19 = Gigabit port 1
0x1A = Gigabit port 2
14.7.20 Multicast Hash Registers
Multicast Hash registers are used to distribute multicast traffic. 16 registers are used to form a 4-entry array; each
entry has 27 bits, with each bit representing one port. Any port not belonging to a trunk group should be
programmed with 1. Ports belonging to the same trunk group should only have a single port set to “1” per entry.
The port set to “1” is picked to transmit the multicast frame when the hash value is met.
Hash Value =0
Hash Value =1
Hash Value =2
Hash Value =3
HASH0_3
HASH1_3
HASH2_3
HASH3_3
HASH0_2
HASH1_2
HASH2_2
HASH3_2
HASH0_1
HASH1_1
HASH2_1
HASH3_1
HASH0_0
HASH1_0
HASH2_0
HASH3_0
P
o
r
P
o
r
P
o
r
P
o
r
P P
P
o
r
P
o
o o
r
r
r
t
t
t
t
t
t
t
26
16 15
t
7
0
23
24
C
P
U
8
Multicast_HASH0-0 – Multicast hash result 0 mask byte 0
CPU Address:h220
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
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14.7.20.1 Multicast_HASH0-1 – Multicast hash result 0 mask byte 1
CPU Address:h221
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.2 Multicast_HASH0-2 – Multicast hash result 0 mask byte 2
CPU Address:h222
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.3
MULTICAST_HASH0-3 – MULTICAST HASH RESULT 0 MASK BYTE 3
CPU Address:h223
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.4 Multicast_HASH1-0 – Multicast hash result 1 mask byte 0
CPU Address:h224
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.5
MULTICAST_HASH1-1 – MULTICAST HASH RESULT 1 MASK BYTE 1
CPU Address:h225
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.6 Multicast_HASH1-2 – Multicast hash result 1 mask byte 2
CPU Address:h226
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.7 Multicast_HASH1-3 – Multicast hash result 1 mask byte 3
CPU Address:h227
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
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14.7.20.8 Multicast_HASH2-0 – Multicast hash result 2 mask byte 0
CPU Address:h228
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.9
MULTICAST_HASH2-1 – MULTICAST HASH RESULT 2 MASK BYTE 1
CPU Address:h229
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.10
MULTICAST_HASH2-2 – MULTICAST HASH RESULT 2 MASK BYTE 2
CPU Address:h22A
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.11
MULTICAST_HASH2-3 – MULTICAST HASH RESULT 2 MASK BYTE 3
CPU Address:h22B
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.12
MULTICAST_HASH3-0 – MULTICAST HASH RESULT 3 MASK BYTE 0
CPU Address:h22C
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.13
MULTICAST_HASH3-1 – MULTICAST HASH RESULT 3 MASK BYTE 1
CPU Address:h22D
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.7.20.14
MULTICAST_HASH3-2 – MULTICAST HASH RESULT 3 MASK BYTE 2
CPU Address:h22E
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
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14.7.20.15 Multicast_HASH3-3 – Multicast hash result 3 mask byte 3
CPU Address:h22F
Accessed by CPU, serial interface (R/W)
Bit [7:0]
(Default FF)
14.8 Group 3 Address CPU Port Configuration Group
5
0
MAC5
MAC4
MAC3 MAC2 MAC1
MAC0
MAC5 to MAC0 registers form the CPU MAC address. When a packet with destination MAC address match MAC
[5:0], the packet is forwarded to the CPU.
14.8.1 MAC0 – CPU Mac address byte 0
CPU Address:h300
Accessed by CPU
Bit [7:0] Byte 0 of the CPU MAC address. (Default 00)
14.8.2 MAC1 – CPU Mac address byte 1
CPU Address:h301
Accessed by CPU
Bit [7:0] Byte 1 of the CPU MAC address. (Default 00)
14.8.3 MAC2 – CPU Mac address byte 2
CPU Address:h302
Accessed by CPU
Bit [7:0] Byte 2 of the CPU MAC address. (Default 00)
14.8.4 MAC3 – CPU Mac address byte 3
CPU Address:h303
Accessed by CPU
Bit [7:0] Byte 3 of the CPU MAC address. (Default 00)
14.8.5 MAC4 – CPU Mac address byte 4
CPU Address:h304
Accessed by CPU
Bit [7:0] Byte 4 of the CPU MAC address. (Default 00)
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14.8.6 MAC5 – CPU Mac address byte 5
CPU Address:h305
Accessed by CPU
Bit [7:0] Byte 5 of the CPU MAC address. (Default 00).
14.8.7 INT_MASK0 – Interrupt Mask 0
CPU Address:h306
Accessed by CPU, serial interface (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0xFF)
Bit [7:0] MASK
- 1: Mask the interrupt
- 0: Unmask the interrupt (Enable interrupt)
Bit [0]:
Bit [1]:
•
•
CPU frame interrupt. CPU frame buffer has data for CPU to read
Control Command 1 interrupt. Control Command Frame buffer1 has data for
CPU to read
Bit [2]:
•
•
Control Command 2 interrupt. Control command Frame buffer2 has data for
CPU to read
Bit [7:3]:
Reserved
14.8.8 INTP_MASK0 – Interrupt Mask for MAC Port 0,1
CPU Address:h310
Accessed by CPU, serial interface (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0xFF)
7
6
5
4
3
2
1
0
P1
P0
- 1: Mask the interrupt
- 0: Unmask the interrupt
Bit [0]:
Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a
statistic counter wraps around. Refer to hardware statistic counter for interrupt
sources.
Bit [1]:
Bit [4]:
Port 0 link change mask
Port 1 statistic counter wrap around interrupt mask. Refer to hardware statistic
counter for interupt sources.
Bit [5]:
Port 1 link change mask
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14.8.9 INTP_MASK1 – Interrupt Mask for MAC Port 2,3
CPU Address:h311
Accessed by CPU, serial interface (R/W)
14.8.10 INTP_MASK2 – Interrupt Mask for MAC Port 4,5
CPU Address:h312
Accessed by CPU, serial interface (R/W)
14.8.11 INTP_MASK3 – Interrupt Mask for MAC Port 6,7
CPU Address:h313
Accessed by CPU, serial interface (R/W)
14.8.12 INTP_MASK4 – Interrupt Mask for MAC Port 8,9
CPU Address:h314
Accessed by CPU, serial interface (R/W)
14.8.13 INTP_MASK5 – Interrupt Mask for MAC Port 10,11
CPU Address:h315
Accessed by CPU, serial interface (R/W)
14.8.14 INTP_MASK6 – Interrupt Mask for MAC Port 12,13
CPU Address:h316
Accessed by CPU, serial interface (R/W)
14.8.15 INTP_MASK7 – Interrupt Mask for MAC Port 14,15
CPU Address:h317
Accessed by CPU, serial interface (R/W)
14.8.16 INTP_MASK8 – Interrupt Mask for MAC Port 16,17
CPU Address:h318
Accessed by CPU, serial interface (R/W)
14.8.17 NTP_MASK9 – Interrupt Mask for MAC Port 18,19
CPU Address:h319
Accessed by CPU, serial interface (R/W)
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14.8.18 INTP_MASK10 – Interrupt Mask for MAC Port 20,21
CPU Address:h31A
Accessed by CPU, serial interface (R/W)
14.8.19 INTP_MASK11 – Interrupt Mask for MAC Port 22,23
CPU Address:h31B
Accessed by CPU, serial interface (R/W)
14.8.20 INTP_MASK12 – Interrupt Mask for MAC Port G1,G2
CPU Address:h31C
Accessed by CPU, serial interface (R/W)
14.8.21 RQS – Receive Queue Select CPU Address:h323)
Accessed by CPU, serial interface (RW)
Select which receive queue is used.
7
6
5
4
3
2
1
0
FQ3
FQ2
FQ1
FQ0
SQ3
SQ2
SQ1
SQ0
Bit [0]:
Select Queue 0. If set to one this queue may be scheduled to CPU port. If set to zero,
this queue will be blocked. If multiple queues are selected, a strict priority will be
applied. Q3> Q2> Q1> Q0. Same applies to bits [3:1]. See QoS Application Note for
more information.
Bit [1]:
Bit[2]:
Bit [3]:
Select Queue 1
Select Queue 2
Select Queue 3
Note: Strip priority applies between different selected queues (Q3>Q2>Q1>Q0)
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Enable flush Queue 0
Enable flush Queue 1
Enable flush Queue 2
Enable flush Queue 3
When flush (drop frames) is enable, it starts when queue is too long or entry is too old. A queue is too long when it
reaches WRED thresholds. Queue 0 is not subject to early drop. Packets in queue 0 are dropped only when the
queue is too old. An entry is too old when it is older than the time programmed in the register TX_AGE [5:0]. CPU
can dynamically program this register reading register RQSS [7:4].
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14.8.22 RQSS – Receive Queue Status
CPU Address:h324
Accessed by CPU, serial interface (RO)
7
5
4
3
0
LQ3
LQ2
LQ1 LQ0
NeQ3
NeQ2
NeQ1
NeQ0
CPU receive queue status
Bit [3:0]: Queue 3 to 0 not empty
Bit [4]: Head of line entry for Queue 0 is valid for too long. CPU Queue 0 has no WRED threshold.
Bit [7:5]: Head of line entry for Queue 3 to 1 is valid for too long or Queue length is longer than WRED
threshold.
14.8.23 TX_AGE – Tx Queue Aging timer
2
I C Address: h07;CPU Address:h324
Accessed by CPU, serial interface (RW)
7
6
5
0
Tx Queue Agent
Bit [5:0]: Unit of 100ms (Default 8)
Disable transmission queue aging if value is zero. Aging timer for all ports and queues.
This register must be set to 0 for ‘No Packet Loss Flow Control Test’.
14.9 Group 4 Address Search Engine Group
14.9.1 AGETIME_LOW – MAC address aging time Low
2
I C Address h0A8; CPU Address:h400
2
Accessed by CPU, serial interface and I C (R/W)
The MVTX2600 removes the MAC address from the data base and sends a Delete MAC Address Control
Command to the CPU. MAC address aging is enable/disable by boot strap TSTOUT9.
Bit [7:0] Low byte of the MAC address aging timer.
14.9.2 AGETIME_HIGH –MAC address aging time High
2
I C Address h0A9; CPU Address h401
2
Accessed by CPU, serial interface and I C (R/W)
Bit [7:0]: High byte of the MAC address aging timer.
The default setting provide 300 seconds aging time. Aging time is based on the following equation:
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{AGETIME_TIME,AGETIME_LOW} X (# of MAC entries in the memory X100µsec). Number of MAC entries = 32 K
when 1 MB is used per Bank. Number of entries = 64 K when 2 MB is used per Bank.
14.9.3 V_AGETIME – VLAN to Port aging time
CPU Address h402
Accessed by CPU (R/W)
Bit [7:0] (Default FF) V_AGETIME X 256 X 100 msec is the age time for the VLAN. This timer is for controlling how
long a port is associated to a particular VLAN. It can use dynamic shrinking of a VLAN domain if no packet arrives
for the VLAN. The 2600 does not remove the port from the VLAN domain. It sends an Age VLAN Port Control
Command to the CPU. The CPU has to remove the port.
14.9.4 SE_OPMODE – Search Engine Operation Mode
CPU Address:h403
Accessed by CPU (R/W)
Note: ECR2[2] enable/disable learning for each port.
7
6
5
4
3
2
1
0
SL
DMS
ARP DRA DA
DRD
DRN
FL
Bit [0]:
1 – Enable fast learning mode. In this mode, the hardware learns all
the new MAC addresses at highest rate, and reports to the CPU while
the hardware scans the MAC database. When the CPU report queue is
full, the MAC address is learned and marked as “Not reported”. When
the hardware scans the database and finds a MAC address marked as
“Not Reported” it tries to report it to the CPU. The scan rate must be
set. SCAN Control register sets the scan rate. (Default 0)
0 – Search Engine learns a new MAC address and sends a message
to the CPU report queue. If queue is full, the learning is temporarily
halted.
Bit [1]:
Bit [2]:
1 – Disable report new VLAN port association(Default 0)
0 – Report new VLAN port association
Report control
• 1 – Disable report MAC address deletion (Default 0)
• 0 – Report MAC address deletion (MAC address is deleted from MCT after
aging time)
Bit [3]:
Delete Control
• 1 – Disable aging logic from removing MAC during aging (Default 0)
• 0 – MAC address entry is removed when it is old enough to be aged.
However, a report is still sent to the CPU in both cases, when bit[2] = 0
Bit [4]:
Bit [5]:
1 – Disable report aging VLAN port association (Default 0)
0 – Enable Report aging VLAN. VLAN is not removed by hardware.
The CPU needs to remove the VLAN –port association.
1 - Report ARP packet to CPU (Default 0)
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Bit [6]:
Bit [7]:
Disable MCT speedup aging (Default 0)
• 1 – Disable speedup aging when MCT resource is low.
• 0 – Enable speedup aging when MCT resource is low.
Slow Learning (Default 0)
• 1– Enable slow learning. Learning is temporary disabled when search
demand is high
• 0 – Learning is performed independent of search demand
14.9.5 SCAN – SCAN Control Register (default 00)
CPU Address h404
Accessed by CPU (R/W)
7
6
0
R
Ratio
SCAN is used when fast learning is enabled (SE_OPMODE bit 0). It is used for setting up the report rate for newly
learned MAC addresses to the CPU.
Bit [6:0]:
Bit [7]:
•
•
Ratio between database scanning and aging round (Default 00)
Reverse the ratio between scanning round and aging round (Default 0)
Examples:
R= 0, Ratio = 0: All rounds are used for aging. Never scan for new MAC addresses.
R= 0, Ratio = 1: Aging and scanning in every other aging round
R= 1, Ratio = 7: In eight rounds, one is used for scanning and seven are used for aging
R= 0, Ratio = 7: In eight rounds, one is used for aging and seven are used for scanning
14.10 Group 5 Address Buffer Control/QOS Group
14.10.1 FCBAT – FCB Aging Timer
2
I C Address h0AA; CPU Address:h500
7
0
FCBAT
Bit [7:0]:
•
•
FCB Aging time. Unit of 1ms. (Default FF)
This is for buffer aging control. It is used to configure the buffer aging
time. This function can be enabled/disabled through bootstrap pin. It
is not suggested to use this function for normal operation.
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14.10.2 QOSC – QOS Control
2
I C Address h0AB; CPU Address:h501
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
4
3
1
0
L
Tos-d Tos-p
PMCQ
VF1c
Bit [0]:
•
•
QoS frame lost is OK. Priority will be available for flow control enabled
source only when this bit is set (Default 0)
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Per VLAN Multicast Flow Control (Default 0)
• 0 – Disable
• 1 – Enable
•
•
•
Select processor multicast queue size
• 0 = 16 entries
• 1 = 64 entries
Select TOS bits for Priority (Default 0)
• 0 – Use TOS [4:2] bits to map the transmit priority
• 1 – Use TOS [7:5] bits to map the transmit priority
Select TOS bits for Drop priority(Default 0)
• 0 – Use TOS [4:2] bits to map the drop priority
• 1 – Use TOS [7:5] bits to map the drop priority
14.10.3 FCR – Flooding Control Register
2
I C Address h0AC; CPU Address:h502
2
Accessed by CPU, serial interface and I C (R/W)
7
6
4
3
0
Tos
TimeBase
U2MR
Bit [3:0]:
•
U2MR: Unicast to Multicast Rate. Units in terms of time base defined in
bits [6:4]. This is used to limit the amount of flooding traffic. The value
in U2MR specifies how many packets are allowed to flood within the
time specified by bit [6:4]. To disable this function, program U2MR to
0. (Default = 8)
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Bit [6:4]:
Time Base: (Default = 000)
000 = 100 us
001 = 200 us
010 = 400 us
011 = 800 us
100 = 1.6 ms
101 = 3.2 ms
110 = 6.4 ms
111 = 100 us, same as 000.
Bit [7]:
Select VLAN tag or TOS (IP packets) to be preferentially picked to map
transmit priority and drop priority (Default = 0).
0 – Select VLAN Tag priority field over TOS
1 – Select TOS over VLAN tag priority field
14.10.4 AVPML – VLAN Tag Priority Map
2
I C Address h0AD; CPU Address:h503
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
3
2
0
VP2
VP1
VP0
Registers AVPML, AVPMM and AVPMH allow the eight VLAN Tag priorities to map into eight Internal level transmit
priorities. Under the Internal transmit priority, seven is the highest priority where as zero is the lowest. This feature
allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0
of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used
inside the 2600. When the packet goes out it carries the original priority.
Bit [2:0]:
Bit [5:3]:
Bit [7:6]:
Priority when the VLAN tag priority field is 0 (Default 0)
Priority when the VLAN tag priority field is 1 (Default 0)
Priority when the VLAN tag priority field is 2 (Default 0)
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14.10.5 AVPMM – VLAN Priority Map
2
I C Address h0AE, CPU Address:h504
2
Accessed by CPU, serial interface and I C (R/W)
Map VLAN priority into eight level transmit priorities:
7
6
4
3
1
0
VP5
VP4
VP3
VP2
Bit [0]:
Priority when the VLAN tag priority field is 2 (Default 0)
Priority when the VLAN tag priority field is 3 (Default 0)
Priority when the VLAN tag priority field is 4 (Default 0)
Priority when the VLAN tag priority field is 5 (Default 0)
Bit [3:1]:
Bit [6:4]:
Bit [7]:
14.10.6 AVPMH – VLAN Priority Map
2
I C Address h0AF, CPU Address:h505
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
2
1
0
VP7
VP6
VP5
Map VLAN priority into eight level transmit priorities:
Bit [1:0]:
Bit [4:2]:
Bit [7:5]:
Priority when the VLAN tag priority field is 5 (Default 0)
Priority when the VLAN tag priority field is 6 (Default 0)
Priority when the VLAN tag priority field is 7 (Default 0)
14.10.7 TOSPML – TOS Priority Map
2
I C Address h0B0, CPU Address:h506
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
3
2
0
TP2
TP1
TP0
Map TOS field in IP packet into eight level transmit priorities
Bit [2:0]:
Bit [5:3]:
Bit [7:6]:
Priority when the TOS field is 0 (Default 0)
Priority when the TOS field is 1 (Default 0)
Priority when the TOS field is 2 (Default 0)
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14.10.8 TOSPMM – TOS Priority Map
2
I C Address h0B1, CPU Address:h507
2
Accessed by CPU, serial interface and I C (R/W)
7
6
4
3
0
1
TP5
TP4
TP3
TP2
Map TOS field in IP packet into eight level transmit priorities
Bit [0]:
Priority when the TOS field is 2 (Default 0)
Bit [3:1]:
Bit [6:4]:
Bit [7]:
Priority when the TOS field is 3 (Default 0)
Priority when the TOS field is 4 (Default 0)
Priority when the TOS field is 5 (Default 0)
14.10.9 TOSPMH – TOS Priority Map
2
I C Address h0B2, CPU Address:h508
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
2
1
0
TP7
TP6
TP5
Map TOS field in IP packet into eight level transmit priorities:
Bit [1:0]:
Bit [4:2]:
Bit [7:5]:
Priority when the TOS field is 5 (Default 0)
Priority when the TOS field is 6 (Default 0)
Priority when the TOS field is 7 (Default 0)
14.10.10 AVDM – VLAN Discard Map
2
I C Address h0B3, CPU Address:h509
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
4
3
2
1
0
FDV7
FDV6 FDV5 FDV4 FDV3 FDV2 FDV1 FDV0
Map VLAN priority into frame discard when low priority buffer usage is above threshold
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Frame drop priority when VLAN Tag priority field is 0 (Default 0)
Frame drop priority when VLAN Tag priority field is 1 (Default 0)
Frame drop priority when VLAN Tag priority field is 2 (Default 0)
Frame drop priority when VLAN Tag priority field is 3 (Default 0)
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Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Frame drop priority when VLAN Tag priority field is 4 (Default 0)
Frame drop priority when VLAN Tag priority field is 5 (Default 0)
Frame drop priority when VLAN Tag priority field is 6 (Default 0)
Frame drop priority when VLAN Tag priority field is 7 (Default 0)
14.10.11 TOSDML – TOS Discard Map
2
I C Address h0B4, CPU Address:h50A
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
4
3
2
1
0
FDT7 FDT6 FDT5 FDT4 FDT3 FDT2
FDT1
FDT0
Map TOS into frame discard when low priority buffer usage is above threshold
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]:
Frame drop priority when TOS field is 0 (Default 0)
Frame drop priority when TOS field is 1 (Default 0)
Frame drop priority when TOS field is 2 (Default 0)
Frame drop priority when TOS field is 3 (Default 0)
Frame drop priority when TOS field is 4 (Default 0)
Frame drop priority when TOS field is 5 (Default 0)
Frame drop priority when TOS field is 6 (Default 0)
Frame drop priority when TOS field is 7 (Default 0)
14.10.12 BMRC - Broadcast/Multicast Rate Control
2
I C Address h0B5, CPU Address:h50B)
2
Accessed by CPU, serial interface and I C (R/W)
7
4
3
0
Broadcast Rate
Multicast Rate
This broadcast and multicast rate defines for each port, the number of packets allowed to be forwarded within a
specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field
to 0. Time base is based on register FCR [6:4]
Bit [3:0] :
Multicast Rate Control. Number of multicast packets allowed within the time
defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default 0).
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Bit [7:4] :
Broadcast Rate Control. Number of broadcast packets allowed within the
time defined in bits 6 to 4 of the Flooding Control Register (FCR). (Default
0)
14.10.13 UCC – Unicast Congestion Control
2
I C Address h0B6, CPU Address: 50C
2
Accessed by CPU, serial interface and I C (R/W)
7
0
Unicast congest threshold
Bit [7:0] :
Number of frame count. Used for best effort dropping at B% when destination
port’s best effort queue reaches UCC threshold and shared pool is all in use.
Granularity 1 frame. (Default: h10 for 2 MB/bank or h08 for 1 MB/bank)
14.10.14 MCC – Multicast Congestion Control
2
I C Address h0B7, CPU Address: 50D
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
0
FC reaction period
Multicast congest threshold
Bit [4:0]:
Bit [7:5]:
In multiples of two frames (granularity). Used for triggering MC flow control
when destination port’s multicast best effort queue reaches MCC
threshold.(Default 0x10)
Flow control reaction period (Default 2) Granularity 4uSec.
14.10.15 PR100 – Port Reservation for 10/100 ports
2
I C Address h0B8, CPU Address 50E
2
Accessed by CPU, serial interface and I C (R/W)
7
4
3
0
Buffer low threshold
SP Buffer reservation
Bit [3:0]:
Per source port buffer reservation.
Define the space in the FDB reserved for each 10/100 port and CPU.
Expressed in multiples of 4 packets. For each packet 1536 bytes are
reserved in the memory.
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Bits [7:4]:
Expressed in multiples of 4 packets. Threshold for dropping all best effort
frames when destination port best efforts queues reaches UCC threshold,
shared pool is all used and source port reservation is at or below the
PR100[7:4] level. Also the threshold for initiating UC flow control.
•
Default:
- h36 for 24+2 configuration with memory 2 MB/bank;
- h24 for 24+2 configuration with 1MB/bank;
14.10.16 PRG – Port Reservation for Giga ports
2
I C Address h0B9, CPU Address 50F
2
Accessed by CPU, serial interface and I C (R/W)
7
4
3
0
Buffer low threshold
SP buffer reservation
Bit [3:0]:
Per source port buffer reservation.
Define the space in the FDB reserved for each Gigabit port. Expressed in
multiples of 16 packets. For each packet 1536 bytes are reserved in the
memory.
Bits [7:4]:
Expressed in multiples of 16 packets. Threshold for dropping all best effort
frames when destination port best effort queues reach UCC threshold,
shared pool is all used and source port reservation is at or below the
PRG[7:4] level. Also the threshold for initiating UC flow control.
•
Default:
- h58 for memory 2 MB/bank;
- h35 for 1 MB/bank;
14.10.17 SFCB – Share FCB Size
2
I C Address h0BA), CPU Address 510
2
Accessed by CPU, serial interface and I C (R/W)
7
0
Shared pool buffer size
Bits [7:0]:
Expressed in multiples of 4 packets. Buffer reservation for shared pool.
•
Default:
- h64 for 24+2 configuration with memory of 2 MB/bank;
- h14 for 24+2 configuration with memory of 1 MB/bank;
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14.10.18 C2RS – Class 2 Reserve Size
2
I C Address h0BB, CPU Address 511
Accessed by CPU, serial interface and I C (R/W)
2
7
0
Class 2 FCB Reservation
Buffer reservation for class 2 (third lowest priority). Granularity 1. (Default 0)
14.10.19 C3RS – Class 3 Reserve Size
2
I C Address h0BC, CPU Address 512
2
Accessed by CPU, serial interface and I C (R/W)
7
0
0
Class 3 FCB Reservation
Buffer reservation for class 3. Granularity 1. (Default 0)
14.10.20 C4RS – Class 4 Reserve Size
2
I C Address h0BD, CPU Address 513
2
Accessed by CPU, serial interface and I C (R/W)
7
Class 4 FCB Reservation
Buffer reservation for class 4. Granularity 1. (Default 0)
14.10.21 C5RS – Class 5 Reserve Size
2
I C Address h0BE; CPU Address 514
2
Accessed by CPU, serial interface and I C (R/W)
7
0
Class 5 FCB Reservation
Buffer reservation for class 5. Granularity 1. (Default 0)
14.10.22 C6RS – Class 6 Reserve Size
2
I C Address h0BF; CPU Address 515
2
Accessed by CPU, serial interface and I C (R/W)
7
0
Class 6 FCB Reservation
Buffer reservation for class 6 (second highest priority). Granularity 1. (Default 0)
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14.10.23 C7RS – Class 7 Reserve Size
2
I C Address h0C0; CPU Address 516
2
Accessed by CPU, serial interface and I C (R/W)
7
0
Class 7 FCB Reservation
Buffer reservation for class 7 (highest priority). Granularity 1. (Default 0)
14.10.24 QOSCn - Classes Byte Limit Set 0
2
Accessed by CPU; serial interface and I C (R/W):
2
C — QOSC00 – BYTE_C01 (I C Address h0C1, CPU Address 517)
2
B — QOSC01 – BYTE_C02 (I C Address h0C2, CPU Address 518)
2
A — QOSC02 – BYTE_C03 (I C Address h0C3, CPU Address 519)
QOSC00 through QOSC02 represents one set of values A-C for a 10/100 port when using the Weighted Random
Early Drop (WRED) Scheme described in Chapter 7. There are four such sets of values A-C specified in Classes
Byte Limit Set 0, 1, 2, and 3. For CPU port A-C values are defined using register CPUQOSC1, 2 and 3.
Each 10/ 100 port can choose one of the four Byte Limit Sets as specified by the QoS Select field located in bits 5
to 4 of the ECR2n register. The values A-C are per-queue byte thresholds for random early drop. QOSC02
represents A, and QOSC00 represents C.
Granularity when Delay bound is used: QOSC02: 128 bytes, QOSC01: 256 bytes, QOSC00: 512 bytes. Granularity
when WFQ is used: QOSC02: 512 bytes, QOSC01: 512 bytes, QOSC00: 512 bytes.
14.10.25 Classes Byte Limit Set 1
2
Accessed by CPU, serial interface and I C (R/W):
2
C - QOSC03 – BYTE_C11 (I C Address h0C4, CPU Address 51a)
2
B - QOSC04 – BYTE_C12 (I C Address h0C5, CPU Address 51b)
2
A - QOSC05 – BYTE_C13 (I C Address h0C6, CPU Address 51c)
QOSC03 through QOSC05 represents one set of values A-C for a 10/100 port when using the Weighted Random
Early Drop (WRED) scheme.
Granularity when Delay bound is used: QOSC05: 128 bytes, QOSC04: 256 bytes, QOSC03: 512 bytes. Granularity
when WFQ is used: QOSC05: 512 bytes, QOSC04: 512 bytes, QOSC03: 512 bytes.
14.10.26 Classes Byte Limit Set 2
Accessed by CPU and serial interface (R/W):
C - QOSC06 – BYTE_C21 (CPU Address 51d)
B - QOSC07 – BYTE_C22 (CPU Address 51e)
A - QOSC08 – BYTE_C23 (CPU Address 51f)
QOSC06 through QOSC08 represents one set of values A-C for a 10/100 port when using the Weighted Random
Early Drop (WRED) scheme.
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Granularity when Delay bound is used: QOSC08: 128 bytes, QOSC07: 256 bytes, QOSC06: 512 bytes.
Granularity when WFQ is used: QOSC08: 512 bytes, QOSC07: 512 bytes, QOSC06: 512 bytes
14.10.27 Classes Byte Limit Set 3
Accessed by CPU and serial interface (R/W):
C - QOSC09 – BYTE_C31 (CPU Address 520)
B - QOSC10 – BYTE_C32 (CPU Address 521)
A - QOSC11 – BYTE_C33 (CPU Address 522)
QOSC09 through QOSC011 represents one set of values A-C for a 10/100 port when using the Weighted Random
Early Drop (WRED) scheme.
Granularity when Delay bound is used: QOSC11: 128 bytes, QOSC10: 256 bytes, QOSC09: 512 bytes.
Granularity when WFQ is used: QOSC11: 512 bytes, QOSC10: 512 bytes, QOSC09: 512 bytes
14.10.28 Classes Byte Limit Giga Port 1
2
Accessed by CPU, serial interface and I C (R/W):
2
F - QOSC12 – BYTE_C2_G1 (I C Address h0C7, CPU Address 523)
2
E - QOSC13 – BYTE_C3_G1 (I C Address h0C8, CPU Address 524)
2
D - QOSC14 – BYTE_C4_G1 (I C Address h0C9, CPU Address 525)
2
C -QOSC15 – BYTE_C5_G1 (I C Address h0CA, CPU Address 526)
2
B - QOSC16 – BYTE_C6_G1 (I C Address h0CB, CPU Address 527)
2
A - QOSC17 – BYTE_C7_G1 (I C Address h0CC, CPU Address 528)
QOSC12 through QOSC17 represent the values A-F for Gigabit port 1. They are per-queue byte thresholds for
random early drop. QOSC17 represents A, and QOSC12 represents F.
Granularity when Delay bound is used: QOSC17 and QOSC16: 256 bytes, QOSC15 and QOSC14: 512 bytes,
QOSC13 and QOSC12: 1024 bytes.
Granularity when WFQ is used: QOSC17 to QOSC12: 1024 bytes
14.10.29 Classes Byte Limit Giga Port 2
2
Accessed by CPU, serial interface and I C (R/W)
2
F - QOSC18 – BYTE_C2_G2 (I C Address h0CD, CPU Address 529)
2
E - QOSC19 – BYTE_C3_G2 (I C Address h0CE, CPU Address 52a)
2
D - QOSC20 – BYTE_C4_G2 (I C Address h0CF, CPU Address 52b)
2
C - QOSC21 – BYTE_C5_G2 (I C Address h0D0, CPU Address 52c)
2
B - QOSC22 – BYTE_C6_G2 (I C Address h0D1, CPU Address 52d)
2
A - QOSC23 – BYTE_C7_G2 (I C Address h0D2, CPU Address 52e)
QOSC12 through QOSC17 represent the values A-F for Gigabit port 2. They are per-queue byte thresholds for
random early drop. QOSC17 represents A, and QOSC12 represents F.
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Granularity when Delay bound is used: QOSC17 and QOSC16: 256 bytes, QOSC15 and QOSC14: 512 bytes,
QOSC13 and QOSC12: 1024 bytes.
Granularity when WFQ is used: QOSC17 to QOSC12: 1024 bytes
14.10.30 Classes WFQ Credit Set 0
Accessed by CPU and serial interface
W0 - QOSC24[5:0] – CREDIT_C00 (CPU Address 52f)
W1 - QOSC25[5:0] – CREDIT_C01 (CPU Address 530)
W2 - QOSC26[5:0] – CREDIT_C02 (CPU Address 531)
W3 - QOSC27[5:0] – CREDIT_C03 (CPU Address 532)
QOSC24 through QOSC27 represents one set of WFQ parameters for a 10/100 port. There are four such sets of
values. The granularity of the numbers is 1, and their sum must be 64. QOSC27 corresponds to W3 and QOSC24
corresponds to W0.
QOSC24[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4.
QOSC25[7]: Priority service allow flow control for the ports select this parameter set.
QOSC25[6]: Flow control pause best effort traffic only
Both flow control allow and flow control best effort only can take effect only the priority type is WFQ.
14.10.31 Classes WFQ Credit Set 1
Accessed by CPU and serial interface
W0 - QOSC28[5:0] – CREDIT_C10 (CPU Address 533)
W1 - QOSC29[5:0] – CREDIT_C11 (CPU Address 534)
W2 - QOSC30[5:0] – CREDIT_C12 (CPU Address 535)
W3 - QOSC31[5:0] – CREDIT_C13 (CPU Address 536)
QOSC28 through QOSC31 represents one set of WFQ parameters for a 10/100 port. There are four such sets of
values. The granularity of the numbers is 1, and their sum must be 64. QOSC31 corresponds to W3 and QOSC28
corresponds to W0.
QOSC28[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4.
QOSC29[7]: Priority service allow flow control for the ports select this parameter set.
QOSC29[6]: Flow control pause best effort traffic only
14.10.32 Classes WFQ Credit Set 2
Accessed by CPU and serial interface
W0 - QOSC32[5:0] – CREDIT_C20 (CPU Address 537)
W1 - QOSC33[5:0] – CREDIT_C21 (CPU Address 538)
W2 - QOSC34[5:0] – CREDIT_C22 (CPU Address 539)
W3 - QOSC35[5:0] – CREDIT_C23 (CPU Address 53a)
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QOSC35 through QOSC32 represents one set of WFQ parameters for a 10/100 port. There are four such sets of
values. The granularity of the numbers is 1 and their sum must be 64. QOSC35 corresponds to W3 and QOSC32
corresponds to W0.
QOSC32[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4.
QOSC33[7]: Priority service allow flow control for the ports select this parameter set.
QOSC33[6]: Flow control pause for best effort traffic only
14.10.33 Classes WFQ Credit Set 3
Accessed by CPU and serial interface
W0 - QOSC36[5:0] – CREDIT_C30 (CPU Address 53b)
W1 - QOSC37[5:0] – CREDIT_C31 (CPU Address 53c)
W2 - QOSC38[5:0] – CREDIT_C32 (CPU Address 53d)
W3 - QOSC39[5:0] – CREDIT_C33 (CPU Address 53e)
QOSC39 through QOSC36 represents one set of WFQ parameters for a 10/100 port. There are four such sets of
values. The granularity of the numbers is 1 and their sum must be 64. QOSC39 corresponds to W0 and QOSC36
corresponds to W0.
QOSC36[7:6]: Priority service type for the ports select this parameter set. Option 1 to option 4.
QOSC37[7]: Priority service allow flow control for the ports select this parameter set.
QOSC37[6]: Flow control pause best effort traffic only
14.10.34 Classes WFQ Credit Port G1
Accessed by CPU and serial interface
W0 - QOSC40[5:0] - CREDIT_C0_G1(CPU Address 53f)
[7:6]: Priority service type. Option 1 to 4.
W1 - QOSC41[5:0] – CREDIT_C1_G1 (CPU Address 540)
[7]: Priority service allow flow control for the ports select this parameter set.
[6]: Flow control pause best effort traffic only
W2 - QOSC42[5:0] – CREDIT_C2_G1 (CPU Address 541)
W3 - QOSC43[5:0] – CREDIT_C3_G1 (CPU Address 542)
W4 - QOSC44[5:0] – CREDIT_C4_G1 (CPU Address 543)
W5 - QOSC45[5:0] – CREDIT_C5_G1 (CPU Address 544)
W6 - QOSC46[5:0] – CREDIT_C6_G1 (CPU Address 545)
W7 - QOSC47[5:0] – CREDIT_C7_G1 (CPU Address 546)
QOSC40 through QOSC47 represents the set of WFQ parameters for Gigabit port 24. The granularity of the
numbers is 1 and their sum must be 64. QOSC47 corresponds to W7 and QOSC40 corresponds to W0. In the 2G
trunk configuration, the sum of all values QOSC40 through QOSC47 must be equal to 128.
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14.10.35 Classes WFQ Credit Port G2
Accessed by CPU and serial interface
W0 - QOSC48[5:0] – CREDIT_C0_G2(CPU Address 547)
[7:6]: Priority service type. Option 1 to 4
W1 - QOSC49[5:0] – CREDIT_C1_G2(CPU Address 548)
[7]: Priority service allow flow control for the ports select this parameter set.
[6]: Flow control pause best effort traffic only
W2 - QOSC50[5:0] – CREDIT_C2_G2(CPU Address 549)
W3 - QOSC51[5:0] – CREDIT_C3_G2(CPU Address 54a)
W4 - QOSC52[5:0] – CREDIT_C4_G2(CPU Address 54b)
W5 - QOSC53[5:0] – CREDIT_C5_G2(CPU Address 54c)
W6 - QOSC54[5:0] – CREDIT_C6_G2(CPU Address 54d)
W7 - QOSC55[5:0] – CREDIT_C7_G2(CPU Address 54e)
QOSC48 through QOSC55 represents the set of WFQ parameters for Gigabit port 2. The granularity of the
numbers is 1 and their sum must be 64. QOSC55 corresponds to W7 and QOSC48 corresponds to W0. In the 2G
trunk configuration, the sum of all values QOSC48 through QOSC55 must be equal to 128.
14.10.36 Class 6 Shaper Control Port G1
Accessed by CPU and serial interface
QOSC56[5:0] – TOKEN_RATE_G1 (CPU Address 54f). Programs de average rate for gigabit port 1. When equal to
0, shaper is disable. Granularity is 1.
QOSC57[7:0] – TOKEN_LIMIT_G1 (CPU Address 550). Programs the maximum counter for gigabit port 1.
Granularity is 16 bytes.
Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is
limited to gigabit ports and queue P6 when it is in strict priority. QOSC41 programs the peak rate for gigabit port 1.
See Programming QoS Registers Application Note for more information.
14.10.37 Class 6 Shaper Control Port G2
Accessed by CPU and serial interface
QOSC58[5:0] – TOKEN_RATE_G2 (CPU Address 551). Programs de average rate for gigabit port 2. When equal
to 0, shaper is disable. Granularity is 1.
QOSC59[7:0] – TOKEN_LIMIT_G2 (CPU Address 552). Programs the maximum counter for gigabit port 2.
Granularity is 16 bytes.
Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is
limited to gigabit ports and queue P6 when it is in strict priority. QOSC49 programs the peak rate for gigabit port 2.
See Programming QoS Register application note for more information.
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14.10.38 RDRC0 – WRED Rate Control 0
2
I C Address 0FB, CPU Address 553
c
Accessed by CPU, Serial Interface and I C (R/W)
7
4
3
0
X Rate
Y Rate
Bits [7:4]:
Bits [3:0]:
Corresponds to the frame drop percentage X% for WRED. Granularity
6.25%.
Corresponds to the frame drop percentage Y% for WRED. Granularity
6.25%.
See Programming QoS Registers application note for more information
14.10.39 RDRC1 – WRED Rate Control 1
2
I C Address 0FC, CPU Address 554
2
Accessed by CPU, Serial Interface and I C (R/W)
7
4
3
0
Z Rate
B Rate
Bits [7:4]:
Bits [3:0]:
Corresponds to the frame drop percentage Z% for WRED. Granularity
6.25%.
Corresponds to the best effort frame drop percentage B%, when shared pool
is all in use and destination port best effort queue reaches UCC. Granularity
6.25%.
See Programming QoS Registers application note for more information
14.10.40 User Defined Logical Ports and Well Known Ports
The MVTX2600AG supports classifying packet priority through layer 4 logical port information. It can be setup by 8
Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported
are:
•
•
•
•
•
•
•
•
0:23
1:512
2:6000
3:443
4:111
5:22555
6:22
7:554
Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_
Enable can individually turn on/off each Well Known Port if desired.
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Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select
specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7
registers. Two registers are required to be programmed for the logical port number. The respective priority can be
programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via
User_Port_Enable register.
The User Defined Range provides a range of logical port numbers with the same priority level. Programming is
similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need
to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper
limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than
the upper limit and more than the lower limit will use the priority specified in RPRIORITY.
14.10.40.1
USER_PORT0_(0~7) – USER DEFINE LOGICAL PORT (0~7)
2
USER_PORT_0 - I C Address h0D6 + 0DE; CPU Address 580(Low) + 581(high)
2
USER_PORT_1 - I C Address h0D7 + 0DF; CPU Address 582 + 583
2
USER_PORT_2 - I C Address h0D8 + 0E0; CPU Address 584 + 585
2
USER_PORT_3 - I C Address h0D9 + 0E1; CPU Address 586 + 587
2
USER_PORT_4 - I C Address h0DA + 0E2; CPU Address 588 + 589
2
USER_PORT_5 - I C Address h0DB + 0E3; CPU Address 58A + 58B
2
USER_PORT_6 - I C Address h0DC + 0E4; CPU Address 58C + 58D
2
USER_PORT_7 - I C Address h0DD + 0E5; CPU Address 58E + 58F
2
Accessed by CPU, serial interface and I C (R/W)
7
0
0
TCP/UDP Logic Port Low
7
TCP/UDP Logic Port High
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define
eight separate ports.
14.10.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
2
I C Address h0E6, CPU Address 590
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
1
0
Priority 1
Drop Priority 0
Drop
The chip allows the CPU to define the priority
Bits [3:0]:
Bits [7:4]:
Priority setting, transmission + dropping, for logic port 0
Priority setting, transmission + dropping, for logic port 1 (Default 00)
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14.10.40.3 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
2
I C Address h0E7, CPU Address 591
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
1
0
Priority 3
Drop
Priority 2
Drop
14.10.40.4 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
2
I C Address h0E8, CPU Address 592
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
1
0
Priority 5
Drop
Priority 4
Drop
(Default 00)
14.10.40.5
USER_PORT_[7:6]_PRIORITY - USER DEFINE LOGIC PORT 7 AND 6 PRIORITY
2
I C Address h0E9, CPU Address 593
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
1
0
Priority 7
Drop
Priority 6
Drop
(Default 00)
14.10.40.6 USER_PORT_ENABLE[7:0] – User Define Logic 7 to 0 Port Enables
2
I C Address h0EA, CPU Address 594
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
(Default 00)
14.10.40.7 WELL_KNOWN_PORT[1:0] PRIORITY- Well Known Logic Port 1 and 0 Priority
2
I C Address h0EB, CPU Address 595
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
1
0
Priority 1
Drop Priority 0
Drop
Priority 0 - Well known port 23 for telnet applications.
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Priority 1 - Well Known port 512 for TCP/UDP.
(Default 00)
14.10.40.8 WELL_KNOWN_PORT[3:2] PRIORITY- Well Known Logic Port 3 and 2 Priority
2
I C Address h0EC, CPU Address 596
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
1
0
Priority 3
Drop
Priority 2
Drop
Priority 2 - Well known port 6000 for XWIN.
Priority 3 - Well known port 443 for http.sec
(Default 00)
14.10.40.9 WELL_KNOWN_PORT [5:4] PRIORITY- Well Known Logic Port 5 and 4 Priority
2
I C Address h0ED, CPU Address 597
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
1
0
Priority 5
Drop
Priority 4
Drop
Priority 4 - Well Known port 111 for sun remote procedure call.
Priority 5 - Well Known port 22555 for IP Phone call setup.
(Default 00)
14.10.40.10 WELL_KNOWN_PORT [7:6] PRIORITY- WELL KNOWN LOGIC PORT 7 AND 6 PRIORITY
2
I C Address h0EE, CPU Address 598
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
1
0
Priority 7
Drop
Priority 6
Drop
Priority 6 - well know port 22 for ssh.
Priority 7 – well Known port 554 for rtsp.
(Default 00)
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14.10.40.11 WELL KNOWN_PORT_ENABLE [7:0] – Well Known Logic 7 to 0 Port Enables
2
I C Address h0EF, CPU Address 599
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
1 – Enable
0 - Disable
(Default 00)
14.10.40.12
RLOWL – USER DEFINE RANGE LOW BIT 7:0
2
I C Address h0F4, CPU Address: 59a
2
Accessed by CPU, serial interface and I C (R/W)
(Default 00)
14.10.40.13 RLOWH – User Define Range Low Bit 15:8
2
I C Address h0F5, CPU Address: 59b
2
Accessed by CPU, serial interface and I C (R/W)
(Default 00)
14.10.40.14 RHIGHL – User Define Range High Bit 7:0
2
I C Address h0D3, CPU Address: 59c
2
Accessed by CPU, serial interface and I C (R/W)
(Default 00)
14.10.40.15 RHIGHH – User Define Range High Bit 15:8
2
I C Address h0D4, CPU Address: 59d
2
Accessed by CPU, serial interface and I C (R/W)
(Default 00)
14.10.40.16 RPRIORITY – User Define Range Priority
2
I C Address h0D5, CPU Address: 59e
2
Accessed by CPU, serial interface and I C (R/W)
7
4
3
0
Range Transmit Priority
Drop
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RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY.
Bit[3:1]
Bits[0]:
Transmit Priority
Drop Priority
14.10.41 CPUQOSC123
CPU Address: 5a0, 5a1, 5a2
Accessed by CPU and serial interface (R/W)
2
C - CPUQOSC1 – CPU BYTE_C1 I C Address h0C1, CPU Address 517)
2
B - CPUQOSC2 – CPU BYTE_C2 I C Address h0C2, CPU Address 518)
2
A - CPUQOSC3 – CPU BYTE_C3 I C Address h0C3, CPU Address 519)
Represents values A-C for a CPU port. The values A-C are per-queue byte thresholds for random early drop.
QOSC3 represents A, and QOSC1 represents C. Granularity: 256 bytes
14.11 Group 6 Address MISC Group
14.11.1 MII_OP0 – MII Register Option 0
2
I C Address F0, CPU Address:h600
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
4
0
hfc 1prst DisJ Vendor Spc. Reg Addr
Bits [7]: Half duplex flow control feature
0 = Half duplex flow control always enable
1 = Half duplex flow control by negotiation
Link partner reset auto-negotiate disable
Bits [6]:
Bits [5]:
Disable jabber detection. This is for HomePNA applications or any serial
operation slower than 10 Mbps.
0 = Enable
1 = Disable
Bit [4:0]:
Vendor specified link status register address (null value means don’t use it)
(Default 00). This is used if the Linkup bit position in the PHY is non-
standard.
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14.11.2 MII_OP1 – MII Register Option 1
2
I C Address F1, CPU Address:h601
2
Accessed by CPU, serial interface and I C (R/W)
7
4
3
0
Speed bit location
Duplex bit location
Bits [3:0]:
Bits [7:4]:
Duplex bit location in vendor specified register
Speed bit location in vendor specified register
(Default 00)
14.11.3 FEN – Feature Register
2
I C Address F2, CPU Address:h602)
2
Accessed by CPU, serial interface and I C (R/W)
7
6
5
4
3
2
1
0
DML Mii Rp
IP Mul
V-Sp DS RC
SC
Bits [0]:
Bits [1]:
Statistic Counter Enable (Default 0)
•
•
0 – Disable
1 – Enable (all ports)
When statistic counter is enable, an interrupt control frame is generated to
the CPU, every time a counter wraps around. This feature requires an
external CPU.
Rate Control Enable (Default 0)
•
•
0 – Disable
1 – Enable; Must also set ECR2Pn[3] = 1
This bit enables/disables the rate control for all 10/100 ports. To start rate
control in a 10/100 port the rate control memory must be programmed. This
feature requires an external CPU. See Programming QoS Registers
Application Note and Processor Interface Application Note for more
information.
Bit [2]:
Support DS EF Code. (Default 0)
•
•
0 – Disable
1 – Enable (all ports)
When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for
110 and drop is set for 0.
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Data Sheet
Bit [3]:
Bit [4]:
Bit [5]:
Enable VLAN spanning tree support (Default 0)
•
•
0 – Disable
1 – Enable
When VLAN spanning tree is enable the registers ECR1Pn are NOT used to
program the port spanning tree status. The port status is programmed using
the Control Command Frame.
Disable IP Multicast Support (Default 1)
•
•
0 – Enable IP Multicast Support
1 – Disable IP Multicast Support
When enable, IGMP packets are identified by search engine and are passed
to the CPU for processing. IP multicast packets are forwarded to the IP
multicast group members according to the VLAN port mapping table.
Enable report to CPU(Default 0)
•
•
0 – Disable report to CPU
1 – Enable report to CPU
When disable new VLAN port association report, new MAC address report or
aging reports are disable for all ports. When enable, register SE_OPEMODE
is used to enable/disable selectively each function.
Bit [6]:
Bit [7]:
Disable MII Management State Machine (Default 0)
•
•
0: Enable MII Management State Machine
1: Disable MII Management State Machine
Disable using MCT Link List structure (Default 0)
0 – Enable using MCT Link structure
1 - Disable using MCT Link List structure
14.11.4 MIIC0 – MII Command Register 0
CPU Address:h603
Accessed by CPU and serial interface only (R/W)
Bit [7:0] - MII Data [7:0]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then
program MII command.
14.11.5 MIIC1 – MII Command Register 1
CPU Address:h604
Accessed by CPU and serial interface only (R/W)
Bit [7:0] - MII Data [15:8]
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
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Data Sheet
14.11.6 MIIC2 – MII Command Register 2
CPU Address:h605
Accessed by CPU and serial interface only (R/W)
7
6
5
4
0
Mii OP
Register address
Bit [4:0] -
Bit [6:5] -
REG_AD – Register PHY Address
OP – Operation code “10” for read command and “01” for write command
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command.
14.11.7 MIIC3 – MII Command Register 3
CPU Address:h606
Accessed by CPU and serial interface only (R/W)
7
6
5
4
0
Rdy
Valid
PHY address
Bits [4:0] -
Bit [6] -
PHY_AD – 5 Bit PHY Address
VALID – Data Valid from PHY (Read Only)
Bit [7] -
RDY – Data is returned from PHY (Ready Only)
Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then
program MII command. Writing this register will initiate a serial management cycle to the MII management
interface.
14.11.8 MIID0 – MII Data Register 0
CPU Address:h607
Accessed by CPU and serial interface only (RO)
Bit [7:0] - MII Data [7:0]
14.11.9 MIID1 – MII Data Register 1
CPU Address:h608
Accessed by CPU and serial interface only (RO)
Bit [7:0] - MII Data [15:8]
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Data Sheet
14.11.10 LED Mode – LED Control
CPU Address:h609
2
Accessed by CPU, serial interface and I C (R/W)
7
5
4
3
2
1
0
Clock rate
Hold Time
Bit [0]
Bit [2:1]:
Reserved(Default 0)
Hold time for LED signal (Default 00)
00=8 msec
01=16 msec
11=64 msec
10=32 msec
Bit [4:3]:
LED clock frequency (Default 0)
For 100MHz SCLK
00 = 100 M/8 = 12.5 MHz
01 = 100 M/16 = 6.25 MHz
10 = 100 M/32 = 3.125 MHz 11 = 100 M/64 = 1.5625 MHz
For 125 MHz SCLK
00 = 125 M/64 = 1953 KHz
10 = 125 M/512 = 244 KHz
01 = 125 M/128 = 977 KHz
11 = 125 M/1024 = 122 KHz
Bit [7:5]:
Reserved. Must be set to ‘0’ (Default 0)
14.11.11 DEVICE Mode
CPU Address:h60a
Accessed by CPU and serial interface (R/W)
7
4
3
0
Device ID
Bit [1:0]:
Reserved. Must be set to ‘0’ (Default 0)
Support < = 1536 frames
Bit [2]:
0: < = 1518 bytes (< = 1522 bytes with VLAN tag) (Default)
1: < = 1536 bytes
Bit [3:0]:
Bit [7:4]:
Reserved. Must be set to ‘0’ (Default 0)
DEVICE ID (Default 0). This is for stacking operation. This is the stack ID
for loop topology.
14.11.12 CHECKSUM - EEPROM Checksum
2
I C Address FF, CPU Address:h60b
2
Accessed by CPU, serial interface and I C (R/W)
Bit [7:0]: (Default 0)
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Data Sheet
This register is used in unmanaged mode only. Before requesting that the MVTX2604 updates the EEPROM
device, the correct checksum needs to be calculated and written into this checksum register. The checksum
formula is:
FF
2
Σ
i C register = 0
i = 0
When the MVTX2604 boots from the EEPROM the checksum is calculated and the value must be zero. If the
checksum is not zeroed the MVTX2604 does not start and pin CHECKSUM_OK is set to zero.
14.12 Group 7 Address Port Mirroring Group
14.12.1 MIRROR1_SRC - Port Mirror source port
CPU Address 700
Accessed by CPU and serial interface (R/W) (Default 7F)
7
6
5
4
0
I/O
Src Port Select
Bit [4:0]:
Bit [5]:
Source port to be mirrored. Use illegal port number to disable mirroring
1 - select ingress data
0 - select egress data
Reserved
Bit [6]:
Bit [7]:
Reserved must be se to '1'
14.12.2 MIRROR1_DEST – Port Mirror destination
CPU Address 701
Accessed by CPU, serial interface (R/W) (Default 17)
7
5
4
0
Dest Port Select
Bit [4:0]:
Port Mirror Destination
When port mirroring is enable, destination port can not serve as a data port.
14.12.3 MIRROR2_SRC – Port Mirror source port
CPU Address 702
Accessed by CPU, serial interface (R/W) (Default FF)
7
6
5
4
0
I/O Src Port Select
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Data Sheet
Bit [4:0]:
Bit [5]:
Source port to be mirrored. Use illegal port number to disable mirroring
1 – select ingress data
0 – select egress data
Reserved
Bit [6]
Bit [7]
Reserved must be set to '1'
14.12.4 MIRROR2_DEST – Port Mirror destination
CPU Address 703
Accessed by CPU, serial interface (R/W) (Default 00)
7
5
4
0
Dest Port Select
Bit [4:0]:
Port Mirror Destination
When port mirroring is enable, destination port can not serve as a data port.
14.13 Group F Address CPU Access Group
14.13.1 GCR-Global Control Register
CPU Address: hF00
Accessed by CPU and serial interface. (R/W)
7
5
4
3
2
1
0
Init
Reset Bist
SR SC
Bit [0]:
Bit [1]:
Bit [2]:
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is
found in the DCR register.
Bit [3]:
Soft Reset (Default = 0)
Write ‘1’ to reset chip
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Data Sheet
Bit [4]:
Initialization Done (Default = 0).
This bit is meaningless in unmanaged mode. In managed mode, CPU write
this bit with ‘1’ to indicate initialization is completed and ready to forward
packets.
1 = Initialization is done.
0 = Initialization is not complete.
14.13.2 DCR-Device Status and Signature Register
CPU Address: hF01
Accessed by CPU and serial interface. (RO)
7
6
5
4
3
2
1
0
Revision
Signature
RE
BinP
BR BW
2
Bit [0]:
1: Busy writing configuration to I C
2
0: Not busy (not writing configuration to I C)
2
Bit [1]:
1: Busy reading configuration from I C
2
0: Not busy ( not reading configuration from I C)
1: BIST in progress
0: BIST not running
1: RAM Error
Bit [2]:
Bit [3]:
0: RAM OK
Bit [5:4]:
Bit [7:6]:
Device Signature
11: MVTX2604 device
Revision
00: Initial Silicon
01: XA1 Silicon
10: Production Silicon
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Data Sheet
14.3.13 DCR1-Giga port status
CPU Address: hF02
Accessed by CPU and serial interface. (RO)
7
6
4
3
2
1
0
CIC
GIGA1
GIGA0
Bit [1:0]:
Bit [3:2]
Bit [7]
Giga port 0 strap option
- 00 – 100 Mb MII mode
- 01 – 2 G mode
- 10 – GMII
- 11 – PCS
Giga port 1 strap option
- 00 – 100 Mb MII mode
- 01 – 2 G mode
- 10 – GMII
- 11 – PCS
Chip initialization completed
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Data Sheet
14.3.14 DPST – Device Port Status Register
CPU Address:hF03
Accessed by CPU and serial interface (R/W)
Bit [4:0]:
Read back index register. This is used for selecting what to read back from
DTST. (Default 00)
- 5’b00000 - Port 0 Operating mode and Negotiation status
- 5’b00001 - Port 1 Operating mode and Negotiation status
- 5’b00010 - Port 2 Operating mode and Negotiation status
- 5’b00011 - Port 3 Operating mode and Negotiation status
- 5’b00100 - Port 4 Operating mode and Negotiation status
- 5’b00101 - Port 5 Operating mode and Negotiation status
- 5’b00110 - Port 6 Operating mode and Negotiation status
- 5’b00111 - Port 7 Operating mode and Negotiation status
- 5’b01000 - Port 8 Operating mode and Negotiation status
- 5’b01001 - Port 9 Operating mode and Negotiation status
- 5’b01010 - Port 10 Operating mode and Negotiation status
- 5’b01011 - Port 11 Operating mode and Negotiation status
- 5’b01100 - Port 12 Operating mode and Negotiation status
- 5’b01101 - Port 13 Operating mode and Negotiation status
- 5’b01110 - Port 14 Operating mode and Negotiation status
- 5’b01111 - Port 15 Operating mode and Negotiation status
- 5’b10000 - Port 16 Operating mode and Negotiation status
- 5’b10001 - Port 17 Operating mode and Negotiation status
- 5’b10010 - Port 18 Operating mode and Negotiation status
- 5’b00011 - Port 19 Operating mode and Negotiation status
- 5’b10100 - Port 20 Operating mode and Negotiation status
- 5’b10101 - Port 21 Operating mode and Negotiation status
- 5’b10110 - Port 22 Operating mode and Negotiation status
- 5’b10111 - Port 23 Operating mode and Negotiation status
- 5’b11000 - Port 24 Operating mode/Neg status (CPU port)
- 5’b11001 - Port 25 Operating mode/Neg status (Gigabit 1)
- 5’b11010 - Port 26 Operating mode/Neg status (Gigabit 2)
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Data Sheet
14.3.15 DTST – Data read back register
CPU Address: hF04
Accessed by CPU and serial interface (RO)
This register provides various internal information as selected in DPST bit[4:0]. Refer to the PHY Control
Application Note.
7
6
5
4
3
2
1
0
MD
Info
Sig
Giga
Inkdn FE
Fdpx
FcEn
When bit is 1:
Bit [0] – Flow control enable
Bit [1] – Full duplex port
Bit [2] – Fast Ethernet port (if not gigabit port)
Bit [3] – Link is down
Bit [4] – Giga port
Bit [5] – Signal detect (when PCS interface mode)
Bit [6] - 2G signal detect (2G mode only)
Bit [7] – Module detected (for hot swap purpose)
14.3.16 DA – DA Register
CPU Address: hFFF
Accessed by CPU and serial interface (RO)
Always return 8’h DA. Indicate the CPU interface or serial port connection is good.
14.4 TBI Registers
Two sets of TBI registers are used for configure the two Gigabit ports if they are operating in TBI mode. These TBI
registers are located inside the switching chip and they are accessed through the MII command and MII data
registers.
14.4.1 Control Register
MII Address: h00
Read/Write
Bit [15]
Reset PCS logic and all TBI registers
1 = Reset.
0 = Normal operation.
Bit [14]
Bit [13]
Reserved. Must be programmed with “0”.
Speed selection (See bit 6 for complete details)
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Data Sheet
Bit [12]
Auto Negotiation Enable
1 = Enable auto-negotiation process.
0 = Disable auto-negotiation process (Default).
Reserved. Must be programmed with “0”
Restart Auto Negotiation.
1 = Restart auto-negotiation process.
0 = Normal operation (Default).
Reserved.
Bit [11:10]
Bit [9]
Bit [8:7]
Bit [6]
Speed Selection
Bit[6][13]
1 1 = Reserved
1 0 =1000 Mb/s (Default)
0 1 =100 Mb/s
0 0 =10 Mb/s
Bit [5:0]
Reserved. Must be programmed with “0”.
14.4.2 Status Register
MII Address: h01
Read Only
Bit [15:9]
Bit [8]
Reserved. Always read back as “0”.
Reserved. Always read back as “1”.
Reserved. Always read back as “0”.
Auto-Negotiation Complete
Bit [7:6]
Bit [5]
1 = Auto-negotiation process completed.
0 = Auto-negotiation process not completed.
Reserved. Always read back as “0”
Reserved. Always read back as “1”
Link Status
Bit [4]
Bit [3]
Bit [2]
1 = Link is up.
0 = Link is down.
Bit [1]
Bit [0]
Reserved. Always read back as “0”.
Reserved. Always read back as “1”.
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Data Sheet
14.4.3 Advertisement Register
MII Address: h04
Read/Write
Bit [15]
Next Page
1 = Has next page capabilities.
0 = Do not has next page capabilities (Default).
Bit [14]
Reserved. Always read back as “0”. Read Only.
Remote Fault. Default is “0”.
Bit [13:12]
Bit [11:9]
Bit [8:7]
Bit [6]
Reserved. Always read back as “0”. Read Only.
Pause. Default is “00”
Half Duplex
1 = Support half duplex (Default).
0 = Do not support half duplex.
Bit [5]
Full duplex
1 = Support full duplex (Default).
0 = Do not support full duplex.
Bit [4:0]
Reserved. Always read back as “0”. Read Only.
14.4.4 Link Partner Ability Register
MII Address: h05
Read Only
Bit [15]
Next Page
1 = Has next page capabilities.
0 = Do not has next page capabilities.
Acknowledge
Bit [14]
Bit [13:12]
Bit [11:9]
Bit [8:7]
Bit [6]
Remote Fault.
Reserved. Always read back as “0”.
Pause.
Half Duplex
1 = Support half duplex.
0 = Do not support half duplex.
Full duplex
Bit [5]
1 = Support full duplex.
0 = Do not support full duplex.
Bit [4:0]
Reserved. Always read back as “0”.
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Data Sheet
14.4.5 Expansion Register
MII Address: h06
Read Only
Bit [15:2]
Bit [1]
Reserved. Always read back as “0”.
Page Received.
1 = A new page has been received.
0 = A new page has not been received.
Reserved. Always read back as “0”.
Bit [0]
14.4.6 Extended Status Register
MII Address: h15
Read Only
Bit [15]
Bit [14]
Bit [13:0]
1000 Full Duplex
1 = Support 1000 full duplex operation (Default).
0 = Do not support 1000 full duplex operation.
1000 Half Duplex
1 = Support 1000 half duplex operation (Default).
0 = Do not support 1000 half duplex operation.
Reserved. Always read back as “0”.
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Data Sheet
15.0 BGA and Ball Signal Descriptions
15.1 BGA Views (Top-View)
15.1.1 Encapsulated view in unmanaged mode
1
2
3
4
5
6
7
8
9
1 0
1 1
1 3
1 2
1 6
1 3
1 9
1 4
3 3
1 5
3 6
1 6
3 9
1 7
4 2
1 8
4 5
1 9
2 0
2 1
K 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D L A _ D O E _ C L A _ C T R U N M I R R M I R R
S T R O T S T O
A
B
C
S C L S D A
4
7
1 0
1 3
1 5
4
E 0 _
8
L K 0 L K 0
O R 4 O R 1
B E U T 7
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D L A _ D O E _ C L A _ C L A _ D M I R R M I R R T R U N R E S E
T S T O T S T O
U T 8 U T 3
D 0
K 2 R V E D
1
3
6
9
1 2
1 4 D S C _ E 1 _
7
1 2
1 5
1 8
3 2
3 5
3 8
4 1
4 4
L K 1 L K 1
6 2
O R 5 O R 2
L A _ C L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ W T _ M O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D O E _ C L A _ C
L K 1 1 E _ E _ D E 1 1 1 1 4 1 7 2 0 3 4 3 7 4 0 4 3 L K 2 L K 2
T R U N M I R R M I R R A U T O T S T O T S T O T S T O T S T O
P _ D
0
2
5
8
3
K 0
O R 3 O R 0
F D U T 1 1 U T 9 U T 4 U T 0
A G N L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ A L A _ W L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D S C A N S C A N T S T O T S T O T S T O T S T O T S T O T S T O
D
E
F
D
1 7
1 9
2 1
2 3
2 5
2 7
2 9
3 1
6
1 0
E 0 _
4 9
5 1
5 3
5 5
5 7
5 9
6 1
6 3
4 7
C O L C L K U T 1 4 U T 1 3 U T 1 2 U T 1 0 U T 5 U T 1
S C A N
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ A L A _ W L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D R E S E L A _ D
S C A N T S T O M 2 6 _ M 2 6 _
L I N K U T 1 5 C R S T X E R
T S T O T S T O
U T 6 U T 2
S C L K
M O D
1 6
1 8
2 0
2 2
2 4
2 6
2 8
3 0
5
9
E 1 _
4 8
5 0
5 2
5 4
5 6
5 8
6 0 R V E D 4 6
E
M 2 6 _
M 2 6 _
T X C L
T X E N
K
M 2 6 _ M 2 6 _ M 2 6 _
M T X R X D R X C L
A V C R E S I S C A N L B _ D L B _ D
V C C V C C V C C V C C V C C
C
N _
E N
6 3
6 2
C L K
V
K
R E S E
T O UT
_
M 2 6 _ M 2 6 _ M 2 6 _
L B _ C
L K
L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _
R X E R C O L
G
H
J
T X D 1 T X D 1 R X D 1
4 7 6 1 6 0
4
5
5
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
L B _ D L B _ D L B _ D L B _ D L B _ D
4 6 4 5 4 4 5 9 5 8
T X D 1 T X D 1 R X D 1 R X D 1 R X D 1
2
3
2
3
4
M 2 6 _ M 2 6 _
M 2 6 _ M 2 6 _
L B _ D L B _ D L B _ D L B _ D L B _ D
4 3 4 2 4 1 5 7 5 6
M 2 6 _
R X D 9
T X D 1 T X D 1
R X D 1 R X D 1
0
1
0
1
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 9 T X D 8 R X D 6 R X D 7 R X D 8
K
L
V D D V D D
V D D V D D
4 0
3 9
3 8
5 5
5 4
L B _ D L B _ D L B _ D L B _ D L B _ D
3 7 3 6 3 5 5 3 5 2
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 4 T X D 6 R X D 3 R X D 4 R X D 5
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 7 T X D 5 R X D 0 R X D 1 R X D 2
M
N
P
V D D
V D D
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V D D
V D D
3 4
3 3
3 2
5 1
5 0
G R E F
L B _ A L B _ A L B _ A L B _ D L B _ D
M 2 6 _ M 2 6 _
_ C L K
V C C
V C C
V C C
V C C
V C C
V C C
V C C
V C C
1 8
1 9
2 0
4 9
4 8
T X D 2 T X D 3
1
G R E F
L B _ A L B _ A L B _ A L B _ W L B _
M 2 6 _ M 2 6 _
M D I O _ C L K
T X D 0 T X D 1
0
1 5 1 6 1 7 E 0 _ W E 1 _
L B _ A L B _ A L B _ A L B _ A L B _ A
M 2 5 _ M 2 5 _
C R S T X E R
M _ C L
M D C
K
R
T
1 0
1 1
1 2
1 3
1 4
M 2 5 _
M 2 5 _ M 2 5 _ M 2 5 _
V C C T X C L
M T X R X D R X C L
T X E N
K C L K
L B _ A L B _ A L B _ A L B _ A L B _ A
M 2 5 _
5
6
7
8
9
V
K
M 2 5 _ M 2 5 _ M 2 5 _
L B _ O L B _ O T _ M O L B _ D L B _ D
M 2 5 _ M 2 5 _
R X E R C O L
U
V
V D D
V D D
V D D
V D D
V C C T X D 1 T X D 1 R X D 1
E 0 _
E 1 _ D E 0
3 1
3 0
4
5
5
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
L B _ A L B _ O L B _ W L B _ D L B _ D
T X D 1 T X D 1 R X D 1 R X D 1 R X D 1
D S C _ E _ E _ 2 9 2 8
2
3
2
3
4
M 2 5 _ M 2 5 _
M 2 5 _ M 2 5 _
L B _ D L B _ A L B _ A L B _ D L B _ D
M 2 5 _
R X D 9
W
Y
T X D 1 T X D 1
R X D 1 R X D 1
1 5
3
4
2 7
2 6
0
1
0
1
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
R X D 6 T X D 8 R X D 9 R X D 7 R X D 8
V D D V D D
V D D V D D
1 4 1 3 1 2 2 5 2 4
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
T X D 6 T X D 7 R X D 3 R X D 4 R X D 5
A
A
1 1
1 0
9
2 3
2 2
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
T X D 4 T X D 5 R X D 0 R X D 1 R X D 2
A
B
8
7
6
2 1
2 0
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 3 _ M 2 3 _ M 2 3 _
T X D 2 T X D 3 C R S R X D 0 R X D 1
A
C
5
4
3
1 9
1 8
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 3 _ M 2 3 _ M 2 3 _
T X D 0 T X D 1 T X D 1 T X D 0 T X E N
A
D
V C C V C C V C C V C C V C C
2
1
0
1 7
1 6
M 0 _ T M 0 _ T M 0 _ T M 3 _ T M 3 _ T M 3 _ R M 5 _ T M 5 _ T M 5 _ R M 8 _ T M 8 _ T M 8 _ R M 1 0 _ M 1 0 _ M 1 0 _ M 1 3 _ M 1 6 _ M 1 5 _ M 1 6 _ M 1 5 _ M 1 5 _ M 1 8 _ M 1 8 _ M 1 8 _ M 2 0 _ M 2 0 _ M 2 0 _ M 2 2 _
X E N X D 0 X D 1 X D 1 X E N X D 0 X D 1 X E N X D 0 X D 1 X E N X D 0 T X D 1 T X E N R X D 0 T X D 1 T X D 0 T X D 1 R X D 1 T X E N R X D 0 T X D 1 T X E N R X D 0 T X D 1 T X E N R X D 0 R X D 1
A
E
M 0 _ R M 0 _ R M 0 _ C M 3 _ T M 3 _ C M 3 _ R M 5 _ T M 5 _ C M 5 _ R M 8 _ T M 8 _ C M 8 _ R M 1 0 _ M 1 0 _ M 1 0 _ M 1 3 _ M 1 3 _ M 1 3 _ M 1 4 _ M 1 6 R M 1 5 _ M 1 7 _ M 1 7 _ M 1 8 _ M 2 0 _ M 2 0 _ M 2 0 _ M 2 2 _ M 2 2 _
A F
X D 1 X D 0
R S
X D 0
R S
X D 1 X D 0
R S
X D 1 X D 0
R S
X D 1 T X D 0 C R S R X D 1 T X D 0 C R S R X D 1 C R S X D 0 R X D 1 R X D 0 C R S R X D 1 T X D 0 C R S R X D 1 R X D 0 C R S
M 1 _ T M 1 _ T M 1 _ T M 2 _ T M 2 _ C M 4 _ T M 4 _ C M 6 _ T M 6 _ C M 7 _ T M 7 _ C M 9 _ T M 9 _ C M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 5 _ M 1 6 _ M 1 6 _ M 1 8 _ M 1 8 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _ M 2 2 _ M 2 2 _
A
G
X E N X D 0 X D 1 X D 1
R S
X D 1
R S
X D 1
R S
X D 1
R S
X D 1
R S T X D 1 C R S T X D 1 C R S T X D 1 T X D 0 T X D 1 C R S T X D 0 C R S T X D 1 C R S T X D 1 C R S T X E N T X D 0
M 1 _ R M 1 _ C M 2 _ T M 2 _ R M 4 _ T M 4 _ R M 6 _ T M 6 _ R M 7 _ T M 7 _ R M 9 _ T M 9 _ R M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 4 _ M 1 3 _ M 1 5 _ M 1 7 _ M 1 7 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _ M 2 2 _
A
H
X D 0
R S
X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 T X D 0 R X D 0 T X D 0 R X D 0 T X D 0 R X D 0 R X D 0 C R S T X D 0 R X D 1 T X D 0 R X D 0 T X D 0 R X D 0 T X D 1
M 1 _ R M 2 _ T M 2 _ R M 4 _ T M 4 _ R M 6 _ T M 6 _ R M 7 _ T M 7 _ R M 9 _ T M 9 _ R M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 4 _ M 1 6 _ M 1 3 _ M 1 7 _ M 1 7 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _
X D 1 X E N X D 1 X E N X D 1 X E N X D 1 X E N X D 1 X E N X D 1 T X E N R X D 1 T X E N R X D 1 T X E N R X D 1 T X E N T X E N T X E N T X D 1 T X E N R X D 1 T X E N R X D 1
A J
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
123
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.1.2 Encapsulated view in managed mode
1
2
3
4
5
6
7
8
9
1 0
1 1
1 3
1 2
1 6
1 3
1 9
1 4
3 3
1 5
3 6
1 6
3 9
1 7
4 2
1 8
4 5
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D L A _ D P _ D A P _ D A P _ D A P _ D A P _ D A
T S T O
U T 7
A
B
C
P _ A 0 P _ A 1 P _ W E
4
7
1 0
1 3
1 5
4
E 0 _
8
T A 1 3 T A 1 0 T A 7 T A 4 T A 1
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D L A _ D P _ D A P _ D A L A _ D P _ D A P _ D A P _ D A P _ I N
T S T O T S T O
U T 8 U T 3
P _ R D
1
3
6
9
1 2
1 4 D S C _ E 1 _
7
1 2
1 5
1 8
3 2
3 5
3 8
4 1
4 4
T A 1 4 T A 1 1
6 2
T A 5 T A 2 T A 6
T
P -
P _ D A
L A _ C L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ O L A _ W T _ M O L A _ A L A _ A L A _ A L A _ A L A _ D L A _ D L A _ D L A _ D P _ D A P _ D A P _ D A
T S T O T S T O T S T O T S T O
U T 1 1 U T 9 U T 4 U T 0
P _ A 2 D A T A
T A 0
P _ C S
L K
0
2
5
8
1 1
3
E _ E _
D E 1
1 1
1 4
1 7
2 0
3 4
3 7
4 0
4 3
T A 1 5 T A 1 2 T A 9
3
A G N L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ A L A _ W L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D S C A N S C A N T S T O T S T O T S T O T S T O T S T O T S T O
D
E
F
D
1 7
1 9
2 1
2 3
2 5
2 7
2 9
3 1
6
1 0
E 0 _
4 9
5 1
5 3
5 5
5 7
5 9
6 1
6 3
4 7
C O L C L K U T 1 4 U T 1 3 U T 1 2 U T 1 0 U T 5 U T 1
S C A N
L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ A L A _ A L A _ W L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D L A _ D P _ D A L A _ D
S C A N T S T O M 2 6 _ M 2 6 _
L I N K U T 1 5 C R S T X E R
T S T O T S T O
U T 6 U T 2
S C L K
M O D
1 6
1 8
2 0
2 2
2 4
2 6
2 8
3 0
5
9
E 1 _
4 8
5 0
5 2
5 4
5 6
5 8
6 0
T A 8
4 6
E
M 2 6 _
M 2 6 _
T X C L
T X E N
K
M 2 6 _ M 2 6 _ M 2 6 _
M T X R X D R X C L
A V C R E S I S C A N L B _ D L B _ D
V C C V C C V C C V C C V C C
C
N _
E N
6 3
6 2
C L K
V
K
R E S E
T O UT
_
M 2 6 _ M 2 6 _ M 2 6 _
L B _ C
L K
L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _
R X E R C O L
G
H
J
T X D 1 T X D 1 R X D 1
4 7 6 1 6 0
4
5
5
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
L B _ D L B _ D L B _ D L B _ D L B _ D
4 6 4 5 4 4 5 9 5 8
T X D 1 T X D 1 R X D 1 R X D 1 R X D 1
2
3
2
3
4
M 2 6 _ M 2 6 _
M 2 6 _ M 2 6 _
L B _ D L B _ D L B _ D L B _ D L B _ D
4 3 4 2 4 1 5 7 5 6
M 2 6 _
R X D 9
T X D 1 T X D 1
R X D 1 R X D 1
0
1
0
1
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 9 T X D 8 R X D 6 R X D 7 R X D 8
K
L
V D D V D D
V D D V D D
4 0
3 9
3 8
5 5
5 4
L B _ D L B _ D L B _ D L B _ D L B _ D
3 7 3 6 3 5 5 3 5 2
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 4 T X D 6 R X D 3 R X D 4 R X D 5
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _ M 2 6 _
T X D 7 T X D 5 R X D 0 R X D 1 R X D 2
M
N
P
V D D
V D D
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V S S V S S V S S V S S V S S V S S V S S
V D D
V D D
3 4
3 3
3 2
5 1
5 0
G R E F
L B _ A L B _ A L B _ A L B _ D L B _ D
M 2 6 _ M 2 6 _
_ C L K
V C C
V C C
V C C
V C C
V C C
V C C
V C C
V C C
1 8
1 9
2 0
4 9
4 8
T X D 2 T X D 3
1
G R E F
L B _ A L B _ A L B _ A L B _ W L B _
M 2 6 _ M 2 6 _
M D I O _ C L K
T X D 0 T X D 1
0
1 5 1 6 1 7 E 0 _ W E 1 _
L B _ A L B _ A L B _ A L B _ A L B _ A
M 2 5 _ M 2 5 _
C R S T X E R
M _ C L
M D C
K
R
T
1 0
1 1
1 2
1 3
1 4
M 2 5 _
M 2 5 _ M 2 5 _ M 2 5 _
V C C T X C L
M T X R X D R X C L
T X E N
K C L K
L B _ A L B _ A L B _ A L B _ A L B _ A
M 2 5 _
5
6
7
8
9
V
K
M 2 5 _ M 2 5 _ M 2 5 _
L B _ O L B _ O T _ M O L B _ D L B _ D
M 2 5 _ M 2 5 _
R X E R C O L
U
V
V D D
V D D
V D D
V D D
V C C T X D 1 T X D 1 R X D 1
E 0 _
E 1 _ D E 0
3 1
3 0
4
5
5
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
L B _ A L B _ O L B _ W L B _ D L B _ D
T X D 1 T X D 1 R X D 1 R X D 1 R X D 1
D S C _ E _ E _ 2 9 2 8
2
3
2
3
4
M 2 5 _ M 2 5 _
M 2 5 _ M 2 5 _
L B _ D L B _ A L B _ A L B _ D L B _ D
M 2 5 _
R X D 9
W
Y
T X D 1 T X D 1
R X D 1 R X D 1
1 5
3
4
2 7
2 6
0
1
0
1
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
R X D 6 T X D 8 R X D 9 R X D 7 R X D 8
V D D V D D
V D D V D D
1 4 1 3 1 2 2 5 2 4
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
T X D 6 T X D 7 R X D 3 R X D 4 R X D 5
A
A
1 1
1 0
9
2 3
2 2
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _ M 2 5 _
T X D 4 T X D 5 R X D 0 R X D 1 R X D 2
A
B
8
7
6
2 1
2 0
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 3 _ M 2 3 _ M 2 3 _
T X D 2 T X D 3 C R S R X D 0 R X D 1
A
C
5
4
3
1 9
1 8
L B _ D L B _ D L B _ D L B _ D L B _ D
M 2 5 _ M 2 5 _ M 2 3 _ M 2 3 _ M 2 3 _
T X D 0 T X D 1 T X D 1 T X D 0 T X E N
A
D
V C C V C C V C C V C C V C C
2
1
0
1 7
1 6
M 0 _ T M 0 _ T M 0 _ T M 3 _ T M 3 _ T M 3 _ R M 5 _ T M 5 _ T M 5 _ R M 8 _ T M 8 _ T M 8 _ R M 1 0 _ M 1 0 _ M 1 0 _ M 1 3 _ M 1 6 _ M 1 5 _ M 1 6 _ M 1 5 _ M 1 5 _ M 1 8 _ M 1 8 _ M 1 8 _ M 2 0 _ M 2 0 _ M 2 0 _ M 2 2 _
X E N X D 0 X D 1 X D 1 X E N X D 0 X D 1 X E N X D 0 X D 1 X E N X D 0 T X D 1 T X E N R X D 0 T X D 1 T X D 0 T X D 1 R X D 1 T X E N R X D 0 T X D 1 T X E N R X D 0 T X D 1 T X E N R X D 0 R X D 1
A
E
M 0 _ R M 0 _ R M 0 _ C M 3 _ T M 3 _ C M 3 _ R M 5 _ T M 5 _ C M 5 _ R M 8 _ T M 8 _ C M 8 _ R M 1 0 _ M 1 0 _ M 1 0 _ M 1 3 _ M 1 3 _ M 1 3 _ M 1 4 _ M 1 6 R M 1 5 _ M 1 7 _ M 1 7 _ M 1 8 _ M 2 0 _ M 2 0 _ M 2 0 _ M 2 2 _ M 2 2 _
A F
X D 1 X D 0
R S
X D 0
R S
X D 1 X D 0
R S
X D 1 X D 0
R S
X D 1 T X D 0 C R S R X D 1 T X D 0 C R S R X D 1 C R S X D 0 R X D 1 R X D 0 C R S R X D 1 T X D 0 C R S R X D 1 R X D 0 C R S
M 1 _ T M 1 _ T M 1 _ T M 2 _ T M 2 _ C M 4 _ T M 4 _ C M 6 _ T M 6 _ C M 7 _ T M 7 _ C M 9 _ T M 9 _ C M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 5 _ M 1 6 _ M 1 6 _ M 1 8 _ M 1 8 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _ M 2 2 _ M 2 2 _
A
G
X E N X D 0 X D 1 X D 1
R S
X D 1
R S
X D 1
R S
X D 1
R S
X D 1
R S T X D 1 C R S T X D 1 C R S T X D 1 T X D 0 T X D 1 C R S T X D 0 C R S T X D 1 C R S T X D 1 C R S T X E N T X D 0
M 1 _ R M 1 _ C M 2 _ T M 2 _ R M 4 _ T M 4 _ R M 6 _ T M 6 _ R M 7 _ T M 7 _ R M 9 _ T M 9 _ R M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 4 _ M 1 3 _ M 1 5 _ M 1 7 _ M 1 7 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _ M 2 2 _
A
H
X D 0
R S
X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 X D 0 T X D 0 R X D 0 T X D 0 R X D 0 T X D 0 R X D 0 R X D 0 C R S T X D 0 R X D 1 T X D 0 R X D 0 T X D 0 R X D 0 T X D 1
M 1 _ R M 2 _ T M 2 _ R M 4 _ T M 4 _ R M 6 _ T M 6 _ R M 7 _ T M 7 _ R M 9 _ T M 9 _ R M 1 1 _ M 1 1 _ M 1 2 _ M 1 2 _ M 1 4 _ M 1 4 _ M 1 6 _ M 1 3 _ M 1 7 _ M 1 7 _ M 1 9 _ M 1 9 _ M 2 1 _ M 2 1 _
X D 1 X E N X D 1 X E N X D 1 X E N X D 1 X E N X D 1 X E N X D 1 T X E N R X D 1 T X E N R X D 1 T X E N R X D 1 T X E N T X E N T X E N T X D 1 T X E N R X D 1 T X E N R X D 1
A J
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
124
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.2 Ball – Signal Descriptions in Managed Mode
All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive.
15.2.1 Ball Signal Descriptions in Managed Mode
Ball No(s)
Symbol
I/O
Description
CPU BUS Interface in Managed Mode
C19, B19, A19,
C20, B20, A20,
C21, E20, A21,
B24, B22, A22,
C23, B23, A23,
C24
P_DATA[15:0]
I/O-TS with pull up
Except P_DATA[7:6]
I/O-TS with pull down
Processor Bus Data Bit [15:0].
P_DATA[7:0] is used in 8-bit mode.
C22, A24, A25
A26
P_A[2:0]
P_WE#
Input
Processor Bus Address Bit [2:0]
CPU Bus-Write Enable
Input with weak
internal pull up
B26
C25
B25
P_RD#
P_CS#
P_INT#
Input with weak
internal pull up
CPU Bus-Read Enable
Chip Select
Input with weak
internal pull up
Output
CPU Interrupt
Frame Buffer Interface
D20, B21, D19,
E19,D18, E18,
LA_D[63:0]
I/O-TS with pullup
Frame Bank A– Data Bit [63:0]
D17, E17, D16,
E16, D15, E15,
D14, E14, D13,
E13, D21, E21,
A18, B18, C18,
A17, B17, C17,
A16, B16, C16,
A15, B15, C15,
A14, B14, D9, E9,
D8, E8, D7, E7, D6,
E6, D5, E5, D4, E4,
D3, E3, D2, E2, A7,
B7, A6, B6, C6, A5,
B5, C5, A4, B4, C4,
A3, B3, C3, B2, C2
C14, A13, B13,
C13, A12, B12,
C12, A11, B11,
C11, D11, E11,
A10, B10, D10,
E10, A8, C7
LA_A[20:3]
Output
Frame Bank A – Address Bit [20:3]
125
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
LA_ADSC#
I/O
Description
B8
Output with pull up
Frame Bank A Address Status
Control
C1
C9
LA_CLK
LA_WE#
Output
Frame Bank A Clock Input
Output with pull up
Frame Bank A Write Chip Select for
one layer SRAM configuration
D12
E12
LA_WE0#
LA_WE1#
Output with pull up
Output with pull up
Frame Bank A Write Chip Select for
lower layer of two layers SRAM
configuration
Frame Bank A Write Chip Select for
upper layer of two layers SRAM
configuration
C8
A9
LA_OE#
Output with pull up
Output with pull up
Frame Bank A Read Chip Select for
one bank SRAM configuration
LA_OE0#
Frame Bank A Read Chip Select for
lower layer of two layers SRAM
configuration
B9
LA_OE1#
Output with pull up
I/O-TS with pullup.
Frame Bank A Read Chip Select for
upper layer of two layers SRAM
configuration
F4, F5, G4, G5, H4, LB_D[63:0]
H5, J4, J5, K4, K5,
L4, L5, M4, M5, N4,
N5, G3, H1, H2,
Frame Bank B– Data Bit [63:0]
H3, J1, J2, J3, K1,
K2, K3, L1, L2, L3,
M1, M2, M3, U4,
U5, V4, V5, W4,
W5, Y4, Y5, AA4,
AA5, AB4, AB5,
AC4, AC5, AD4,
AD5, W1, Y1, Y2,
Y3, AA1, AA2, AA3,
AB1, AB2, AB3,
AC1, AC2, AC3,
AD1, AD2, AD3
N3, N2, N1, P3, P2, LB_A[20:3]
P1, R5, R4, R3, R2,
R1, T5, T4, T3, T2,
Output
Frame Bank B – Address Bit [20:3]
T1, W3, W2
V1
LB_ADSC#
Output with pull up
Frame Bank B Address Status
Control
G1
V3
LB_CLK
LB_WE#
Output with pull up
Output with pull up
Frame Bank B Clock Input
Frame Bank B Write Chip Select for
one layer SRAM configuration
126
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
LB_WE0#
I/O
Description
P4
P5
Output with pull up
Frame Bank B Write Chip Select for
lower layer of two layer SRAM
configuration
LB_WE1#
Output with pull up
Frame Bank B Write Chip Select for
upper layer of two layers SRAM
configuration
V2
U1
LB_OE#
Output with pull up
Output with pull up
Frame Bank B Read Chip Select for
one layer SRAM configuration
LB_OE0#
Frame Bank B Read Chip Select for
lower layer of two layers SRAM
configuration
U2
LB_OE1#
Output with pull up
Frame Bank B Read Chip Select for
upper layer of two layers SRAM
configuration
Fast Ethernet Access Ports [23:0] RMII
R28
P28
R29
M_MDC
M_MDIO
M_CLKI
Output
MII Management Data Clock –
(Common for all MII Ports [23:0])
I/O-TS with pull up
MII Management Data I/O –
(Common for all MII Ports –[23:0]))
Input
Reference Input Clock
AC29, AE28, AJ27, M[23:0]_RXD[1]
AF27, AJ25, AF24,
AH23, AE19, AF21,
AJ19, AF18, AJ17,
AJ15, AF15, AJ13,
AF12, AJ11, AJ9,
Input with weak
internal pull up
resistors.
Ports [23:0] – Receive Data Bit [1]
AF9, AJ7, AF6,
AJ5, AJ3, AF1
AC28, AF28, AH27, M[23:0]_RXD[0]
AE27, AH25, AE24,
AF22, AF20, AE21,
AH19, AH20,
Input with weak
internal pull up
resistors
Ports [23:0] – Receive Data Bit [0]
AH17, AH15,
AE15, AH13, AE12,
AH11, AH9, AE9,
AH7, AE6, AH5,
AH2, AF2
127
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
I/O
Description
AC27, AF29,
M[23:0]_CRS_DV
Input with weak
internal pull down
resistors.
Ports [23:0] – Carrier Sense and
Receive Data Valid
AG27, AF26,
AG25, AG23,
AF23, AG21,
AH21, AF19, AF17,
AG17, AG15,
AF14, AG13, AF11,
AG11, AG9, AF8,
AG7, AF5, AG5,
AH3, AF3
AD29, AG28, AJ26, M[23:0]_TXEN
AE26, AJ24, AE23,
AJ22, AJ20, AE20,
AJ18, AJ21, AJ16,
AJ14, AE14, AJ12,
AE11, AJ10, AJ8,
I/O- TS with pull up ,
slew
Ports [23:0] – Transmit Enable
Strap option for RMII/GPSI
AE8, AJ6, AE5,
AJ4, AG1, AE1
AD27, AH28,
M[23:0]_TXD[1]
Output, slew
Ports [23:0] – Transmit Data Bit [1]
AG26, AE25,
AG24, AE22, AJ23,
AG20, AE18,
AG18, AE16,
AG16, AG14,
AE13, AG12,
AE10, AG10, AG8,
AE7, AG6, AE4,
AG4, AG3, AE3
AD28, AG29,
M[23:0]_TXD[0]
Output, slew
Ports [23:0] – Transmit Data Bit [0]
AH26, AF25, AH24,
AG22, AH22,
AE17, AG19,
AH18, AF16, AH16,
AH14, AF13, AH12,
AF10, AH10, AH8,
AF7, AH6, AF4,
AH4, AG2, AE2
GMII/TBI GiGabit Ethernet Access Ports 0 & 1
U26, U25, V26,
V25, W26, W25,
Y27, Y26, AA26,
AA25, AB26, AB25,
AC26, AC25,
M25_TXD[15:0]
Output
Transmit Data Bit [15:0]
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
AD26, AD25
T28
U28
R25
M25_RX_DV
M25_RX_ER
M25_CRS
Input w/ pull down
Input w/ pull up
Receive Data Valid
Receive Error
Input w/ pull down
Carrier Sense
128
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
M25_COL
I/O
Description
Collision Detected
U29
T29
Input w/ pull up
Input w/ pull up
Input w/ pull up
M25_RXCLK
Receive Clock
U27, V29, V28,
V27, W29, W28,
W27, Y29, Y28,
Y25, AA29, AA28,
AA27, AB29, AB28,
AB27
M25_RXD[15:0]
Receive Data Bit [15:0]
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
T26
R26
T27
T25
P29
M25_TX_EN
M25_TX_ER
M25_ MTXCLK
M25_ TXCLK
GREF_CLK0
M26_TXD[15:0]
Output w/ pull up
Output w/ pull up
Input w/ pull down
Output
Transmit Data Enable
Transmit Error
MII Mode Transmit Clock
Gigabit Transmit Clock
Gigabit Reference Clock
Input w/ pull up
Output
G26, G25, H26,
H25, J26, J25, K25,
K26, M25, L26,
M26, L25, N26,
N25, P26, P25
Transmit Data Bit [15:0]
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
F28
G28
E25
G29
F29
M26_RX_DV
M26_RX_ER
M26_CRS
Input w/ pull down
Input w/ pull up
Input w/ pull down
Input w/ pull up
Input w/ pull up
Input w/ pull up
Receive Data Valid
Receive Error
Carrier Sense
M26_COL
Collision Detected
Receive Clock
M26_RXCLK
M26_RXD[15:0]
G27,H29, H28,
H27, J29, J28, J27,
K29, K28, K27,
L29, L28, L27,
Receive Data Bit [15:0]
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
M29, M28, M27
F26
M26_TX_EN
M26_TX_ER
M26_ MTXCLK
M26_ TXCLK
GREF_CLK1
Output w/ pull up
Output w/ pull up
Input w/ pull down
Output
Transmit Data Enable
Transmit Error
E26
F27
MII Mode Transmit Clock
Gigabit Transmit Clock
Gigabit Reference Clock
F25
N29
Input w/ pull up
LED Interface
C29
LED_CLK/TSTOUT0 I/O- TS with pull up
LED_SYN/TSTOUT1 I/O- TS with pull up
LED Serial Interface Output Clock
LED Output Data Stream Envelope
D29
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Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
I/O
Description
E29
B28
LED_BIT/TSTOUT2
I/O- TS with pull up
LED Serial Data Output Stream
G1_RXTX#/TSTOUT I/O- TS with pull up
3
LED for Gigabit port 1 (receive +
transmit)
C28
D28
E28
A27
B27
C27
D27
C26
D26
D25
D24
E24
G1_DPCOL#/TSTO
UT4
I/O- TS with pull up
LED for Gigabit port 1 (full duplex +
collision)
G1_LINK#/TSTOUT
5
I/O- TS with pull up
LED for Gigabit port 1
G2_RXTX#/TSTOUT I/O- TS with pull up
6
LED for Gigabit port 2 (receive +
transmit)
G2_DPCOL#/TSTO
UT7
I/O- TS with pull up
I/O- TS with pull up
I/O- TS with pull up
LED for Gigabit port 2 (full duplex +
collision)
G2_LINK#/TSTOUT
8
LED for Gigabit port 2
System start operation
Start initialization
INIT_DONE/TSTOU
T9
INIT_START/TSTOU I/O- TS with pull up
T10
CHECKSUM_OK/TS I/O- TS with pull up
TOUT11
EEPROM read OK
FCB_ERR/TSTOUT
12
I/O- TS with pull up
FCB memory self test fail
MCT memory self test fail
Processing memory self test
Memory self test done
MCT_ERR/TSTOUT
13
I/O- TS with pull up
BIST_IN_PRC/TSTO I/O- TS with pull up
UT14
BIST_DONE/TSTOU I/O- TS with pull up
T15
Test Facility
U3, C10
T_MODE0,
T_MODE1
I/O-TS
Test Pins
00 – Test mode – Set Mode upon
Reset, and provides NAND Tree test
output during test mode
01 - Reserved - Do not use
10 - Reserved - Do not use
11 – Normal mode. Use external pull
up for normal mode
F3
E27
SCAN_EN
SCANMODE
Input with pull down
Input with pull down
Scan Enable
1 – Enable Test mode
0 - Normal mode (open)
130
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
System Clock, Power, and Ground Pins
E1 SCLK
Symbol
I/O
Description
Input
Power
System Clock at 100 MHz
+2.5 Volt DC Supply
K12, K13, K17,K18 VDD
M10, N10, M20,
N20, U10, V10,
U20, V20, Y12,
Y13, Y17, Y18
F13, F14, F15,
VCC
VSS
Power
+3.3 Volt DC Supply
Ground
F16, F17, N6, P6,
R6, T6, U6, N24,
P24, R24, T24,
U24, AD13, AD14,
AD15, AD16, AD17
M12, M13, M14,
M15, M16, M17,
M18, N12, N13,
N14, N15, N16,
N17, N18, P12,
P13, P14, P15,
P16, P17, P18,
R12, R13, R14,
R15, R16, R17,
R18, T12, T13,
T14, T15, T16,
T17, T18, U12,
U13, U14, U15,
U16, U17, U18,
V12, V13, V14,
V15, V16, V17,
V18,
Power Ground
F1
D1
AVCC
AGND
Analog Power
Analog Ground
Analog +2.5 Volt DC Supply
Analog Ground
MISC
D22
SCANCOL
SCANCLK
Input/ output
Output
Scans the Collision signal of Home
PHY
Clock for scanning Home PHY
collision and link
D23
E23
F2
SCANLINK
RESIN#
Input/ output
Input
Link up signal from Home PHY
Reset Input
G2
RESETOUT#
Output
Reset PHY
Bootstrap Pins (Default = pull up, 1= pull up 0= pull down)
After reset TSTOUT0 to TSTOU15 are used by the LED interface.
C29
TSTOUT0
Default 1
GIGA Link polarity
0 – active low
1 – active high
131
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
TSTOUT1
I/O
Description
D29
E29
B28
C28
D28
E28
A27
Default 1
RMII MAC Power Saving Enable
0 – No power saving
1 – power saving
TSTOUT2
TSTOUT3
TSTOUT4
TSTOUT5
TSTOUT6
TSTOUT7
Default: Enable (1)
Recommend disable
(0) with pull-down
Giga Half Duplex Support
0 - Disable
1 - Enable
Default 1
Default 1
Default 1
Default 1
Default 1
Module detect enable
0 – Hot swap enable
1 – Hot swap disable
Memory is SBRAM/ZBT
0 – ZBT
1 – Pipeline SBRAM
Scan Speed: ¼ SCLK or SCLK
0 – ¼ SCLK (HPNA)
1 - SCLK
CPU Port Mode
0 - 8 bit Bus Mode
1 - 16 bit Bus Mode
Memory Size
0 - 256 K x 32 or 256 K x 64
(4 M total)
1 - 128 K x 32 or 128 K x 64
(2 M total)
B27
C27
D27
C26
TSTOUT8
TSTOUT9
TSTOUT10
TSTOUT11
Default 1
Default 1
Default 1
Default 1
EEPROM Installed
0 – EEPROM installed
1 – EEPROM not installed
MCT Aging
0 – MCT aging disable
1 – MCT aging enable
FCB Aging
0 - FCB aging disable
1 – FCB aging enable
Timeout Reset
0 – Time out reset disable
1 – Time out reset enable. Issue
reset if any state machine did not go
back to idle for 5sec.
D26
D25
TSTOUT12
TSTOUT13
Reserved
Default 1
Default 1
Default 1
FDB RAM depth (1 or 2 layers)
0 – 2 layer
1 – 1 layer
D24
E24
TSTOUT14
TSTOUT15
CPU installed
0 – CPU installed
1 – CPU not installed
SRAM Test Mode
0 – Enable test mode
1 – Normal operation
132
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
T26, R26
Symbol
I/O
Description
G0_TXEN,
Default: PCS
Giga0
G0_TXER
Mode: G0_TXEN G0_TXER
0
0
1
1
0
1
0
1
MII
2G
GMII
PCS
F26, E26
G1_TXEN,
G1_TXER
Default: PCS
Default: RMII
Giga1
Mode: G1_TXEN G1_TXER
0
0
1
1
0
1
0
1
MII
2G
GMII
PCS
AD29, AG28, AJ26, M[23:0] TXEN
AE26, AJ24, AE23,
AJ22, AJ20, AE20,
AJ18, AJ21, AJ16,
AJ14, AE14, AJ12,
AE11, AJ10, AJ8,
0 – GPSI
1 – RMII
AE8, AJ6, AE5,
AJ4, AG1, AE1
C21
C19, B19, A19
P_D[9]
P_D[15:13]
Must be pulled-down
Default: 111
Reserved. Must be pulled-down.
Programmable delay for internal
OE_CLK from SCLK input. The
OE_CLK is used for generating the
OE0 and OE1 signals
Suggested value is 001.
C20, B20, A20
P_D[12:10]
P_D[5:0]
Default: 111
Programmable delay for LA_CLK
and LB_CLK from internal OE_CLK.
The LA_CLK and LB_CLK delay
from SCLK is the sum of the delay
programmed in here and the delay in
P_D[15:13].
Suggested value is 011.
B22, A22, C23,
B23, A23, C24
Default: 111111
Dedicated Port Mirror Mode. The
first 5 bits select the port to be
mirrored. The last bit selects either
ingress or egress data.
Notes
# = Active low signal
Input = Input signal
In-ST = Input signal with Schmitt-Trigger
Output = Output signal (Tri-State driver)
Out-OD = Output signal with Open-Drain driver
I/O-TS = Input & Output signal with Tri-State driver
I/O-OD = Input & Output signal with Open-Drain driver
133
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.2.2 Ball – Signal Descriptions in Unmanaged Mode
Ball No(s)
Symbol
I/O
Description
2
2
I C Interface Note: In unmanaged mode, Use I C and Serial control interface to configure the system
2
A24
A25
SCL
SDA
Output
I C Data Clock
2
I/O-TS with internal pull
up
I C Data I/O
Serial Control Interface
A26
B26
C25
STROBE
Input with weak internal
pull up
Serial Strobe Pin
D0
Input with weak internal
pull up
Serial Data Input
AUTOFD
Output with pull up
Serial Data Output (AutoFD)
Frame Buffer Interface
D20, B21, D19,
E19,D18, E18,
D17, E17, D16,
E16, D15, E15,
D14, E14, D13,
E13, D21, E21,
A18, B18, C18,
A17, B17, C17,
A16, B16, C16,
A15, B15, C15,
A14, B14, D9, E9,
D8, E8, D7, E7,
D6, E6, D5, E5,
D4, E4, D3, E3,
D2, E2, A7, B7,
A6, B6, C6, A5,
B5, C5, A4, B4,
C4, A3, B3, C3,
B2, C2
LA_D[63:0]
I/O-TS with pull up
Frame Bank A– Data Bit [63:0]
C14, A13, B13,
C13, A12, B12,
C12, A11, B11,
C11, D11, E11,
A10, B10, D10,
E10, A8, C7
LA_A[20:3]
LA_ADSC#
Output
Frame Bank A – Address Bit
[20:3]
B8
Output with pull up
Frame Bank A Address Status
Control
C1
C9
LA_CLK
LA_WE#
Output with pull up
Output with pull up
Frame Bank A Clock Input
Frame Bank A Write Chip
Select for one layer SRAM
application
134
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
D12
Symbol
LA_WE0#
I/O
Description
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Output with pull up
I/O-TS with pull up.
Frame Bank A Write Chip
Select for lower layer of two
bank SRAM application
E12
C8
A9
LA_WE1#
LA_OE#
Frame Bank A Write Chip
Select for upper bank of two
layer SRAM application
Frame Bank A Read Chip
Select for one layer SRAM
application
LA_OE0#
LA_OE1#
LB_D[63:0]
Frame Bank A Read Chip
Select for lower layer of two
layers SRAM application
B9
Frame Bank A Read Chip
Select for upper layer of two
layers SRAM application
F4, F5, G4, G5,
H4, H5, J4, J5,
K4, K5, L4, L5,
M4, M5, N4, N5,
G3, H1, H2, H3,
J1, J2, J3, K1, K2,
K3, L1, L2, L3,
M1, M2, M3, U4,
U5, V4, V5, W4,
W5, Y4, Y5, AA4,
AA5, AB4, AB5,
AC4, AC5, AD4,
AD5, W1, Y1, Y2,
Y3, AA1, AA2,
AA3, AB1, AB2,
AB3, AC1, AC2,
AC3, AD1, AD2,
AD3
Frame Bank B– Data Bit [63:0]
N3, N2, N1, P3,
P2, P1, R5, R4,
R3, R2, R1, T5,
T4, T3, T2, T1,
W3, W2
LB_A[20:3]
LB_ADSC#
Output
Frame Bank B – Address Bit
[20:3]
V1
Output with pull up
Frame Bank B Address Status
Control
G1
V3
LB_CLK
LB_WE#
Output with pull up
Output with pull up
Frame Bank B Clock Input
Frame Bank B Write Chip
Select for one layer SRAM
application
135
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
LB_WE0#
I/O
Description
P4
P5
V2
U1
U2
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Frame Bank B Write Chip
Select for lower layer of two
layers SRAM application
LB_WE1#
LB_OE#
Frame Bank B Write Chip
Select for upper layer of two
layers SRAM application
Frame Bank B Read Chip
Select for one layer SRAM
application
LB_OE0#
LB_OE1#
Frame Bank B Read Chip
Select for lower layer of two
layers SRAM application
Frame Bank B Read Chip
Select for upper layer of two
layers SRAM application
Fast Ethernet Access Ports [23:0] RMII
R28
P28
R29
M_MDC
Output
MII Management Data Clock –
(Common for all MII Ports
[23:0])
M_MDIO
I/O-TS with pull up
MII Management Data I/O –
(Common for all MII Ports –
[23:0])
M_CLKI
Input
Reference Input Clock
AC29, AE28,
AJ27, AF27,
AJ25, AF24,
AH23, AE19,
AF21, AJ19,
AF18, AJ17,
AJ15, AF15,
AJ13, AF12,
AJ11, AJ9, AF9,
AJ7, AF6, AJ5,
AJ3, AF1
M[23:0]_RXD[1]
Input with weak internal
pull up resistors.
Ports [23:0] – Receive Data Bit
[1]
AC28, AF28,
AH27, AE27,
AH25, AE24,
AF22, AF20,
AE21, AH19,
AH20, AH17,
AH15, AE15,
AH13, AE12,
AH11, AH9, AE9,
AH7, AE6, AH5,
AH2, AF2
M[23:0]_RXD[0]
Input with weak internal
pull up resistors
Ports [23:0] – Receive Data Bit
[0]
136
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
I/O
Description
AC27, AF29,
AG27, AF26,
AG25, AG23,
AF23, AG21,
AH21, AF19,
AF17, AG17,
AG15, AF14,
AG13, AF11,
AG11, AG9, AF8,
AG7, AF5, AG5,
AH3, AF3
M[23:0]_CRS_DV
Input with weak internal
pull down resistors.
Ports [23:0] – Carrier Sense
and Receive Data Valid
AD29, AG28,
AJ26, AE26,
AJ24, AE23,
AJ22, AJ20,
AE20, AJ18,
AJ21, AJ16,
AJ14, AE14,
AJ12, AE11,
AJ10, AJ8, AE8,
AJ6, AE5, AJ4,
AG1, AE1
M[23:0]_TXEN
M[23:0]_TXD[1]
M[23:0]_TXD[0]
I/O- TS with pull up ,
slew
Ports [23:0] – Transmit Enable
Strap option for RMII/GPSI
AD27, AH28,
AG26, AE25,
AG24, AE22,
AJ23, AG20,
AE18, AG18,
AE16, AG16,
AG14, AE13,
AG12, AE10,
AG10, AG8, AE7,
AG6, AE4, AG4,
AG3, AE3
Output, slew
Ports [23:0] – Transmit Data Bit
[1]
AD28, AG29,
AH26, AF25,
AH24, AG22,
AH22, AE17,
AG19, AH18,
AF16, AH16,
AH14, AF13,
AH12, AF10,
AH10, AH8, AF7,
AH6, AF4, AH4,
AG2, AE2
Output, slew
Ports [23:0] – Transmit Data Bit
[0]
137
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
I/O
Description
GMII/TBI GiGabit Ethernet Access Ports 0 & 1
U26, U25, V26,
V25, W26, W25,
Y27, Y26, AA26,
AA25, AB26,
AB25, AC26,
AC25, AD26,
AD25
M25_TXD[15:0]
Output
Transmit Data Bit [15:0]
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
T28
U28
R25
U29
T29
M25_RX_DV
M25_RX_ER
M25_CRS
Input w/ pulldown
Input w/ pullup
Input w/ pulldown
Input w/ pullup
Input w/ pullup
Input w/ pullup
Receive Data Valid
Receive Error
Carrier Sense
M25_COL
Collision Detected
Receive Clock
M25_RXCLK
M25_RXD[15:0]
U27, V29, V28,
V27, W29, W28,
W27, Y29, Y28,
Y25, AA29, AA28,
AA27, AB29,
Receive Data Bit [15:0]
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
AB28, AB27
T26
R26
T25
P29
M25_TX_EN
M25_TX_ER
M25_ TXCLK
GREF_CLK0
M26_TXD[15:0]
Output w/ pullup
Output w/ pullup
Output
Transmit Data Enable
Transmit Error
Gigabit Transmit Clock
Gigabit Reference Clock
Input w/ pullup
Output
G26, G25, H26,
H25, J26, J25,
K25, K26, M25,
L26, M26, L25,
N26, N25, P26,
P25
Transmit Data Bit [15:0]
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
F28
G28
E25
G29
F29
M26_RX_DV
M26_RX_ER
M26_CRS
Input w/ pulldown
Input w/ pullup
Input w/ pulldown
Input w/ pullup
Input w/ pullup
Input w/ pullup
Receive Data Valid
Receive Error
Carrier Sense
M26_COL
Collision Detected
Receive Clock
M26_RXCLK
M26_RXD[15:0]
G27,H29, H28,
H27, J29, J28,
J27, K29, K28,
K27, L29, L28,
L27, M29, M28,
M27
Receive Data Bit [15:0]
[7:0] - GMII
[9:0] - TBI
[15:0] - 2G
138
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
M26_TX_EN
I/O
Description
F26
E26
F25
Output w/ pullup
Output w/ pullup
Output
Transmit Data Enable
Transmit Error
M26_TX_ER
M26_ TXCLK
GREF_CLK1
Gigabit Transmit Clock
Gigabit Reference Clock
N29
Input w/ pullup
LED Interface
C29
LED_CLK/TSTOUT0
LED_SYN/TSTOUT1
I/O- TS with pull up
I/O- TS with pull up
LED Serial Interface Output
Clock
D29
LED Output Data Stream
Envelope
E29
B28
LED_BIT/TSTOUT2
I/O- TS with pull up
I/O- TS with pull up
LED Serial Data Output Stream
G1_RXTX#/TSTOUT3
LED for Gigabit port 1 (receive
+ transmit)
C28
G1_DPCOL#/TSTOUT4
I/O- TS with pull up
LED for Gigabit port 1 (full
duplex + collision)
D28
E28
G1_LINK#/TSTOUT5
G2_RXTX#/TSTOUT6
I/O- TS with pull up
I/O- TS with pull up
LED for Gigabit port 1
LED for Gigabit port 2 (receive
+ transmit)
A27
G2_DPCOL#/TSTOUT7
I/O- TS with pull up
LED for Gigabit port 2 (full
duplex + collision)
B27
C27
D27
C26
G2_LINK#/TSTOUT8
INIT_DONE/TSTOUT9
INIT_START/TSTOUT10
I/O- TS with pull up
I/O- TS with pull up
I/O- TS with pull up
I/O- TS with pull up
LED for Gigabit port 2
System start operation
Start initialization
CHECKSUM_OK/TSTOU
T11
EEPROM read OK
D26
FCB_ERR/TSTOUT12
MCT_ERR/TSTOUT13
I/O- TS with pull up
I/O- TS with pull up
FCB memory self test fail
MCT memory self test fail
Processing memory self test
Memory self test done
D25
D24
BIST_IN_PRC/TSTOUT14 I/O- TS with pull up
E24
BIST_DONE/TSTOUT15
I/O- TS with pull up
Trunk Enabale
C22
TRUNK0
Input w/ weak internal
pull down resistors
Trunk Port Enable in
unmanaged mode
In managed mode doesn't care
A21
B24
TRUNK1
TRUNK2
Input w/ weak internal
pull down resistors
Trunk Port Enable in
unmanaged mode
In managed mode doesn't care
Input w/ weak internal
pull down resistors
Trunk Port Enable in
unmanaged mode
In managed mode doesn't care
139
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
I/O
Description
Test Facility
U3, C10
T_MODE0, T_MODE1
I/O-TS
Test Pins
00 – Test mode – Set Mode
upon Reset, and provides
NAND Tree test output during
test mode
01 - Reserved - Do not use
10 - Reserved - Do not use
11 – Normal mode. Use
external pull up for normal
mode
F3
SCAN_EN
Input with pull down
Input with pull down
Scan Enable
0 - Normal mode (open)
E27
SCANMODE
1 – Enable Test mode
0 - Normal mode (open)
System Clock, Power, and Ground Pins
E1
SCLK
VDD
Input
System Clock at 100 MHz
+2.5 Volt DC Supply
K12, K13,
Power
K17,K18 M10,
N10, M20, N20,
U10, V10, U20,
V20, Y12, Y13,
Y17, Y18
F13, F14, F15,
F16, F17, N6, P6,
R6, T6, U6, N24,
P24, R24, T24,
U24, AD13,
VCC
VSS
Power
+3.3 Volt DC Supply
AD14, AD15,
AD16, AD17
M12, M13, M14,
M15, M16, M17,
M18, N12, N13,
N14, N15, N16,
N17, N18, P12,
P13, P14, P15,
P16, P17, P18,
R12, R13, R14,
R15, R16, R17,
R18, T12, T13,
T14, T15, T16,
T17, T18, U12,
U13, U14, U15,
U16, U17, U18,
V12, V13, V14,
V15, V16, V17,
V18,
Power Ground
Ground
140
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
I/O
Description
F1
D1
AVCC
AGND
Analog Power
Analog Ground
Analog +2.5 Volt DC Supply
Analog Ground
MISC
D22
SCANCOL
SCANCLK
Input
Scans the Collision signal of
Home PHY
D23
Input/ output
Clock for scanning Home PHY
collision and link
E23
SCANLINK
RESIN#
Input
Input
Output
N/A
Link up signal from Home PHY
Reset Input
F2
G2
RESETOUT#
RESERVED
Reset PHY
E20, B25
Reserved Pins. Leave
unconnected.
Bootstrap Pins (Default = pull up, 1= pull up 0= pull down)
After reset TSTOUT0 to TSTOU15 are used by the LED interface.
C29
D29
TSTOUT0
TSTOUT1
Default 1
Default 1
GIGA Link polarity
0 – active low
1 – active high
RMII MAC Power Saving
Enable
0 – No power saving
1 – power saving
E29
B28
TSTOUT2
TSTOUT3
Reserved
Default 1
Default 1
Default 1
Default 1
Default 1
Module detect enable
0 – Hot swap enable
1 – Hot swap disable
C28
D28
E28
A27
TSTOUT4
TSTOUT5
TSTOUT6
TSTOUT7
Memory is SBRAM/ZBT
0 – ZBT
1 – Pipeline SBRAM
Scan Speed: ¼ SCLK or SCLK
0 – ¼ SCLK (HPNA)
1 - SCLK
CPU Port Mode
0 - 8 bit Bus Mode
1 - 16 bit Bus Mode
Memory Size
0 - 256 K x 32 or 256 K x 64
(4 M total)
1 - 128 K x 32 or 128 K x 64
(2 M total)
141
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
B27
Symbol
TSTOUT8
I/O
Description
Default 1
Default 1
Default 1
Default 1
EEPROM Installed
0 – EEPROM installed
1 – EEPROM not installed
C27
D27
C26
TSTOUT9
TSTOUT10
TSTOUT11
MCT Aging
0 – MCT aging disable
1 – MCT aging enable
FCB Aging
0 - FCB aging disable
1 – FCB aging enable
Timeout Reset
0 – Time out reset disable
1 – Time out reset enable. Issue
reset if any state machine did
not go back to idle for 5sec.
D26
D25
TSTOUT12
TSTOUT13
Reserved
Default 1
FDB RAM depth (1 or 2 layers)
0 – 2 layer
1 – 1 layer
D24
TSTOUT14
Default 1
CPU installed
0 – CPU installed
1 – CPU not installed
E24
TSTOUT15
Default 1
SRAM Test Mode
0 – Enable test mode
1 – Normal operation
T26, R26
G0_TXEN, G0_TXER
Default: PCS
Giga0
Mode: G0_TXEN G0_TXER
0
0
1
1
0
1
0
1
MII
2G
GMII
PCS
F26, E26
G1_TXEN, G1_TXER
Default: PCS
Giga1
Mode: G1_TXEN G1_TXER
0
0
1
1
0
1
0
1
MII
2G
GMII
PCS
142
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No(s)
Symbol
M[23:0]_TXEN
I/O
Description
AD29, AG28,
AJ26, AE26,
AJ24, AE23,
AJ22, AJ20,
AE20, AJ18,
AJ21, AJ16,
AJ14, AE14,
AJ12, AE11,
AJ10, AJ8, AE8,
AJ6, AE5, AJ4,
AG1, AE1,
Default: RMII
0 – GPSI
1 - RMII
C21
P_D
Must be pulled-down
Default: 111
Reserved. Must be pulled-
down.
C19, B19, A19
OE_CLK[2:0]
Programmable delay for internal
OE_CLK from SCLK input. The
OE_CLK is used for generating
the OE0 and OE1 signals
Suggested value is 001.
C20, B20, A20
LA_CLK[2:0]
MIRROR[5:0]
Default: 111
Programmable delay for
LA_CLK and LB_CLK from
internal OE_CLK. The LA_CLK
and LB_CLK delay from SCLK
is the sum of the delay
programmed in here and the
delay in P_D[15:13].
Suggested value is 011.
B22, A22,
C23, B23,
A23, C24
Default: 111111
Dedicated Port Mirror Mode.
The first 5 bits select the port to
be mirrored. The last bit selects
either ingress or egress data.
Note:
# = Active low signal
Input = Input signal
In-ST = Input signal with Schmitt-Trigger
Output = Output signal (Tri-State driver)
Out-OD = Output signal with Open-Drain driver
I/O-TS = Input & Output signal with Tri-State driver
I/O-OD = Input & Output signal with Open-Drain driver
143
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.3 Ball – Signal Name in Unmanaged Mode
Ball No.
Signal Name
LA_D[63]
Ball No.
D3
Signal Name
Ball No.
Signal Name
LA_OE0#
D20
B21
D19
E19
D18
E18
D17
E17
D16
E16
D15
E15
D14
E14
D13
E13
D21
E21
A18
B18
C18
A17
B17
C17
A16
B16
C16
A15
B15
C15
LA_D[19]
LA_D[18]
LA_D[17]
LA_D[16]
LA_D[15]
LA_D[14]
LA_D[13]
LA_D[12]
LA_D[11]
LA_D[10]
LA_D[9]
LA_D[8]
LA_D[7]
LA_D[6]
LA_D[5]
LA_D[4]
LA_D[3]
LA_D[2]
LA_D[1]
LA_D[0]
LA_A[20]
LA_A[19]
LA_A[18]
LA_A[17]
LA_A[16]
LA_A[15]
LA_A[14]
LA_A[13]
LA_A[12]
LA_A[11]
A9
B9
F4
F5
G4
G5
H4
H5
J4
LA_D[62]
LA_D[61]
LA_D[60]
LA_D[59]
LA_D[58]
LA_D[57]
LA_D[56]
LA_D[55]
LA_D[54]
LA_D[53]
LA_D[52]
LA_D[51]
LA_D[50]
LA_D[49]
LA_D[48]
LA_D[47]
LA_D[46]
LA_D[45]
LA_D[44]
LA_D[43]
LA_D[42]
LA_D[41]
LA_D[40]
LA_D[39]
LA_D[38]
LA_D[37]
LA_D[36]
LA_D[35]
LA_D[34]
E3
LA_OE1#
LB_D[63]
LB_D[62]
LB_D[61]
LB_D[60]
LB_D[59]
LB_D[58]
LB_D[57]
LB_D[56]
LB_D[55]
LB_D[54]
LB_D[53]
LB_D[52]
LB_D[51]
LB_D[50]
LB_D[49]
LB_D[48]
LB_D[47]
LB_D[46]
LB_D[45]
LB_D[44]
LB_D[43]
LB_D[42]
LB_D[41]
LB_D[40]
LB_D[39]
LB_D[38]
LB_D[37]
LB_D[36]
D2
E2
A7
B7
A6
B6
C6
A5
J5
B5
K4
K5
L4
L5
M4
M5
N4
N5
G3
H1
H2
H3
J1
C5
A4
B4
C4
A3
B3
C3
B2
C2
C14
A13
B13
C13
A12
B12
C12
A11
B11
C11
J2
J3
K1
K2
K3
L1
L2
144
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
LA_D[33]
Ball No.
Signal Name
Ball No.
Signal Name
LB_D[35]
A14
B14
D9
D11
E11
LA_A[10]
L3
LA_D[32]
LA_D[31]
LA_D[30]
LA_D[29]
LA_D[28]
LA_D[27]
LA_D[26]
LA_D[25]
LA_D[24]
LA_D[23]
LA_D[22]
LA_D[21]
LA_D[20]
LB_D[21]
LB_D[20]
LB_D[19]
LB_D[18]
LB_D[17]
LB_D[16]
LB_D[15]
LB_D[14]
LB_D[13]
LB_D[12]
LB_D[11]
LB_D[10]
LB_D[9]
LA_A[9]
M1
LB_D[34]
LB_D[33]
A10
B10
D10
E10
A8
LA_A[8]
M2
E9
LA_A[7]
M3
LB_D[32]
D8
LA_A[6]
U4
LB_D[31]
E8
LA_A[5]
U5
LB_D[30]
D7
LA_A[4]
V4
LB_D[29]
E7
C7
LA_A[3]
V5
LB_D[28]
D6
B8
LA_DSC#
LA_CLK
W4
LB_D[27]
E6
C1
W5
LB_D[26]
D5
C9
LA_WE#
Y4
LB_D[25]
E5
D12
E12
C8
LA_WE0#
LA_WE1#
LA_OE#
Y5
LB_D[24]
D4
AA4
AA5
AH7
AE6
AH5
AH2
AF2
AC27
AF29
AG27
AF26
AG25
AG23
AF23
AG21
AH21
AF19
AF17
AG17
LB_D[23]
E4
LB_D[22]
AB4
AB5
AC4
AC5
AD4
AD5
W1
Y1
U2
LB_OE1#
M[4]_RXD[0]
M[3]_RXD[0]
M[2]_RXD[0]
M[1]_RXD[0]
M[0]_RXD[0]
R28
P28
R29
AC29
AE28
AJ27
AF27
AJ25
AF24
AH23
AE19
AF21
AJ19
AF18
AJ17
AJ15
MDC
MDIO
M_CLK
M[23]_RXD[1]
M[22]_RXD[1]
M[21]_RXD[1]
M[20]_RXD[1]
M[19]_RXD[1]
M[18]_RXD[1]
M[17]_RXD[1]
M[16]_RXD[1]
M[15]_RXD[1]
M[14]_RXD[1]
M[13]_RXD[1]
M[12]_RXD[1]
M[11]_RXD[1]
M[23]_CRS_DV
M[22]_CRS_DV
M[21]_CRS_DV
M[20]_CRS_DV
M[19]_CRS_DV
M[18]_CRS_DV
M[17]_CRS_DV
M[16]_CRS_DV
M[15]_CRS_DV
M[14]_CRS_DV
M[13]_CRS_DV
M[12]_CRS_DV
Y2
Y3
AA1
AA2
AA3
AB1
AB2
AB3
AC1
LB_D[8]
LB_D[7]
LB_D[6]
LB_D[5]
145
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
LB_D[4]
Ball No.
Signal Name
Ball No.
Signal Name
AC2
AC3
AD1
AD2
AD3
N3
N2
N1
P3
AF15
AJ13
AF12
AJ11
AJ9
M[10]_RXD[1]
M[9]_RXD[1]
M[8]_RXD[1]
M[7]_RXD[1]
M[6]_RXD[1]
M[5]_RXD[1]
M[4]_RXD[1]
M[3]_RXD[1]
M[2]_RXD[1]
M[1]_RXD[1]
M[0]_RXD[1]
M[23]_RXD[0]
M[22]_RXD[0]
M[21]_RXD[0]
M[20]_RXD[0]
M[19]_RXD[0]
M[18]_RXD[0]
M[17]_RXD[0]
M[16]_RXD[0]
M[15]_RXD[0]
M[14]_RXD[0]
M[13]_RXD[0]
M[12]_RXD[0]
M[11]_RXD[0]
M[10]_RXD[0]
M[9]_RXD[0]
M[8]_RXD[0]
M[7]_RXD[0]
M[6]_RXD[0]
M[5]_RXD[0]
M[6]_TXD[0]
AG15
AF14
AG13
AF11
AG11
AG9
M[11]_CRS_DV
M[10]_CRS_DV
M[9]_CRS_DV
M[8]_CRS_DV
M[7]_CRS_DV
M[6]_CRS_DV
M[5]_CRS_DV
M[4]_CRS_DV
M[3]_CRS_DV
M[2]_CRS_DV
M[1]_CRS_DV
M[0]_CRS_DV
M[23]_TXEN
M[22]_TXEN
M[21]_TXEN
M[20]_TXEN
M[19]_TXEN
M[18]_TXEN
M[17]_TXEN
M[16]_TXEN
M[15]_TXEN
M[14]_TXEN
M[13]_TXEN
M[12]_TXEN
M[11]_TXEN
M[10]_TXEN
M[9]_TXEN
LB_D[3]
LB_D[2]
LB_D[1]
LB_D[0]
LB_A[20]
LB_A[19]
LB_A[18]
LB_A[17]
LB_A[16]
LB_A[15]
LB_A[14]
LB_A[13]
LB_A[12]
LB_A[11]
LB_A[10]
LB_A[9]
AF9
AJ7
AF8
AF6
AG7
AJ5
AF5
P2
AJ3
AG5
P1
AF1
AH3
R5
R4
R3
R2
R1
T5
AC28
AF28
AH27
AE27
AH25
AE24
AF22
AF20
AE21
AH19
AH20
AH17
AH15
AE15
AH13
AE12
AH11
AH9
AF3
AD29
AG28
AJ26
AE26
AJ24
AE23
AJ22
AJ20
AE20
AJ18
AJ21
AJ16
AJ14
AE14
AJ12
AE11
AJ10
AJ8
T4
LB_A[8]
T3
LB_A[7]
T2
LB_A[6]
T1
LB_A[5]
W3
W2
V1
LB_A[4]
LB_A[3]
LB_ADSC#
LB_CLK
LB_WE#
LB_WE0#
LB_WE1#
LB_OE#
LB_OE0#
M[5]_TXEN
G1
V3
P4
P5
M[8]_TXEN
V2
M[7]_TXEN
U1
AE8
AE9
M[6]_TXEN
AH8
G27
M26_RXD[15]
146
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
M[4]_TXEN
Ball No.
Signal Name
Ball No.
Signal Name
AJ6
AF7
M[5]_TXD[0]
M[4]_TXD[0]
M[3]_TXD[0]
M[2]_TXD[0]
M[1]_TXD[0]
M[0]_TXD[0]
M25_TXD[15]
M25_TXD[14]
M25_TXD[13]
M25_TXD[12]
M25_TXD[11]
M25_TXD[10]
M25_TXD[9]
M25_TXD[8]
M25_TXD[7]
M25_TXD[6]
M25_TXD[5]
M25_TXD[4]
M25_TXD[3]
M25_TXD[2]
M25_TXD[1]
M25_TXD[0]
M25_RXD[15]
M25_RXD[14]
M25_RXD[13]
M25_RXD[12]
M25_RXD[11]
M25_RXD[10]
M25_RXD[9]
M25_RXD[8]
M25_RXD[7]
H29
H28
H27
J29
M26_RXD[14]
M26_RXD[13]
M26_RXD[12]
M26_RXD[11]
M26_RXD[10]
M26_RXD[9]
M26_RXD[8]
M26_RXD[7]
M26_RXD[6]
M26_RXD[5]
M26_RXD[4]
M26_RXD[3]
M26_RXD[2]
M26_RXD[1]
M26_RXD[0]
M26_TXD[15]
M26_TXD[14]
M26_TXD[13]
M26_TXD[12]
M26_TXD[11]
M26_TXD[10]
M26_TXD[9]
M26_TXD[8]
M26_TXD[7]
M26_TXD[6]
M26_TXD[5]
M26_TXD[4]
M26_TXD[3]
M26_TXD[2]
M26_TXD[1]
M26_TXD[0]
AE5
M[3]_TXEN
AH6
AF4
AJ4
M[2]_TXEN
AG1
M[1]_TXEN
AH4
AG2
AE2
U26
AE1
M[0]_TXEN
J28
AD27
AH28
AG26
AE25
AG24
AE22
AJ23
AG20
AE18
AG18
AE16
AG16
AG14
AE13
AG12
AE10
AG10
AG8
M[23]_TXD[1]
M[22]_TXD[1]
M[21]_TXD[1]
M[20]_TXD[1]
M[19]_TXD[1]
M[18]_TXD[1]
M[17]_TXD[1]
M[16]_TXD[1]
M[15]_TXD[1]
M[14]_TXD[1]
M[13]_TXD[1]
M[12]_TXD[1]
M[11]_TXD[1]
M[10]_TXD[1]
M[9]_TXD[1]
M[8]_TXD[1]
M[7]_TXD[1]
M[6]_TXD[1]
M[5]_TXD[1]
M[4]_TXD[1]
M[3]_TXD[1]
M[2]_TXD[1]
M[1]_TXD[1]
M[0]_TXD[1]
M[23]_TXD[0]
M[22]_TXD[0]
J27
K29
K28
K27
L29
L28
L27
M29
M28
M27
G26
G25
H26
H25
J26
U25
V26
V25
W26
W25
Y27
Y26
AA26
AA25
AB26
AB25
AC26
AC25
AD26
AD25
U27
J25
K25
K26
M25
L26
M26
L25
N26
N25
P26
P25
AE7
V29
AG6
V28
AE4
V27
AG4
W29
W28
W27
Y29
AG3
AE3
AD28
AG29
Y28
147
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
M[21]_TXD[0]
Ball No.
Signal Name
Ball No.
Signal Name
M26_RX_DV
AH26
AF25
AH24
AG22
AH22
AE17
AG19
AH18
AF16
Y25
M25_RXD[6]
M25_RXD[5]
M25_RXD[4]
M25_RXD[3]
M25_RXD[2]
M25_RXD[1]
M25_RXD[0]
M25_TX_ER
M25_TXCLK
F28
G28
E25
G29
F29
F26
E26
F25
E24
M[20]_TXD[0]
M[19]_TXD[0]
M[18]_TXD[0]
M[17]_TXD[0]
M[16]_TXD[0]
M[15]_TXD[0]
M[14]_TXD[0]
M[13]_TXD[0]
AA29
AA28
AA27
AB29
AB28
AB27
R26
M26_RX_ER
M26_CRS
M26_COL
M26_RXCLK
M26_TX_EN
M26_TX_ER
M26_TXCLK
T25
BIST_DONE/TSTO
UT[15]
AH16
AH14
AF13
AH12
AF10
AH10
M[12]_TXD[0]
M[11]_TXD[0]
M[10]_TXD[0]
M[9]_TXD[0]
M[8]_TXD[0]
M[7]_TXD[0]
T26
T28
U28
R25
U29
T29
M25_TX_EN
M25_RX_DV
M25_RX_ER
M25_CRS
D24
D25
D26
C26
D27
C27
BIST_IN_PRC/TST0
UT[14]
MCT_ERR/TSTOUT
[13]
FCB_ERR/TSTOUT[
12]
CHECKSUM_OK/TS
TOUT[11]
M25_COL
INIT_START/TSTOU
T[10]
M25_RXCLK
INIT_DONE/TSTOU
T[9]
B27
A27
G2_LINK#/TSTOUT[8] U18
VSS
VSS
N12
N13
VSS
VSS
G2_DPCOL#/TSTOUT V12
[7]
E28
G2_RXTX#/TSTOUT[
6]
V13
VSS
K17
VDD
D28
C28
G1_LINK#/TSTOUT[5] V14
VSS
VSS
K18
M10
VDD
VDD
G1_DPCOL#/TSTOUT V15
[4]
B28
G1_RXTX#/TSTOUT[
3]
V16
VSS
N10
VDD
E29
D29
C29
N29
LED_BIT/TSTOUT[2]
V17
VSS
VSS
VSS
VSS
M20
N20
U10
V10
VDD
VDD
VDD
VDD
LED_SYN/TSTOUT[1] V18
LED_CLK/TSTOUT[0]
GREF_CLK1
N14
N15
148
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
GREF_CLK0
Ball No.
Signal Name
Ball No.
Signal Name
VDD
P29
F3
N16
N17
N18
P12
P13
P14
P15
P16
C19
B19
A19
R13
R14
R15
R16
R17
R18
T12
T13
T14
T15
T16
T17
T18
U12
U13
U14
U15
U16
U17
M12
VSS
U20
V20
Y12
Y13
Y17
Y18
K12
K13
M16
M17
M18
F16
F17
N6
SCAN_EN
SCLK
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E1
VSS
U3
T_MODE0
T_MODE1
TRUNK2
TRUNK1
TRUNK0
STROBE
D0
VSS
C10
B24
A21
C22
A26
B26
C25
A24
A25
F1
VSS
VSS
VSS
VSS
OE_CLK2
OE_CLK1
OE_CLK0
VSS
AUTOFD
SCL
SDA
VSS
AVCC
VSS
D1
AGND
VSS
P6
D22
E23
E27
N28
N27
F2
SCANCOL
SCANLINK
SCANMODE
VSS
R6
VSS
T6
VSS
U6
VSS
N24
P24
R24
T24
U24
AD13
AD14
AD15
AD16
AD17
F13
F14
F15
VSS
RESIN#
VSS
G2
RESETOUT#
MIRROR5
MIRROR4
MIRROR3
MIRROR2
MIRROR1
MIRROR0
SCANCLK
M25_MTXCLK
M26_MTXCLK
VSS
B22
A22
C23
B23
A23
C24
D23
T27
F27
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
149
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
LA_CLK2
Ball No.
Signal Name
Ball No.
Signal Name
C20
B20
A20
C21
E20
B25
M13
M14
M15
P17
P18
R12
VSS
VSS
VSS
VSS
VSS
VSS
LA_CLK1
LA_CLK0
P_D
RESERVED
RESERVED
15.4 Ball – Signal Name in Managed Mode
Ball No.
Signal Name
LA_D[63]
Ball No.
Signal Name
Ball No.
A9
Signal Name
LA_OE0#
D20
B21
D19
E19
D18
E18
D17
E17
D16
E16
D15
E15
D14
E14
D13
E13
D21
E21
A18
B18
C18
A17
D3
E3
D2
E2
A7
B7
A6
B6
C6
A5
B5
C5
A4
B4
C4
A3
B3
C3
B2
C2
C14
A13
LA_D[19]
LA_D[18]
LA_D[17]
LA_D[16]
LA_D[15]
LA_D[14]
LA_D[13]
LA_D[12]
LA_D[11]
LA_D[10]
LA_D[9]
LA_D[8]
LA_D[7]
LA_D[6]
LA_D[5]
LA_D[4]
LA_D[3]
LA_D[2]
LA_D[1]
LA_D[0]
LA_A[20]
LA_A[19]
LA_D[62]
LA_D[61]
LA_D[60]
LA_D[59]
LA_D[58]
LA_D[57]
LA_D[56]
LA_D[55]
LA_D[54]
LA_D[53]
LA_D[52]
LA_D[51]
LA_D[50]
LA_D[49]
LA_D[48]
LA_D[47]
LA_D[46]
LA_D[45]
LA_D[44]
LA_D[43]
LA_D[42]
B9
F4
F5
G4
G5
H4
H5
J4
LA_OE1#
LB_D[63]
LB_D[62]
LB_D[61]
LB_D[60]
LB_D[59]
LB_D[58]
LB_D[57]
LB_D[56]
LB_D[55]
LB_D[54]
LB_D[53]
LB_D[52]
LB_D[51]
LB_D[50]
LB_D[49]
LB_D[48]
LB_D[47]
LB_D[46]
LB_D[45]
LB_D[44]
J5
K4
K5
L4
L5
M4
M5
N4
N5
G3
H1
H2
H3
150
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
LA_D[41]
Ball No.
Signal Name
Ball No.
J1
Signal Name
LB_D[43]
B17
C17
A16
B16
C16
A15
B15
C15
A14
B14
D9
B13
C13
A12
B12
C12
A11
B11
C11
D11
E11
A10
B10
D10
E10
A8
LA_A[18]
LA_A[17]
LA_A[16]
LA_A[15]
LA_A[14]
LA_A[13]
LA_A[12]
LA_A[11]
LA_A[10]
LA_A[9]
LA_D[40]
LA_D[39]
LA_D[38]
LA_D[37]
LA_D[36]
LA_D[35]
LA_D[34]
LA_D[33]
LA_D[32]
LA_D[31]
LA_D[30]
LA_D[29]
LA_D[28]
LA_D[27]
LA_D[26]
LA_D[25]
LA_D[24]
LA_D[23]
LA_D[22]
LA_D[21]
LA_D[20]
LB_D[21]
LB_D[20]
LB_D[19]
LB_D[18]
LB_D[17]
LB_D[16]
LB_D[15]
LB_D[14]
LB_D[13]
J2
LB_D[42]
LB_D[41]
LB_D[40]
LB_D[39]
LB_D[38]
LB_D[37]
LB_D[36]
LB_D[35]
LB_D[34]
LB_D[33]
LB_D[32]
LB_D[31]
LB_D[30]
LB_D[29]
LB_D[28]
LB_D[27]
LB_D[26]
LB_D[25]
LB_D[24]
LB_D[23]
LB_D[22]
M[4]_RXD[0]
M[3]_RXD[0]
M[2]_RXD[0]
M[1]_RXD[0]
M[0]_RXD[0]
J3
K1
K2
K3
L1
L2
L3
M1
LA_A[8]
M2
E9
LA_A[7]
M3
D8
LA_A[6]
U4
E8
LA_A[5]
U5
D7
LA_A[4]
V4
E7
C7
LA_A[3]
V5
D6
B8
LA_DSC#
LA_CLK
W4
W5
Y4
E6
C1
D5
C9
LA_WE#
LA_WE0#
LA_WE1#
LA_OE#
E5
D12
E12
C8
Y5
D4
AA4
AA5
AH7
AE6
AH5
AH2
AF2
AC27
AF29
AG27
AF26
E4
AB4
AB5
AC4
AC5
AD4
AD5
W1
Y1
U2
LB_OE1#
MDC
R28
P28
R29
AC29
AE28
AJ27
AF27
AJ25
MDIO
M_CLK
M[23]_RXD[1]
M[22]_RXD[1]
M[21]_RXD[1]
M[20]_RXD[1]
M[19]_RXD[1]
M[23]_CRS_DV
M[22]_CRS_DV
M[21]_CRS_DV
M[20]_CRS_DV
Y2
151
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
LB_D[12]
Ball No.
Signal Name
Ball No.
Signal Name
M[19]_CRS_DV
Y3
AF24
AH23
AE19
AF21
AJ19
AF18
AJ17
AJ15
AF15
AJ13
AF12
AJ11
AJ9
M[18]_RXD[1]
M[17]_RXD[1]
M[16]_RXD[1]
M[15]_RXD[1]
M[14]_RXD[1]
M[13]_RXD[1]
M[12]_RXD[1]
M[11]_RXD[1]
M[10]_RXD[1]
M[9]_RXD[1]
M[8]_RXD[1]
M[7]_RXD[1]
M[6]_RXD[1]
M[5]_RXD[1]
M[4]_RXD[1]
M[3]_RXD[1]
M[2]_RXD[1]
M[1]_RXD[1]
M[0]_RXD[1]
M[23]_RXD[0]
M[22]_RXD[0]
M[21]_RXD[0]
M[20]_RXD[0]
M[19]_RXD[0]
M[18]_RXD[0]
M[17]_RXD[0]
M[16]_RXD[0]
M[15]_RXD[0]
M[14]_RXD[0]
M[13]_RXD[0]
M[12]_RXD[0]
AG25
AG23
AF23
AG21
AH21
AF19
AF17
AG17
AG15
AF14
AG13
AF11
AG11
AG9
AA1
AA2
AA3
AB1
AB2
AB3
AC1
AC2
AC3
AD1
AD2
AD3
N3
LB_D[11]
LB_D[10]
LB_D[9]
LB_D[8]
LB_D[7]
LB_D[6]
LB_D[5]
LB_D[4]
LB_D[3]
LB_D[2]
LB_D[1]
LB_D[0]
LB_A[20]
LB_A[19]
LB_A[18]
LB_A[17]
LB_A[16]
LB_A[15]
LB_A[14]
LB_A[13]
LB_A[12]
LB_A[11]
LB_A[10]
LB_A[9]
LB_A[8]
LB_A[7]
LB_A[6]
LB_A[5]
LB_A[4]
LB_A[3]
M[18]_CRS_DV
M[17]_CRS_DV
M[16]_CRS_DV
M[15]_CRS_DV
M[14]_CRS_DV
M[13]_CRS_DV
M[12]_CRS_DV
M[11]_CRS_DV
M[10]_CRS_DV
M[9]_CRS_DV
M[8]_CRS_DV
M[7]_CRS_DV
M[6]_CRS_DV
M[5]_CRS_DV
M[4]_CRS_DV
M[3]_CRS_DV
M[2]_CRS_DV
M[1]_CRS_DV
M[0]_CRS_DV
M[23]_TXEN
AF9
N2
AJ7
AF8
N1
AF6
AG7
P3
AJ5
AF5
P2
AJ3
AG5
P1
AF1
AH3
R5
AC28
AF28
AH27
AE27
AH25
AE24
AF22
AF20
AE21
AH19
AH20
AH17
AF3
R4
AD29
AG28
AJ26
AE26
AJ24
AE23
AJ22
AJ20
AE20
AJ18
AJ21
R3
M[22]_TXEN
R2
M[21]_TXEN
R1
M[20]_TXEN
T5
M[19]_TXEN
T4
M[18]_TXEN
T3
M[17]_TXEN
T2
M[16]_TXEN
T1
M[15]_TXEN
W3
W2
M[14]_TXEN
M[13]_TXEN
152
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
LB_ADSC#
Ball No.
Signal Name
Ball No.
Signal Name
M[12]_TXEN
V1
AH15
AE15
AH13
AE12
AH11
AH9
AE9
M[11]_RXD[0]
M[10]_RXD[0]
M[9]_RXD[0]
M[8]_RXD[0]
M[7]_RXD[0]
M[6]_RXD[0]
M[5]_RXD[0]
M[6]_TXD[0]
M[5]_TXD[0]
M[4]_TXD[0]
M[3]_TXD[0]
M[2]_TXD[0]
M[1]_TXD[0]
M[0]_TXD[0]
M25_TXD[15]
M25_TXD[14]
M25_TXD[13]
M25_TXD[12]
M25_TXD[11]
M25_TXD[10]
M25_TXD[9]
M25_TXD[8]
M25_TXD[7]
M25_TXD[6]
M25_TXD[5]
M25_TXD[4]
M25_TXD[3]
M25_TXD[2]
M25_TXD[1]
M25_TXD[0]
M25_RXD[15]
AJ16
AJ14
AE14
AJ12
AE11
AJ10
AJ8
G27
H29
H28
H27
J29
G1
LB_CLK
M[11]_TXEN
M[10]_TXEN
M[9]_TXEN
V3
LB_WE#
P4
LB_WE0#
P5
LB_WE1#
M[8]_TXEN
V2
LB_OE#
M[7]_TXEN
U1
LB_OE0#
M[6]_TXEN
AE8
AJ6
M[5]_TXEN
M[4]_TXEN
M[3]_TXEN
M[2]_TXEN
M[1]_TXEN
M[0]_TXEN
M[23]_TXD[1]
M[22]_TXD[1]
M[21]_TXD[1]
M[20]_TXD[1]
M[19]_TXD[1]
M[18]_TXD[1]
M[17]_TXD[1]
M[16]_TXD[1]
M[15]_TXD[1]
M[14]_TXD[1]
M[13]_TXD[1]
M[12]_TXD[1]
M[11]_TXD[1]
M[10]_TXD[1]
M[9]_TXD[1]
M[8]_TXD[1]
M[7]_TXD[1]
M[6]_TXD[1]
AH8
AF7
M26_RXD[15]
M26_RXD[14]
M26_RXD[13]
M26_RXD[12]
M26_RXD[11]
M26_RXD[10]
M26_RXD[9]
M26_RXD[8]
M26_RXD[7]
M26_RXD[6]
M26_RXD[5]
M26_RXD[4]
M26_RXD[3]
M26_RXD[2]
M26_RXD[1]
M26_RXD[0]
M26_TXD[15]
M26_TXD[14]
M26_TXD[13]
M26_TXD[12]
M26_TXD[11]
M26_TXD[10]
M26_TXD[9]
M26_TXD[8]
AE5
AJ4
AH6
AF4
AG1
AE1
AD27
AH28
AG26
AE25
AG24
AE22
AJ23
AG20
AE18
AG18
AE16
AG16
AG14
AE13
AG12
AE10
AG10
AG8
AH4
AG2
AE2
J28
J27
U26
K29
K28
K27
L29
U25
V26
V25
W26
W25
Y27
L28
L27
M29
M28
M27
G26
G25
H26
H25
J26
Y26
AA26
AA25
AB26
AB25
AC26
AC25
AD26
AD25
U27
J25
K25
K26
153
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
M[5]_TXD[1]
Ball No.
Signal Name
Ball No.
Signal Name
M26_TXD[7]
AE7
V29
M25_RXD[14]
M25_RXD[13]
M25_RXD[12]
M25_RXD[11]
M25_RXD[10]
M25_RXD[9]
M25_RXD[8]
M25_RXD[7]
M25_RXD[6]
M25_RXD[5]
M25_RXD[4]
M25_RXD[3]
M25_RXD[2]
M25_RXD[1]
M25_RXD[0]
M25_TX_ER
M25_TXCLK
M25_TX_EN
M25
L26
M26
L25
N26
N25
P26
P25
F28
G28
E25
G29
F29
F26
E26
F25
E24
D24
AG6
M[4]_TXD[1]
M[3]_TXD[1]
M[2]_TXD[1]
M[1]_TXD[1]
M[0]_TXD[1]
M[23]_TXD[0]
M[22]_TXD[0]
M[21]_TXD[0]
M[20]_TXD[0]
M[19]_TXD[0]
M[18]_TXD[0]
M[17]_TXD[0]
M[16]_TXD[0]
M[15]_TXD[0]
M[14]_TXD[0]
M[13]_TXD[0]
M[12]_TXD[0]
V28
M26_TXD[6]
M26_TXD[5]
M26_TXD[4]
M26_TXD[3]
M26_TXD[2]
M26_TXD[1]
M26_TXD[0]
M26_RX_DV
M26_RX_ER
M26_CRS
AE4
V27
AG4
W29
W28
W27
Y29
AG3
AE3
AD28
AG29
AH26
AF25
AH24
AG22
AH22
AE17
AG19
AH18
AF16
AH16
Y28
Y25
AA29
AA28
AA27
AB29
AB28
AB27
R26
M26_COL
M26_RXCLK
M26_TX_EN
M26_TX_ER
M26_TXCLK
T25
BIST_DONE/TSTOUT[15]
T26
BIST_IN_PRC/TST0UT[1
4]
AH14
AF13
AH12
M[11]_TXD[0]
M[10]_TXD[0]
M[9]_TXD[0]
T28
U28
R25
M25_RX_DV
M25_RX_ER
M25_CRS
D25
D26
C26
MCT_ERR/TSTOUT[13]
FCB_ERR/TSTOUT[12]
CHECKSUM_OK/TSTOU
T[11]
AF10
AH10
B27
A27
E28
D28
C28
B28
E29
M[8]_TXD[0]
U29
T29
U18
V12
V13
V14
V15
V16
V17
M25_COL
M25_RXCLK
VSS
D27
C27
N12
N13
K17
K18
M10
N10
M20
INIT_START/TSTOUT[10]
M[7]_TXD[0]
INIT_DONE/TSTOUT[9]
G2_LINK#/TSTOUT[8]
G2_DPCOL#/TSTOUT[7]
G2_RXTX#/TSTOUT[6]
G1_LINK#/TSTOUT[5]
G1_DPCOL#/TSTOUT[4]
G1_RXTX#/TSTOUT[3]
LED_BIT/TSTOUT[2]
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
154
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
D29
C29
N29
P29
F3
LED_SYN/TSTOUT[1]
LED_CLK/TSTOUT[0]
GREF_CLK1
GREF_CLK0
SCAN_EN
SCLK
V18
N14
N15
C19
B19
A19
P12
P13
P14
P15
P16
N16
N17
N18
R13
R14
R15
R16
R17
R18
T12
T13
T14
T15
T16
T17
T18
U12
U13
U14
U15
VSS
N20
U10
V10
U20
V20
Y12
Y13
Y17
Y18
K12
K13
M16
M17
M18
F16
F17
N6
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
P_DATA15
P_DATA14
P_DATA13
VSS
E1
U3
T_MODE0
T_MODE1
P_DATA6
P_DATA7
P_A2
C10
B24
A21
C22
A26
B26
C25
A24
A25
F1
VSS
VSS
VSS
VSS
P_WE
VSS
P_RD
VSS
P_CS
VSS
P_A1
VSS
P_A0
VSS
AVCC
VSS
D1
AGND
VSS
P6
D22
E23
E27
N28
N27
F2
SCANCOL
SCANLINK
SCANMODE
VSS
R6
VSS
T6
VSS
U6
VSS
N24
P24
R24
T24
U24
AD13
AD14
AD15
AD16
AD17
VSS
RESIN#
VSS
G2
RESETOUT#
P_DATA5
P_DATA4
P_DATA3
P_DATA2
P_DATA1
P_DATA0
VSS
B22
A22
C23
B23
A23
C24
VSS
VSS
VSS
VSS
VSS
VSS
155
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
Ball No.
Signal Name
SCANCLK
Ball No.
Signal Name
Ball No.
Signal Name
D23
T27
F27
C20
B20
A20
C21
E20
B25
U16
U17
M12
M13
M14
M15
P17
P18
R12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F13
F14
F15
VCC
VCC
VCC
M25_MTXCLK
M26_MTXCLK
P_DATA12
P_DATA11
P_DATA10
P_DATA9
P_DATA8
P_INT
15.5 AC/DC Timing
15.5.1 Absolute Maximum Ratings
Storage Temperature
-65°C to +150°C
-40°C to +85°C
+125°C
Operating Temperature
Maximum Junction Temperature
Supply Voltage VCC with Respect to VSS
Supply Voltage VDD with Respect to VSS
Voltage on Input Pins
+3.0 V to +3.6 V
+2.38 V to +2.75 V
-0.5 V to (VCC + 3.3 V)
Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for
extended periods may affect device reliability. Functionality at or above these limits is not implied.
15.5.2 DC Electrical Characteristics
VCC = 3.0 V to 3.6 V (3.3v +/- 10%)T
VDD = 2.5 V +10% - 5%
= -40°C to +85°C
AMBIENT
156
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.5.3 Recommended Operating Conditions
Symbol
Parameter Description
Frequency of Operation
Min.
Typ.
100
Max.
Unit
f
I
I
MHz
mA
mA
V
osc
Supply Current – @ 100 MHz (VCC=3.3 V)
Supply Current – @ 100 MHz (VDD=2.5 V)
Output High Voltage (CMOS)
450
CC
DD
1500
V
V
V
V
2.4
2.0
OH
Output Low Voltage (CMOS)
0.4
V
OL
Input High Voltage (TTL 5 V tolerant)
Input Low Voltage (TTL 5 V tolerant)
VCC + 2.0
V
IH-TTL
IL-TTL
0.8
10
V
I
Input Leakage Current (0.1 V < V < VCC)
µA
IL
IN
(all pins except those with internal pull-up/pull-
down resistors)
I
Output Leakage Current (0.1 V < VOUT < VCC)
Input Capacitance
10
5
µA
OL
C
C
C
pF
IN
Output Capacitance
5
pF
OUT
I/O
I/O Capacitance
7
pF
θ
θ
θ
θ
θ
Thermal resistance with 0 air flow
Thermal resistance with 1 m/s air flow
Thermal resistance with 2 m/s air flow
Thermal resistance between junction and case
Thermal resistance between junction and board
11.2
10.2
8.9
3.1
6.6
C/W
C/W
C/W
C/W
C/W
ja
ja
ja
jc
jb
157
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.5.4 Typical Reset & Bootstrap Timing Diagram
RESIN#
RESETOUT#
Tri-Stated
R1
R3
Bootstrap Pins
Outputs
Inputs
Outputs
R2
Figure 16 - Typical Reset & Bootstrap Timing Diagram
Symbol
R1
Parameter
Min.
Typ.
Note:
Delay until RESETOUT# is tri-stated
10 ns
RESETOUT# state is then determined
by the external pull-up/down resistor
R2
R3
Bootstrap stabilization
1 µs
10 µs
Bootstrap pins sampled on rising
a
edge of RESIN#
RESETOUT# assertion
2 ms
Table 14 - Reset & Bootstrap Timing
a. The TSTOUT[8:0] pins will switch over to the LED interface functionality in 3 SCLK cycles after RESIN# goes high
158
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.5.5 Typical CPU Timing Diagram for a CPU Write Cycle
ADDR1
P_ADDR
ADDR0
P_CS#
P_WE#
TWA
TWS
TWA
TWH
TWS
TWH
TDH
at least
at least
2 SCLKs
2 SCLKs
TWR
Recovery Time
TDH
DATA 0
DATA 1
DATA to VTX2600
TDS
TDS
Hold time
Set up time
Figure 17 - Typical CPU Timing Diagram for a CPU Write Cycle
Description
(SCLK=100 Mhz)
Min. Max.
10
(SCLK=125 Mhz)
Min. Max.
10
Refer to Figure 17
Write Cycle
Symbol
Write Set up Time
Write Active Time
Write Hold Time
Write Recovery time
Data Set Up time
Data Hold time
T
T
T
T
T
T
WS
20
2
16
2
At least 2 SCLK
At least 3 SCLK
WA
WH
WR
DS
30
10
2
24
10
2
DH
159
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.5.6 Typical CPU Timing Diagram for a CPU Read Cycle
ADDR1
P_ADDR
ADDR0
P_CS#
P_RD#
TRA
TRH
TRS
TRH
TRA
TRS
at least
at least
TRR
2 SCLKs
2 SCLKs
Recovery Time
at least 3 SCLKs
DATA to CPU
DATA 0
DATA 1
TDV
TDI
TDV
TDI
2ns
Valid time
Invalid time
Figure 18 - Typical CPU Timing Diagram for a CPU Read Cycle
Description
(SCLK=100 Mhz) (SCLK=125 Mhz)
Refer to Figure 18
Read Cycle
Symbol
Min.
Max.
Min.
Max.
Read Set up Time
Read Active Time
Read Hold Time
Read Recovery time
Data Valid time
T
T
T
T
T
T
10
20
2
10
16
2
RS
RA
RH
RR
Dv
DI
At least 2 SCLK
At least 3 SCLK
30
24
10
6
10
6
Data Invalid time
15.6 Local Frame Buffer SBRAM Memory Interface
15.6.1 Local SBRAM Memory Interface
LA_CLK
L1
L2
LA_D[63:0]
Figure 19 - Local Memory Interface – Input Setup and Hold Timing
160
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
LA_CLK
LA_D[63:0]
LA_A[20:3]
LA_ADSC#
LA_WE[1:0]#
L3-max
L3-min
L4-max
L4-min
L6-max
L6-min
L7-max
L7-min
L8-max
L8-min
LA_OE[1:0]#
LA_WE#
L9-max
L9-min
L10-max
L10-min
LA_OE#
Figure 20 - Local Memory Interface - Output Valid Delay Timing
-100 MHz
Symbol
L1
Parameter
Note
Min. (ns) Max. (ns)
LA_D[63:0] input set-up time
LA_D[63:0] input hold time
LA_D[63:0] output valid delay
LA_A[20:3] output valid delay
LA_ADSC# output valid delay
LA_WE[1:0]#output valid delay
LA_OE[1:0]# output valid delay
LA_WE# output valid delay
LA_OE# output valid delay
4
L2
L3
L4
L6
L7
L8
L9
L10
1.5
1.5
2
7
7
7
7
1
7
5
C = 25 pf
L
C = 30 pf
L
1
C = 30 pf
L
1
C = 25 pf
L
-1
1
C = 25 pf
L
C = 25 pf
L
1
C = 25 pf
L
Table 15 - AC Characteristics – Local Frame Buffer SBRAM Memory Interface
161
Zarlink Semiconductor Inc.
MVTX2604
15.7 Local Switch Database SBRAM Memory Interface
15.7.1 Local SBRAM Memory Interface
Data Sheet
LB_CLK
L1
L2
LB_D[63:0]
Figure 21 - Local Memory Interface – Input Setup and Hold Timing
LB_CLK
L3-max
L3-min
LB_D[31:0]
L4-max
L4-min
LB_A[21:2]
L6-max
L6-min
LB_ADSC#
L8-max
L8-min
LB_WE[1:0]#
L9-max
L9-min
LB_OE[1:0]#
L10-max
L10-min
LB_WE#
L11-max
L11-min
LB_OE#
Figure 22 - Local Memory Interface - Output Valid Delay Timing
162
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
-100 MHz
Symbol
L1
Parameter
Note:
Min. (ns) Max. (ns)
LB_D[63:0] input set-up time
LB_D[63:0] input hold time
LB_D[63:0] output valid delay
LB_A[20:3] output valid delay
LB_ADSC# output valid delay
LB_WE[1:0]#output valid delay
LB_OE[1:0]# output valid delay
LB_WE# output valid delay
LB_OE# output valid delay
4
L2
1.5
L3
1.5
2
7
7
7
7
1
7
5
C = 25 pf
L
L4
C = 30 pf
L
L6
1
C = 30 pf
L
L8
1
C = 25 pf
L
L9
-1
1
C = 25 pf
L
L10
L11
C = 25 pf
L
1
C = 25 pf
L
Table 16 - AC Characteristics – Local Switch Database SBRAM Memory Interface
163
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.8 AC Characteristics
15.8.1 Reduced Media Independent Interface
M_CLKI
M[23:0]_TXEN
M6-max
M6-min
M7-max
M7-min
M[23:0] _TXD[1:0]
Figure 23 - AC Characteristics – Reduced Media Independent Interface
M_CLKI
M2
M[23:0]_RXD
M3
M4
M[23:0]_CRS_DV
M5
Figure 24 - AC Characteristics – Reduced Media Independent Interface
-50 MHz
Symbol
M2
Parameter
Note
Min. (ns)
Max. (ns)
M[23:0]_RXD[1:0] Input Setup Time
M[23:0]_RXD[1:0] Input Hold Time
M[23:0]_CRS_DV Input Setup Time
M[23:0]_CRS_DV Input Hold Time
M[23:0]_TXEN Output Delay Time
M[23:0]_TXD[1:0] Output Delay Time
4
1
4
1
2
2
M3
M4
M5
M6
M7
11
11
C = 20 pF
L
C = 20 pF
L
Table 17 - AC Characteristics – Reduced Media Independent Interface
164
Zarlink Semiconductor Inc.
MVTX2604
15.8.2 Gigabit Media Independent Interface - Port A
M25_TXCLK
Data Sheet
G12-max
G12-min
M25_TXD [15:0]
M25_TX_EN]
M25_TX_ER
G13-max
G13-min
G14-max
G14-min
Figure 25 - AC Characteristics- GMII
M25_RXCLK
G1
G2
M25_RXD[15:0]
G3
G4
M25_RX_DV
G5
G6
M25_RX_ER
G7
G8
M25_RX_CRS
Figure 26 - AC Characteristics – Gigabit Media Independent Interface
-125 Mhz
Symbol
G1
Parameter
Note
Min. (ns)
Max. (ns)
M[25]_RXD[15:0] Input Setup Times
M[25]_RXD[15:0] Input Hold Times
M[25]_RX_DV Input Setup Times
M[25]_RX_DV Input Hold Times
M[25]_RX_ER Input Setup Times
M[25]_RX_ER Input Hold Times
M[25]_CRS Input Setup Times
M[25]_CRS Input Hold Times
2
1
2
1
2
1
2
1
1
1
1
G2
G3
G4
G5
G6
G7
G8
G12
G13
G14
M[25]_TXD[15:0] Output Delay Times
M[25]_TX_EN Output Delay Times
M[25]_TX_ER Output Delay Times
6
6.5
6
C = 20 pf
L
C = 20 pf
L
C = 20 pf
L
Table 18 - AC Characteristics – Gigabit Media Independent Interface
165
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.8.3 Ten Bit Interface - Port A
M25_TXCLK
TIMIN
M25_TXD [9:0]
TIMAX
Figure 27 - Gigabit TBI Interface Transmit Timing
M25_RXCLK
M25_COL
T2
T2
M25_RXD[9:0]
T3
T3
Figure 28 - Gigabit TBI Interface Receive Timing
Symbol
T1
Parameter
Min. (ns)
Max. (ns)
Note
C = 20 pf
M25_TXD[9:0] Output Delay Time
1
6
L
Table 19 - Output Delay Timing
Symbol
T2
T3
Parameter
Min. (ns)
Ma.x (ns)
Note
M25_RXD[9:0] Input Setup Time
M25_RXD[9:0] Input Hold Time
3
3
Table 20 - Input Setup Timing
15.8.4 Gigabit Media Independent Interface - Port B
M26_TXCLK
G12-max
G12-min
M26_TXD [15:0]
M26_TX_EN]
M26_TX_ER
G13-max
G13-min
G14-max
G14-min
Figure 29 - AC Characteristics- GMII
166
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
M26_RXCLK
G1
G3
G2
M26_RXD[15:0]
M26_RX_DV
M26_RX_ER
M26_RX_CRS
G4
G5
G7
G6
G8
Figure 30 - AC Characteristics – Gigabit Media Independent Interface
-125 Mhz
Symbol
G1
Parameter
Note
Min. (ns)
Max. (ns)
M[26]_RXD[15:0] Input Setup Times
M[26]_RXD[15:0] Input Hold Times
M[26]_RX_DV Input Setup Times
M[26]_RX_DV Input Hold Times
M[26]_RX_ER Input Setup Times
M[26]_RX_ER Input Hold Times
M[26]_CRS Input Setup Times
M[26]_CRS Input Hold Times
2
1
2
1
2
1
2
1
1
1
1
G2
G3
G4
G5
G6
G7
G8
G12
G13
G14
M[26]_TXD[15:0] Output Delay Times
M[26]_TX_EN Output Delay Times
M[26]_TX_ER Output Delay Times
6
6.5
6
C = 20 pf
L
C = 20 pf
L
C = 20 pf
L
Table 21 - AC Characteristics – Gigabit Media Independent Interface
15.8.5 Ten Bit Interface - Port B
M26_TXCLK
TIMIN
M26_TXD [9:0]
TIMAX
Figure 31 - Gigabit TBI Interface Transmit Timing
167
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
M26_RXCLK
M26_COL
T2
T2
M26_RXD[9:0]
T3
T3
Figure 32 - Gigabit TBI Interface Timing
Symbol
T1
Parameter
Min. (ns)
Max. (ns)
Note
C = 20 pf
M26_TXD[9:0] Output Delay Time
1
6
L
Table 22 - Output Delay Timing
Parameter
Min. (ns)
Max. (ns)
Symbol
T2
Note
M26_RXD[9:0] Input Setup Time
M26_RXD[9:0] Input Hold Time
3
3
T3
Table 23 - Input Setup Timing
168
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.8.6 LED Interface
LED_CLK
LED_SYN
LED_BIT
LE5-max
LE5-min
LE6-max
LE6-min
Figure 33 - AC Characteristics – LED Interface
Variable FREQ.
Parameter
Symbol
Note
C = 30 pf
Min. (ns)
Max. (ns)
LE5
LE6
LED_SYN Output Valid Delay
LED_BIT Output Valid Delay
-1
-1
7
7
L
C = 30 pf
L
Table 24 - AC Characteristics – LED Interface
169
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.8.7 SCANLINK SCANCOL Output Delay Timing
SCANCLK
C5-max
C5-min
SCANLINK
C7-max
C7-min
SCANCOL
Figure 34 - SCANLINK SCANCOL Output Delay Timing
SCANCLK
C1
C3
C2
C4
SCANLINK
SCANCOL
Figure 35 - SCANLINK, SCANCOL Setup Timing
-25 MHz
Parameter
Symbol
C1
Note
Min. (ns) Max. (ns)
SCANLINK input set-up time
20
2
C2
C3
C4
C5
C7
SCANLINK input hold time
SCANCOL input setup time
SCANCOL input hold time
SCANLINK output valid delay
SCANCOL output valid delay
20
1
0
10
10
C = 30pf
L
0
C = 30pf
L
Table 25 - SCANLINK, SCANCOL Timing
170
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.9 MDIO Input Setup and Hold Timing
MDC
D1
D2
MDIO
Figure 36 - MDIO Input Setup and Hold Timing
MDC
D3-max
D3-min
MDIO
Figure 37 - MDIO Output Delay Timing
1 MHz
Parameter
Symbol
D1
Note:
Min. (ns) Max. (ns)
MDIO input setup time
10
2
D2
D3
MDIO input hold time
MDIO output delay time
1
20
C = 50 pf
L
Table 26 - MDIO Timing
171
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.9.1 I2C Input Setup Timing
SCL
SDA
S2
S1
2
Figure 38 - I C Input Setup Timing
SCL
S3-max
S3-min
SDA
2
Figure 39 - I C Output Delay Timing
50 KHz
Symbol
S1
Parameter
Note
Min. (ns)
Max. (ns)
SDA input setup time
SDA input hold time
SDA output delay time
20
1
S2
S3*
4 usec
6 usec
C = 30 pf
L
* Open Drain Output. Low to High transistor is controlled by external pullup resistor.
2
Table 27 - I C Timing
172
Zarlink Semiconductor Inc.
MVTX2604
Data Sheet
15.9.2 Serial Interface Setup Timing
STROBE
D0
D4
D5
D1
D1
D2
D2
Figure 40 - Serial Interface Setup Timing
STROBE
D3-max
D3-min
AutoFd
Figure 41 - Serial Interface Output Delay Timing
Symbol
D1
Parameter
Min. (ns) Max. (ns)
Note
D0 setup time
D0 hold time
20
D2
D3
D4
D5
3 µs
AutoFd output delay time
Strobe low time
1
50
C = 100 pf
L
5 µs
5 µs
Strobe high time
Table 28 - Serial Interface Timing
173
Zarlink Semiconductor Inc.
DIMENSION
MIN
MAX
A
A1
A2
D
D1
E
2.20
0.50
2.46
0.70
1.17 REF
37.70
37.30
37.30
34.50 REF
37.70
E1
E
E1
b
e
34.50 REF
0.60
0.90
1.27
553
Conforms to JEDEC MS - 034
e
D
D1
A2
b
NOTE:
1. CONTROLLING DIMENSIONS ARE IN MM
2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER
3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
4. N IS THE NUMBER OF SOLDER BALLS
5. NOT TO SCALE.
6. SUBSTRATE THICKNESS IS 0.56 MM
Package Code
Previous package codes:
ISSUE
ACN
DATE
APPRD.
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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