MVTX2604A [ETC]

MVTX260x Physical Port Control ; MVTX260x物理端口控制\n


型号：	MVTX2604A
厂家：	ETC
描述：	MVTX260x Physical Port Control MVTX260x物理端口控制\n
文件：	总9页 (文件大小：120K)
中文：	中文翻译
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MSAN-213

MVTX260x Physical Port Control

Application Note

Contents

Issue 1

October 2002

1.0 Purpose

2.0 Scope

1.0 Purpose

3.0 ECR Register Basics

This application note describes the PHY Port Control

on the MVTX260x chipsets.

3.1 ECR1 (ECR1Pn): Port N Control Register

3.2 ECR2 (ECR2Pn): Port N Control Register

3.3 GGControl – Extra GIGA port control

2.0 Scope

4.0 Operation Mode

5.0 Status Register Basics

5.1 DCR1-Giga port status

This document will cover PHY Port Control for the

MVTX260x device. The reader should be familiar with

the MVTX260x data sheet before reading this

application note.

5.2 DPST – Device Port Status Register

5.3 DTST – Data Read Back Register

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MSAN-213

Application Note

3.0 ECR Register Basics

3.1 ECR1 (ECR1Pn): Port N Control Register

I²C EEPROM address 000-01A; CPU Address:0000+2x1A

Bit

•

Bit [0] (F) Flow control

•

1: Flow Control Off

0: Flow Control On

Bit [1] (D) Duplex mode selection

•

1: Half Duplex

0: Full Duplex

Bit [2] (S) Speed selection

•

1: 10Mbps

0: 100Mbps

Bit [4:3] (AN) Auto-negotiation control

•

00: Enable hardware state machine for auto-

negotiation

01: Limited Disable auto Neg. Poll MII for

link status

10: Force link down and disable auto

negotiation state machine.

11: Force link up. The configuration in ECR1

[2:0] is used for (speed/duplex/flow control)

setup.

•

Bit [5] (A) Asymmetric Flow Control Enable.

•

1: Never send out a flow control frame.

0: Normal flow control mode (default)

Bit [7:6] (SS) Spanning tree state

•

00: Blocking: Frame is dropped

01: Listening: Frame is dropped

10: Learning: Frame is dropped. Source

MAC address is learned.

11: Forwarding: Frame is forwarded. Source

MAC address is learned. (default)

•

Zarlink Semiconductor Inc.

Application Note

MSAN-213

3.2 ECR2 (ECR2Pn): Port N Control Register

I²C EEPROM address 0x01B-0x035; CPU Address:0001+2x1A

Security

QoS

FUT

• Bit [0]: Filter untagged frame

• 0: Disable (default)

•

1: Enable

•

Bit [1]: Filter Tag frame (FT)

•

0: Disable (default)

1: All untagged frames from this port

are discarded

•

Bit [2]: Learning Disable (LD)

•

0 Learning is enabled on this port

(default)

•

1 Learning is disabled on this port

Bit [3]: must be 1

• Bit [5:4] QoS mode selection (QoS)

These two bits selects one of the 4 sets of

QoS settings used for 10/100 ports.

00: select classes byte limit set 0 and

classes WFQ credit set 0 (default)

01: select classes byte limit set 1 and

classes WFQ credit set 1

10: select classes byte limit set 2 and

classes WFQ credit set 2

11: select classes byte limit set 3 and

classes WFQ credit set 3

Zarlink Semiconductor Inc.

MSAN-213

Application Note

•

Bit[7:6] · Security Mode Enable (Security)

The MVTX260x checks the incoming data for

one of the following conditions:

1. whether the incoming MAC address is

secure or already defined in the MAC table;

2. whether the incoming port is not disabled

3. whether the packet is tagged or untagged.

If one of these three conditions is violated, the

packet will be handled according to one of the

following specified options:

CPU installed

•

00: Disable port security

01: Discard violating packets

10: Send packet to CPU and port

11: Send packet to CPU only

CPU is not installed

•

00: Disable port security

01: Disable the port that receives

security violation packets

10: N/A

•

11: N/A

3.3 GGControl – Extra GIGA port control

(CPU Address:h036) Access by CPU and serial interface (R/W)

MiiB RstA

MiiA RstA

•

Bit [0] Reset GIGA port A

•

0: Normal operation (default)

1: Reset Gigabit port A

Bit [1] GIGA port A use MII interface (10/100M)

•

0: Gigabit port operates at 1000 mode

1: Gigabit port operates at 10/100 mode

Bit [2] Device information insertion enable for Gigabit port A

•

0: Disable preamble stack device ID insertion (default).

1: Insert stack device ID into the preamble (must be

enabled for ring mode).

•

Bit [3] GIGA port A direct flow control

MVTX260x supports extra flow control mechanism, so the flow

control frame is not sent through the Gigabit port data path.

•

0: Direct flow control disabled (default)

1: Direct flow control enabled

Zarlink Semiconductor Inc.

Application Note

MSAN-213

•

Bit [4] Reset Gigabit port B

•

0: Normal operation (default)

1: Reset Gigabit port B

Bit [5] GIGA port B use MII interface (10/100M)

•

0: Gigabit port operates at 1000 mode

1: Gigabit port operates at 10/100 mode

Bit [6] Device information insertion enable for Gigabit port B

•

0: Disable preamble stack device ID insertion (default).

1: Insert stack device ID into the preamble (must be

enabled for ring mode).

•

Bit [7] GIGA port B direct flow control

MVTX260x supports extra flow control mechanism, so the flow

control frame is not sent through the Gigabit port data path.

•

0: Direct flow control disabled (default)

1: Direct flow control enabled

4.0 Operation Mode

In normal operation mode, the ECR1[4:3] is set to 00. The hardware state machine will program MII registers via

MDIO interface, then polling MII register status of ports and setting up the hardware connection mode.

By setting the ECR1[4:3] to 01, then hardware will not program the MII register but the hardware state machine still

polls the MII register 1 for the link status. If the hardware state machine detects link status change, it will update the

internal link status register, which will cause an interrupt to the CPU. After received the “link status change”

interrupts, the management software needs to read the MII register, check the PHY connection mode, and update

the ECR1[2:0].

A typical implementation to emulate an auto negotiation with software is shown below:

•

Setup:

•

Program MII register for full advertisement.

Set ECR1[4:3] = 01 to enable link change detection.

•

When link change interrupt is received:

•

For a link up interrupt:

1. Read MII register of the link change port and determine the PHY connection mode.

2. By setting ECR1[4:3]=11 to force linkup, and set the port connection mode via ECR1[2:0].

3. Set ECR1[4:3] =01 to enable link change detection (ECR1[2:0] bits are not used when

ECR1[4:3]=01).

•

For a link down interrupt, no ECR1 setup is required.

A typical implementation to force a fixed configuration is shown below:

•

Setup:

•

Program MII register for advertisement of the fixed speed and operation speed.

Set ECR1[4:3] = 01 to enable link change detection.

Zarlink Semiconductor Inc.

MSAN-213

Application Note

•

When link change interrupt is received:

•

For a link up interrupt:

1. By setting ECR1[4:3]=11 to force linkup, and set the port connection mode via ECR1[2:0].

2. Set ECR1[4:3] =01 to enable link change detection (ECR1[2:0] bits are not used when

ECR1[4:3]=01).

•

For a link down interrupt, no ECR1 setup is required.

A typical implementation to force a fixed configuration for Gigabit port is shown below:

•

Setup:

•

Program MII register for advertisement of the fixed speed and operation speed.

Set ECR1[4:3] = 01 to enable link change detection.

If the port is operate in 1000Mbps, set the MIIA/B in GGC to 0, else set the MIIA/B in GGC to 1.

•

When link change interrupt is received:

•

For a link up interrupt:

1. By setting ECR1[4:3]=11 to force linkup, and set the port connection mode via ECR1[2:0] (speed is

ignore if port is in 1000Mbps mode).

2. Set ECR1[4:3] =01 to enable link change detection (ECR1[2:0] bits are not used when

ECR1[4:3]=01).

•

For a link down interrupt, no ECR1 setup is required.

5.0 Status Register Basics

5.1 DCR1-Giga port status

(CPU Address: hF02) Access by CPU and serial interface. (RO)

CIC

GIGA1

GIGA0

•

Bit [1:0] Gigabit port 0 strap option

•

00 – 100Mb MII mode

01 – 2G mode

10 – GMII

11 – PCS

Bit [3:2] Gigabit port 1 strap option

•

00 – 100Mb MII mode

01 – 2G mode

10 – GMII

11 – PCS

Bit [7] Chip initialization completed

Zarlink Semiconductor Inc.

Application Note

MSAN-213

5.2 DPST – Device Port Status Register

(CPU Address:hF03) Access by CPU and serial interface (R/W)

)

• Bit [4:0]: Read back index register.

This is used for selecting what to read back from DTST.

5’b00000 - Port 0 Operating mode/Neg status (default)

5’b00001 - Port 1 Operating mode/Neg status

5’b00010 - Port 2 Operating mode/Neg status

5’b00011 - Port 3 Operating mode/Neg status

5’b00100 - Port 4 Operating mode/Neg status

5’b00101 - Port 5 Operating mode/Neg status

5’b00110 - Port 6 Operating mode/Neg status

5’b00111 - Port 7 Operating mode/Neg status

5’b01000 - Port 8 Operating mode/Neg status

5’b01001 - Port 9 Operating mode/Neg status

5’b01010 - Port A Operating mode/Neg status

5’b01011 - Port B Operating mode/Neg status

5’b01100 - Port C Operating mode/Neg status

5’b01101 - Port D Operating mode/Neg status

5’b01110 - Port E Operating mode/Neg status

5’b01111 - Port F Operating mode/Neg status

5’b10000 - Port 10 Operating mode/Neg status

5’b10001 - Port 11 Operating mode/Neg status

5’b10010 - Port 12 Operating mode/Neg status

5’b00011 - Port 13 Operating mode/Neg status

5’b10100 - Port 14 Operating mode/Neg status

5’b10101 - Port 15 Operating mode/Neg status

5’b10110 - Port 16 Operating mode/Neg status

5’b10111 - Port 17 Operating mode/Neg status

5’b11000 - Port 18 Operating mode/Neg status

5’b11001 - Port 19 Operating mode/Neg status

5’b11010 - Port 1A Operating mode/Neg status

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MSAN-213

Application Note

5.3 DTST – Data Read Back Register

(CPU Address: hF04) Access by CPU and serial interface (RO)

This register provides various MAC status selected via DPST bit[4:0]

Info

Sig

Giga lnkdn

Fdpx FcEn

•

Bit[0]:Flow control enabled

Bit[1]:Full duplex port

Bit[2]:Fast ethernet port (if not giga)

Bit[3]:Link is down

Bit[4]:GIGA port

Bit[5]:Signal detect (when PCS interface

mode)

•

Bit[6]:2G signal detected (2G mode only)

Bit[7]:Module detected (for hot swap purpose)

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MVTX2604A [ETC]

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