VSC7961YD [VITESSE]
3.125Gb/s PECL Limiting Amplifier with LOS Detect; 3.125Gb / s的PECL限幅放大器与LOS检测
| 型号： | VSC7961YD |
| 厂家： | 
VITESSE SEMICONDUCTOR CORPORATION |
| 描述： | 3.125Gb/s PECL Limiting Amplifier with LOS Detect |
| 文件： | 总10页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Features
Applications
• 3.3V or 5V Power Supply
• Typical Supply Current of 32mA
• SONET/SDH at 622Mb/s, 1.244Gb/s, 2.488Gb/s,
and 3.125Gb/s
• Positive Emitter-Coupled Logic (PECL) Outputs
• Optional Output Squelch
• Full-Speed Fibre Channel (1.062Gb/s)
• Small Form Factor (SFF) Receivers
• ATM Optical Receivers
• Loss of Signal Detect
• Output Offset Correction
• Rise/Fall Times Faster than 100ps
• Packages: TSSOP-16, Bare Die
General Description
The VSC7961 is a single-supply limiting amplifier with Loss of Signal (LOS) detect for SONET/SDH and
Fibre Channel applications up to 3.125Gb/s. The VSC7961 provides a constant output signal swing for a wide
range of input voltages and has Positive Emitter-Coupled Logic (PECL). The VSC7959 provides the same func-
tionality as the VSC7961 with Current-Mode Logic (CML) outputs. Key features of the VSC7961 are its RMS
power detectors for programmable LOS detection, optional output squelch, adjustable output levels, excellent
jitter performance, and fast edge rates. The VSC7961 is available in die form or in a TSSOP-16 package.
Block Diagram
VSC7961
VCC
8k
Ω
LOS
VCC
8k
Ω
TH
LOS
SQUELCH
LEVEL
RMS Power
Detect and
Control
Output Control
IN+
IN-
OUT+
OUT-
100
Ω
Lowpass Filter
10pF
Offset Correction
CZ1
CZ2
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52360-0, Rev 2.0
02/09/01
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Electrical Characteristics
Table 1: DC Specifications
Symbol
Parameter
Power Supply Voltage
Min
Typ
Max Units
Conditions
VCC
3.135
5.5
V
59
62
31
35
58
62
20
23
mA
mA
mA
mΑ
mA
mA
mA
mA
µA
VCC = 3.3V
CC = 5V
VCC = 3.3V
CC = 5V
ICC
Power Supply Current(1)
Power Supply Current(1)
V
IEE
V
VCC = 3.3V
VCC = 5V
Power Supply Current when
Squelched(1)
ICCSQ
VCC = 3.3V
Power Supply Current when
Squelched(1)
IEESQ
VCC = 5V
ISQ
Squelch Input Current
0
400
PSSR
Power Supply Rejection Ratio
20
dB
f < 2MHz
NOTE: (1) See Figure 4 for supply current measurement setup.
Table 2: DC Specifications
Symbol
Parameter
Min
Typ
Max Units
Conditions
Peak-to-peak
Data Rate
3.125
10
Gb/s
VIN
JD
Input Voltage Range
Deterministic Jitter
Random Jitter
1200
25
mV
ps
See Note 1
JR
8
ps
See Note 2, RMS
20% to 80%
tR, F
t
Rise and Fall Times
Input Referred Noise
Differential Input Resistance
55
100
230
ps
VN
µV
Ω
RMS, IN+ to IN-
IN+ to IN-
RDIFF
100
2
MHz CZ open
fL
Low Frequency Cutoff
2
kHz CZ = 0.1µF
VSQ
VOH
Output Signal When Squelched
PECL Output High Voltage
20
mV
mV
mV
mV
mV
Ω
Output AC-coupled
-1025
-1810
-850
-850
Squelched
-1620
-1620
VOL
ZO
PECL Output Low Voltage
Output Resistance
Squelched
100
Single-ended
NOTES: (1) Deterministic jitter measured peak-to-peak with K28.5 pattern. (2) Random jitter measured with minimum input.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 2
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Table 3: Loss of Signal Specifications
Symbol
Parameter
LOS Hystersis
Min
Typ
Max Units
Conditions
HLOS
ILOS
3.1
3.3
0.25
8.2
5.5
dB
µs
HLOS = 20 log (VTHD/VTHA)
LOS Assert/Deassert Time
0.22
0.28
mV
mV
mV
mV
mV
mV
V
RTH = 2.5kΩ
VTHA
LOS Assert Threshold
12.8
19.8
57.2
11.4
29.0
75.2
21.8
31.6
RTH = 7kΩ
RTH = 20kΩ
R
TH = 2.5kΩ
VTHD
LOS Deassert Threshold
26.2
3.3
RTH = 7kΩ
RTH = 20kΩ
ILOS = –30µA
ILOS = +1.2µA
VLOSH
VLOSL
LOS Output HIGH Voltage
LOS Output LOW Voltage
0.168
V
Table 4: Loss of Signal Truth Table
SQUELCH
LOS
Output
High
Low
High
Low
Low
High
Low
Low
Off
On
On
On
Absolute Maximum Ratings(1)
Power Supply Voltage (V )............................................................................................................. -0.5V to +6V
CC
Maximum Junction Temperature Range .........................................................................................................TBD
Storage Temperature Range (T )................................................................................................. -55°C to +150°C
S
NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Rail (V ).................................................................................................................. 3.3V or 5V
CC
Junction Temperature Range (T )................................................................................................ -40°C to +100°C
J
Ambient Temperature Range (T )................................................................................................. -40°C to +85°C
A
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52360-0, Rev 2.0
02/09/01
Page 3
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Package Pin Descriptions
Figure 1: Pin Diagram
Top View
TSSOP-16 Package
CZ1
CZ2
GND
IN+
1
2
3
4
5
6
7
8
NC
16
15
14
13
12
11
10
9
SQUELCH
VCC
OUT+
OUT-
VCC
VSC7961
IN-
GND
NC
LOS
TH
LOS
Table 5: Pin Identifications
Pin Name Pin No.
Description
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant
of offset correction loop. See Detailed Description section.
CZ1
CZ2
1
2
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant
of offset correction loop. See Detailed Description section.
GND
IN+
3
4
5
6
Supply Ground
Noninverted Input Signal
Inverted Input Signal
Supply Ground
IN-
GND
This pin may be either connected to ground of left unconnected. This pin does not effet the
performance of the device.
NC
7
8
Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal
level at which LOS outputs will be asserted. See Application Information section.
TH
Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by
TH. See Detailed Description section.
LOS
LOS
9
Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold
programmed by TH. See Detailed Description section.
10
VCC
OUT-
OUT+
VCC
11
12
13
14
Power Supply
Inverted Data Output
Noninverted Data Output
Power Supply
Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is
HIGH, OUT+ and OUT- are forced to static levels. See Detailed Description section.
SQUELCH
NC
15
16
No Connection
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 4
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Bare Die Descriptions
Figure 2: Pad Assignments
1597µm (0.06287")
Pad1
CAZ1
Pad 16
NC
Pad 2
CAZ2
Pad 15
SQ
Pad 3
GNDA
Pad 14
VCCA
Pad 4
LAINP
Pad 13
LAOP
VSC7961
1597µm
Pad 5
LAINM
Pad 12
LAOM
(0.06287")
Pad 6
GNDA
Pad 11
VCCA
Pad 7
NC
Pad 10
LOS
Pad 8
TH
Pad 9
LOS
Die Size:
Pad Pitch:
1597µm x 1597µm (0.06287" x 0.06287")
180µm (0.00709")
Pad Passivation Opening: 95µm x 95µm (0.00374" x 0.00374")
The back side of the die may either be left floating or connected ot ground.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52360-0, Rev 2.0
02/09/01
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Table 6: Pad Coordinates
Coordinates (µm)
Pad
Name
Pad/Pin
Number
Pin Name
CZ1
Description
X
Y
Offset Correction Loop Capacitor. Place capacitor between
this pin and CZ2 to alter time constant of offset correction
loop. See Detailed Description section.
CZ1
1
2
270.525
1359.05
Offset Correction Loop Capacitor. Place capacitor between
CZ2
CZ2
80.95
1170.525 this pin and CZ1 to alter time constant of offset correction
loop. See Detailed Description section.
GNDA
LAINP
LAINM
GNDA
GND
IN+
3
4
5
6
80.95
80.95
80.95
80.95
990.525
810.525
630.525
450.525
Supply Ground
Noninverted Input Signal
Inverted Input Signal
Supply Ground
IN-
GND
This pin may be either connected to ground of left
unconnected. This pin does not effet the performance of the
device.
NC
NC
TH
7
80.95
270.525
Loss of Signal (LOS) Threshold. Connect a resistor from
this pin to ground to set the input signal level at which LOS
outputs will be asserted. See Application Information
section.
TH
8
270.525
80.95
Inverted Loss of Signal Output. LOS is HIGH for input
signals above the threshold programmed by TH. See
Detailed Description section.
LOS
LOS
LOS
LOS
9
1169.475
1359.05
80.95
Noninverted Loss of Signal Output. LOS is LOW for input
signals above the threshold programmed by TH. See
Detailed Description section.
10
270.525
VCCA
LOAM
LAOP
VCCA
VCC
OUT-
OUT+
VCC
11
12
13
14
1359.05
1359.05
1359.05
1359.05
450.525
630.525
810.525
990.525
Power Supply
Inverted Data Output
Noninverted Data Output
Power Supply
Squelch Input. Squelch is disabled if this pin is
unconnected or set LOW. When SQUELCH is HIGH,
OUT+ and OUT- are forced to static levels. See Detailed
Description section.
SQ
NC
SQUELCH
15
1359.05
1170.525
1359.05
—
—/16
1169.475
No Connection
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 6
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Detailed Description
The VSC7961 is a high-speed limiting amplifier with Loss of Signal (LOS) detect. The device is designed
to operate with a 3.3V or 5V supply in SDH/SONET and Fibre Channel applications up to 3.125Gb/s. The
VSC7961 has positive emitter-coupled logic (PECL) outputs. The VSC7959 provides the same functionality as
the VSC7961 with current-mode logic (CML) outputs. The key features of the VSC7961 are Loss-of-Signal
(LOS) detect, output offset correction, output squelch, low power supply current, and fast rise and fall times.
The inputs of the device provide 100Ω input impedance between IN+ and IN- and are intended to be DC-
coupled. The PECL output circuits should be terminated through 50Ω to V - 2V.
CC
Loss of Signal (LOS) Detect
This feature utilizes an rms power detector with programmable LOS indicator to provide two outputs, LOS
and LOS. The input TH is used to set the threshold at which the loss of signal detector outputs, LOS and LOS,
change state. See Loss of Signal Specifications (Table 3) for setting the resistor value between TH and ground.
The Loss-of-Signal Truth Table (Table 4) clarifies how LOS and SQUELCH interact.
Optional Squelch
Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to
TTL high level and LOS is asserted, the data outputs, OUT+ and OUT- are forced to static levels. If LOS is not
asserted, the outputs will not be squelched.
Offset Correction
This feature is provided to ensure that the offsets in the amplifier coupled with its gain do not cause the out-
put buffer to give a false output. Because of the high gain of the amplifier, offset correction using a low-fre-
quency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low
frequency cut-off is 2MHz. If a 0.1µF capacitor is placed between CZ1 and CZ2, the low frequency cut-off is
lowered to about 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open. For
ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1µF capacitor between
CZ1 and CZ2. This maintains a one-decade separation between the lowest input frequency and the low fre-
quency cut-off. The low frequency cut-off of the offset correction loop is given by the following equation:
f
= 43 / [2π * 35k (C + 100pF)]
OC
Z
-6
= 196* 10 / (C + 100pF)
Z
-6
= 196* 10 / (0.1µF + 100pF)
= 1.96kHz
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52360-0, Rev 2.0
02/09/01
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Output Level Control
The LEVEL pin adjusts the output levels to 20mA when grounded and to 16mA when left unconnected.
Figure 3: Supply Current Measurement
VCC
ICC
A
IOUT
100Ω
100Ω
100Ω
100Ω
IMOD
VSC7961
A
IEE
VEE
Supply Current (ICC and IEE
)
Applications Information
Wire Bonding
For best performance, gold ball-bonding techniques are recommended. To minimize inductance, keep wire
bond lengths short.
PCB Layout Guidelines
Use high frequency PCB layout techniques with solid ground planes to minimize crosstalk and EMI. Keep
high speed traces as short as possible for signal integrity. Short input and output traces will provide best perfor-
mance.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 8
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Package Information
TSSOP-16
1. All dimensioning and tolerancing per ASME.Y14.5-1994
2. Controlling dimension: millimeter
3. This outline conforms to JEDEC Publication 95 Registration MS-026
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52360-0, Rev 2.0
02/09/01
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Ordering Information
The order number for this product is formed by a combination of the device type and package type.
xx
VSC7961
Device Type
3.125Gb/s PECL Limiting Amplifier
with LOS Detect
Package
YD: TSSOP-16
W: Dice Waffle Pack
Notice
Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production
information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of
features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this
document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or
will be suitable for or will accomplish any particular task.
Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without writ-
ten consent is prohibited.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 10
G52360-0, Rev 2.0
02/09/01
相关型号：
©2020 ICPDF网 联系我们和版权申明