VSC7962RO [MICROSEMI]
Telecom IC,;
Microsemi 
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Features
Applications
• 3.3V Power Supply
• SONET/SDH at 622Mb/s, 1.244Gb/s, 2.488Gb/s
and 3.125Gb/s
• Laser Driver AC-Coupled to Laser Diode
• Full-Speed Fibre Channel (1.062Gb/s)
• Programmable Laser Driver Modulation Current
from 5mA to 60mA
• Programmable Laser Driver Bias Current from
1mA to 100mA
• Laser Driver Enable Control
• Automatic Optical Average Power Control
• Supply Current of 80mA
• PECL Limiting Amplifier Outputs
• 48-Pin TQFP Package
General Description
The VSC7962 is a single 3.3V supply combination limiting amplifier and laser diode driver for
SONET/SDH applications up to 3.125Gb/s. The limiting amplifier features Loss of Signal (LOS) detect, output
offset correction, and optional output squelch. Laser driver data inputs accept differential PECL signals and the
output modulation and bias currents are easily controlled via external components. The laser diode driver Auto-
matic Power Control (APC) loop maintains a constant average optical power over temperature and lifetime. The
dominant pole of the APC loop can be controlled with an external capacitor. Other features include enable con-
trol, short-circuit protection for the modulation and bias inputs, short rise and fall times, and failure-monitor
output to indicate when the APC loop is unable to maintain the average optical power. The VSC7962 is avail-
able in die form or in a 48-pin TQFP package. The VSC7960 provides similar features to the VSC7962 but the
limiting amplifier has CML outputs.
Block Diagram
VSC7962
DATA+
DATA-
OUT+
OUT-
VSC7939
Laser Driver
LAO+
LAO-
VSC7961
Limiting Amplifier
IN+
IN-
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52361-0, Rev 2.1
05/01/01
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Electrical Characteristics
Table 1: Limiting Amplifier DC Specifications
Symbol
Parameter
Power Supply Range
Power Supply Current(1)
Min
Typ
Max Units
Conditions
VCC
ICC
3.135
5.5
V
31
38
21
24
mA
mA
mA
mA
µA
dB
VCC = 3.3V
VCC = 3.3V
VCC = 3.3V
VCC = 3.3V
IEE
Power Supply Current(1)
ICCSQ
IEESQ
ISQ
Power Supply Current when Squelched(1)
Power Supply Current when Squelched(1)
Squelch Input Current
0
400
PSSR
Power Supply Rejection Ratio
20
30
f < 2MHz
NOTE: (1) See Figure5 for supply current measurement setup.
Table 2: Laser Driver DC Specifications
Symbol
Parameter
Min
Typ
Max Units
Conditions
VCC
Power Supply Voltage Range
3.125
3.465
V
R
MODSET=7.3kΩ,
RBIASMAX=4.8kΩ
BIAS and IMOD excluded VCC=5V
mA Voltage at BIAS pin=(VCC-1.6)
ICC
Supply Current
TBD
45
mA
I
IBIAS
Bias Current Range
1
100
100
IBIAS-OFF Bias Off Current
µA
ENABLE=low or DISABLE=high(1)
APC open loop. IBIAS=100mA
APC open loop. IBIAS=1mA
230
900
±15
SBIAS
Bias Current Stability
ppm/°C
Bias Current Absolute Accuracy
%
V
Refers to part-to-part variation.
VRMD
IMD
Monitor Diode Reverse Bias Voltage
Monitor Diode Reverse Current Range
1.5
18
1000
480
µA
-480
50
90
I
MD=1mA(1)
IMD=18µA(1)
Monitor Diode Bias Setpoint Stability
ppm/°C
Monitor Diode Bias Absolute Accuracy
Modulation Current Range
-15
5
15
60
%
mA
µA
%
Refers to part-to-part variation.
IMOD
IMOD-OFF Modulation Off Current
Modulation Current Absolute Accuracy
200
ENABLE=low or DISABLE=high(2)
See Note 2
±15
-50
-480
480
I
I
MOD=60mA
MOD=5mA
Modulation Current Stability
ppm/°C
250
NOTES: (1) Both I
and I
will turn off if any of the current set pins are grounded. (2) Assumes laser diode to monitor diode transfer
MOD
BIAS
function does not change with temperature.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Page 2
G52361-0, Rev 2.1
05/01/01
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Table 3: Limiting Amplifier AC Specifications
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Data Rate
3.125
10
Gb/s
mV
ps
VIN
JD
Input Voltage Range
Deterministic Jitter
Random Jitter
1200
25
peak-to-peak
See Note 1
JR
8
ps
rms, see Note 2
20%-80%
t
R, tF
Rise/Fall Times
55
100
230
ps
vN
Input Referred Noise
Differential Input Resistance
µV
rms, IN+ to IN-
IN+ to IN-
RDIFF
100
2
W
MHz
kHz
mV
mV
mV
mV
mV
Ω
CZ open
fL
Low Frequency Cut-off
2
CZ=0.1µF
VSQ
VOH
Output Signal when Squelched
PECL Output High Voltage
20
Outputs AC-coupled
-1025
-1810
-850
-850
-1620
-1620
Squelched
VOL
ZO
PECL Output Low Voltage
Output Resistance
Squelched
100
Single-ended
NOTES: (1) Deterministic Jitter measured peak-to-peak with K28.5 pattern. (2) Random Jitter measured with minimum input.
Table 4: Laser Driver AC Specifications
Symbol
Parameter
Input Latch Setup Time
Min
Typ
Max
Units
Conditions
LATCH=high
tSU
tH
100
100
ps
ps
Input Latch Hold Time
Enable/Start-up Delay
Output Rise Time
LATCH=high
250
60
ns
tR
80
80
50
ps
20% to 80%
20% to 80%
See Notes 1, 2
tF
Output Fall Time
60
ps
PWD
Pulse Width Distortion
10
ps
CIDMAX Maximum Consecutive Identical Digits
80
bits
Jitter BW=12kHz to 20MHz,
0-1 pattern.
tJ Jitter Generation
7
20
psp-p
NOTES: (1) Measured with 622Mb/s 0-1 pattern, LATCH=high. (2) PWD = (wider pulse - narrower pulse) / 2)
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52361-0, Rev 2.1
05/01/01
Page 3
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Table 5: PECL and TTL/CMOS Inputs and Outputs Specifications
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VID
Differential Input Voltage
100
1600
mVp-p (DATA+) - (DATA-)
VCC
1.49
-
VCC
1.32
-
VCC
ID/4
10
-
VICM
IIN
Common-Mode Input Voltage
Clock and Data Input Current
V
µA
V
PECL compatible
V
-1
TTL Input High Voltage
(ENABLE, LATCH, DISABLE)
VIH
2.0
TTL Input Low Voltage
(ENABLE, LATCH, DISABLE)
VIL
0.8
V
VCC
0.3
-
VOH
VOL
TTL Output High Voltage (FAIL)
TTL Output Low Voltage (FAIL)
2.4
0.1
VCC
0.44
V
V
Sourcing 50µA
Sinking 100µA
Table 6: Limiting Amplifier Loss of Signal Specifications
Symbol
Parameter
LOS Hysteresis
Min
Typ
Max
Units
Conditions
HLOS= 20 log (VTHD / VTHA
HLOS
tLOS
3.1
3.3
0.25
8.2
5.5
dB
µs
)
LOS Assert / Deassert Time
0.22
0.28
RTH=2.5kΩ
VTHA
LOS Assert Threshold
12.8
19.8
57.2
11.4
29
21.8
31.6
mV
mV
RTH=7kΩ
RTH=20kΩ
RTH=2.5kΩ
VTHD
LOS Deassert Threshold
26.2
3.3
RTH=7kΩ
75.2
RTH=20kΩ
ILOS=-30µA
ILOS=+1.2µA
VLOSH
VLOSL
LOS Output High Voltage
LOS Output Low Voltage
V
V
0.168
Table 7: Limiting Amplifier Loss of Signal Truth Table
SQUELCH
LOS
Output
High
Low
High
Low
High
High
Low
Low
Off
On
On
On
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
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G52361-0, Rev 2.1
05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Absolute Maximum Ratings(1)
Power Supply Voltage (V )...............................................................................................................-0.5V to 6V
CC
Current into BIAS.................................................................................................................... -20mA to +150mA
Current into OUT+, OUT- .............................................................................................................................. TBD
Current into MD ............................................................................................................................ -5mA to +5mA
Current into FAIL .........................................................................................................................-10mA to 30mA
Voltage at DATA+, DATA-, ENABLE, LATCH, FAIL......................................................-0.5V to (V + 0.5V)
CC
Voltage at MODSET, BIASMAX, APCSET_MD .........................................................................-0.5V to +3.0V
Voltage at BIAS ..................................................................................................................-0.5V to (V + 0.5V)
CC
Voltage at OUT+, OUT-......................................................................................................-0.5V to (V + 1.5V)
CC
Continouous Power Dissipation (T = +85°C, TQFP derate 20.8mW/°C above +85°C)....................... 1350mW
A
Operating Junction Temperature Range ......................................................................................-55°C to +150°C
Storage Temperature Range.........................................................................................................-55°C to +165°C
NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Rail (V )..........................................................................................................................+3.3V
CC
Junction Temperature Range (T )................................................................................................-40°C to +100°C
J
Ambient Temperature Range (T ).................................................................................................-40°C to +85°C
A
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52361-0, Rev 2.1
05/01/01
Page 5
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Package Pin Descriptions
Figure 1: Pin Diagram
GND
SQUELCH
VCCA
GND
1
2
BIASMON
MODMON
GND
36
35
34
33
32
31
30
29
28
27
26
25
3
4
BIASMAX
MODSET
VCC
CZ1
5
CZ2
6
GND
7
GND
VSC7962
GND
8
RESERVED
APCSET_MD
CAPC
IN+
9
IN-
10
11
12
GND
NC
LEVEL
ENABLE
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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G52361-0, Rev 2.1
05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Table 8: Pin Description
Pin/Pad
Number
Pin Name
Pad Name
Section
Description
1, 4, 7, 8,
11, 16,
17, 23,
GNDA or
GND
GND
Both
Ground
30, 34,
41, 42, 44
3, 19, 22,
31, 37,
40, 43,
45, 48
VCC
VCC or VCCA
Both
3.3V Supply
Squelch Input. Squelch is disabled if this pin in unconnected or
set low. When SQUELCH is high, OUT+ and OUT- are forced
to static levels. See Detailed Description section.
Limiting
Amplifier
SQUELCH
CZ1
SQ
2
5
6
Offset Correction Loop Capacitor. Place capacitor between this
pin and CZ2 to alter time constant of offset correction loop.
See Detailed Description section.
Limiting
Amplifier
CZ1
CZ2
Offset Correction Loop Capacitor. Place capacitor between this
pin and CZ1 to alter time constant of offset correction loop.
See Detailed Description section.
Limiting
Amplifier
CZ2
Limiting
Amplifier
IN+
IN-
LAINP
9
Noninverted Limiting Amplifier Input Signal
Inverted Limiting Amplifier Input Signal
Limiting
Amplifier
LAINM
10
Output Current Level. This pin may be either connected to
GND or left unconnected. Connecting to GND causes output
Amplifier current to be 20mA. The output is 16mA when unconnected.
Limiting
LEVEL
LVL
12
See Detailed Description section.
Loss of Signal (LOS) Threshold. Connect a resistor from this
Limiting
TH
TH
13
14
15
pin to GND to set the input signal level at which LOS outputs
Amplifier
will be asserted. See Applications Information section.
Inverted Loss of Signal Output. LOS is high for input signals
above the threshold programmed by TH. See Detailed
Description section.
Limiting
Amplifier
LOS
LOS
LOS
LOS
Noninverted Loss-of-Signal Output. LOS is low for input
signals above the threshold programmed by TH. See Detailed
Description section.
Limiting
Amplifier
Laser
BIAS
OUT+
OUT-
BIAS
OUT+
OUT-
18
20
21
Laser Bias current output
Driver
Laser
Driver
Noninverted Laser Modulation Current Output. IMOD flows
when input data is high.
Laser
Driver
Inverted Laser Modulation Current Output. IMOD flows when
input data is low.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52361-0, Rev 2.1
05/01/01
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Pin/Pad
Number
Pin Name
Pad Name
Section
Description
Disable Input (TTL/CMOS). If used, leave ENABLE pin
floating. Connect to GND for normal operation and VCC to
disable laser bias and modulation currents.
Laser
Driver
DISABLE
DISABLE
24
Enable Input (TTL/CMOS). If used, connect DISABLE to
GND. Connect to VCC for normal operation and GND to
disable laser bias and modulation currents.
Laser
Driver
ENABLE
ENABLE
25
Laser
Driver
FAIL
FAIL
26
27
Output (TTL/CMOS). When low, indicates APC failure.
Laser
Driver
Capacitor to GND sets dominant pole of the APC feedback
loop.
CAPC
CAPC
APCSET and Monitor Diode Input. Resistor to GND sets
desired average laser optical power. If APC is not used connect
100kΩ resistor to GND. Connect to monitor photodiode anode.
Connect capacitor to ground to filter high-speed AC monitor
photocurrent.
Laser
Driver
APCSET_MD
APCSET_MD
28
Laser
Driver
RESERVED
MODSET
AUTSEL
MODSET
29
32
Do not connect.
Laser
Driver
Connect resistor to GND to set desired laser modulation
current.
Connect resistor to GND to set maximum laser bias current.
The APC function can subtract from this value, but it cannot
add to it.
Laser
Driver
BIASMAX
BIASMAX
33
Laser
Driver
Modulation current monitor. Sink current source that is
proportional to the laser modulation current.
MODMON
BIASMON
DATA+
DATA-
MODMON
BIASMON
DATA+
35
36
38
39
46
47
Laser
Driver
Bias current monitor. Sink current source that is proportional to
the laser bias current.
Laser
Driver
Laser Driver Noninverted Data Input (PECL)
Laser Driver Inverted Data Input (PECL)
Laser
Driver
DATA-
Limiting
Amplifier
LAO-
LAOM
Inverted Limiting Amplifier Data Output (PECL)
Noninverted Limiting Amplifier Data Output (PECL)
Limiting
Amplifier
LAO+
LAOP
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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G52361-0, Rev 2.1
05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Bare Die Pad Information
(37)
VCC
DISABLE (24)
(38) DATA+
(39) DATA-
GND
VCC
OUT-
OUT+
VCC
BIAS
GNDA
GNDA
LOS
(23)
(22)
(21)
(20)
(19)
(18)
(17)
(16)
(15)
(14)
(13)
VSC7939
(40)
(41)
(42)
(43)
VCC
GND
GND
VCC
(44) GNDA
(45) VCCA
(46) LAOM
VSC7962
(47)
LAOP
LOS
(48) VCCA
TH
Die Size Not Including Scribe: 2076µm x 2740µm (0.08174” x 0.10788”)
Scribe Size: 157µm (0.00618”)
Pad Passivation Opening: 95µm x 95µm (0.00374” x 0.00374”)
Pad Pitch: 130µm
Die Thickness: 625µm (0.02461”)
The back side of the die may be either left floating or connected to ground.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52361-0, Rev 2.1
05/01/01
Page 9
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Table 9: Pad Coordinates
Pad/Pin
Number
X-Coordinate
(µm)
Y-Coordinate
(µm)
Pad Name
Pin Name
Section
GNDA
SQ
GND
SQUELCH
VCC
1
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Laser Driver
322.500
452.500
80.950
80.950
2
VCCA
GNDA
CZ1
3
582.500
80.950
GND
4
712.500
80.950
CZ1
5
842.500
80.950
CZ2
CZ2
6
972.500
80.950
GNDA
GNDA
LAINP
LAINM
GNDA
LVL
GND
7
1102.500
1232.500
1362.500
1492.500
1622.500
1752.500
1995.050
1995.050
1995.050
1995.050
1995.050
1995.050
1995.050
1995.050
1995.050
1995.050
1995.050
1995.050
1752.500
1622.500
1492.500
1362.500
1232.500
1102.500
972.500
80.950
GND
8
80.950
IN+
9
80.950
IN-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
80.950
GND
80.950
LEVEL
TH
80.950
TH
324.475
514.475
704.475
894.475
1084.475
1274.475
1464.475
1654.475
1844.475
2034.475
2224.475
2414.475
2659.050
2659.050
2659.050
2659.050
2659.050
2659.050
2659.050
2659.050
2659.050
2659.050
2659.050
2659.050
LOS
LOS
LOS
LOS
GNDA
GNDA
BIAS
GND
GND
Laser Driver
BIAS
Laser Driver
VCC
VCC
Laser Driver
OUT+
OUT-
OUT+
OUT-
Laser Driver
Laser Driver
VCC
VCC
Laser Driver
GND
GND
Laser Driver
DISABLE
ENABLE
FAIL
DISABLE
ENABLE
FAIL
Laser Driver
Laser Driver
Laser Driver
CAPC
APCSET_MD
AUTSEL
GND
CAPC
APCSET_MD
RESERVED
GND
Laser Driver
Laser Driver
Laser Driver
Laser Driver
VCC
VCC
Laser Driver
MODSET
BIASMAX
GND
MODSET
BIASMAX
GND
Laser Driver
842.500
Laser Driver
712.500
Laser Driver
582.500
MODMON
BIASMON
MODMON
BIASMON
Laser Driver
452.500
Laser Driver
322.500
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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G52361-0, Rev 2.1
05/01/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Pad/Pin
Number
X-Coordinate
(µm)
Y-Coordinate
(µm)
Pad Name
Pin Name
Section
VCC
VCC
DATA+
DATA-
VCC
37
38
39
40
41
42
43
44
45
46
47
48
Laser Driver
Laser Driver
80.975
80.975
80.975
80.975
80.975
80.975
80.975
80.975
80.975
80.975
80.975
80.975
2414.475
2224.475
2034.475
1844.475
1654.475
1464.475
1274.475
1084.475
894.475
DATA+
DATA-
VCC
Laser Driver
Laser Driver
GND
GND
GND
VCC
Laser Driver
GND
Laser Driver
VCC
Laser Driver
GNDA
VCCA
LAOM
LAOP
VCC
GND
VCC
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
Limiting Amplifier
LAO-
LAO+
VCC
704.475
514.475
324.475
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52361-0, Rev 2.1
05/01/01
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Detailed Description
The VSC7962 is a combination limiting amplifier and high-speed laser driver with Automatic Power Con-
trol (APC). The device is designed to operate up to 3.125Gb/s with a 3.3V supply. The limiting amplifier pro-
vides Loss of Signal (LOS) detect, output offset correction, and output squelch. The limiting amplifier of the
VSC7962 has PECL outputs. The VSC7962 is identical to the VSC7960 except with CML limiting amplifier
outputs. The laser driver data and clock inputs support PECL inputs as well as other inputs that meet the com-
mon mode voltage and differential voltage swing specifications. The differential pair output laser driver stage is
capable of driving up to 60mA into the laser with typical rise and fall times of 60ps. To allow for larger output
swings, the VSC7962 was designed to be AC-coupled to the laser cathode with a pull-up inductor for DC-bias-
ing. This configuration will isolate laser forward voltage from the output circuitry and will allow the output at
OUT+ to swing above and below the supply voltage VCC. The laser driver output bias and modulation currents
may be easily controlled via external circuitry. The key features of the VSC7962 are Automatic Power Control,
Loss of Signal detect, low power supply current, and fast rise and fall times.
Figure 2: Limiting Amplifier Block Diagram
VCC
8kΩ
LOS
VCC
8k
Ω
TH
LOS
SQUELCH
LEVEL
RMS Power
Detect and
Control
Output Control
IN+
IN-
OUT+
OUT-
100Ω
Lowpass Filter
10pF
Offset Correction
CZ1
CZ2
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SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Figure 3: Laser Driver Block Diagram
VCC
CD
IOUT+
IOUT-
CF
RF
MUX
DATA+
DATA-
VCC
BIAS
VCC
VCC
ENABLE
DISABLE
MODMON
BIASMON
APC
FAIL
APCSET_MD
1nF
MODSET BIASMAX
CAPC
Limiting Amplifier Squelch
Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to
TTL high level and LOS is asserted, the data outputs, OUT+ and OUT- are forced to static levels. If LOS is not
asserted, the outputs will not be squelched.
Limiting Amplifier Loss of Signal (LOS) Detect
This features utilizes an RMS power detector with programmable LOS indicator to provide two outputs,
LOS and LOS. The input TH is used to set the threshold at which the loss of signal detector outputs, LOS and
LOS, change state. See Loss-of-Signal Specifications table (Table 6) for setting the resistor value between TH
and ground. The Loss of Signal Truth Table (Table 7) clarifies how LOS and SQUELCH interact.
Limiting Amplifier Offset Correction
This feature is provided to ensure that the offsets in the limiting amplifier coupled with its gain do not cause
the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a low-
frequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low
frequency cut-off is 2MHz. If a 0.1µF capacitor is placed between CZ1 and CZ2, the low frequency cut-off is
lowered to approximately 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2
open. For ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1µF capacitor
between CZ1 and CZ2. This maintains a one-decade separation between the lowest input frequency and the low
frequency cut-off. The low frequency cut-off of the offset correction loop is given by the following equation:
f
= 43 / [2π * 35k (C + 100pF)]
Z
OC
-6
= 196* 10 / (C + 100pF)
Z
-6
= 196* 10 / (0.1µF + 100pF)
= 1.96kHz
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SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Figure 4: Supply Current Measurement
VCC
ICC
A
IOUT
100Ω
100Ω
100Ω
100Ω
IMOD
VSC7959
A
IEE
VEE
Supply Current (ICC and IEE
)
Laser Driver Automatic Power Control
To ensure constant average optical power, the device utilizes an Automatic Power Control loop (APC). A
photodiode mounted in the laser package provides optical feedback to compensate for changes in average laser
output power due to changes that affect laser performance such as temperature and laser lifetime. The laser bias
current is adjusted by the APC loop according to the reference current set at APCSET_MD by an external resis-
tor. An external capacitor at CAPC controls the time constant for the APC feedback loop. The recommended
value for CAPC is 0.1µF. This value reduces pattern-dependent jitter associated with the APC feedback loop
and guarantees stability. If the APC loop cannot adjust the bias current to track the desired monitor current,
FAIL is set low.
The device may be operated with or without APC. To utilize APC, a capacitor must be connected at CAPC
(0.1µF) and a resistor must be connected at APCSET_MD to set the average optical power. For open-loop oper-
ation (no APC), a 100kΩ resistor should be connected between APCSET_MD and GND. CAPC has no effect
on open-loop operation. In both modes of operation, resistors to ground should be placed at BIASMAX and
MODSET to set the bias and modulation currents.
The device may be operated with or without APC. To utilize APC, a capacitor must be connected at CAPC
(0.1µF) and a resistor must be connected at APCSET_MD to set the average optical power. For open-loop oper-
ation (no APC), a 100kΩ resistor should be connected between APCSET_MD and GND. CAPC has no effect
on open-loop operation. In both modes of operation, resistors to ground should be placed at BIASMAX and
MODSET to set the bias and modulation currents.
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Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Laser Driver Short-Circuit Protection
If BIASMAX or MODSET are shorted to ground, the output modulation and bias currents will be turned
off.
Laser Driver Enable/Disable
Two pins are provided to allow either ENABLE or DISABLE control. If ENABLE is used, connect disable
to ground. If DISABLE is used, leave ENABLE floating. Both modulation and bias currents are turned off
when ENABLE is low or DISABLE is high. Typically, ENABLE or DISABLE responds within approximately
250ns.
Controlling the Laser Driver Modulation Current
The output modulation current may be determined from the following equation where P is peak-to-peak
p-p
optical power, P
is average power, r is extinction ratio, and η is laser slope efficiency:
e
AVE
I
= P / η= 2 * P
* (r -1) / (r +1) / η
MOD
p-p
AVE e e
A resistor at MODSET controls the output bias current. Graphs of IMODSET vs. RMODSET in Typical Operat-
ing Characteristics describe the relationship between the resistor at MODSET and the output modulation cur-
rent at 25°C. After determining the desired output modulation current, use the graph to determine the
appropriate resistor value at MODSET.
Controlling the Laser Driver Bias Current
A resistor at BIASMAX should be used to control the output bias current. Graphs of IBIASMAX Vs. RBIASMAX
in Typical Operating Characteristics describe the relationship between the resistor at BIASMAX and the output
bias current at 25°C. If the APC is not used, the appropriate resistor value at BIASMAX is determined by first
selecting the desired output bias current, and then using the graph to determine the appropriate resistor value at
BIASMAX. When using APC, BIASMAX sets the maximum allowed bias current. After determining the max-
imum end-of-life bias current at 85°C for the laser, refer to the graph of IBIASMAX Vs. RBIASMAX in Typical Oper-
ating Characteristics to select the appropriate resistor value.
Controlling the Laser Driver APC Loop
To select the resistor at APCSET_MD, use the graph of IMD vs. RAPCSET in Typical Operating Characteris-
tics. The graph relates the desired monitor current to the appropriate resistance value at APCSET_MD. IMD may
be calculate from the desired optical average power, PAVE,, and the laser-to-monitor transfer, ρMON, for a specific
laser using the following equation:
I
MD = PAV E * ρMON
Laser Diode Interface
An RC shunt network should be placed at the laser output interface. The sum of the resistor placed at the
output and the laser diode resistance should be 25Ω. For example, if the laser diode has a resistance of 5Ω, a
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Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
20Ω resistor should be placed in series with the laser. For optimal performance, a bypass capacitor should be
placed close to the laser anode.
A “snubber network” consisting of a capacitor CF and resistor RF should be placed at the laser output to
minimize reflections from the laser (see Block Diagram, page 1). Suggested values for these components are
80Ω and 2pF, respectively. However, these values should be adjusted until a suitable optical output waveform is
obtained.
Reducing Pattern-Dependent Jitter
Three design values significantly affect pattern-dependent jitter: the capacitor at CAPC, the pull-up induc-
tor at the output (LP), and the AC-coupling capacitor at the output (CD). As previously stated, the recommended
value for the capacitor at CAPC is 0.1µF. This results in a 10kHz loop bandwidth which makes the pattern-
dependent jitter from the APC loop negligible.
For 2.5Gb/s data rates, the recommended value for CD is 0.056µF. The time constant at the output is domi-
nated by LP. The variation in the peak voltage should be less that 12% of the average voltage over the maximum
consecutive identical digit (CID) period. The following equation approximates this time constant for a CID
period, t, of 100UI = 40ns:
τ
LP = -t / ln(1-12%) = 7.8t = LP / 25Ω
Therefore, the inductor LP should be a 7.8µH SMD ferrite bead inductor for this case.
Input/Output Considerations
Although the VSC7962 laser driver is PECL-compatible, this is not required to drive the device. The inputs
must only meet the common-mode voltage and differential voltage swing specifications.
Laser Driver Power Consumption
The following equation provides the device supply current (IS) in terms of quiescent current (IQ), modula-
tion current (IMOD), and bias current (IBIAS):
IS = IQ + 0.47 * IMOD + 0.15 * IBIAS
For 3.3V operation, IQ is 15mA.
This equation may be used to determine the estimated power dissipation:
P
DIS = VCC * IS
For example, the device operated at 3.3V with a 30mA modulation current and a 10mA bias current would
have a supply current of:
IS = 15mA + 0.47 * 30mA + 0.15 * 10mA = 31mA
This corresponds to a power dissipation of 3.3V * 31mA = 102mW.
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SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Typical Operating Characteristics
IMODSET vs. RMODSET
IBIASMAX vs. RBIASMAX
T=25°C, VCC = 3.3V
T=25°C, VCC = 3.3V
IMD vs. RAPCSET
T=25°C, VCC = 3.3V
,
Rise and Fall Times
T=85°C, VCC = 3.3V
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Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Monte Carlo Simulation of ICC
Applications Information
The following is a typical design example for the laser driver of the VSC7962 assuming 3.3V operation
with APC.
Select a Laser
The following table provides specifications for a typical communication-grade laser capable of operating at
2.5 Gb/s.
Table 10: Typical Laser Characteristics
Symbol
Parameter
Value
Units
λ
Wavelength
1310
nm
mW
PAVE
Ith
ρMON
η
Average Optical Output Power
Threshold Current
6
6
mA
Laser to Monitor Transfer
Laser Slope Efficiency
Operating Temperature Range
0.04
mA/mW
mW/mA
°C
0.4
TC
-40 to +85
Select Resistor for APCSET_MD
The monitor diode current is estimated by IMD = PAVE * ρMON = 6mW * 0.04mA/mW = 0.24mA. The IMD
vs. RAPCSET in Typical Operating Characteristics shows the resistor at APCSET_MD should be 5kΩ.
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3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Select Resistor for MODSET
To ensure some minimum extinction ratio over temperature and lifetime, assume an optimal extinction ratio
of 20 (13dB) at 25°C. The modulation current may be calculated from the following equation:
I
= P / η= 2 * P
* (r -1) / (r +1) / η = 2 * 6mA * (20-1) / (20 + 1) / 0.4 = 27.1mA
MOD
p-p
AVE e e
The graph of IMODSET vs. RMODSET in Typical Operating Characteristics shows the resistor for MODSET
should be 8.5kΩ.
Select Resistor for BIASMAX
The maximum threshold current at +85°C and end-of-life must be determined. A graph of a typical laser’s
I versus TC reveals a maximum threshold current of 30mA at 85°C. Therefore, the maximum bias can be
th
approximated by:
IBIASMAX = ITH-MAX + IMOD / 2 = 30mA + 27.1mA / 2 = 43.6mA
The graph of IBIASMAX vs. RBIASMAX in Typical Operating Characteristics shows the resistor for BIASMAX
should be 5kΩ.
Wire Bonding
For best performance gold ball-bonding techniques are recommended. Wedge bonding is not recom-
mended. For best performance and to minimize inductance keep wire bond lengths short.
PCB Layout Guidelines
Use high frequency PCB layout techniques with solid ground planes to minimize crosstalk and EMI. Keep
high speed traces as short as possible for signal integrity. The output traces to the laser diode must be short to
minimize inductance. Short output traces will provide best performance.
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Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Package Information - 48-pin TQFP
1. All dimensioning and tolerancing conform to ANSI Y14.5-1982.
2. Controlling dimension: millimeter.
3. This outline conforms to JEDEC Publication 95 Registration MS-026.
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SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
Ordering Information
The order number for this product is formed by a combination of the device type and package type.
XX
VSC7962
Device Type
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
Package Style:
W : Bare Die in Waffle Pack
RO : 48-pin TQFP
Notice
Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production
information about Vitesse products in their concept, development and/or testing phase. All informaiton in this document, including descriptions of
features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this
document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or
will be suitable for or will accomplish any particular task.
Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without writ-
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Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
and Laser Driver with Automatic Power Control
VSC7962
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