VSC7969-W [VITESSE]
Telecom Circuit, 1-Func, DIE-26;
| 型号： | VSC7969-W |
| 厂家： | 
VITESSE SEMICONDUCTOR CORPORATION |
| 描述： | Telecom Circuit, 1-Func, DIE-26 放大器 |
| 文件： | 总14页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Features
Applications
• Integrated TIA and Limiting Amplifier
• Low Power Consumption for SFF Applications
• TO Package-Compatible Layout
• 2.488Gb/s, 3.125Gb/s SONET OC-48/
SDH STM-16
• 2.125Gb/s Fibre Channel
• On-Chip Signal Detect
• 2.5Gb/s or 3.125Gb/s Ethernet Applications with
• On-Chip Linear Photocurrent Monitor
• Single 3.3V Supply
8B/10B Overhead
• SFF Transceivers
• 5V Supply Operation via Wirebond Option
• Compatible with PIN or Avalanche Detectors
• Packages: 16-Pin TSSOP, TO-46, Bare Die
General Description
The VSC7969 is a 3.125Gb/s transimpedance amplifier IC with a built-in limiting amplifier, a signal detect
feature and a photocurrent monitor. The VSC7969 does not require any external electrical components in the
construction of a high performance optical receiver such as for SONET/SDH applications. The analog output is
a differential signal with a minimum amplitude of 200mVp-p (single-ended). The VSC7969 operates with a sin-
gle power supply with a maximum power dissipation of 300mW. A PIN photodiode or APD can be connected
and separately biased to provide optimal performance.
The VSC7969 provides filtered bias for MSM and PIN photodetectors; applications using an APD photode-
tector must supply bias separately. The VSC7969 also provides a photocurrent monitor whose output is linearly
proportional to the input photocurrent.
The VSC7969 can operate from a single +3.3V supply or a +5V or -5.2V supply. The VSC7969 is offered
in die form and in a 16-pin plastic thin-shrink small outline package (TSSOP-16). A fully tested TO-46 outline
packaged receiver with a photodetector is also available.
Block Diagram
Dual power supply pins are
provided for +5V or +3.3V
VCCS
operation. Only one power
supply pin should be connected.
Filter
+3.3V
+5V
Regulator
VCCD
GND
+3.3V
Outputs need to
be AC-coupled
50Ω
50Ω
VOUTP
VOUTN
In
0.1µF
0.1µF
Signal
Detect
SD_OUT
SD_ADJ
IMON
Monitor
VSC7969
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52355-0, Rev 2.0
02/09/01
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Electrical Characteristics
Table 1: AC Specifications
Symbol
Parameter
Min
Typ
Max Units
Conditions
Peak-to-peak AC current
amplitude
∆IPH
Input Photocurrent Swing
2.2
mA
µA
-23dBm average optical power
with a detector responsitivity of
0.8A/W.
IPHS-AVG
Average Photocurrent Sensitivity
Peak Input Photocurrent Sensitivity
4
8
-23dBm average optical power
with a detector responsitivity of
0.8A/W.
IPHS-PEAK
µA
Single-Ended Output Voltage
Amplitude
Single-ended peak-to-peak
measurement, IIN >20µA.
∆VOUT-SE
∆VOUT-DIFF
tR, tF
200
250
500
300
600
mV
mV
Differential peak-to-peak
measurement, IIN >20µA.
Differential Output Voltage Amplitude 400
Rise and Fall Time
At 2.2mAp-p input photocurrent
swing. 20% to 80%.
60
27k
1
100
40k
ps
Ω
(1)
ZT
Transimpedance Gain
20k
Differential measurement
Modulation frequency between FL
and BW
(1)
∆ZT
Ripple in Passband Transimpedance
dB
Referenced to 10MHz,
CPD = 0.6pF
BW
FL
Upper -3dB Bandwidth
2.2
2.5
3.0
GHz
Referenced to 10MHz, CPD =
0.6pF with no external
components
Lower -3dB Cutoff Frequency
100
kHz
ZO
Output Impedance
50
TBD
500
0.6
2
Ω
Single-ended
PSRR
INOISE
CPD
Power Supply Rejection Ratio
Input-Referred rms Noise Current
Photodetector Capacitance
Signal Detect Hysterisis
nA
pF
dB
30kHz to 2.5GHz
0.4
1
0.8
4
Bias voltage on detector at 2.0V
Electrical measurement on SD pin
SDH
Average photocurrent with SD
open.
SDA-OPEN
SDD-OPEN
SDA-SHORT
SDD-SHORT
Signal Detect Assertion Level
Signal Detect Deasseration Level
Signal Detect Asseration Level
Signal Detect Deasseration Level
3
5
9
µA
µA
µA
µA
Average photocurrent with SD
open.
1.0
6
2.2
10
4.4
3.0
18
6.0
Average photocurrent with SD
shorted to ground.
Average photocurrent with SD
shorted to ground.
2.0
VCCS
- 0.3
SDHIGH
SDLOW
Signal Detect HIGH Logic Level
Signal Detect LOW Logic Level
V
V
0.5
0.8
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
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Page 2
G52355-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Symbol
Parameter
Min
Typ
Max Units
Conditions
Slope of Linear Analog Photocurrent
Monitor vs Input Optical Power
0Ω to 2kΩ to VCC with a detector
responsitivity of 0.8A/W
MON
DC
0.8
µA/µW
Duty Cycle
-5
5
+5
200
10
%
µA
µA
ps
IMONRANGE Photocurrent Monitor Linearity Range
IMONOFFSET Photocurrent Monitor Offset
0
RJ
DJ
Random Jitter(2)
Deterministic Jitter(3)
TBD
TBD
Peak-to-peak
Peak-to-peak
ps
NOTES: (1) The transimpedance gain is defined as Z = (∆V
)/∆I . (2) Using 1111100000 pattern at 2.5Gb/s to measure the
PH
T
OUT - DIFF
standard deviation of the edge of the pattern, multiply the standard deviation by 14 to achieve the total random jitter. (3) +K28.5
- K28.5 (00111110101100000101).
Table 2: DC Specifications
Symbol
Parameter
Negative Supply Rail
Min
Typ
Max Units
Conditions
GND
VCCS
VCCD
ICC
0
3.3
V
Positive Supply Rail for 3.3V Operation
Positive Supply Rail for 5V Operation
Power Supply Current
3.0
4.5
3.6
5.5
75
V
V
5.0
65
mA
3.3V
VCCS
125mV
-
Applicable to VOUTP and
VOUTN pins at 50Ω load.
VOUT-CM
VANODE
VCATHODE
VCAT-EXT
VAPD
Common-Mode Voltage on Output Pins
Internal DC Bias Voltage on Detector
Anode Contact
0.8
0.9
1.0
VCCS
10
V
V
V
V
Interal DC Bias Voltage on Detector
Cathode Contact
VCCS -
0.15V
External DC Bias Voltage Permissable
on Detector Cathode Contact
3.3
60
External DC Bias Voltage for Use with
Avalanche Photodetector
Absolute Maximum Ratings(1) (at TA = +25°C, unless otherwise specified)
Power Supply Voltage (V
Power Supply Voltage (V
)......................................................................................................................... 3.6V
CCS
) ........................................................................................................................ 5.5V
CCD
Junction Temperature Range ........................................................................................................-40°C to +125°C
Storage Temperature Range .........................................................................................................-40°C to +125°C
Relative Ambient Humidity ................................................................................................................. 85%/+85°C
NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Supply (V
Positive Voltage Supply (V
)...................................................................................................................... 3.3V
CCS
)...................................................................................................................... 5.0V
CCD
Negative Voltage Rail (GND) ............................................................................................................................ 0V
(1)
Ambient Temperature Range (T ) ..............................................................................................-40°C to +85°C
A
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52355-0, Rev 2.0
02/09/01
Page 3
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Bare Die Descriptions
Figure 1: Pad Assignments
1467µm (57.2mil)
Pad 6
VOUTN
Pad 7
SD_OUT
Pad 8
GND
Pad 9
VOUTN
Pad 10
GND
Pad 11
VOUTP
Pad 12
GND
Pad 13
IMON
Pad 14
VOUTP
Pad 5
SD_ADJ
Pad 15
GND
Pad 4
SD_TP
Pad 16
CSDN
1143µm
(45.0mil)
Pad 3
GND
Pad 17
CSDP
VSC7969
Pad 2
BG_VREF
Pad 18
GND
Pad 1
GND
Pad 19
GND
Pad 26
VCCD
Pad 25
VCCS
Pad 24
GND
Pad 23
IN
Pad 22
FILTER
Pad 21
GND
Pad 20
GND
Die Size: 1143µm x 1453µm (45.0mil x 57.2mil)
Die Thickness: 279µm (11.0mil)
Pad Size: 100µm x 100µm (3.9mil x 3.9mil)
Pad Passivation Opening: 86µm x 86µm (3.4mil x 3.4mil)
Scribe Size: 143µm (5.6mil)
143µm
(5.6mil)
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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G52355-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Table 3: Pad Coordinates
Coordinates (µm)
Signal
Name
Pad
Number
Description
X
Y
GND
1
2
3
4
130
130
130
130
250
375
500
625
Negative power supply rail (typically 0V)
BG_VREF
GND
Band Gap voltage reference 1.24V for testpoint, no connect
Negative power supply rail (typically 0V)
SD_TP
Signal Detect test point, DO NOT CONNECT.
Signal Detect threshold adjustment (see Application amd Usage
section)
SD_ADJ
VOUTN
5
6
130
137
750
875
Complementary logic output (logic LOW when photocurrent is
HIGH)
Signal detect output (logic HIGH when photocurrent exceeds
SDA)
SD_OUT
GND
7
8
9
280
405
530
875
875
875
Negative power supply rail (typically 0V)
Complementary logic output (logic LOW when photocurrent is
HIGH)
VOUTN
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
655
780
875
875
875
875
875
750
625
500
375
250
125
125
125
125
125
125
125
Negative power supply rail (typically 0V)
VOUTP
GND
Positive logic output (logic HIGH when photocurrent is HIGH)
Negative power supply rail (typically 0V)
905
IMON
VOUTP
GMD
CSDN
CSDP
GND
1030
1173
1180
1180
1180
1180
1180
1030
905
Photocurrent Monitor
Positive logic output (logic HIGH when photocurrent is HIGH)
Negative power supply rail (typically 0V)
Test point for Signal Detect capacitor. DO NOT CONNECT.
Test point for Signal Detect capacitor. DO NOT CONNECT.
Negative power supply rail (typically 0V)
GND
Negative power supply rail (typically 0V)
GND
Negative power supply rail (typically 0V)
GND
Negative power supply rail (typically 0V)
FILTER
IN
780
Photodetector cathode connection (filtered VCC
)
530
Photodetector anode connection
GND
405
Negative power supply rail (typically 0V)
Positive power supply rail for 3.3V operation
Positive power supply rail for 5V operation
VCCS
VCCD
280
137
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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02/09/01
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Package Pin Descriptions
Figure 2: Pin Diagram
VCC
GND
GND
IN
1
2
3
4
5
6
7
8
SD_ADJ
SD_OUT
GND
16
15
14
13
12
11
10
9
VOUTN
VOUTP
GND
VSC7969
FILTER
GND
GND
GND
GND
IMON
Table 4: Pin Identifications
Pin Name Pin No.
Description
VCC
1
2
Power Supply
Ground
GND
GND
3
Ground
IN
4
Photodetector Anode Connection
Photodetector Cathode Connection (filtered VCC)
FILTER
GND
5
6
Ground
GND
7
Ground
GND
8
Ground
IMON
GND
9
Photocurrent Monitor
Ground
10
11
12
13
14
15
16
GND
Ground
VOUTP
VOUTN
GND
Positive Logic Output (logic HIGH when photocurrent is HIGH)
Complementary Logic Output (logic LOW when photocurrent is HIGH)
Ground
SD_OUT
SD_ADJ
Signal Detect Output (logic HIGH when photocurrent exceeds SDA)
Signal Detect Threshold Adjustment (see Applications and Usage section)
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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G52355-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Typical Operating Characteristics
Electrical Eye Diagram,
Input = 8µAp-p, 3.125Gb/s, PRBS 231-1
TA = º+25C, VCC = 3.3V
Electrical Eye Diagram,
Input = 100µAp-p, 3.125Gb/s, PRBS 231-1
TA = º+25C, VCC = 3.3V
IMON Characteristic,
0µA to 200µA Input
Bit Error Rate vs Input Level
I
MON CHARACTERISTIC
0µA to 200µA Input
BIT ERROR RATE vs INPUT LEVEL
1.00E-07
250
200
150
100
50
1.00E-08
1.00E-09
1.00E-10
1.00E-11
1.00E-12
1.00E-13
0
6.0
6.5
7.0
7.5
8.0
8.5
0
50
100
150
200
IN (IPD) (µAp-p)
IN (DC Current) (µA)
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02/09/01
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Circuit Description
The VSC7969 data path consists of several stages: transimpedance input stage, limiting amplifier, and out-
put driver. The transimpedance amplifier accepts current from a photodetector connected to the input pad ‘IN’
and converts the input current to a differential output voltage. The signal then travels to the second stage limit-
ing amplifier which provides DC restoration, eliminating the DC component of the input signal. The linear pho-
tocurrent monitor and signal detect function is also provided by this stage. The final stage consists of an output
driver with a differential pair connected to V via 50Ω internal pull-up resistors. The overall effective differ-
CC
ential transimpedance of the VSC7969 is typically 27kΩ. The limited output single-ended voltage swing is typ-
ically 250mVp-p.
Design Guidelines
Power Supply
The VSC7969 is supplied by a single supply voltage; for +3.3V operation, the supply votlage should be
applied to only V
. For +5V operation, the supply voltage should be applied to only V
.
CCD
CCS
Data Outputs
The outputs of the VSC7969 need to be AC-coupled. This capacitor will determine the low frequency cut-
off for the system, which is directly related to the receiver’s deterministic jitter. For ATM/SONET or other
applications using PRBS NRZ data, select a capacitor of at least 0.1µF or greater, which provides less than
32kHz low frequency cutoff. For Fibre Channel, Gigabit Ethernet, or other applications requiring 8B/10B data
coding, select a capacitor of at least 0.01µF or greater, which provides less than 320kHz low frequency cutoff.
The outputs can be used single-ended or differential. For best performance, differential operation is recom-
mended. If single-ended operation is necessary, the unused output should be AC-coupled and terminated with
an impedance equal to the load on the pin in use.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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G52355-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Signal Detect
The signal detect feature of the VSC7969 provides a CMOS level output corresponding to the input current
level to the transimpedance amplifier. The assert and deassert levels of the signal detect pin can be adjusted by
placing an optional resistor from SD_ADJ to ground. The following tables show the two extremes at which the
signal detect pin will operate; open circuit and short-ciruit to ground.
Table 5: Signal Detect Function, SD_ADJ Open
Electrical
Min
Typ
Max
Units
Assert
3
1
1
5
2.2
2
9
3
4
µA
µA
dB
Deassert
Hysteresis
With SD_ADJ (pin 16) shorted to ground, thresholds are 3dB higher, as shown in Table 6.
Table 6: Signal Detect Function, SD_ADJ Shorted to Ground
Electrical
Min
Typ
Max
Units
Assert
6
2
1
10
4.4
2
18
6
µA
µA
dB
Deassert
Hysteresis
4
Photodetector Current Monitor
The IMON pin provides a linear measurement of the average input current from the photodetector to the
transimpedance amplifier. For example, if 20µA is the average input current to the transimpedance amplifier,
the current through the IMON pin will be 20µA (see the typical operating curve “IMON Characteristic, 0µA to
200µA). To use this feature, connect the IMON pin to V using a resistor less than 2kΩ. If this feature is not
CC
used, the IMON pin can be left unconnected.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
G52355-0, Rev 2.0
02/09/01
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Application Information
VCC
IMON
VOUTP
GND
NOTES:
No external components required.
Unused output is AC-coupled and terminated to 50Ω.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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G52355-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Package Information
TSSOP-16
1. All dimensioning and tolerancing per ASME.Y14.5-1994
2. Controlling dimension: millimeter
3. This outline conforms to JEDEC Publication 95 Registration MS-026
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02/09/01
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
TO-46 Ball Lens Package
TOP VIEW
SIDE VIEW
1. Controlling dimenstion: millimeter
Reference Isometric
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SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
TO-46 Flat Window Package
TOP VIEW
Reference Isometric
1. Controlling dimension: millimeter
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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02/09/01
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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
VSC7969
Ordering Information
The order number for this product is formed by a combination of the device type and package type.
xx
VSC7969
Device Type
3.125Gb/s Integrated Transimpedance
and Limiting Amplfier with Signal Detect
Package
YD1: TSSOP-16, 3.3V Supply
YD2: TSSOP-16, 5V Supply
W:
Dice Waffle Pack
WD1A: TO-46 Ball Lens, 3.3V Supply, VOUTN/VOUTP Outputs
WD1B: TO-46 Ball Lens, 3.3V Supply, VOUTN/IMON Outputs
WD2A: TO-46 Ball Lens, 5V Supply, VOUTN/VOUTP Outputs
WD2B: TO-46 Ball Lens, 5V Supply, VOUTN/IMON Outputs
Notice
Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production
information about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of
features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this
document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or
will be suitable for or will accomplish any particular task.
Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without writ-
ten consent is prohibited.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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G52355-0, Rev 2.0
02/09/01
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