VSC7961YD-1 [MICROSEMI]
Amplifier,;
Microsemi 
VSC7961
Data Sheet
PECL Limiting Amplifier with LOS Detect
FEATURES
● +3.3V or +5V Power Supply
APPLICATIONS
● SONET/SDH at 155Mb/s, 622Mb/s, 1.244Gb/s, and
2.488Gb/s
● Typical Supply Current of 31mA
● Positive Emitter-Coupled Logic Outputs
● Optional Output Squelch
● Full-Speed Fibre Channel (1.062Gb/s/2.124Gb/s)
● Small Form Factor Receivers
● ATM Optical Receivers
● Loss of Signal Detect
● Output Offset Correction
● Typical Rise/Fall Times of Faster than 100ps
● TSSOP-16 and 24-Pin QFP-N Package, and Bare Dice
GENERAL DESCRIPTION
The VSC7961 is a single-supply limiting amplifier with Loss of Signal (LOS) detect for SONET/SDH and Fibre
Channel applications up to 2.5Gb/s. The VSC7961 provides a constant output signal swing for a wide range of input
voltages and has positive emitter-coupled logic (PECL) outputs. The VSC7959 provides the same functionality as the
VSC7961 with current-mode logic (CML) outputs. Key features of the VSC7961 are its rms power detectors for
programmable LOS detection, optional output squelch, excellent jitter performance, and fast edge rates. The
VSC7961 is available in die form, a TSSOP-16 package, or a 24-pin QFP-N package.
VSC7961 Block Diagram
VCC
VSC7961
8kΩ
LOS
VCC
TH
8kΩ
LOS
RTH
VCC
rms Power Detect
and
SQUELCH
LEVEL
Output
Control
Control
0.01µF
0.01µF
IN+
IN-
OUT+
OUT-
100Ω
50Ω
VCC - 2V
50Ω
Lowpass Filter
10pF
VCC - 2V
Offset Correction
CZ1
CZ2
0.1µF
G52360 Revision 4.1
October 28, 2003
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: prodinfo@vitesse.com
Internet: www.vitesse.com
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VSC7961
Data Sheet
ELECTRICAL SPECIFICATIONS
Over Recommended Operating Conditions.
Table 1. DC Specifications
Symbol Parameter
Min
Typ
Max
5.5
37
Units
V
Condition
VCC
IEE
Power Supply Voltage
3.135
Power Supply Current(1)
31
35
59
62
23
30
62
67
mA
mA
mA
mA
mA
mA
mA
mA
µA
VCC = 3.3V
43
V
CC = 5V
VCC = 3.3V
CC = 5V
VCC = 3.3V
CC = 5V
VCC = 3.3V
CC = 5V
ICC
Power Supply Current Including Load
Current(1)
67
72
V
IEESQ
Power Supply Current When
Squelched(1)
30
35
V
ICCSQ
Power Supply Current Including Load
Current When Squelched(1)
72
75
V
ISQ
Squelch Input Current
0
400
PSRR
Power Supply Rejection Ratio
20
dB
f < 2MHz, VIN = 100mV
1. See Figure 1 for supply current measurement setup.
All AC voltage measurements are differential peak-to-peak, unless otherwise specified.
Table 2. AC Specifications
Symbol Parameter
Maximum Data Rate
Min
2.5
5
Typ
Max
Units Condition
Gb/s
mV
VIN
JD
Input Voltage Range
Deterministic Jitter(1)
1200
35
ps
ps
V
IN >10mV.
50
VIN = 5mV, VCC = +3.3V.
JR
Random Jitter(2)
9
ps
rms, VIN > 10mV.
VIN = 5mV, VCC = +3.3V.
11
90
ps
t
R, tF
Rise and Fall Times
120
230
ps
20% to 80%, VIN >10mV.
20% to 80%, VIN = 5mV, VCC = +3.3V.
rms, IN+ to IN–.
140
ps
VN
Input Referred Noise
µV
Ω
RDIFF
fL
Differential Input Resistance
Low Frequency Cutoff
100
2
IN+ to IN–.
MHz
kHz
mV
V
CZ open.
2
CZ = 0.1µF.
VSQ
VOH
Output Signal When Squelched
PECL Output HIGH Voltage
40
Output AC-coupled.
Tested at 3.3V.
VCC
–
VCC
–
0.105
0.85
VCC
0.85
–
V
V
V
Tested at 3.3V. Squelched.
Tested at 3.3V.
VOL
PECL Output LOW Voltage
VCC
–
VCC
1.47
–
1.81
VCC
–
Tested at 3.3V. Squelched.
0.95
1. Deterministic jitter measured peak-to-peak with K28.5 pattern.
2. Random jitter measured with minimum input.
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Data Sheet
Table 3. Loss of Signal Specifications
Symbol
Parameter
Min
Typ
Max
Units Condition
HLOS
LOS Hystersis
2.2
4.0
5.5
dB
HLOS = 20 log (VTHD/VTHA)
K28.5 pattern.
tLOS
LOS Assert/Deassert Time
LOS Assert Threshold
1.0
µs
Response time for a 10dB
change in input power.
VTHA
VTHD
15
mV
mV
RTH = 5.6kΩ, f = 2.5Gb/s,
K28.5 pattern
LOS Deassert Threshold
35
RTH = 5.6kΩ, f = 2.5Gb/s,
K28.5 pattern.
VLOSH
VLOSL
LOS Output HIGH Voltage
LOS Output LOW Voltage
2.4
3.5
V
V
ILOS = –30µA.
ILOS = 1.2mA.
0.3
Table 4. Loss of Signal Truth Table
SQUELCH
HIGH
LOS
LOW
HIGH
HIGH
LOW
Output
On
LOW
On
HIGH
Off
LOW
On
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Data Sheet
Recommended Operating Conditions
Table 5. Recommended Operating Conditions
Symbol Parameter
Min
+3.3
–40
Typ
Max
+5
Units
V
Condition
VCC
T
Power Supply Voltage
Operating Temperature Range Under Bias(1)
+85
°C
1. Lower limit of specification is ambient temperature and upper limit is case temperature.
Absolute Maximum Ratings
Table 6. Absolute Maximum Ratings
Symbol Parameter
Min
–0.5
Max
Units
V
Condition
VCC
Power Supply Voltage
+6
VCC + 0.5
VCC + 0.5
2.5
Voltage at IN+, IN–
VCC – 3
–0.5
V
Voltage at SQUELCH, LOS, LOS, TH, LEVEL
Differential Input Voltage (IN+, IN–)
Continuous Current at PECL Outputs (OUT+, OUT–)
Current into LOS, LOS
V
V
25
mA
mA
°C
°C
V
–2
–55
+3
TJ
Junction Temperature
+125
TS
Storage Temperature
–55
+150
VESD
ESD Voltage (Human Body Model)
–2500
+2500
Stresses listed under Absolute Maximum Ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values
listed is not implied. Exposure to these values for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE
This device can be damaged by ESD. Vitesse recommends that all integrated circuits
be handled with appropriate precautions. Failure to observe proper handling and
installation procedures may adversely affect reliability of the device.
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Data Sheet
FUNCTIONAL DESCRIPTION
The VSC7961 is a high-speed limiting amplifier with LOS detect. The VSC7961 is designed to operate with a +3.3V
or +5V supply in SDH/SONET and Fibre Channel applications up to 2.5Gb/s. The VSC7961 has PECL outputs (the
VSC7959 provides the same functionality as the VSC7961 with CML outputs). Key features of the VSC7961 are
LOS detect, output offset correction, output squelch, low power supply current, and fast rise and fall times.
The inputs of the VSC7961 provide 100Ω input impedance between IN+ and IN– and are intended to be AC-coupled.
The PECL output circuits should be terminated through 50Ω to V – 2V. If the outputs are to be AC-coupled, the
CC
VSC7959 is the preferred device as it will dissipate less power.
LOS Detect
The LOS Detect feature utilizes an rms power detector with programmable LOS indicator to provide two outputs,
LOS and LOS. The input, TH, is used to set the threshold at which the LOS detector outputs, LOS and LOS, change
state. See Table 3, “Loss of Signal Specifications” on page 3 for setting the resistor value between TH and ground.
Table 4, “Loss of Signal Truth Table” on page 3 clarifies the interaction of LOS and SQUELCH.
Optional Squelch
Squelch is disabled when SQUELCH is not connected or is set to TTL LOW level. When SQUELCH is set to TTL
HIGH level and LOS is asserted, the data outputs, OUT+ and OUT– are forced to static levels. If LOS is not asserted,
the outputs will not be squelched.
Offset Correction
The offset correction feature is provided to ensure that the offsets in the limiting amplifier, coupled with its gain, do
not cause the output buffer to give a false output. Because of the high gain of the amplifier, offset correction using a
low-frequency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low-
frequency cut-off is 200kHz. If a 0.1µF capacitor is placed between CZ1 and CZ2, the low-frequency cut-off is
lowered to approximately 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open.
For ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1µF capacitor between CZ1
and CZ2. This maintains a one-decade separation between the lowest input frequency and the low-frequency cut-off.
The low-frequency cut-off of the offset correction loop is given by the following equation:
f
= 43 / [2π * 35k (C + 100pF)]
(EQ 1)
OC
Z
–6
= 196 • 10 / (C + 100pF)
Z
–6
= 196 • 10 / (0.1µF + 100pF)
= 1.96kHz
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VSC7961
Data Sheet
.
VCC
60µA
ICC
VSC7961
OUT+
OUT-
50Ω
VCC - 2V
50Ω
VCC - 2V
IIMOD
60µA
IEE
Supply Current: ICC and IEE
VEE
Figure 1. Supply Current Measurement
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Data Sheet
TYPICAL OPERATING CHARACTERISTICS
Tested at T = +25°C unless specified otherwise.
A
Differential Voltage Input = 10mVp-p
f = 3.125Gb/s, VCC = +2V, VEE = –1.3V
Differential Voltage Input = 1200mVp-p
f = 3.125Gb/s, VCC = +2V, VEE = –1.3V
Differential Voltage Input vs. Voltage Output
1000
800
600
400
200
0
5V
3.3V
0
5
10
15
Differential Voltage Input (mVp-p)
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Data Sheet
LOS Sensitivty
LOS Hysterisis
f = 2.5GHz, K28.5 Pattern
f = 2.5Gb/s, K28.5 Pattern
12k
10k
8k
5
4
3
2
1
0
Assert
6k
Deassert
4k
2k
0k
0
10
20
30
40
50
0
2k
4k
6k
8k
10k
12k
Differential Voltage Input (mVp-p)
Threshold Resistance (Ω)
LOS Typical Distribution
LOS Typical Distribution
Assert/Deassert, RTH = 5.6kΩ
Hysterisis, RTH = 5.6kΩ
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
Hysterisis
Assert
Deassert
0
0
Voltage Input Level (mVp-p)
Hysterisis (dB)
PCB LAYOUT GUIDELINES
Use high frequency PCB layout techniques with solid ground planes to minimize crosstalk and EMI. Keep high-speed
traces as short as possible for signal integrity. The output traces to the laser diode must be short to minimize
inductance. Short output traces will provide best performance.
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Data Sheet
BARE DICE AND PACKAGE INFORMATION
1597µm (0.06287")
Pad1
CAZ1
Pad 16
NC
Pad 2
CAZ2
Pad 15
SQ
Pad 3
GND
Pad 14
VCC
Pad 4
LAINP
Pad 13
LAOP
VSC7961
Top View
1597µm
(0.06287")
Pad 5
LAINM
Pad 12
LAOM
Pad 6
GND
Pad 11
VCC
Pad 7
NC
Pad 10
LOS
Pad 8
TH
Pad 9
LOS
Die Size Including Scribe:
Die Size Not Including Scribe: 1440µm x 1440µm (0.0567 x 0.0567")
Pad Pitch:
1597µm x 1597µm (0.0629" x 0.0629")
180µm (0.0071")
Pad Passivation Opening:
Die Thickness:
95µm x 95µm (0.0037" x 0.0037")
280µm (0.011")
The back side of the die may either be left floating or connected
to the most negative potential.
Figure 2. Pad Diagram for Bare Die (-W)
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Data Sheet
Table 7. Coordinates for Bare Dice (-W)
Coordinates (µm)
Pad/Pin
Pad Name
Pin Name Number
X
Y
Description
CZ1
CZ1
1
270.525
1359.05
Offset Correction Loop Capacitor. Place capacitor between
this pin and CZ2 to alter time constant of offset correction
loop. See “Functional Description” on page 5.
CZ2
CZ2
2
80.95
1170.525 Offset Correction Loop Capacitor. Place capacitor between
this pin and CZ1 to alter time constant of offset correction
loop. See “Functional Description” on page 5.
GND
LAINP
LAINM
GND
GND
IN+
3
4
5
6
7
80.95
80.95
80.95
80.95
80.95
990.525
810.525
630.525
450.525
270.525
Supply ground.
Noninverted input signal.
Inverted input signal.
Supply ground.
IN–
GND
NC
NC
This pin may be either connected to ground or left uncon-
nected. This pin does not effect the performance of the
device.
TH
TH
8
9
270.525
1169.475
1359.05
80.95
80.95
Loss of Signal (LOS) Threshold. Connect a resistor from this
pin to ground to set the input signal level at which LOS out-
puts will be asserted.
LOS
LOS
LOS
LOS
Inverted Loss of Signal Output. LOS is HIGH for input signals
above the threshold programmed by TH. See “Functional
Description” on page 5.
10
270.525
Noninverted Loss of Signal Output. LOS is LOW for input sig-
nals above the threshold programmed by TH. See “Functional
Description” on page 5.
VCC
LOAM
LAOP
VCC
SQ
VCC
OUT–
11
12
13
14
15
1359.05
1359.05
1359.05
1359.05
1359.05
450.525
630.525
810.525
990.525
Power supply.
Inverted data output.
Noninverted data output.
Power supply.
OUT+
VCC
SQUELCH
1170.525 Squelch Input. Squelch is disabled if this pin is unconnected
or set LOW. When SQUELCH is HIGH, OUT+ and OUT– are
forced to static levels. See “Functional Description” on page 5.
NC
NC
16
1169.475
1359.05
No connection.
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Data Sheet
CZ1
CZ2
GND
IN+
1
2
3
4
5
6
7
8
NC
16
15
14
13
12
11
10
9
SQUELCH
VCC
OUT+
OUT−
VCC
VSC7961
Top View
IN-
GND
NC
LOS
TH
LOS
Figure 3. Pin Diagram for TSSOP-16 (YD)
Table 8. Pin Identification for TSSOP-16 (YD)
Pin Name
Pin Number
Description
CZ1
1
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time con-
stant of offset correction loop. See “Functional Description” on page 5.
CZ2
2
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time con-
stant of offset correction loop. See “Functional Description” on page 5.
GND
IN+
3
4
5
6
7
Supply ground.
Noninverted input signal.
Inverted input signal.
Supply ground.
IN–
GND
NC
This pin may be either connected to ground or left unconnected. This pin does not affect the per-
formance of the device.
TH
8
9
Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal
level at which LOS outputs will be asserted.
LOS
LOS
Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed
by TH. See “Functional Description” on page 5.
10
Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold pro-
grammed by TH. See “Functional Description” on page 5.
VCC
11
12
13
14
15
Power supply.
OUT–
OUT+
VCC
Inverted data output.
Noninverted data output.
Power supply.
SQUELCH
Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is
HIGH, OUT+ and OUT– are forced to static levels. See “Functional Description” on page 5.
NC
16
No connection.
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Data Sheet
1
2
3
4
5
6
18
17
16
15
14
13
CZ2
GND
IN+
SQUELCH
VCC
OUT+
OUT−
VCC
VSC7961
IN−
Top View
GND
LEVEL
LOS
Exposed paddle must be connected to most negative
rail or left floating. Heat must be removed through the
printed circuit board (PCB).
Figure 4. Pin Diagram for 24-Pin QFP-N (YF)
Table 9. Pin Identification for 24-Pin QFP-N (YF)
Pin Name Pin Number Description
CZ2
1
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant of off-
set correction loop.
GND
IN+
2
3
4
5
6
Supply ground.
Noninverted data input.
Inverted data input.
Supply ground.
IN–
GND
LEVEL
Output Current Level. This pin may be either connected to ground or left unconnected. Connecting to
ground causes output current to be 20mA. The output is 16mA when left unconnected.
TH
7
Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal level at
which LOS outputs will be asserted.
NC
8
No connection.
NC
9
No connection.
NC
10
11
12
13
14
15
16
17
18
No connection.
LOS
NC
Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by TH.
No connection.
LOS
VCC
OUT–
OUT+
VCC
SQUELCH
Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold programmed by TH.
Power zsupply.
Inverted data output.
Noninverted data output.
Power supply.
Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is HIGH,
OUT+ and OUT– are forced to static levels when LOS is HIGH.
NC
NC
NC
NC
NC
CZ1
19
20
21
22
23
24
No connection.
No connection.
No connection.
No connection.
No connection.
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant of off-
set correction loop.
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Data Sheet
1. All dimensioning and tolerancing per ASME.Y14.5-1994
2. Controlling dimension: millimeter
3. This outline conforms to JEDEC Publication 95 Registration MS-026
Figure 5. Package Drawing for TSSOP-16 (YD)
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Data Sheet
Figure 6. Package Drawing for 24-Pin QFP-N (YF)
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Data Sheet
Moisture Sensitivity Level
This device is rated moisture sensitivity level 3 or better as specified in JEDEC standard IPC/JEDEC J-STD-020B.
For more information, see the JEDEC standard.
ORDERING INFORMATION
VSC7961 PECL Limiting Amplifier with LOS Detect
Part Number
VSC7961YD-1
VSC7961YF-1
VSC7961-W
Description
TSSOP-16, 4.4mm x 4.4mm body
24-pin leadless QFP-N, 4mm x 4mm body
Bare dice in waffle pack
CORPORATE HEADQUARTERS
Vitesse Semiconductor Corporation
741 Calle Plano
Camarillo, CA 93012
Tel: 1-800-VITESSE
·
FAX:1-(805) 987-5896
For application support, latest technical literature, and locations of sales offices,
please visit our web site at
www.vitesse.com
Copyright © 2001–2003 by Vitesse Semiconductor Corporation
PRINTED IN THE U.S.A
Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications to improve performance, reliability or manufactura-
bility. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without
notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Vitesse for its use. Furthermore,
the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer.
Vitesse products are not intended for use in life support products where failure of a Vitesse product could reasonably be expected to result in death or personal
injury. Anyone using a Vitesse product in such an application without express written consent of an officer of Vitesse does so at their own risk, and agrees to fully
indemnify Vitesse for any damages that may result from such use or sale.
Vitesse Semiconductor Corporation is a registered trademark. All other products or service names used in this publication are for identification purposes only, and
may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their
respective holders.
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Data Sheet
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