SUD50N02-04P [VISHAY]
N-Channel 20-V (D-S) 175C MOSFET; N通道20 -V （D -S ） 175C MOSFET
| 型号： | SUD50N02-04P |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 20-V (D-S) 175C MOSFET |
| 文件： | 总3页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model SUD50N02-04P
Vishay Siliconix
N-Channel 20-V (D-S) 175°C MOSFET
CHARACTERISTICS
• N- and P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72389
08-Jun-04
www.vishay.com
1
SPICE Device Model SUD50N02-04P
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated
Data
Measured
Data
Parameter
Symbol
Test Conditions
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
1.7
V
A
VDS = VGS, ID = 250 µA
VDS = 5 V, VGS = 10 V
VGS = 10 V, ID = 20 A
1190
0.0035
0.0048
0.0049
68
0.0035
0.0048
0.90
Drain-Source On-State Resistancea
rDS(on)
Ω
VGS = 10 V, ID = 20 A, TJ = 125°C
VGS = 4.5 V, ID = 20 A
VDS = 15 V, ID = 20 A
Forward Transconductancea
Forward Voltagea
gfs
S
V
VSD
IS = 50 A, VGS = 0 V
0.91
Dynamicb
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Chargec
Gate-Drain Chargec
Turn-On Delay Timec
Rise Timec
Ciss
Coss
Crss
Qg
4807
1664
641
40
5000
1650
770
40
V
GS = 0 V, VDS = 10 V, f = 1 MHz
Pf
VDS = 10 V, VGS = 4.5 V, ID = 50 A
NC
Qgs
Qgd
td(on)
tr
14
14
13
13
31
20
18
20
VDD = 10 V, RL = 0.20 Ω
Ns
Turn-Off Delay Timec
Fall Timec
td(off)
tf
34
50
I
D ≅ 50 A, VGEN = 10 V, RG = 2.5 Ω
31
15
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com
2
Document Number: 72389
08-Jun-04
SPICE Device Model SUD50N02-04P
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72389
08-Jun-04
www.vishay.com
3
相关型号：
SUD50N02-06P-E3
TRANSISTOR 26 A, 20 V, 0.006 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252, TO-252, 3 PIN, FET General Purpose Power
VISHAY
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