SUD50N02-06P_06 [VISHAY]
N-Channel 20-V (D-S) 175Celsius MOSFET; N通道20 -V (D -S ) 175Celsius MOSFET型号: | SUD50N02-06P_06 |
厂家: | VISHAY |
描述: | N-Channel 20-V (D-S) 175Celsius MOSFET |
文件: | 总4页 (文件大小:200K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SPICE Device Model SUD50N02-06P
Vishay Siliconix
N-Channel 20-V (D-S) 175° MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 70104
S-60543Rev. B, 10-Apr-06
1
SPICE Device Model SUD50N02-06P
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated
Data
Measured
Data
Parameter
Symbol
Test Condition
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
1.4
V
A
V
DS = VGS, ID = 250 µA
VDS = 5 V, VGS = 10 V
964
VGS = 10 V, ID = 20 A
0.0041
0.0057
0.0065
0.91
0.0046
Drain-Source On-State Resistancea
rDS(on)
Ω
VGS = 10 V, ID = 20 A, TJ = 125°C
VGS = 4.5 V, ID = 20 A
0.0073
1.2
Forward Voltagea
VSD
IS = 50 A, VGS = 0 V
V
Dynamicb
Input Capacitance
Ciss
Coss
Crss
Qg
2418
816
348
20
7.5
6
2550
900
415
19
V
GS = 0 V, VDS = 25 V, f = 1 MHz
pF
nC
Output Capacitance
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Chargec
Gate-Drain Chargec
Turn-On Delay Timec
Rise Timec
VDS = 10 V, VGS = 4.5 V, ID = 50 A
Qgs
Qgd
td(on)
tr
7.5
6
11
10
9
11
10
VDD = 10 V, RL = 0.20 Ω
Turn-Off Delay Timec
Fall Timec
td(off)
tf
24
I
D ≅ 50 A, VGEN = 10 V, RG = 2.5 Ω
ns
9
9
Source-Drain Reverse Recovery Time
trr
31
35
IF = 50 A, di/dt = 100 A/µs
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com
Document Number: 70104
S-60543Rev. B, 10-Apr-06
2
SPICE Device Model SUD50N02-06P
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 70104
S-60543Rev. B, 10-Apr-06
3
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Disclaimer
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Document Number: 91000
Revision: 18-Jul-08
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