SIE810DF [VISHAY]
N-Channel 20-V (D-S) MOSFET; N通道20 -V （D -S ）的MOSFET
| 型号： | SIE810DF |
| 厂家： | 
VISHAY |
| 描述： | N-Channel 20-V (D-S) MOSFET |
| 文件： | 总3页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model SiE810DF
Vishay Siliconix
N-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 4.5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
www.vishay.com
Document Number: 74188
S-60992Rev. A, 12-Jun-06
1
SPICE Device Model SiE810DF
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated
Data
Measured
Data
Parameter
Symbol
Test Condition
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
1.1
V
A
V
DS = VGS, ID = 250 µA
VDS ≤ 5 V, VGS = 4.5 V
VGS = 4.5 V, ID = 25 A
1490
0.0013
0.0021
202
0.0013
0.0022
163
Drain-Source On-State Resistancea
rDS(on)
Ω
V
GS = 2.5 V, ID = 25 A
Forward Transconductancea
Forward Voltagea
gfs
VDS = 10 V, ID = 25 A
IS = 10 A
S
V
VSD
0.84
0.90
Dynamicb
Input Capacitance
Ciss
Coss
Crss
13430
1774
803
190
91
13000
1600
1000
200
90
V
DS = 10 V, VGS = 0 V, f = 1 MHz
pF
nC
Output Capacitance
Reverse Transfer Capacitance
VDS = 10V, VGS = 10 V, ID = 20 A
Total Gate Charge
Qg
VDS = 10 V, VGS = 4.5 V, ID = 20 A
Gate-Source Charge
Gate-Drain Charge
Qgs
Qgd
21
21
19
19
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
Document Number: 74188
S-60992Rev. A, 12-Jun-06
2
SPICE Device Model SiE810DF
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
www.vishay.com
Document Number: 74188
S-60992Rev. A, 12-Jun-06
3
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