SN74SSTVF32852 [TI]
24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS; 24位至48位寄存缓冲器与SSTL_2输入和输出
| 型号： | SN74SSTVF32852 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS |
| 文件： | 总11页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
Member of the Texas Instruments
Widebus Family
Outputs Meet SSTL_2 Class I
Specifications
Operates at 2.3 V to 2.7 V for PC1600,
PC2100, and PC2700; 2.5 V to 2.7 V for
PC3200
Supports SSTL_2 Data Inputs
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
RESET Input
Pinout and Functionality Compatible With
JEDEC Standard SSTV32852
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
Pinout Optimizes 1U DDR DIMM Layout
600 ps Faster (Simultaneous Switching)
Than the JEDEC Standard SSTV32852 in
PC2700 DIMM Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1-to-2 Outputs Support Stacked DDR
DIMMs
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
One Device Per DIMM Required
– 1000-V Charged-Device Model (C101)
Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
description/ordering information
This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V
operation.
CC
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits,
optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications.
The SN74SSTVF32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V
) inputs are allowed. In addition, when
REF
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
LFBGA – GKF
A
0°C to 70°C
Tape and reel SN74SSTVF32852KR
SVF852
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
GKF PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
A
B
C
D
E
F
Q2A
Q3A
Q5A
Q7A
Q8A
Q10A
Q12A
Q13A
Q14A
Q17A
Q18A
Q20A
Q22A
Q23A
Q24A
D2
Q1A
CLK
GND
CLK
GND
Q1B
Q2B
V
DDQ
Q4A
V
DDQ
Q4B
Q3B
V
DDQ
GND
V
DDQ
GND
Q5B
Q6A
GND
Q9A
Q6B
GND
Q9B
Q7B
V
DDQ
V
DDQ
Q8B
E
F
G
H
J
V
DDQ
V
DDQ
Q10B
Q12B
Q13B
Q14B
Q17B
Q18B
Q20B
Q22B
Q23B
Q24B
D14
G
H
J
Q11A
GND
GND
Q11B
V
CC
V
DDQ
GND
V
DDQ
GND
V
CC
Q15A
Q16A
Q19A
Q15B
Q16B
Q19B
K
L
V
DDQ
GND
V
DDQ
GND
K
L
M
N
P
R
T
V
DDQ
GND
GND
V
DDQ
M
N
P
R
T
Q21A
V
DDQ
GND
V
DDQ
GND
Q21B
V
DDQ
V
DDQ
V
CC
D1
RESET
D6
V
REF
D18
V
CC
D13
U
V
W
D4
D3
D7
D9
D10
D11
D22
D23
D24
D15
D19
D21
D16
U
V
D5
D17
D8
D12
D20
W
FUNCTION TABLE
INPUTS
OUTPUT
Q
RESET
CLK
CLK
↓
D
H
H
H
H
↑
↑
H
L
↓
L
L or H
X or
L or H
X or
X
Q
0
X or
L
L
floating floating floating
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
logic diagram (positive logic)
R3
RESET
A3
CLK
A4
CLK
R4
V
REF
One of 24 Channels
T2
D1
A2
A5
Q1A
Q1B
1D
C1
R
To 23 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
DDQ
CC
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O
O
DDQ
DDQ
Continuous output current, I (V = 0 to V
Continuous current through each V , V
Package thermal impedance,
Storage temperature range, T
O
O
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
(see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
CC DDQ
JA
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
recommended operating conditions (see Note 4)
MIN
NOM
MAX
2.7
UNIT
V
V
Supply voltage
V
V
CC
DDQ
2.3
PC1600, PC2100, PC2700
PC3200
2.7
Output supply voltage
V
V
DDQ
2.5
1.15
1.25
2.7
PC1600, PC2100, PC2700
PC3200
1.25
1.3
1.35
1.35
V
REF
Reference voltage (V
= V /2)
DDQ
REF
V
V
V
V
V
V
V
V
V
V
Termination voltage
Input voltage
V
–40mV
V
REF
V
+40mV
V
V
TT
REF
REF
0
V
CC
I
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs
Data inputs
Data inputs
Data inputs
RESET
V
REF
+310mV
+150mV
1.7
V
IH
V
REF
–310mV
–150mV
V
IL
V
REF
V
IH
V
REF
V
IL
V
IH
RESET
0.7
V
IL
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
CLK, CLK
CLK, CLK
0.97
360
1.53
V
ICR
I(PP)
mV
I
I
–8
8
OH
mA
Low-level output current
OL
T
A
Operating free-air temperature
0
70
C
NOTE 4: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential
inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics for PC1600, PC2100, and PC2700 over recommended operating free-air
temperature range (unless otherwise noted)
†
‡
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
V
I = –18 mA
2.3 V
2.3 V to 2.7 V
2.3 V
–1.2
V
IK
I
I
I
I
I
= –100 µA
= –8 mA
= 100 µA
= 8 mA
V
DDQ
1.95
–0.2
OH
OH
OL
OL
V
V
OH
2.3 V to 2.7 V
2.3 V
0.2
0.35
±5
V
OL
I
I
All inputs
V = V
or GND
2.7 V
µA
µA
I
I
CC
RESET = GND
RESET = V , V = V
Static standby
Static operating
10
I
I
= 0
= 0
2.7 V
CC
O
or V
or V
35
mA
CC
I
IH(AC)
IH(AC)
IL(AC)
IL(AC)
Dynamic operating –
clock only
RESET = V , V = V
,
,
µA/
MHz
CC
I
38
7
CLK and CLK switching 50% duty cycle
RESET = V , V = V or V
IL(AC)
CLK and CLK switching 50% duty cycle,
One data input switching at one-half
clock frequency, 50% duty cycle
µA/
clock
MHz/
D input
CC
I
IH(AC)
I
2.5 V
CCD
O
Dynamic operating –
per each data input
Data inputs
CLK, CLK
RESET
V = V
I
± 310 mV
2.8
2.5
3
3.3
3
3.8
3.5
4.5
REF
= 1.25 V, V
C
V
ICR
= 360mV
pF
2.5 V
i
I(PP)
or GND
V = V
I
4
CC
†
‡
For this test condition, V
always is equal to V
.
CC
DDQ
All typical values are at V = 2.5 V, T = 25°C.
CC
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
electrical characteristics for PC3200 over recommended operating free-air temperature range
(unless otherwise noted)
†
‡
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
V
I = –18 mA
2.5 V
2.5 V to 2.7 V
2.5 V
–1.2
V
IK
I
I
I
I
I
= –100 µA
= –8 mA
= 100 µA
= 8 mA
V
DDQ
1.95
–0.2
OH
OH
OL
OL
V
V
OH
2.5 V to 2.7 V
2.5 V
0.2
0.35
±5
V
OL
I
I
All inputs
V = V
or GND
2.7 V
µA
µA
I
I
CC
RESET = GND
RESET = V , V = V
Static standby
Static operating
10
I
I
= 0
= 0
2.7 V
CC
O
or V
or V
35
mA
CC
I
IH(AC)
IH(AC)
IL(AC)
IL(AC)
Dynamic operating –
clock only
RESET = V , V = V
,
,
µA/
MHz
CC
I
38
7
CLK and CLK switching 50% duty cycle
RESET = V , V = V or V
IL(AC)
CLK and CLK switching 50% duty cycle,
One data input switching at one-half
clock frequency, 50% duty cycle
µA/
clock
MHz/
D input
CC
I
IH(AC)
I
2.6 V
CCD
O
Dynamic operating –
per each data input
Data inputs
CLK, CLK
RESET
V = V
I
± 310 mV
2.8
2.5
3
3.3
3
3.8
3.5
4.5
REF
= 1.25 V, V
C
V
ICR
= 360mV
pF
2.6 V
i
I(PP)
or GND
V = V
I
4
CC
†
‡
For this test condition, V
always is equal to V
.
CC
DDQ
All typical values are at V = 2.6 V, T = 25°C.
CC
A
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V
± 0.2 V
V
= 2.6 V
± 0.1 V
CC
CC
†
†
UNIT
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
500
500
MHz
ns
clock
Pulse duration, CLK, CLK high or low
Differential inputs active time (see Note 5)
Differential inputs inactive time (see Note 6)
1
1
w
22
22
22
22
ns
act
ns
inact
Fast slew rate (see Notes 7 and 9)
0.75
0.9
0.75
0.9
t
Setup time
Hold time
ns
ns
Data before CLK↑, CLK↓
Data after CLK↑, CLK↓
su
Slow slew rate (see Notes 8 and 9)
Fast slew rate (see Notes 7 and 9)
Slow slew rate (see Notes 8 and 9)
0.75
0.9
0.75
0.9
t
h
†
For this test condition, V
always is equal to V
.
CC
DDQ
must be held at a valid input level and data inputs must be held low for a minimum time of t
NOTES: 5. V
max, after RESET is taken high.
, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of t max, after RESET is taken
REF
act
6.
V
REF inact
low.
7. For data signal input slew rate ≥1 V/ns.
8. For data signal input slew rate ≥0.5 V/ns and <1 V/ns.
9. CLK, CLK signals input slew rates are ≥1 V/ns.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
± 0.2 V
V
= 2.6 V
± 0.1 V
CC
CC
FROM
(INPUT)
TO
(OUTPUT)
†
†
PARAMETER
UNIT
MIN
500
1.1
MAX
MIN
500
1.1
MAX
f
t
MHz
ns
max
CLK and CLK
Q
Q
2.6
5
2.6
5
pd
t
ns
RESET
PHL
†
For this test condition, V
always is equal to V
.
CC
DDQ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTVF32852
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES426A – FEBRUARY 2003 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
C
= 30 pF
L
R
= 500 Ω
L
(see Note A)
LOAD CIRCUIT
t
w
V
V
IH
V
V
V
Input
REF
REF
V
IL
LVCMOS
RESET
Input
CC
V
/2
V
/2
CC
CC
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
V
I(PP)
t
t
act
inact
Timing
Inputs
V
ICR
ICR
I
(operation)
(standby)
I
CC
CC
90%
(see
Note B)
10%
I
CC
t
t
PHL
PLH
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
V
OH
/2
Output
V
DDQ
/2
V
DDQ
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
V
V
IH
Timing
Inputs
LVCMOS
RESET
Input
V
ICR
V
CC
/2
IL
t
PHL
/2
t
t
h
su
V
V
V
OH
IH
V
Output
Input
V
REF
V
REF
DDQ
V
OL
IL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.
B.
C
includes probe and jig capacitance.
tested with clock and data inputs held at V
L
I
or GND, and I = 0 mA.
CC
CC O
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
H.
V
V
V
= V
/2
DDQ
REF
IH
IL
= V
= V
+ 310 mV (ac voltage levels) for differential inputs. V = V
for LVCMOS input.
CC
REF
IH
– 310 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
REF
and t
IL
t
are the same as t
.
PLH
PHL
pd
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2005
PACKAGING INFORMATION
Orderable Device
74SSTVF32852ZKFR
SN74SSTVF32852KR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LFBGA
ZKF
114
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
LFBGA
GKF
114
1000
TBD
SNPB
Level-3-220C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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