SN74TVC16222-1 [TI]
10-BIT VOLTAGE CLAMP; 10位电压钳位
| 型号： | SN74TVC16222-1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT VOLTAGE CLAMP |
| 文件： | 总21页 (文件大小：763K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
Designed to be Used in Voltage-Limiting
Applications
6.5-Ω On-State Connection Between Ports
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
A1
A2
A3
A4
A5
A6
A7
A8
GATE
B1
B2
B3
B4
B5
B6
B7
B8
A and B
2
3
Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
4
5
Direct Interface With GTL+ Levels
6
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
7
8
9
10
11
12
A9
A10
A11
B9
B10
B11
description/ordering information
The SN74TVC3010 provides 11 parallel NMOS
pass transistors with a common gate. The low
on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device can be used as a 10-bit switch with the gates cascaded together to a reference transistor. The
low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to
protect components with inputs that are sensitive to high-state voltage-level overshoots. (See Application
Information in this data sheet.)
All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can
be used as the reference transistor. Since, within the device, the characteristics from transistor to transistor are
equal, the maximum output high-state voltage (V ) is approximately the reference voltage (V
), with
OH
REF
minimal deviation from one output to another. This is a large benefit of the TVC solution over discrete devices.
Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the
low-voltage side, and the I/O signals are bidirectional through each FET.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
Tape and reel
–40°C to 85°C SSOP (QSOP) – DBQ Tape and reel
SN74TVC3010DW
SN74TVC3010DWR
SN74TVC3010DBQR
SN74TVC3010PWR
SN74TVC3010DGVR
SOIC – DW
TVC3010
TVC3010
TT010
TSSOP – PW
TVSOP – DGV
Tape and reel
Tape and reel
TT010
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
simplified schematic
GATE
24
B1
23
B2
22
B3
21
B4
20
B11
13
1
2
3
4
5
12
A11
GND
A1
A2
A3
A4
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Input/output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I/O
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Package thermal impedance, θ (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are
observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
0
TYP
MAX
5
UNIT
V
V
V
Input/output voltage
GATE voltage
I/O
0
5
V
GATE
PASS
I
Pass-transistor current
Operating free-air temperature
20
64
85
mA
°C
T
A
–40
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
application operating conditions (see Figure 3)
MIN
TYP
2.1
2.1
1.5
2.5
14
MAX
5
UNIT
V
V
V
V
V
BIAS voltage
V
V
+ 0.6
BIAS
GATE
REF
REF
GATE voltage
+ 0.6
0
5
V
REF
Reference voltage
4.4
2.64
V
Drain pullup voltage
Pass-transistor current
Reference-transistor current
Operating free-air temperature
2.36
V
DPU
I
I
mA
µA
°C
PASS
5
REF
T
A
–40
85
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
IK
V
BIAS
= 0,
–1.2
V
I
I
V
= 5 A,
= 2.625 V,
V
R
= 1.365 V,
= 150 Ω
V = 0.175 V,
S
See Figure 1
REF
REF
DPU
V
350
mV
OL
DPU
V = 3 V or 0
C
C
C
24
4
pF
pF
pF
i(GATE)
io(off)
I
V
V
= 3 V or 0
= 3 V or 0
12
30
O
12
io(on)
O
I
V
= 5 A,
V
R
= 1.365 V,
= 150 Ω
DPU
V = 0.175 V,
S
See Figure 1
REF
REF
‡
12.5
Ω
r
on
= 2.625 V,
DPU
†
‡
All typical values are at T = 25°C.
A
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range,
V
= 2.36 V to 2.64 V (unless otherwise noted) (see Figure 1)
DPU
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
t
t
0
0
4
4
PLH
A or B
B or A
ns
PHL
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
V
DPU
3.3 V
Motherboard
Interface
200 kΩ
R
150 Ω
=
R
DPU
150 Ω
=
R
150 Ω
=
R
150 Ω
=
DPU
DPU
DPU
†
†
†
†
‡
GATE
24
B1 (V
23
)
B2
22
B3
21
B4
20
B11
13
BIAS
TVC3010
1
2
3
4
A3 (V )
5
12
A11 (V )
S
A1 (V
)
A2 (V )
A4 (V )
REF
S
S
S
§
§
§
§
Open-Drain
Test Interface
TESTER CALIBRATION SETUP (see Note C)
Input
2.5 V
0 V
GATE
1.25 V
1.25 V
Tester
t
t
PHLREF
PLHREF
DEFINITION
SYMBOL
2.5 V
†
‡
§
Output tested
Output reference
Input tested
Output
Reference
1.25 V
1.25 V
V
OL
t
t
PLHDUT
PHLDUT
2.5 V
Output
Device
1.25 V
1.25 V
V
Under Test
OL
PHL
(see Note E)
t
t
PLH
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
B. The outputs are measured one at a time with one transition per measurement.
C. Test procedure: t and t are obtained by measuring the propagation delay of a reference measuring point.
PLHREF
PHLREF
t
t
t
and t are obtained by measuring the propagation delay of the device under test.
PLHDUT
PHLDUT
– t
D.
E.
= t
PLH PLHDUT PLHREF
= t – t
PHL PHLDUT PHLREF
Figure 1. Tester Calibration Setup and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
APPLICATION INFORMATION
TVC background information
In personal computer (PC) architecture, there are industry-accepted bus standards. These standards define,
among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host
bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate
with existing bus infrastructure. Providing an evolutionary upgrade path is important in the design of PC
architecture, but the existing bus standards must be preserved.
To achieve the ever-present need for smaller, faster, lighter devices that draw less power, yet have faster
performance, most new high-performance digital integrated circuits are being designed and produced with
advanced submicron semiconductor process technologies. These devices have thin gate-oxide or short
channel lengths and very low absolute-maximum voltages that can be tolerated at the inputs/outputs (I/Os)
without causing damage. In many cases, the I/Os of these devices are not tolerant of the high-state voltage
levels on the preexisting buses with which they must communicate. Therefore, it became necessary to protect
the I/Os of devices by limiting the I/O voltages.
The Texas Instruments (TI) translation voltage-clamp (TVC) family was designed specifically for protecting
sensitive I/Os (see Figure 2). The information in this data sheet describes the I/O-protection application of the
TVC family and should enable the design engineer to successfully implement an I/O-protection circuit utilizing
the TI TVC solution.
TVC Family
Voltage-Clamp
Device
Low-Voltage
I/O Device
Standard-Voltage
I/O Bus
Figure 2. Thin Gate-Oxide Protection Application
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
APPLICATION INFORMATION
TVC voltage-limiting application
For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any
one of the transistors (see Figure 3). This connection determines the V input of the reference transistor. The
BIAS
V
inputisconnectedthroughapullupresistor(typically,200kΩ)totheV supply.AfiltercapacitoronV
BIAS
DD BIAS
is recommended. The opposite side of the reference transistor is used as the reference voltage (V
)
REF
connection. The V
The reference transistor regulates the gate voltage (V
the characteristic gate-to-source voltage difference (V ) because V
input must be less than V
– 1 V to bias the reference transistor into conduction.
) of all the pass transistors. V
REF
DDREF
is determined by
GATE
GS
GATE
= V
+ V . The low-voltage side
GATE
REF GS
of the pass transistors has a high-level voltage limited to a maximum of V
– V , or V
.
GATE
GS
REF
V
= 3.3 V
V
DPU
DDREF
Motherboard
Interface
200 kΩ
150 Ω
150 Ω
150 Ω
150 Ω
†
†
GATE
24
B1 (V
23
)
B2
22
B3
21
B4
20
B11
13
BIAS
TVC3010
1
2
3
A2
4
A3
5
A4
12
A11
†
A1 (V
)
REF
Open-Drain
CPU Interface
†
V
REF
and V
can be applied to any one of the pass transistors. GATE must be connected externally to V
.
BIAS
BIAS
Figure 3. Typical Application Circuit
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
APPLICATION INFORMATION
electrical characteristics
The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE
simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in
Figures 5 and 6, show the current through a pass transistor versus the voltage at the source for different
reference voltages. The plots of the dc characteristics clearly reveal that the device clamps at the desired
reference voltage for the varying device environments.
Figure 5 shows the V-I characteristics, with low reference voltages and a reference-transistor drain-supply
voltage of 3.3 V. To further investigate the spread of the V-I characteristic curves, V
was held at 2.5 V and
REF
I
was increased by raising V
(see Figure 6). The result was a tighter grouping of the V-I curves.
REF
DDREF
V
V
DDREF
DDPASS
R
R
DREF
DPASS
V
GATE
V
BIAS
DPASS
V
REF
V
SPASS
Figure 4. TI SPICE Simulation Schematic and Voltage-Node Names
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
APPLICATION INFORMATION
V
V
= 1 V
–2
–4
REF
DDREF
= 3.3 V
R
R
= 200 kΩ
= 150 Ω
DREF
–6
DPASS
DDPASS
–8
V
= 3.3 V
–10
–12
–14
–16
–18
–20
Weak
Nominal
Strong
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
V
V
V
– Low Reference Voltage – V
SPASS
–2
–4
V
V
= 1.5 V
REF
DDREF
= 3.3 V
R
R
V
= 200 kΩ
= 150 Ω
DREF
–6
DPASS
DDPASS
–8
= 3.3 V
–10
–12
–14
–16
–18
–20
Weak
Nominal
Strong
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
– Low Reference Voltage – V
SPASS
V
V
= 2 V
–2
–4
REF
DDREF
= 3.3 V
R
R
= 200 kΩ
= 150 Ω
DREF
–6
DPASS
DDPASS
–8
V
= 3.3 V
–10
–12
–14
–16
–18
–20
Weak
Nominal
Strong
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
– Low Reference Voltage – V
SPASS
Figure 5. Electrical Characteristics at Low V
Voltages
REF
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
APPLICATION INFORMATION
V
V
= 2.5 V
REF
DDREF
–2
–4
= 3.3 V
R
R
= 200 kΩ
= 150 Ω
DREF
–6
DPASS
DDPASS
–8
V
= 3.3 V
–10
–12
–14
–16
–18
–20
Weak
Nominal
Strong
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
V
– Low Reference Voltage – V
SPASS
V
V
= 2.5 V
REF
DDREF
–2
–4
= 4 V
R
R
= 200 kΩ
= 150 Ω
DREF
–6
DPASS
DDPASS
–8
V
= 3.3 V
–10
–12
–14
–16
–18
–20
Weak
Nominal
Strong
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
V
– Low Reference Voltage – V
SPASS
V
V
= 2.5 V
–2
–4
REF
DDREF
= 5 V
R
R
= 200 kΩ
= 150 Ω
DREF
–6
DPASS
DDPASS
–8
V
= 3.3 V
–10
–12
–14
–16
–18
–20
Weak
Nominal
Strong
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
V
– Low Reference Voltage – V
SPASS
Figure 6. Electrical Characteristics at V
= 2.5 V
REF
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74TVC3010
10-BIT VOLTAGE CLAMP
SCDS088G – APRIL 1999 – REVISED AUGUST 2003
APPLICATION INFORMATION
features and benefits
The TVC family has several features that benefit a system designer when implementing a
sensitive-I/O-protection solution. Table 1 lists these features and their associated benefits.
Table 1. Features and Benefits
FEATURES
BENEFITS
Any FET can be used as the reference transistor.
All FETs on one die, tight process control
No active control logic (passive device)
Flow-through pinout
Ease of layout
Very low spread of V relative to V
O
REF
No logic power supply (V ) required
CC
Ease of trace routing
Devices offered in different bit-widths and packages
Optimizes design and cost effectiveness
Allows migration to lower-voltage I/Os without board redesign
Designer flexibility with V
input
REF
conclusion
The TI TVC family provides the designer with a solution for protection of circuits with I/Os that are sensitive to
high-state voltage-level overshoots. The flexibility of TVC enables a low-voltage migration path for advanced
designs to align with industry standards.
frequently asked questions (FAQ)
1. Q: Can any of the transistors in the array be used as the reference transistor?
A: Yes, any transistor can be used as long as its V
pin is connected to the GATE pin.
BIAS
2. Q: In the recommended operating conditions table of the data sheet, the typical V
is 3.3 V.
BIAS
Should V
be equal to or greater than V
on the reference transistor?
BIAS
REF
A: V
isavariablethatisdeterminedbyV
. V
isconnectedtoV througharesistortoallowthe
BIAS
REF BIAS DD
bias voltage to be controlled by V
than V
. V
can be as high as 5.5 V. V
needs to be at least 1 V less
REF DD
REF
on the reference transistor.
DDREF
3. Q: Do both A and B ports have 5-V I/O tolerance or is 5-V I/O tolerance provided only on the low-voltage
side?
A: Both ports are 5-V tolerant.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74TVC3010DBQR
SN74TVC3010DBQRE4
SN74TVC3010DBQRG4
SN74TVC3010DGVR
SN74TVC3010DGVRE4
SN74TVC3010DGVRG4
SN74TVC3010DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
TVSOP
TVSOP
TVSOP
SOIC
DBQ
DBQ
DBQ
DGV
DGV
DGV
DW
DW
DW
DW
DW
DW
PW
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
2500
2500
2500
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74TVC3010DWE4
SN74TVC3010DWG4
SN74TVC3010DWR
SN74TVC3010DWRE4
SN74TVC3010DWRG4
SN74TVC3010PW
SOIC
25
Green (RoHS
& no Sb/Br)
SOIC
25
Green (RoHS
& no Sb/Br)
SOIC
2000
2000
2000
60
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
SN74TVC3010PWE4
SN74TVC3010PWG4
SN74TVC3010PWR
SN74TVC3010PWRE4
PW
60
Green (RoHS
& no Sb/Br)
PW
60
Green (RoHS
& no Sb/Br)
PW
2000
2000
Green (RoHS
& no Sb/Br)
PW
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74TVC3010PWRG4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74TVC3010DBQR
SN74TVC3010DGVR
SN74TVC3010DWR
SN74TVC3010PWR
SSOP
TVSOP
SOIC
DBQ
DGV
DW
24
24
24
24
2500
2000
2000
2000
330.0
330.0
330.0
330.0
16.4
12.4
24.4
16.4
6.5
6.9
9.0
5.6
2.1
1.6
2.7
1.6
8.0
8.0
16.0
12.0
24.0
16.0
Q1
Q1
Q1
Q1
10.75 15.7
6.95 8.3
12.0
8.0
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74TVC3010DBQR
SN74TVC3010DGVR
SN74TVC3010DWR
SN74TVC3010PWR
SSOP
TVSOP
SOIC
DBQ
DGV
DW
24
24
24
24
2500
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
45.0
38.0
TSSOP
PW
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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