SN74TVC16222ADGGR_技术文档

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

D

Member of the Texas Instruments

Widebus Family

Designed to Be Used in Voltage-Limiting

Applications

GND

A1

GATE

B1

1

48

47

46

45

2

6.5-Ω On-State Connection Between Ports

A and B

A2

B2

3

A3

B3

4

Flow-Through Pinout for Ease of Printed

Circuit Board Trace Routing

A4

5

44 B4

43 B5

A5

6

7

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A6

B6

D

Direct Interface With GTL+ Levels

8

A7

B7

D

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

9

A8

B8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A9

B9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

− 1000-V Charged-Device Model (C101)

description/ordering information

The SN74TVC16222A provides 23 parallel

NMOS pass transistors with a common gate. The

low on-state resistance of the switch allows

connections to be made with minimal propagation

delay.

The device can be used as a 22-bit switch, with the

gates cascaded together to a reference transistor.

The low-voltage side of each pass transistor is

limited to a voltage set by the reference transistor.

This is done to protect components with inputs

that are sensitive to high-state voltage-level

overshoots. (See Application Information in this

data sheet.)

All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can

be used as the reference transistor. Because, within the device, the characteristics from transistor to transistor

are equal, the maximum output high-state voltage (V ) is approximately the reference voltage (V

), with

OH

REF

minimal deviation from one output to another. This is a benefit of the TVC solution over discrete devices.

Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the

low-voltage side, and the I/O signals are bidirectional through each FET.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

Tube

SN74TVC16222DL

SSOP − DL

TVC16222A

Tape and reel

SN74TVC16222DLR

SN74TVC16222DGGR

SN74TVC16222DGVR

−40°C to 85°C

TSSOP − DGG Tape and reel

TVSOP − DGV Tape and reel

TVC16222A

TW222A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and TI are trademarks of Texas Instruments.

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Copyright  2005, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

simplified schematic

GATE

48

B1

47

B2

46

B3

45

B4

44

B23

25

1

2

3

4

5

24

A23

GND

A1

A2

A3

A4

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Input/output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I/O

Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IK

I

Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

JA

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W

DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Storage temperature range, T

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are

observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN

0

TYP

MAX

5.5

64

UNIT

V

Input/output voltage

GATE voltage

I/O

0

V

GATE

PASS

I

Pass-transistor current

Operating free-air temperature

20

mA

°C

T

A

−40

85

application operating conditions (see Figure 3)

MIN

TYP

2.1

1.5

2.5

14

MAX

5

UNIT

V

BIAS voltage

V

+ 0.6

0

BIAS

GATE

REF

GATE voltage

5

V

REF

Reference voltage

4.4

2.64

20

V

Drain pullup voltage

Pass-transistor current

Reference-transistor current

Operating free-air temperature

2.36

V

DPU

I

mA

µA

°C

PASS

REF

5

T

A

−40

85

2

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

TEST CONDITIONS

I = −18 mA

MIN TYP

MAX

UNIT

V

IK

V

BIAS

= 0,

−1.2

V

I

V

= 5 mA,

= 2.625 V,

V

R

= 1.365 V,

= 150 Ω

V = 0.175 V,

S

See Figure 2

REF

DPU

V

350

mV

OL

DPU

V = 3 V or 0

C

73

4

pF

i(GATE)

io(off)

I

V

= 3 V or 0

12

25

O

V

12

io(on)

O

I

V

= 5 mA,

V

R

= 1.365 V,

= 150 Ω

DPU

V = 0.175 V,

S

See Figure 2

REF

‡

12.5

Ω

r

on

= 2.625 V,

DPU

†

‡

All typical values are at T = 25°C.

A

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by

the lower voltage of the two (A or B) terminals.

electrical characteristics from −40°C to 75°C

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

I

V

= 5 mA,

V

R

= 1.552 V,

= 150 Ω

DPU

V = 0.175 V,

S

See Figure 2

REF

‡

10

Ω

r

on

= 2.625 V,

DPU

‡

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by

the lower voltage of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range,

V

= 2.36 V to 2.64 V (unless otherwise noted) (see Figure 1)

DPU

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

MIN

MAX

UNIT

t

0

4

PLH

A or B

B or A

ns

PHL

3

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

PARAMETER MEASUREMENT INFORMATION

V

DPU

3.3 V

Motherboard

Interface

200 kΩ

R

150 Ω

=

R

DPU

150 Ω

=

R

150 Ω

=

R

150 Ω

=

DPU

†

‡

GATE

48

B1 (V

47

)

B2

46

B3

45

B4

44

B23

25

BIAS

TVC16222A

1

2

3

4

A3 (V )

5

24

A23 (V )

S

A1 (V

)

A2 (V )

A4 (V )

REF

S

§

Open-Drain

Test Interface

TESTER CALIBRATION SETUP (see Note C)

Input

2.5 V

0 V

GATE

1.25 V

Tester

t

PHLREF

PLHREF

DEFINITION

SYMBOL

2.5 V

†

‡

§

Output tested

Output reference

Input tested

Output

Reference

1.25 V

V

OL

t

PLHDUT

PHLDUT

2.5 V

Output

Device

1.25 V

V

Under Test

OL

PHL

(see Note E)

t

PLH

(see Note D)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

O

r

f

B. The outputs are measured one at a time, with one transition per measurement.

C. Test procedure: t and t are obtained by measuring the propagation delay of a reference measuring point.

PLHREF PHLREF

t

and t are obtained by measuring the propagation delay of the device under test.

PLHDUT

= t

PHLDUT

D.

E.

− t

PLH PLHDUT PLHREF

= t − t

PHL PHLDUT PHLREF

Figure 1. Tester Calibration Setup and Voltage Waveforms

4

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

APPLICATION INFORMATION

TVC background information

In personal computer (PC) architecture, there are industry-accepted bus standards. These standards define,

among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host

bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate

with existing bus infrastructure. Providing an evolutionary upgrade path is important in the design of PC

architecture, but the existing bus standards must be preserved.

To achieve the ever-present need for smaller, faster, lighter devices that draw less power, yet have faster

performance, most new high-performance digital integrated circuits are designed and produced with advanced

submicron semiconductor process technologies. These devices have thin gate-oxide or short channel lengths

and very low absolute-maximum voltages that can be tolerated at the inputs/outputs (I/Os) without causing

damage. In many cases, the I/Os of these devices are not tolerant of the high-state voltage levels on the

preexisting buses with which they must communicate. Therefore, it became necessary to protect the I/Os of

devices by limiting the I/O voltages.

The Texas Instruments (TI) translation voltage-clamp (TVC) family is designed specifically for protecting

sensitive I/Os (see Figure 2). The information in this data sheet describes the I/O-protection application of the

TVC family and should enable the design engineer to successfully implement an I/O-protection circuit utilizing

the TI TVC solution.

TVC Family

Voltage-Clamp

Device

Low-Voltage

I/O Device

Standard-Voltage

I/O Bus

Figure 2. Thin Gate-Oxide Protection Application

5

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

APPLICATION INFORMATION

TVC voltage-limiting application

For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any

one of the transistors (see Figure 3). This connection determines the V input of the reference transistor. The

BIAS

V

input is connected through a pullup resistor (typically 200 kΩ ) to the V

supply. A filter capacitor on V

BIAS

DD BIAS

is recommended. The opposite side of the reference transistor is used as the reference voltage (V

)

REF

connection. The V

The reference transistor regulates the gate voltage (V

the characteristic gate-to-source voltage difference (V ) because V

input must be less than V

− 1 V to bias the reference transistor into conduction.

) of all the pass transistors. V

REF

DDREF

is determined by

GATE

GS

GATE

= V

+ V . The low-voltage side

GATE

REF GS

of the pass transistors has a high-level voltage limited to a maximum of V

− V , or V

.

GATE

GS

REF

V

= 3.3 V

V

DPU

DDREF

Motherboard

Interface

200 kΩ

150 Ω

†

GATE

48

B1 (V

47

)

B2

46

B3

45

B4

44

B23

25

BIAS

TVC16222A

1

2

3

A2

4

A3

5

A4

24

A23

†

A1 (V

)

REF

Open-Drain

CPU Interface

†

V

REF

and V

BIAS

can be applied to any one of the pass transistors. GATE must be connected externally to V

.

BIAS

Figure 3. Typical Application Circuit

6

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

APPLICATION INFORMATION

electrical characteristics

The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE

simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in

Figures 5 and 6, show the current through a pass transistor versus the voltage at the source for different

reference voltages. The plots of the dc characteristics clearly reveal that the device clamps at the desired

reference voltage for the varying device environments.

Figure 5 shows the V-I characteristics with low reference voltages and a reference-transistor drain-supply

voltage of 3.3 V. To further investigate the spread of the V-I characteristic curves, V

was held at 2.5 V and

REF

I

was increased by raising V

(see Figure 6). The result was a tighter grouping of the V-I curves.

REF

DDREF

V

DDREF

DDPASS

R

DREF

DPASS

V

GATE

V

BIAS

DPASS

V

REF

V

SPASS

Figure 4. TI SPICE-Simulation Schematic and Voltage-Node Names

7

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

APPLICATION INFORMATION

V

= 1 V

−2

−4

REF

DDREF

= 3.3 V

R

= 200 kΩ

= 150 Ω

DREF

−6

DPASS

DDPASS

−8

V

= 3.3 V

−10

−12

−14

−16

−18

−20

Weak

Nominal

Strong

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

V

− Low Reference Voltage − V

SPASS

−2

−4

V

= 1.5 V

REF

DDREF

= 3.3 V

R

V

= 200 kΩ

= 150 Ω

DREF

−6

DPASS

DDPASS

−8

= 3.3 V

−10

−12

−14

−16

−18

−20

Weak

Nominal

Strong

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

− Low Reference Voltage − V

SPASS

V

= 2 V

−2

−4

REF

DDREF

= 3.3 V

R

= 200 kΩ

= 150 Ω

DREF

−6

DPASS

DDPASS

−8

V

= 3.3 V

−10

−12

−14

−16

−18

−20

Weak

Nominal

Strong

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

− Low Reference Voltage − V

SPASS

Figure 5. V-I Electrical Characteristics at Low V

Voltages

REF

8

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

APPLICATION INFORMATION

V

= 2.5 V

REF

DDREF

−2

−4

= 3.3 V

R

= 200 kΩ

= 150 Ω

DREF

−6

DPASS

DDPASS

−8

V

= 3.3 V

−10

−12

−14

−16

−18

−20

Weak

Nominal

Strong

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

V

− Low Reference Voltage − V

SPASS

V

= 2.5 V

−2

−4

REF

DDREF

= 4 V

R

= 200 kΩ

= 150 Ω

DREF

−6

DPASS

DDPASS

−8

V

= 3.3 V

−10

−12

−14

−16

−18

−20

Weak

Nominal

Strong

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

V

− Low Reference Voltage − V

SPASS

V

= 2.5 V

−2

−4

REF

DDREF

= 5 V

R

= 200 kΩ

= 150 Ω

DREF

−6

DPASS

DDPASS

−8

V

= 3.3 V

−10

−12

−14

−16

−18

−20

Weak

Nominal

Strong

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

V

− Low Reference Voltage − V

SPASS

Figure 6. V-I Electrical Characteristics at V

= 2.5 V

REF

9

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SCDS087G − APRIL 1999 − REVISED APRIL 2005

APPLICATION INFORMATION

features and benefits

The TVC family has several features that benefit a system designer when implementing a

sensitive-I/O-protection solution. Table 1 lists these features and their associated benefits.

Table 1. Features and Benefits

FEATURES

BENEFITS

Any FET can be used as the reference transistor.

All FETs on one die, tight process control

No active control logic (passive device)

Flow-through pinout

Ease of layout

Very low spread of V relative to V

O

REF

No logic power supply (V ) required

CC

Ease of trace routing

Devices offered in different bit widths and packages

Optimizes design and cost effectiveness

Allows migration to lower-voltage I/Os without board redesign

Designer flexibility with V

REF

input

conclusion

The TI TVC family provides the designer with a solution for protection of circuits with I/Os that are sensitive to

high-state voltage-level overshoots. The flexibility of TVC enables a low-voltage migration path for advanced

designs to align with industry standards.

frequently asked questions (FAQs)

1. Q: Can any of the transistors in the array be used as the reference transistor?

A: Yes, any transistor can be used as long as its V

pin is connected to the GATE pin.

BIAS

2. Q: In the recommended operating conditions table of the data sheet, the typical V

is 3.3 V.

BIAS

Should V

be equal to or greater than V

on the reference transistor?

BIAS

REF

A: V

is a variable that is determined by V

. V

is connected to V

through a resistor to allow the

needs to be at least 1 V less

BIAS

REF BIAS

DD

bias voltage to be controlled by V

than V

. V

can be as high as 5.5 V. V

REF DD REF

on the reference transistor.

DDREF

3. Q: Do both A and B ports have 5-V I/O tolerance or is 5-V I/O tolerance provided only on the low-voltage

side?

A: Both ports are 5-V tolerant.

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

5-Sep-2005

PACKAGING INFORMATION

Orderable Device

74TVC16222ADGGRE4

74TVC16222ADGVRE4

SN74TVC16222ADGGR

SN74TVC16222ADGVR

SN74TVC16222ADL

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

DGG

48

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TVSOP

TSSOP

TVSOP

SSOP

DGV

DGG

DGV

DL

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74TVC16222ADLR

SSOP

DL

1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

M

0,07

0,40

24

13

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

1

12

0,50

A

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

38

48

56

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

48

0.0135 (0,343)

0.008 (0,203)

0.005 (0,13)

M

25

0.010 (0,25)

0.005 (0,13)

0.299 (7,59)

0.291 (7,39)

0.420 (10,67)

0.395 (10,03)

Gage Plane

0.010 (0,25)

0°–ā8°

1

24

0.040 (1,02)

0.020 (0,51)

A

Seating Plane

0.004 (0,10)

0.008 (0,20) MIN

PINS **

0.110 (2,79) MAX

28

48

0.630

56

DIM

0.380

(9,65)

0.730

A MAX

A MIN

(16,00) (18,54)

0.370

(9,40)

0.620

0.720

(15,75) (18,29)

4040048/E 12/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

M

0,08

0,50

48

25

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

1

24

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

48

56

64

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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amplifier.ti.com

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dsp.ti.com

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www.ti.com/broadband

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www.ti.com/military

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Logic

interface.ti.com

logic.ti.com

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power.ti.com

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www.ti.com/opticalnetwork

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www.ti.com/video

microcontroller.ti.com

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Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	SN74TVC16222ADGGR
厂家：	TEXAS INSTRUMENTS
描述：	22-BIT VOLTAGE CLAMP 22位电压钳位逻辑集成电路电视光电二极管
文件：	总15页 (文件大小：246K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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