SN74STV16857DGGRG4 [TI]
14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TSSOP 0 to 70;型号: | SN74STV16857DGGRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TSSOP 0 to 70 光电二极管 逻辑集成电路 触发器 电视 |
文件: | 总12页 (文件大小:897K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Not Recommended for New Designs
ꢀꢁ ꢂꢃ ꢀꢀ ꢄꢅ ꢆꢇ ꢈꢉ ꢂ
ꢆ ꢃ ꢊꢋꢌ ꢄ ꢍꢎ ꢏꢌ ꢀꢄ ꢎꢍꢎꢐ ꢋ ꢑꢒ ꢒꢎ ꢍ
ꢓ ꢌꢄ ꢔ ꢀꢀ ꢄꢕ ꢖ ꢗ ꢌꢁ ꢘꢑꢄ ꢀ ꢙꢁꢐ ꢚ ꢑꢄ ꢘꢑ ꢄꢀ
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
DGG PACKAGE
(TOP VIEW)
D
Member of the Texas Instruments
Widebus Family
D
Supports SSTL_2 Data Inputs
Q1
Q2
GND
D1
D2
GND
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
D
Outputs Meet SSTL_2 Class II
Specifications
D
D
D
Differential Clock (CLK and CLK) Inputs
V
V
DDQ
Q3
CC
D3
D4
D5
D6
D7
Supports LVCMOS Switching Levels on the
RESET Input
Q4
Q5
GND
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
V
DDQ
Q6 10
39 CLK
D
D
D
Flow-Through Architecture Optimizes PCB
Layout
Q7
CLK
11
12
38
37
V
V
DDQ
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
GND 13
Q8 14
Q9 15
36 GND
35
V
REF
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
34 RESET
33 D8
V
16
DDQ
GND 17
Q10 18
Q11 19
Q12 20
32 D9
– 1000-V Charged-Device Model (C101)
31 D10
30 D11
29 D12
description
V
21
28
V
DDQ
CC
This 14-bit registered buffer is designed for 2.3-V
to 2.7-V V operation.
GND 22
Q13 23
Q14 24
27 GND
26 D13
25 D14
CC
All inputs are SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
The SN74SSTV16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled and undriven (floating) data, clock, and reference voltage (V
) inputs are allowed. In addition, when
REF
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
0°C to 70°C
TSSOP – DGG Tape and reel SN74SSTV16857DGGR
SSTV16857
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
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ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪ ꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Not Recommended for New Designs
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅꢆ ꢇꢈꢉ ꢂ
ꢆꢃ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢀꢄ ꢎ ꢍꢎꢐ ꢋꢑ ꢒꢒ ꢎꢍ
ꢓꢌ ꢄ ꢔ ꢀꢀ ꢄ ꢕ ꢖꢗ ꢌ ꢁꢘ ꢑꢄ ꢀ ꢙꢁ ꢐ ꢚ ꢑꢄꢘ ꢑꢄ ꢀ
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
FUNCTION TABLE
INPUTS
CLK
↓
OUTPUT
Q
RESET
CLK
D
H
↑
↑
H
H
L
H
H
L
↓
L
L or H
L or H
X
Q
0
X, or floating X, or floating X, or floating
L
logic diagram (positive logic)
34
RESET
38
39
CLK
CLK
35
48
V
REF
One of 14 Channels
D1
1D
C1
1
Q1
R
To 13 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
CC
DDQ
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O
O
DDQ
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V , V
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Storage temperature range, T
O
O
DDQ
CC DDQ
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Not Recommended for New Designs
ꢀꢁ ꢂꢃ ꢀꢀ ꢄꢅ ꢆꢇ ꢈꢉ ꢂ
ꢆ ꢃ ꢊꢋꢌ ꢄ ꢍꢎ ꢏꢌ ꢀꢄ ꢎꢍꢎꢐ ꢋ ꢑꢒ ꢒꢎ ꢍ
ꢓ ꢌꢄ ꢔ ꢀꢀ ꢄꢕ ꢖ ꢗ ꢌꢁ ꢘꢑꢄ ꢀ ꢙꢁꢐ ꢚ ꢑꢄ ꢘꢑ ꢄꢀ
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
recommended operating conditions (see Note 4)
MIN
NOM
MAX
2.7
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
V
CC
DDQ
REF
TT
I
DDQ
2.3
Output supply voltage
2.7
V
Reference voltage (V
Termination voltage
Input voltage
= V
DDQ
/2)
1.15
1.25
1.35
V
REF
V
–40mV
V
V
+40mV
REF
V
REF
REF
0
V
CC
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs
Data inputs
Data inputs
Data inputs
RESET
V
+310mV
+150mV
1.7
V
IH
REF
V
–310mV
–150mV
V
IL
REF
V
V
IH
REF
V
V
IL
REF
V
IH
RESET
0.7
V
IL
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
CLK, CLK
CLK, CLK
0.97
360
1.53
V
ICR
I(PP)
mV
I
I
–20
20
OH
mA
Low-level output current
OL
T
Operating free-air temperature
0
70
_C
A
NOTE 4: The RESET input of the device must be held at a valid logic level (not floating) to ensure proper device operation. The differential inputs
must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature
number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
AND
CC
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
DDQ
2.3 V
V
V
I = –18 mA
I
–1.2
V
IK
I
I
I
I
= –100 µA
= –16 mA
= 100 µA
= 16 mA
2.3 V to 2.7 V
2.3 V
V
DDQ
1.95
–0.2
OH
OH
OL
OL
V
V
OH
2.3 V to 2.7 V
2.3 V
0.2
0.35
±5
V
OL
I
I
All inputs
V = V
CC
or GND
2.7 V
µA
µA
I
Static standby
Static operating
RESET = GND
10
I
I
I
= 0
= 0
2.7 V
CC
O
RESET = V , V = V
or V
or V
8
56
mA
CC
I
IH(AC)
IL(AC)
Dynamic operating –
clock only
RESET = V , V = V
CLK and CLK switching 50% duty cycle
,
,
µA/
MHz
CC
I
IH(AC)
IL(AC)
28
RESET = V , V = V or V
CLK and CLK switching 50% duty cycle,
One data input switching at
µA/
clock
MHz/
D input
CC IH(AC) IL(AC)
I
I
2.5 V
CCD
O
Dynamic operating –
per each data input
9
one-half clock frequency, 50% duty cycle
r
r
r
Output high
Output low
I
I
I
= –20 mA
7
7
20
20
Ω
Ω
Ω
2.3 V to 2.7 V
2.3 V to 2.7 V
2.5 V
OH
OH
= 20 mA
OL
OL
r – r
OH OL
= 20 mA, T = 25°C
6
3.5
3.5
3.5
O(∆)
O
A
Data inputs
CLK, CLK
RESET
V = V
I
± 310 mV
2.5
2.5
2.5
3
3
3
REF
V
= 1.25 V, V
= 360 mV
C
pF
2.5 V
ICR
I(PP)
or GND
i
V = V
I
CC
†
All typical values are at V
CC
= 2.5 V, T = 25°C.
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Not Recommended for New Designs
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅꢆ ꢇꢈꢉ ꢂ
ꢆꢃ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢀꢄ ꢎ ꢍꢎꢐ ꢋꢑ ꢒꢒ ꢎꢍ
ꢓꢌ ꢄ ꢔ ꢀꢀ ꢄ ꢕ ꢖꢗ ꢌ ꢁꢘ ꢑꢄ ꢀ ꢙꢁ ꢐ ꢚ ꢑꢄꢘ ꢑꢄ ꢀ
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V
± 0.2 V
CC
†
UNIT
MIN
MAX
f
t
t
t
Clock frequency
200
MHz
ns
clock
Pulse duration
CLK, CLK high or low
2.5
w
Differential inputs active time (see Note 5)
Differential inputs inactive time (see Note 6)
22
22
ns
act
ns
inact
0.75
0.9
Fast slew rate (see Notes 7 and 9)
t
Setup time
Hold time
ns
ns
Data before CLK↑, CLK↓
Data after CLK↑, CLK↓
su
h
Slow slew rate (see Notes 8 and 9)
Fast slew rate (see Notes 7 and 9)
Slow slew rate (see Notes 8 and 9)
0.75
0.9
t
†
For this test condition, V
always is equal to V .
CC
DDQ
NOTES: 5. Data inputs must be held low for a minimum time of t
min, after RESET is taken high.
act
6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of t
7. Data signal input slew rate ≥1 V/ns
min, after RESET is taken low.
inact
8. Data signal input slew rate ≥0.5 V/ns and <1 V/ns
9. CLK, CLK input slew rates are ≥1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
± 0.2 V
CC
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
UNIT
MIN
200
1.1
MAX
f
t
MHz
ns
max
CLK and CLK
RESET
Q
Q
2.8
5
pd
t
ns
PHL
†
For this test condition, V
always is equal to V .
CC
DDQ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Not Recommended for New Designs
ꢀꢁ ꢂꢃ ꢀꢀ ꢄꢅ ꢆꢇ ꢈꢉ ꢂ
ꢆ ꢃ ꢊꢋꢌ ꢄ ꢍꢎ ꢏꢌ ꢀꢄ ꢎꢍꢎꢐ ꢋ ꢑꢒ ꢒꢎ ꢍ
ꢓ ꢌꢄ ꢔ ꢀꢀ ꢄꢕ ꢖ ꢗ ꢌꢁ ꢘꢑꢄ ꢀ ꢙꢁꢐ ꢚ ꢑꢄ ꢘꢑ ꢄꢀ
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
V
TT
50 Ω
Test Point
From Output
Under Test
C
= 30 pF
L
(see Note A)
LOAD CIRCUIT
t
w
V
V
IH
V
V
V
Input
REF
REF
V
IL
LVCMOS
RESET
Input
CC
V
/2
V
/2
CC
CC
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
V
I(PP)
t
t
act
inact
Timing
Input
V
ICR
ICR
I
I
I
CC
CCH
90%
(see
Note B)
10%
CCL
t
t
PLH
PHL
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
V
OH
OL
Output
V
TT
V
TT
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
V
V
IH
Timing
Input
LVCMOS
RESET
Input
V
ICR
V
CC
/2
IL
t
PHL
t
su
t
h
V
V
V
OH
IH
V
REF
Input
V
REF
Output
V
TT
V
OL
IL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.
B.
C
includes probe and jig capacitance.
tested with clock and data inputs held at V
L
I
or GND, and I = 0 mA.
CC
CC O
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
H.
V
V
V
= V
= V
= V /2
TT
IH
IL
REF
REF
DDQ
+ 310 mV (ac voltage levels) for differential inputs. V = V for LVCMOS input.
IH CC
– 310 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
= V
and t
REF IL
t
are the same as t .
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74SSTV16857DGGR
SN74SSTV16857DGVR
SN74SSTV16857DGVRG
SN74STV16857DGGRG4
NRND
TSSOP
TVSOP
TVSOP
TSSOP
DGG
48
48
48
48
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
SSTV16857
NRND
NRND
NRND
DGV
DGV
DGG
Green (RoHS
& no Sb/Br)
0 to 70
SS857
Green (RoHS
& no Sb/Br)
0 to 70
SS857
Green (RoHS
& no Sb/Br)
0 to 70
SSTV16857
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74SSTV16857DGGR TSSOP
SN74SSTV16857DGVR TVSOP
DGG
DGV
48
48
0
0
330.0
330.0
24.4
16.4
8.6
7.1
15.8
10.2
1.8
1.6
12.0
12.0
24.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74SSTV16857DGGR
SN74SSTV16857DGVR
TSSOP
TVSOP
DGG
DGV
48
48
0
0
367.0
367.0
367.0
367.0
45.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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