SN74SSTVF16859 [TI]
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS; 13位到26位寄存缓冲器与SSTL 2输入和输出
| 型号： | SN74SSTVF16859 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS |
| 文件： | 总11页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅ ꢆꢇꢈ ꢉꢊ ꢋ
ꢇ ꢌ ꢍꢎꢏ ꢄ ꢄ ꢐ ꢑ ꢈ ꢍꢎꢏ ꢄ ꢒꢓ ꢔꢏ ꢀꢄ ꢓꢒꢓꢕ ꢎ ꢖꢆ ꢆꢓ ꢒ
ꢗ ꢏꢄ ꢘ ꢀꢀ ꢄꢙ ꢚ ꢑ ꢏꢁ ꢛꢖꢄ ꢀ ꢜꢁꢕ ꢐ ꢖꢄ ꢛꢖ ꢄꢀ
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004
DGG PACKAGE
(TOP VIEW)
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
Operates at 2.3 V to 2.7 V for PC1600,
PC2100, and PC2700
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q13A
Q12A
Q11A
Q10A
Q9A
V
DDQ
2
GND
D13
D12
Operates at 2.5 V to 2.7 V for PC3200 (QFN
Package)
3
4
Pinout and Functionality Compatible With
JEDEC Standard SSTV16859
5
V
V
CC
6
V
DDQ
DDQ
7
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
GND
D11
D10
D9
GND
D8
600 ps Faster (Simultaneous Switching)
Than the JEDEC Standard SSTV16859 in
PC2700 DIMM Applications
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D
D
D
D
D
D
1-to-2 Outputs to Support Stacked DDR
DIMMs
Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
D7
RESET
GND
CLK
CLK
V
V
V
D6
GND
D5
D4
D3
GND
V
V
D2
D1
Outputs Meet SSTL_2 Class I
Specifications
Supports SSTL_2 Data Inputs
V
Differential Clock (CLK and CLK) Inputs
DDQ
DDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
CC
Supports LVCMOS Switching Levels on the
RESET Input
REF
D
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
D
D
D
Pinout Optimizes DIMM PCB Layout
Q6B
GND
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
V
DDQ
Q5B
DDQ
CC
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Q4B
Q3B
Q2B
Q1B
− 1000-V Charged-Device Model (C101)
GND
V
DDQ
description/ordering information
This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
QFN − RGQ
A
SN74SSTVF16859SR
SN74SSTVF16859S8
(Tin-Pb Finish)
Tape and reel
SSF859
0°C to 70°C
QFN − RGQ
(Matte-Tin Finish)
TSSOP − DGG
Tape and reel SN74SSTVF16859GR
SSTVF16859
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅꢆ ꢇꢈ ꢉ ꢊꢋ
ꢇꢌ ꢍꢎꢏ ꢄ ꢄꢐ ꢑ ꢈꢍ ꢎꢏ ꢄ ꢒꢓ ꢔ ꢏꢀ ꢄꢓ ꢒꢓ ꢕ ꢎꢖ ꢆꢆ ꢓ ꢒ
ꢗꢏ ꢄ ꢘ ꢀꢀ ꢄ ꢙ ꢚꢑ ꢏ ꢁ ꢛꢖ ꢄꢀ ꢜꢁ ꢕ ꢐ ꢖꢄꢛ ꢖꢄ ꢀ
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004
description/ordering information (continued)
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS
circuits optimized for unterminated DIMM loads.
The SN74SSTVF16859 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V
) inputs are allowed. In addition, when
REF
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
RGQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
D10
D9
D8
D7
RESET
GND
CLK
CLK
†
GND
9
V
V
V
V
DDQ
DDQ
CC
REF
10
11
12
13
14
Q12B
Q11B
Q10B
Q9B
D6
D5
D4
Q8B
†
The center die pad must be connected to GND.
FUNCTION TABLE
INPUTS
OUTPUT
Q
RESET
CLK
↑
CLK
↓
D
H
H
H
H
H
L
↑
↓
L
L or H
L or H
X
Q
0
X or
X or
X or
L
L
floating floating floating
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢇ ꢌ ꢍꢎꢏ ꢄ ꢄ ꢐ ꢑ ꢈ ꢍꢎꢏ ꢄ ꢒꢓꢔ ꢏ ꢀꢄ ꢓꢒꢓꢕ ꢎ ꢖꢆ ꢆꢓ ꢒ
ꢗ ꢏꢄ ꢘ ꢀꢀ ꢄꢙ ꢚ ꢑ ꢏꢁ ꢛꢖꢄ ꢀ ꢜꢁꢕ ꢐ ꢖꢄ ꢛꢖ ꢄꢀ
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004
logic diagram (positive logic)
51
RESET
48
CLK
49
CLK
45
V
REF
One of 13 Channels
35
D1
16
32
Q1A
Q1B
1D
C1
R
To 12 Other Channels
Pin numbers shown are for the DGG package.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
CC
DDQ
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
CC
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
DDQ
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Output clamp current, I
(V < 0 or V > V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O
O
DDQ
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through each V , V
O
O
DDQ
CC DDQ
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
JA
(see Note 4): RGQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢇꢌ ꢍꢎꢏ ꢄ ꢄꢐ ꢑ ꢈꢍ ꢎꢏ ꢄ ꢒꢓ ꢔ ꢏꢀ ꢄꢓ ꢒꢓ ꢕ ꢎꢖ ꢆꢆ ꢓ ꢒ
ꢗꢏ ꢄ ꢘ ꢀꢀ ꢄ ꢙ ꢚꢑ ꢏ ꢁ ꢛꢖ ꢄꢀ ꢜꢁ ꢕ ꢐ ꢖꢄꢛ ꢖꢄ ꢀ
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004
recommended operating conditions (see Note 5)
MIN
NOM
MAX
2.7
UNIT
V
V
Supply voltage
V
V
CC
DDQ
2.3
PC1600, PC2100, PC2700
PC3200
2.7
Output supply voltage
V
V
DDQ
2.5
1.15
1.25
0
2.7
PC1600, PC2100, PC2700
PC3200
1.25
1.3
1.35
1.35
V
REF
Reference voltage (V
Input voltage
= V /2)
DDQ
REF
V
V
V
V
V
V
V
V
V
V
V
V
I
CC
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs
Data inputs
Data inputs
Data inputs
RESET
V
V
+310mV
+150mV
1.7
IH
IL
REF
V
V
−310mV
−150mV
V
REF
V
IH
IL
REF
V
REF
V
IH
IL
RESET
0.7
V
Common-mode input voltage range
Peak-to-peak input voltage
CLK, CLK
CLK, CLK
0.97
360
1.53
V
ICR
I(PP)
mV
I
I
High-level output current
Low-level output current
Operating free-air temperature
−16
16
OH
mA
OL
T
0
70
°C
A
NOTE 5: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential
inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics for PC1600, PC2100, and PC2700 over recommended operating free-air
temperature range (unless otherwise noted)
†
‡
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
V
I = −18 mA
2.3 V
2.3 V to 2.7 V
2.3 V
−1.2
V
IK
I
I
I
I
I
= −100 µA
= −8 mA
= 100 µA
= 8 mA
V
DDQ
1.95
−0.2
OH
OH
OL
OL
V
V
OH
2.3 V to 2.7 V
2.3 V
0.2
0.35
5
V
OL
I
I
All inputs
V = V
I CC
or GND
2.7 V
µA
µA
Static standby
Static operating
RESET = GND
RESET = V , V = V
10
I
I
I
= 0
= 0
2.7 V
CC
O
or V
or V
25
mA
CC
I
IH(AC)
IH(AC)
IL(AC)
Dynamic operating − RESET = V , V = V
,
,
µA/
MHz
CC
I
IL(AC)
19
7
clock only
CLK and CLK switching 50% duty cycle
RESET = V , V = V or V
CLK and CLK switching 50% duty cycle,
One data input switching at one-half clock
frequency, 50% duty cycle
µA/
clock
MHz/
D input
CC IH(AC) IL(AC)
I
I
2.5 V
CCD
O
Dynamic operating −
per each data input
Data inputs
CLK, CLK
RESET
V = V
I
310 mV
2.5
2.5
2.3
3
3
3
3.5
3.5
3.5
REF
§
C
V
ICR
= 1.25 V, V
= 360mV
pF
2.5 V
i
I(PP)
or GND
V = V
I CC
†
‡
§
For this test condition, V
DDQ
CC
Measured at 50-MHz input frequency
always is equal to V .
CC
All typical values are at V
= 2.5 V, T = 25°C.
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅ ꢆꢇꢈ ꢉꢊ ꢋ
ꢇ ꢌ ꢍꢎꢏ ꢄ ꢄ ꢐ ꢑ ꢈ ꢍꢎꢏ ꢄ ꢒꢓꢔ ꢏ ꢀꢄ ꢓꢒꢓꢕ ꢎ ꢖꢆ ꢆꢓ ꢒ
ꢗ ꢏꢄ ꢘ ꢀꢀ ꢄꢙ ꢚ ꢑ ꢏꢁ ꢛꢖꢄ ꢀ ꢜꢁꢕ ꢐ ꢖꢄ ꢛꢖ ꢄꢀ
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004
electrical characteristics for PC3200 over recommended operating free-air temperature range
(unless otherwise noted)
†
‡
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
V
I = −18 mA
2.5 V
2.5 V to 2.7 V
2.5 V
−1.2
V
IK
I
I
I
I
I
= −100 µA
= −8 mA
= 100 µA
= 8 mA
V
DDQ
1.95
−0.2
OH
OH
OL
OL
V
V
OH
2.5 V to 2.7 V
2.5 V
0.2
0.35
5
V
OL
I
I
All inputs
V = V
I CC
or GND
2.7 V
µA
µA
Static standby
Static operating
RESET = GND
RESET = V , V = V
10
I
I
I
= 0
= 0
2.7 V
CC
O
or V
or V
25
mA
CC
I
IH(AC)
IH(AC)
IL(AC)
Dynamic operating − RESET = V , V = V
,
,
µA/
MHz
CC
I
IL(AC)
19
7
clock only
CLK and CLK switching 50% duty cycle
RESET = V , V = V or V
CLK and CLK switching 50% duty cycle,
One data input switching at one-half clock
frequency, 50% duty cycle
µA/
clock
MHz/
D input
CC IH(AC) IL(AC)
I
I
2.6 V
CCD
O
Dynamic operating −
per each data input
Data inputs
CLK, CLK
RESET
V = V
I
310 mV
2.5
2.5
2.3
3
3
3
3.5
3.5
3.5
REF
§
C
V
ICR
= 1.25 V, V
= 360mV
pF
2.6 V
i
I(PP)
or GND
V = V
I CC
†
‡
§
For this test condition, V
DDQ
CC
Measured at 50-MHz input frequency
always is equal to V .
CC
All typical values are at V
= 2.6 V, T = 25°C.
A
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V
V
= 2.6 V
CC
0.2 V
CC
0.1 V
†
†
UNIT
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
500
500
MHz
ns
clock
Pulse duration, CLK, CLK high or low
Differential inputs active time (see Note 6)
Differential inputs inactive time (see Note 7)
1
1
w
22
22
22
22
ns
act
ns
inact
Fast slew rate (see Notes 8 and 10)
0.65
0.75
0.65
0.8
0.65
0.75
0.65
0.8
t
Setup time
Hold time
ns
ns
Data before CLK↑, CLK↓
Data after CLK↑, CLK↓
su
Slow slew rate (see Notes 9 and 10)
Fast slew rate (see Notes 8 and 10)
Slow slew rate (see Notes 9 and 10)
t
h
†
For this test condition, V
always is equal to V .
CC
DDQ
must be held at a valid input level, and data inputs must be held low for a minimum time of t
NOTES: 6. V
max, after RESET is taken high.
max, after RESET is taken
REF
act
7.
V
, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of t
REF inact
low.
8. For data signal input slew rate ≥1 V/ns.
9. For data signal input slew rate ≥0.5 V/ns and <1 V/ns.
10. CLK, CLK signals input slew rates are ≥1 V/ns.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗꢏ ꢄ ꢘ ꢀꢀ ꢄ ꢙ ꢚꢑ ꢏ ꢁ ꢛꢖ ꢄꢀ ꢜꢁ ꢕ ꢐ ꢖꢄꢛ ꢖꢄ ꢀ
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004
switching characteristics for TSSOP over recommended operating free-air temperature range
(unless otherwise noted) (see Figure 1)
V
= 2.5 V
CC
0.2 V
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
UNIT
MIN
500
1.1
MAX
f
t
MHz
ns
max
‡
CLK and CLK
RESET
Q
Q
2.5
5
pd
t
ns
PHL
†
‡
For this test condition, V
Single-bit switching
always is equal to V .
CC
DDQ
switching characteristics for QFN over recommended operating free-air temperature range
(unless otherwise noted) (see Figure 1)
V
= 2.5 V
V
= 2.6 V
CC
0.2 V
CC
0.1 V
FROM
(INPUT)
TO
(OUTPUT)
†
†
PARAMETER
UNIT
MIN
500
1.1
MAX
MIN
500
1.1
MAX
f
t
MHz
ns
max
‡
CLK and CLK
Q
Q
2.5
5
2.2
5
pd
t
ns
RESET
PHL
†
‡
For this test condition, V
Single-bit switching
always is equal to V
.
DDQ
CC
output slew rates over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V
V
= 2.6 V
CC
0.2 V
CC
0.1 V
†
†
PARAMETER
FROM
TO
UNIT
MIN
1
MAX
MIN
1
MAX
dV/dt_r
dV/dt_f
20%
80%
80%
20%
4
4
4
4
V/ns
V/ns
V/ns
1
1
§
dV/dt_∆
80% or 20%
1
1
20% or 80%
†
§
For this test condition, V
Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
always is equal to V .
CC
DDQ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢀ ꢀꢄ ꢅ ꢆꢇꢈ ꢉꢊ ꢋ
ꢇ ꢌ ꢍꢎꢏ ꢄ ꢄ ꢐ ꢑ ꢈ ꢍꢎꢏ ꢄ ꢒꢓꢔ ꢏ ꢀꢄ ꢓꢒꢓꢕ ꢎ ꢖꢆ ꢆꢓ ꢒ
ꢗ ꢏꢄ ꢘ ꢀꢀ ꢄꢙ ꢚ ꢑ ꢏꢁ ꢛꢖꢄ ꢀ ꢜꢁꢕ ꢐ ꢖꢄ ꢛꢖ ꢄꢀ
SCES429B − MARCH 2003 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V 0.2 V AND V
= 2.6 V 0.1 V
CC
CC
From Output
Under Test
V
I(PP)
Test
Point
Timing
Inputs
V
ICR
V
ICR
C
= 30 pF
L
R
= 500 Ω
(see Note A)
L
t
t
PHL
PLH
V
OH
/2
LOAD CIRCUIT
/2
Output
V
/2
V
DDQ
DDQ
V
OL
V
LVCMOS
RESET
Input
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
CC
V
CC
/2
0 V
V
V
IH
LVCMOS
RESET
Input
t
t
act
inact
V
CC
/2
IL
I
(operating)
(standby)
I
CC
CC
90%
(see
Note B)
t
PHL
10%
I
CC
V
V
OH
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
Output
Output
V
/2
DDQ
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
Timing
Inputs
V
ICR
V
OH
80%
20%
V
OL
t
t
h
su
dV_f
V
IH
dt_f
V
REF
Input
V
REF
V
IL
VOLTAGE WAVEFORMS
HIGH-TO-LOW SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
dt_r
dV_r
t
V
w
OH
80%
V
V
IH
Output
V
REF
V
REF
Input
20%
V
OL
IL
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
PULSE DURATION
NOTES: A.
B.
C
includes probe and jig capacitance.
tested with clock and data inputs held at V or GND, and I = 0 mA.
CC O
L
I
CC
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns 20% (unless otherwise noted).
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
V
V
V
= V
= V
= V /2
TT
IH
IL
REF
REF
DDQ
+ 310 mV (ac voltage levels) for differential inputs. V = V for LVCMOS input.
IH CC
− 310 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
= V
and t
REF IL
t
are the same as t .
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
21-Oct-2005
PACKAGING INFORMATION
Orderable Device
SN74SSTVF16859G4R
SN74SSTVF16859GR
SN74SSTVF16859GRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGQ
56
64
64
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
DGG
DGG
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN74SSTVF16859S8
SN74SSTVF16859SR
ACTIVE
ACTIVE
QFN
QFN
RGQ
RGQ
56
56
2000
2000
TBD
TBD
CU SN
Level-3-235C-168 HR
Level-3-235C-168 HR
CU SNPB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
ꢀ ꢁꢂꢃꢄ ꢅꢆꢂ ꢄꢇ ꢈ ꢄꢉꢄ
MPQF113C − DECEMBER 2001 − REVISED AUGUST 2002
RGQ (S−PQFP−N56)
PLASTIC QUAD FLATPACK
8,15
7,85
A
B
42
29
43
28
8,15
7,85
Pin 1 Identifier
56
15
1
14
7,85
7,65
1,00
0,80
Sq
0,20 Nominal
Lead Frame
Seating Plane
0,08 C
C
0,05
0,00
5,35
5,05
0,50
0,30
56X
1
14
56
15
Pin 1 Identifier
4,65
4,35
6,50
4X
43
28
42
29
0,50
+0,07
−0,05
56X 0,23
Exposed Thermal Die Pad
D
0,10
0,05
C A B
C
M
M
Bottom View
4203438/D 08/2002
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No-Lead) Package configuration.
D. The Package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
This pad may be electrically connected to ground.
E. Package registration with JEDEC MO-220 variation VLLD-2.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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相关型号：
SN74SSTVF16859SRG3
13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
TI
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