CDCE421Y [TI]
Fully Integrated Wide Range Low-Jitter Crystal Oscillator Clock Generator 0-DIESALE;
| 型号： | CDCE421Y |
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TEXAS INSTRUMENTS |
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CDCE421A
www.ti.com ..................................................................................................................................................................................................... SCAS873–APRIL 2009
Fully-Integrated, Wide Range, Low-Jitter
Crystal Oscillator Clock Generator
1
FEATURES
•
Two Fully-Integrated Voltage-Controlled
Oscillators (VCO) Support Wide Output
Frequency Range
2
•
Single Supply at 3.3 V for LVPECL or LVDS
Operation
•
•
Fully Integrated Programmable Loop Filter
Typical Power Consumption at 3.3 V:
•
High-Performance Clock Multiplier,
Incorporating Crystal Oscillator Circuitry with
Integrated Frequency Synthesizer
–
–
274 mW in LVDS mode
•
•
Low Output Jitter: 380 fs RMS typical
(from 10 kHz to 20 MHz)
250 mW in LVPECL mode
•
•
Chip Enable Control Pin
Low Phase Noise at High Frequency (708-MHz
LVPECL):
Simple Serial Interface Allows Programming
after Manufacturing
–
Typically –109 dBc/Hz at 10 kHz and
–146dBc/Hz at 10 MHz from the carrier
•
Integrated On-Chip Nonvolatile Memory
(EEPROM) Stores Settings Without Applying
High Voltage
•
•
•
Supports Crystal or LVCMOS Input
Frequencies from 27.35 MHz to 38.33 MHz
•
•
•
Available in 4-mm × 4-mm QFN-24 Package
ESD Protection Exceeds 2 kV (HBM)
Output Frequency Ranges from 10.9 MHz to
766.7 MHz and from 875.2 MHz to 1175 MHz
Industrial Temperature Range: –40°C to +85°C
Low-Voltage Differential Signaling (LVDS)
Output, 100-Ω Differential Off-Chip
Termination, 10.9-MHz to 400-MHz Frequency
Range
APPLICATIONS
•
Low-Cost, High-Frequency Crystal Oscillator
•
Differential Low-Voltage Positive Emitter
Coupled Logic (LVPECL) Outputs, 10.9-MHz to
1.175-GHz Frequency Range
CE
Program
Output Enable/Programming Interface and EEPROM for Configuration Settings
Loop Filter
Crystal
Oscillator
Input
CLK
Xtal
VCO 1
VCO 2
Feedback
Divider
NCLK
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
CDCE421A
SCAS873–APRIL 2009..................................................................................................................................................................................................... www.ti.com
DESCRIPTION
The CDCE421A is a high-performance, low phase noise clock generator. It has two fully-integrated, low-noise,
LC-based voltage-controlled oscillators (VCOs) that operate in the 1.750-GHz to 2.350-GHz frequency range(1). It
also features an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to
produce a stable frequency reference for the phase-locked loop (PLL) based frequency synthesizer.
The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL). The prescaler divider,
feedback divider, output divider, and VCO selection set the output frequency with respect to fXTAL. Table 2
provides the look-up information for a desired frequency, fOUT, and the corresponding settings for the dividers
and VCO selection. To calculate the exact crystal oscillator frequency required for the desired output, use the
formula in Equation 1.
Output Divider
Feedback Divider
fXTAL
=
´ fOUT
(1)
Where:
•
•
Output divider(1) = 1, 2, 4, 8, 16, and 32
Feedback divider(2) = 12, 16, 20, and 32
In the CDCE421A, the feedback divider is set automatically with respect to the prescaler setting. The product of
the prescaler and the feedback divider should be between 60 and 64 as shown in Table 2 to maintain a stable
control loop.
Figure 1 shows a high-level block diagram of the device. The CDCE421A supports one differential LVDS clock
output or one differential LVPECL output. All device settings are programmable through a proprietary simple
serial interface (SSI).
The device operates in 3.3-V supply environment for both LVPECL and LVDS outputs and is characterized for
operation from –40°C to +85°C. The CDCE421A is available in a QFN-24 4-mm × 4-mm package.
CDCE421 Users:
The CDCE421A provides several device enhancements to the CDCE421. For a complete description of
differences between these products, refer to Appendix C: Application Information.
CDCE421A
XIN1
Crystal
Oscillator
Loop Filter
XIN2
VCO1
1894
VCO2
2157
PFD
Charge Pump
Feedback
Divider
12, 16, 20, and 32
LVPECL
Prescaler
2, 3, 4, and 5
CE
1-Pin Interface
and
Control
EEPROM
LVDS
Output Divider
1, 2, 4, 8, 16, and 32
Program
Figure 1. Functional Block Diagram
(1) Output divider and feedback divider should be from the same row in Table 2.
(2) Feedback divider is set automatically with respect to the prescaler setting in Table 2.
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
TA
PACKAGED DEVICES
CDCE421ARGET
FEATURES
24-pin QFN (RGE) package, small tape and reel
24-pin QFN (RGE) package, tape and reel
–40°C to +85°C
CDCE421ARGER
(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).(1)
CDCE421A
–0.5 to 4.6
–0.5 to VCC to +0.5
–50
UNIT
V
VDD
VI
Supply voltage(2)
Voltage range for all other input pins(2)
V
IO
Output current for LVPECL
mA
kV
°C
°C
°C
ESD
TA
Electrostatic discharge (HBM)
Specified free-air temperature range (no airflow)
Maximum junction temperature
Storage temperature range
2
–40 to +85
+125
TJ
TSTG
–65 to +150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
MIN
3.0
NOM
MAX UNIT
VDD
TA
Supply voltage
3.30
3.60
+85
V
Ambient temperature (no airflow, no heatsink)
–40
°C
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ELECTRICAL CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted).
CDCE421A
PARAMETER
Supply voltage
Total current
TEST CONDITIONS
MIN
TYP
3.30
83
MAX
3.60
103
UNIT
V
VDD
3.00
IVDD (LVDS)
LVDS Mode
mA
mA
IVDD (LVPECL) Total current
tS Start-up time
LVDS Output Mode (See Figure 2 and Figure 4)
LVPECL Mode
91
110
fIN = 27.35 MHz, fOUT = 109.4 MHz,
Power Supply Ramp Time = 1 ms
4
ms
fCLK
Output frequency
10.9
247
400
454
50
MHz
mV
mV
V
|VOD
|
LVDS differential output voltage
LVDS VOD magnitude change
Offset voltage
RL = 100 Ω
ΔVOD
VOS
ΔVOS
tR
–40°C to +85°C
1.1
1.3
50
VOS magnitude change
Output rise time
mV
ps
20% to 80% of VOUT(PP)
230
230
tF
Output fall time
20% to 80% of VOUT(PP)
ps
Short VOUT+ to ground, VOUT = 0 V
Short VOUT– to ground, VOUT = 0 V
30
30
55
1
mA
mA
%
IOS
Short-circuit output current
Duty cycle of the output waveform
RMS jitter
45
tj, RMS
10 kHz to 20 MHz
ps, RMS
LVPECL Output Mode (See Figure 3 and Figure 5)
fCLK
VOH
VOL
|VOD
tR
Output frequency
10.9
VCC – 1.2
VCC – 2.17
407
1175
VCC – 0.81
VCC – 1.36
1076
MHz
LVPECL high-level output voltage
LVPECL low-level output voltage
LVPECL differential output voltage
Output rise time
V
V
|
mV
ps
20% to 80% of VOUT(PP)
20% to 80% of VOUT(PP)
230
230
tF
Output fall time
ps
Duty cycle of the output waveform
RMS jitter
45
55
1
%
tj, RMS
10 kHz to 20 MHz
ps, RMS
LVCMOS Input
VIL, CMOS
VIH, CMOS
IL, CMOS
Low-level CMOS input voltage
High-level CMOS input voltage
Low-level CMOS input current
High-level CMOS input current
VDD = 3.3 V
0.3 × VCC
V
V
VDD = 3.3 V
0.7 × VCC
VDD = VDD, max, VIL = 0.0 V
VDD = VDD, min, VIH = 3.7 V
–200
200
µA
µA
IH, CMOS
4
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CDCE421A
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DEVICE INFORMATION
RGE PACKAGE
QFN-24
(TOP VIEW)
1
2
3
4
5
6
18 NC
17 VCC
16 VCC
15 NC
14 NC
13 NC
CE
NC
Thermal Pad
(Bottom Side)
CDCE421A
SDATA
NC
NC
NC
PIN DESCRIPTIONS
Table 1. CDCE421A Pin Descriptions
TERMINAL
NAME
TERMINAL
NO.
ESD
PROTECTION
TYPE
DESCRIPTION
Chip enable
CE = 1: enable the device and the outputs.
CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z;
in LVPECL mode, LVPECLP = LVPECLN = Hi-Z.
CE
1
I
Y
Y
GND
8, 9
GND
Ground
2, 4–6,
11–15,
No connect
Do not connect these pins. Leave them floating.
18–20, 23,24
High-speed negative differential LVPECL or LVDS outputs. (Outputs are
enabled by CE and selected by the EEPROM configuration registers.)
OUTN
OUTP
7
O
O
Y
Y
High-speed positive differential LVPECL or LVDS outputs. (Outputs are
enabled by CE and selected by the EEPROM configuration registers.)
10
SDATA
VCC
3
I
Y
Y
Programming pin using TI proprietary interface protocol
3.3-V power supply
16, 17
Power
In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the
other end of the crystal. In LVCMOS input single-ended driven mode, XIN1
(pin 21) acts as an input reference, and XIN2 should connect to GND or it can
be left unconnected.
XIN1
XIN2
21
22
I
Y
N
GND/NC
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DEVICE SETUP AND CONFIGURATION
Table 2. Crystal Frequency Selection and Device Settings
DESIRED OUTPUT
FREQUENCY (MHz)
REQUIRED INPUT CRYSTAL
FREQUENCY (MHz)
VCO
SELECTION
OUTPUT
DIVIDER
PRESCALER
SETTING
FEEDBACK
DIVIDER(1)
From
1020
875.2(2)
680
To
1175
1020
766.7(2)
680
From
31.875
27.351
34
To
36.719
31.875
38.333
34
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
1
1
2
2
3
3
4
4
5
5
3
3
4
4
5
5
3
3
4
4
5
5
3
3
4
4
5
5
3
3
4
4
5
5
3
3
4
4
5
5
32
32
20
20
16
16
12
12
20
20
16
16
12
12
20
20
16
16
12
12
20
20
16
16
12
12
20
20
16
16
12
12
20
20
16
16
12
12
1
583.5
510
29.174
31.875
27.351
34
1
587.5
510
36.719
31.875
38.333
34
1
437.6
408
1
460
1
350.1
340
408
29.174
34
1
383.3
340
38.333
34
2
291.7
255
29.174
31.875
27.351
34
2
293.8
255
36.719
31.875
38.333
34
2
218.8
204
2
230
2
175
204
29.174
34
2
170
191.7
170
38.333
34
4
145.9
127.5
109.4
102
29.174
31.875
27.351
34
4
146.9
127.5
115
36.719
31.875
38.333
34
4
4
4
87.5
85
102
29.174
34
4
95.8
85
38.333
34
8
72.9
63.8
54.7
51
29.174
31.875
27.351
34
8
73.4
63.8
57.5
51
36.719
31.875
38.333
34
8
8
8
43.8
42.5
36.5
31.9
27.4
25.5
21.9
21.3
18.2
15.9
13.7
12.8
10.9
29.174
34
8
47.9
42.5
36.7
31.9
28.8
25.5
24
38.333
34
16
16
16
16
16
16
32
32
32
32
32
32
29.174
31.875
27.351
34
36.719
31.875
38.333
34
29.174
34
38.333
34
21.3
18.4
15.9
14.4
12.8
29.174
31.875
27.351
34
36.719
31.875
38.333
34
29.174
(1) Feedback divider is set automatically with respect to the prescaler setting.
(2) Discontinuity in frequency range.
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Device Setup Example
The following example illustrates the process to calculate the required AT-cut crystal frequency that is needed to
generate a desired output frequency.
Assume we need to generate an output frequency of 622.08MHz. We use Table 3 to find that the desired output
frequency lies between 583.5 and 680.0MHz.
Table 3. Crystal Frequency Selection and Device Settings (Selection)
DESIRED OUTPUT
FREQUENCY (MHz)
REQUIRED INPUT CRYSTAL
FREQUENCY (MHz)
VCO
SELECTION
OUTPUT
DIVIDER
PRESCALER
SETTING
FEEDBACK
DIVIDER(1)
From
680.0
583.5
510.0
To
From
34.000
29.174
31.875
To
766.7
680.0
587.5
38.333
34.000
36.719
VCO 2
VCO 1
VCO 2
1
1
1
3
3
4
20
20
16
(1) Feedback divider is set automatically with respect to the prescaler setting.
This frequency value means that the device must be configured in the following way:
VCO: VCO1
Output divider: 1
Prescaler setting: 3
To determine the correct crystal frequency required to achieve 622.08 MHz with these settings, we use
Equation 2, explained earlier in this data sheet.
1
fXTAL
=
´ 622.08 = 31.154 MHz
20
(2)
Thus, the AT-cut frequency should be 31.154 MHz (that is, between 29.174 MHz and 34.000 MHz, as shown in
Table 3).
Serial Interface and Control
The CDCE421A uses a unique, TI-proprietary interface protocol that can be configured and programmed via a
single input pin to the device. The architecture enables only writing to the device from this input pin. Reading the
content of a register can be achieved by sending a read command on the input pin and monitoring the desired
output pins (LVDS or LVPECL). In cases where the output pins cannot be used to read the content, the software
that controls the interface must account for what is written to the EEPROM and when it is programmed.
Monitoring the outputs verifies the programming modes; cycling the power on the device verifies that the
EEPROM contains the proper configuration.
The CDCE421A can be configured and programmed via the SDATA input pin. For this purpose, a pulse-code
shaped programming sequence must be written to the device as described in the EEPROM Programming
section. During the EEPROM programming phase, the device requires a stable supply voltage (VDD) of 3.3 V
±300 mV for securely writing to the EEPROM cells. After each Write to WordX instruction, the written data are
latched, made effective, and offer look-ahead before the actual data are stored into the EEPROM.
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Table 4 summarizes all valid programming commands for the CDCE421A.
Table 4. CDCE421A Programming Commands
SDATA
FUNCTION
001100
Enter Programming Mode (State 1→State 2); bits must be sent in the specified order with the
specified timing. Otherwise a time-out occurs.
111011
Enter Register Readback Mode; bits must be sent in the specified order with the specified timing.
Otherwise a time-out occurs.
000 xxxx xxxx
100 xxxx xxxx
010 xxxx xxxx
110 xxxx xxxx
001 xxxx xxxx
101 xxxx xxxx
111 xxxx xxxx
111 1111 0000
111 0101 0101
111 0000 0000
Write to Word0 (State 2)(1)(2)(3)
Write to Word1 (State 2)(1)(2)(3)
Write to Word2 (State 2)(1)(2)(3)
Write to Word3 (State 2)(1)(2)(3)
Write to Word4 (State 2)(1)(2)(3)
Write to Word5 (State 2)(1)(2)(3)
State Machine Jump: All other patterns not defined as below cause Exit to Normal Mode
Jump: Enter EEPROM programming without EEPROM lock (State2 →State 3)
Jump: Enter EEPROM programming with EEPROM lock (State 2→State 4)
Jump: Exit EEPROM programming (State 3 or State 4→State 1)
(1) Each rising edge causes a bit to be latched.
(2) In between the bits, some longer time delays can occur, but these delays have no effect on the data.
(3) A Write to WordX instruction is expected to be 10 bits long. After the tenth bit, the respective word is latched, and its effect can be
observed as a look-ahead function.
Outputs (LVPECL or LVDS)
The CDCE421A device has two sets of output drivers, LVPECL and LVDS, where the outputs are wire-ORed
together. Only one output can be selected at a given time; the other output goes to a high-impedance (Hi-Z)
state.
If the device is configured for LVPECL outputs, the output buffers go to Hi-Z ,and the termination resistors
determine the state of the output (LVPECLP = LVPECLN = Hi-Z) in the device disable mode (CE = L). If the
device is configured in LVDS mode, the outputs go to a Hi-Z state if the device is disabled (CE = L).
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State Flow
Power Up:
Read EEPROM
and configure
Write
Word0
Power-Up
Reset
Completed
Write
Word1
11th Bit
Written
SDATA =
000 xxxx xxxx
SDATA = 111011
SDATA =
100 xxxx xxxx
State1: Idle
Normal
Operation
11th Bit
Written
Write
Word2
State5:
Readback
Mode
SDATA =
111 1111 1111
SDATA =
010 xxxx xxxx
60th Clock
Applied
11th Bit
Written
State2:
Programming
Mode
SDATA = 001100
SDATA =
110 xxxx xxxx
Write
Word3
11th Bit
Written
SDATA =
001 xxxx xxxx
SDATA =
101 xxxx xxxx
SDATA =
111 0101 0101
SDATA =
111 1111 0000
11th Bit
Written
Write
Word4
11th Bit
Written
SDATA =
111 0000 0000
Write
Word5
SDATA =
111 0000 0000
State3:
State4:
Programming
EEPROM
Programming
EEPROM
No Locking
Locking
(1) In States 2, 3, 4, and 5, the signal pin CE is disregarded and has no influence on power down.
State Flow Diagram of Single Pin Interface
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Enter Programming Mode
Figure 2 shows the timing behavior of data to be written into SDATA. The sequence shown is '001100'. If the
high period is as short as t1, this period is interpreted as '0'. If the high period is as long as t3, this period is
interpreted as a '1'. This behavior is achieved by shifting the incoming signal SDATA by time t5 into signal
SDATA_DELAYED. As Figure 2 shows, SDATA_DELAYED can be used to latch (or strobe) SDATA. The
specification for the timings t1 through t7, tR and tF are shown in Table 5.
t7
CE
t6
t3
tF
tR
t1
t4
t2
SDATA
t5
SDATA
DELAYED
DATA
0
0
1
1
0
0
Figure 2. SDATA/CE Timing
Table 5. SDATA/CE Timing Requirements(1)
PARAMETER
MIN
TYP
70
MAX
UNIT
kHz
ms
fSDATACLK Repeat frequency of programming
60
80
t1
t2
Low signal: High pulse duration
0.2 t
0.8 t
0.8 t
0.8 t
0.2 t
0.2 t
Low signal: Low pulse duration during Entering Programming sequence
Low signal: Low pulse duration during programming bits
High signal: High pulse duration
ms
ms
t3
t4
ms
High signal: Low pulse duration during Entering Programming sequence
High signal: Low pulse duration during programming bits
ms
ms
t6
Time-out during Entering Programming Mode and Enter Readback Mode until
next bit must occur. High-pulse or low-pulse duration each must be less than this
time; otherwise, a time-out results.
16
3 t
ms
t7
EN-high time before first SDATA can be clocked in
Rise and fall time from 20% to 80% of VDD
ms
ns
tR/tF
2
(1) t = 1/fSDATACLK
.
EEPROM Programming
To program the EEPROM, follow the procedure outlined in this section.
Load all the registers in RAM by writing to Word0 ... Word5. After going back to State 2, then go to State 3
(Programming EEPROM, No Locking) or State 4 (Programming EEPROM with Locking). The contents of Word0
… to Word5 are saved in the EEPROM. Wait 10ms in State 3 or State 4 when programming the EEPROM
before moving to State 2 (idle state).
NOTE:
When writing to the device for functionality testing and verification via the serial bus,
you are only accessing the RAM. The programming of the CDCE421A can only be
performed at VCC = 3.3 V and at room temperature (+25°C).
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Programming Cycle of Six Words and Programming Into EEPROM Example
Figure 3 shows an Enter Programming Mode sequence and how the different words can be written. The
addressing of Word0 … Word5 can be seen in bold. After that, the inverted payload for the respective word is
clocked in. In this example, this step is followed by a Jump from State 2→State 3 into Enter EEPROM
programming with EEPROM lock. In the EEPROM programming state, it is required to wait at least 10ms for
save programming to occur. The last command is a jump from State 3 back to State 1 (normal operation). Then
cycle the power and verify that the device is functioning as programmed.
Enter Programming Sequence
Word0
Word1
Payload
Payload
After eight bits, the payload data
are transferred to the RAM
and become active
Word5
Payload
Wait for at least 10 ms
before exiting the EEPROM write phase
for save operation
State Machine Jump
State 2 ® State 3
State Machine Jump
State 3 ® State 1
Figure 3. Programming Cycle of Six Words and Programming Into EEPROM
Enter Register Readback Mode
Similar to the Enter Programming Mode sequence, the Enter Register Readback Mode is written into SDATA.
After the command has been issued, the SDATA-input is reconfigured as the clock input. By applying one clock,
the EEPROM content is read into the shift registers. Then, by applying further clocks at SDATA, the EEPROM
content can be clocked out and observed at FOUT. Additionally, FOUT is reconfigured during this operation, as
can be seen in Figure 4. There are 59 bits to be clocked out. With the 61st rising clock edge, the FOUR pin is
reconfigured for normal operation.
SDATA
1
1
1
0
1
1
Output Oscillation
Output Oscillation
FOUT
0
1
2
56
57
58
Enter Readback Sequence
Fetch EEPROM
content with
first CLK
EEPROM content: first bit available
after first falling edge
60th falling edge
switches back into
normal operation
Figure 4. Register Readback Mode Timing Sequence
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Table 6 summarizes the contents and functions of the output bit-stream. Note that bit 0 is clocked out first.
Table 6. Register Readback Mode: Output Bit-Stream
OUTPUT BIT-STREAM
FUNCTION
Bit[0:2]
Bit[3:8]
Bit[9]
Revision identifier (MSB first)
VCO calibration word
EEPROM Status:
0 = EEPROM has never been written
1 = EEPROM has been programmed before
Bit[10]
EEPROM Lock:
0 = EEPROM can be rewritten
1 = EEPROM is locked; rewriting the EEPROM is no longer possible
Bit[11:18]
Bit[19:26]
Bit[27:34]
Bit[35:42]
Bit[43:50]
Bit[51:58]
Storage value Word5 (MSB first)
Storage value Word4 (MSB first)
Storage value Word3 (MSB first)
Storage value Word2 (MSB first)
Storage value Word1 (MSB first)
Storage value Word0 (MSB first)
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REGISTER DESCRIPTION
Table 7. Word 0
Recommended
Bit
0
Name
C0
Description/Function
Type
W
Value
Register selection
Register selection
Register selection
0
0
1
C1
W
2
C2
W
0
3
SELVCO
VCO select:
0 = VCO1
1 = VCO2
W
User
4
5
6
7
8
9
SELPRESC
SELPRESC
OUTSEL
Prescaler setting, Bit 0
Prescaler setting, Bit 1
Output divider select, Bit 0
Output divider select, Bit1
Output divider select, Bit 2
W
W
W
W
W
W
User
User
User
User
User
User
OUTSEL
OUTSEL
DRVSEL
Driver select:
0 =LVDS
1=PECL
10
TITEST1
Reserved
W
1
4
5
6
7
8
Divide by value (SELPRESC 1, SELPRESC 0)
Divide by 5 = (00), 3 = (01), 4 = (10), and 2 = (11)
Output divider (OUTSEL2, OUTSEL1, OUTSEL0)
Divide by 1 = (000) , 2 = (001), 4 = (010), 8 = (011), 16 = (100), 32 = (101)
Table 8. Word 1
Recommended
Value
Bit
0
Name
C0
Description/Function
Register selection
Type
W
1
0
0
1
1
1
1
1
0
1
0
1
C1
Register selection
W
2
C2
Register selection
W
3
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
Loop filter control settings, Bit 0
Loop filter control settings, Bit 1
Loop filter control settings, Bit 2
Loop filter control settings, Bit 3
Loop filter control settings, Bit 4
Loop filter control settings, Bit 5
Loop filter control settings, Bit 6
Loop filter control settings, Bit 7
W
4
W
5
W
6
W
7
W
8
W
9
W
10
W
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Table 9. Word 2
Recommended
Bit
0
Name
C0
Description/Function
Type
W
Value
Register selection
Register selection
Register selection
0
1
0
1
1
0
0
0
0
0
0
1
C1
W
2
C2
W
3
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
Loop filter control settings, Bit 8
Loop filter control settings, Bit 9
Loop filter control settings, Bit 10
Loop filter control settings, Bit 11
Loop filter control settings, Bit 12
Loop filter control settings, Bit 13
Loop filter control settings, Bit 14
Loop filter control settings, Bit 15
W
4
W
5
W
6
W
7
W
8
W
9
W
10
W
Table 10. Word 3
Recommended
Value
Bit
0
Name
C0
Description/Function
Type
W
Register selection
Register selection
Register selection
1
1
0
0
0
0
1
1
1
1
0
1
C1
W
2
C2
W
3
LFRCSEL
LFRCSEL
LFRCSEL
ICPSEL
ICPSEL
ICPSEL
ICPSEL
TITEST2
Loop filter control settings, Bit 16
Loop filter control settings, Bit 17
Loop filter control settings, Bit 18
Charge pump current Sel, Bit 0
Charge pump current Sel, Bit 1
Charge pump current Sel, Bit 2
Charge pump current Sel, Bit 3
Reserved
W
4
W
5
W
6
W
7
W
8
W
9
W
10
W
Table 11. Word 4
Recommended
Value
Bit
0
Name
C0
Description/Function
Type
W
Register selection
Register selection
Register selection
0
0
1
0
0
0
0
0
0
0
1
1
C1
W
2
C2
W
3
CALWRD
CALWRD
CALWRD
CALWRD
CALWRD
CALWRD
CALOVR
ENCAL
VCO calibration Word, Bit 0
VCO calibration Word, Bit 1
VCO calibration Word, Bit 2
VCO calibration Word, Bit 3
VCO calibration Word, Bit 4
VCO calibration Word, Bit 5
VCO calibration override
Enable VCO calibration
W
4
W
5
W
6
W
7
W
8
W
9
W
10
W
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Table 12. Word 5
Recommended
Bit
0
Name
C0
Description/Function
Type
W
Value
Register selection
Register selection
Register selectiond
TI Test Use, Bit 0
TI Test Use, Bit 1
TI Test Use, Bit 2
TI Test Use, Bit 3
1
0
1
0
0
0
0
0
0
0
0
1
C1
W
2
C2
W
3
TITSTCFG
TITSTCFG
TITSTCFG
TITSTCFG
Not used
Not used
Not used
Not used
W
4
W
5
W
6
W
7
W
8
W
9
W
10
W
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Appendix A: Test Configurations
Test setups are used to characterize the CDCE421A device in both ac- and dc-termination. Figure 5 through
Figure 8 illustrate all four setups used to terminate the clock signal driven by the device under test.
100 W
LVDS
LVDS
Figure 5. LVDS DC Termination Test Configuration
50 W
LVPECL
LVPECL
50 W
VCC - 2 V
Figure 6. LVPECL DC Termination Test Configuration
Phase Noise
Analyzer
LVDS
50 W
Figure 7. LVDS AC Termination Test Configuration
Phase Noise
Analyzer
150 W
LVPECL
150 W
150 W
Figure 8. LVPECL AC Termination Test Configuration
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Appendix B: Jitter Characteristics in Input Clock Mode
If the CDCE421A is being referenced by an external and cleaner LVCMOS input of 35.42 MHz and 33.33 MHz,
respectively, Figure 9 and Table 13 show the SSB phase noise plot and phase noise data of the output at 708
MHz for LVPECL from 100 Hz to 40 MHz from the carrier.
0
-20
-40
-60
-80
-100
-120
-140
-160
10
100
1k
10k
100k
1M
10M
100M
Single-Sideband Frequency (Hz)
Figure 9. SSB Phase Noise at 708-MHz LVPECL Output with LVCMOS Input of 35.42 MHz
Table 13. Phase Noise Data for LVPECL at 708 MHz with LVCMOS Input of 35.42 MHz(1)
PARAMETER
MIN
TYP
–95
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
Phase noise at 100 Hz
Phase noise at 1 kHz
–105
–109
–114
–126
–146
–146
438
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter from 10 kHz to 20 MHz
(1) Phase noise specifications under following assumptions: input frequency = 35.42 MHz (VCO = 2, prescaler = 3, output divider = 1),
output frequency = 708 MHz at LVPECL.
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Figure 10 and Table 14 show the SSB phase noise plot and phase noise at 400 MHz for LVDS from 100 Hz to
40 MHz from the carrier. See Figure 7 and Figure 8 for the test configuration setup for LVPECL and LVDS ac
termination, respectively.
0
-20
-40
-60
-80
-100
-120
-140
-160
10
100
1k
10k
100k
1M
10M
100M
Single-Sideband Frequency (Hz)
Figure 10. SSB Phase Noise at 400-MHz LVDS Output with LVCMOS Input of 33.33 MHz
Table 14. Phase Noise Data for LVDS at 400 MHz with LVCMOS Input of 33.33 MHz(1)
PARAMETER
MIN
TYP
–99
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
Phase noise at 100 Hz
Phase noise at 1 kHz
–109
–119
–121
–130
–147
–147
409
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
RMS jitter from 10 kHz to 20 MHz
(1) Phase noise specifications under following assumptions: input frequency = 33.33 MHz (VCO = 1, prescaler = 5, output divider = 1),
output frequency = 400 MHz at LVDS.
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Appendix C: Application Information
CDCE421 User Information
The CDCE421A includes several device enhancements to the CDCE421.
•
Device Startup
The CDCE421A includes an improved device startup circuit that enables the CDCE421A to be used in
stand-alone applications (for example, configurations in which the device is not connected to a host system).
This design operates over various power-supply ramp time scenarios. For proper operation of the startup
circuit, certain register bits must be programmed as specified in Table 15.
Table 15. CDCE421 vs. CDCE421A Register Settings
CDCE421A
DATA SHEET
REGISTER LOCATION
CDCE421
CDCE421A
REFERENCE
TITEST1 (must always
be written '1')
Word 0, Bit 10
Loop filter bias select
Table 7
TITEST2 (must always
be written '0')
Word 3, Bit 10
Not used
Table 10
space
•
•
LVDS Output Buffer
The CDCE421A incorporates an improved LVDS output buffer. Therefore, the electrical characteristics of the
LVDS output buffer on the CDCE421A are different from those of the CDCE421. Refer to the Electrical
Characteristics table for the details of the CDCE421A LVDS output buffer.
Product Revision Identification
For the product revision identifier bits (bits [2:0]), the value presented by the CDCE421A is '000'. See Table 6
for more details.
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Startup Time Estimation
The startup time for the CDCE421A can be estimated based on the parameters defined in Table 16 and
illustrated in Figure 11.
Based on these parameters, the CDCE421A startup time limits tMAX and tMIN can be calculated as shown in these
equations:
tMAX = tpuh + trsu + tdelay + tVCO_CAL + tPLL_LOCK
tMIN = tpul + trsu + tdelay + tVCO_CAL + tPLL_LOCK
Table 16. Timing Definitions: Startup Time Dependencies
Parameter
Definition
Description
Formula/Method of Determination
1
The reciprocal of the applied reference
frequency (in seconds).
tREF
=
tREF
Reference Clock Period
fREF
Power-Up Time (low
limit)
Power-supply rise time to low limit of Power
On Reset (POR) trip point.
Time required for Power Supply to
ramp to 2.27 V.
tpul
Power-Up Time (high
limit)
Power-supply rise time to high limit of POR
trip point.
Time required for Power Supply to
ramp to 2.64 V.
tpuh
After POR releases, the Colpits oscillator is
enabled. This startup time is required for the
Best case: 500 µs
trsu
Reference Startup Time oscillator to generate the requisite signal
levels for the delay block to be clocked by
the reference input.
Worst case: 800 µs (for a crystal input)
0 s (for an LVCMOS input)
Internal delay time generated from the
tdelay
Delay Time
reference clock. This delay provides time for
the reference oscillator to stabilize.
tdelay = 16384 × tREF
VCO Calibration Time generated from the
reference clock. This process selects the
operating point for the VCO based on the
PLL settings.
tVCO_CAL
VCO Calibration Time
PLL Lock Time
tVCO_CAL = 550 × tREF
Time required for PLL to lock within ±10 ppm Based on the 400-kHz loop bandwidth,
of fREF the PLL will settle in 5 τ or 12.5 µs.
tPLL_LOCK
.
Reference
Startup
Power up
Delay
VCO Calibration
PLL Lock
2.64 V
2.27 V
tpul
tpuh
trsu
tVCO_CAL
Time (s)
tPLL_LOCK
tdelay
Figure 11. Startup Time Dependencies
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2015
PACKAGING INFORMATION
Orderable Device
CDCE421ARGER
CDCE421ARGET
CDCE431YS
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VQFN
VQFN
RGE
24
24
0
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
CDCE
421A
ACTIVE
RGE
YS
250
1
Green (RoHS
& no Sb/Br)
-40 to 85
CDCE
421A
ACTIVE WAFERSALE
TBD
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCE421ARGER
CDCE421ARGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CDCE421ARGER
CDCE421ARGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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