CDCE62002_技术文档

CDCE62002

www.ti.com.............................................................................................................................................................. SCAS882A–JUNE 2009–REVISED JULY 2009

Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

1

FEATURES

•

Flexible Inputs With Innovative Smart

Multiplexer Feature:

•

Frequency Synthesizer With PLL/VCO and

Partially Integrated Loop Filter

–

Two Universal Differential Inputs Accept

Frequencies from 1 MHz up to 500 MHz

(LVPECL), 500 MHz (LVDS), or 250 MHz

(LVCMOS).

Fully Configurable Outputs Including

Frequency and Output Format

Smart Input Multiplexer Automatically

Switches Between one of two Reference

Inputs.

–

One Auxiliary Input Accepts Single Ended

Clock Source or Crystal. Auxiliary Input

Accepts Crystals in the Range of

2MHz–42MHz or an LVCMOS Input up to

75MHz.

•

Multiple Operational Modes Include Clock

Generation via Crystal, SERDES Startup Mode,

Jitter Cleaning, and Oscillator Based Holdover

Mode.

–

Clock Generator Mode Using Crystal Input

Smart Input Multiplexer can be Configured

to Automatically Switch Between Highest

Priority Clock Source Available Allowing

for Fail-Safe Operation.

•

Integrated EEPROM Determines Device

Configuration at Power-up.

•

Excellent Jitter Performance

Integrated Frequency Synthesizer Including

PLL, Multiple VCOs, and Loop Filter:

•

Typical Power Consumption 750mW at 3.3V

Integrated EEPROM Stores Default Settings;

Therefore, the Device can Power up in a

Known, Predefined State.

–

Full Programmability Facilitates Phase

Noise Performance Optimization Enabling

Jitter Cleaner Mode

•

Offered in QFN-32 Package

–

Programmable Charge Pump Gain and

Loop Filter Settings

ESD Protection Exceeds 2kV HBM

Industrial Temperature Range –40°C to 85°C

Unique Dual-VCO Architecture Supports a

Wide Tuning Range 1.750 GHz – 2.356 GHz.

APPLICATIONS

•

Universal Output Blocks Support up to 2

Differential, 4 Single-Ended, or Combinations

of Differential or Single-Ended:

•

Data Converter and Data Aggregation Clocking

Wireless Infrastructure

Switches and Routers

Medical Electronics

Military and Aerospace

Industrial

Clock Generation and Jitter Cleaning

–

0.5 ps RMS (10 kHz to 20 MHz) Output

Jitter Performance

Low Output Phase Noise: –130 dBc/Hz

at 1 MHz offset, Fc = 491.52 MHz

Output Frequency Ranges From 10.94

MHz to 1.175 GHz in Synthesizer Mode

–

LVPECL, LVDS and LVCMOS

Independent Output Dividers Support

Divide Ratios for

1,2,3,4,5,8,10,12,16,20,24 and 32.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CDCE62002

SCAS882A–JUNE 2009–REVISED JULY 2009.............................................................................................................................................................. www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION

The CDCE62002 is a high performance clock generator featuring low output jitter, a high degree of configurability

via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for

clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5

ps RMS⁽¹⁾. It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block

including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock

distribution block includes two individually programmable outputs that can be configured to provide different

combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique

output frequency (ranging from 10.94 MHz to 1.175 GHz⁽²⁾). If Both outputs are configured in single-ended mode

(e.g., LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential

inputs which support frequencies up to 500 MHz and an auxiliary single ended input that can be connected to a

CMOS level clock or configured to connect to an external AT-Cut crystal via an on board oscillator block. The

smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the

synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select

between the highest priority input clock available.

Data

Cleaned Clock

SERDES

ASIC

ASIC Clock

Recovered Clock

CDCE62002

Figure 1. CDCE62002 Application Example

(1) 10 kHz to 20 MHz integration bandwidth.

(2) Frequency range depends on operational mode and output format selected.

2

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DEVICE INFORMATION

PIN FUNCTIONS

Table 1. CDCE62002 Pin Functions⁽¹⁾

TYPE

DESCRIPTION

NAME

QFN

VCC_OUT0

VCC_OUT1

9,12 13,16

Power

3.3V Supply for the Output Buffers.

There is no internal connection between V_CCand AV_CC. It is recommended, that each V_CC

uses its own supply filter.

VCC_PLLDIV

VCC_PLLD

VCC_PLLA

VCC_VCO

VCC_IN

22

4

Power

3.3V Supply Power for the PLL circuitry.

28

24

31

1

A. Power 3.3V Supply Power for the PLL circuitry.

A. Power 3.3V Supply Power for the VCO Circuitry.

Power

3.3V Supply Power for Input Buffer Circuitry

VCC_AUX

GND_PLLDIV

GND

A. Power 3.3V Supply Power for Crystal/Auxiliary Input Buffer Circuitry

21

PAD

7

Ground

OD

Ground for PLL Divider circuitry. (short to GND)

Ground is on Thermal PAD. See Layout recommendation

SPI_MISO

3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial Data

Output to the SPI bus interface.

SPI_LE

18

I

LVCMOS input, control Latch Enable for Serial Programmable Interface.

Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly on the

Rising edge of PD. The input has an internal 150-kΩ pull-up resistor

SPI_CLK

17

8

I

LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis.

SPI_MOSI

LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62002 for the

SPI bus interface.

PD

6

I

PD or Power Down Pin is an active low pin and can be activated externally or via the

corresponding Bit in SPI Register 2

In case of PD is asserted , the Device shuts Down and after PD goes high the EEPROM

Loads into RAM and the VCO core re-starts calibration, PLL will try to relock and the

Output dividers will get re-initiated. The LVPECL outputs are static low and high

respectively and the LVCMOS outputs are all low or high if inverted. The input has an

internal 150-kΩ pull-up resistor if left unconnected it will default to logic level “1”.

Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly into

RAM on the Rising edge of PD.

AUX_IN

2

I

Auxiliary Input is a Crystal input pin that connect to an internal oscillator circuitry. This

input can also be driven by an LVCMOS signal.

This input also serves as the External Feedback Input that feeds directly to the PFD.

Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Reference Clock.

REF+

REF–

29

30

I

Universal Input Buffer (LVPECL, LVDS,) negative input for the Reference Clock. In case of

LVCMOS signaling pull-down this pin.

PLL_LOCK

TESTSYNC

REG_CAP1

REG_CAP2

REG_CAP3

REG_CAP4

VBB

32

O

PLL Lock indicator

19

I

Test Point for Use for TI Internal SYNC Testing.

5

Analog

O

Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)

Capacitor for the internal termination Voltage. Connect to a 1 µF Capacitor (Y5V)

External Loop Filter Input Positive

27

20

23

3

EXT_LFP

EXT_LFN

25

26

External Loop Filter Input Negative.

U0P:U0N

U1P:U1N

11,10 15,14

The Main outputs of CDCE62002 are user definable and can be any combination of up to

2 LVPECL outputs, 2 LVDS outputs or up to 4 LVCMOS outputs. The outputs are

selectable via SPI interface. The power-up setting is EEPROM configurable.

(1) NOTE: All VCC pins need to be connected for the device to operate properly.

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FUNCTIONAL DESCRIPTION

EXT_LFP

EXT_LFN

U0 P

Output

Reference

Divider

Divider 0

U0N

REF_IN

XTAL /

AUX_IN

U1 P

U1N

Output

Divider 1

Input

Divider

PFD /

CP

Prescaler

Feedback

Divider

PD

Interface

&

SPI_LE

SPI _CLK

EEPROM

Control

SPI_MOSI

SPI_MISO

Figure 2. CDCE62002 Block Diagram

The CDCE62002 comprises of four primary blocks: the interface and control block, the input block, the output

block, and the synthesizer block. In order to determine which settings are appropriate for any specific

combination of input/output frequencies, a basic understanding of these blocks is required. The interface and

control block determines the state of the CDCE62002 at power-up based on the contents of the on-board

EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE62002 by writing directly

to the device registers after power-up. The input block selects which of the two input ports is available for use by

the synthesizer block. The output block provides two separate clock channels that are fully programmable. The

synthesizer block multiplies and filters the input clock selected by the input block.

NOTE:

This Section of the data sheet provides a high-level description of the features of the

CDCE62002 for purpose of understanding its capabilities. For a complete description

of device registers and I/O, refer to the Device Configuration Section.

4

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Interface and Control Block

The CDCE62002 is a highly flexible and configurable architecture and as such contains a number of registers so

that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM

determine device configuration at all times. On power-up, the CDCE62002 copies the contents of the EEPROM

into the RAM and the device begins operation based on the default configuration stored in the EEPROM.

Systems that do not have a host system to communicate with the CDCE62002 use this method for device

configuration. The CDCE62002 provides the ability to lock the EEPROM; enabling the designer to implement a

fault tolerant design. After power-up, the host system may overwrite the contents of the RAM via the SPI (Serial

Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62002 during system

operation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM, if the EEPROM is

unlocked.

Static RAM Device Registers

Interface

PD

Register 2

Register

Device

SPI_ LE

SPI_ CLK

SPI_ MOSI

SPI_ MISO

&

Control

1

Hardware

Register 0

EEPROM Device Registers

Register 2

Register

1

Register 0

Figure 3. CDCE62002 Interface and Control Block

Input Block

The Input Block includes one Universal Input Buffer and an Auxiliary Input. The Input Block buffers the incoming

signals and facilitates signal routing to the Internal Synthesizer Block via the smart multiplexer (called the Smart

MUX). The CDCE62002 can divide the REF_IN signal via the dividers present on the inputs of the first stage of

the Smart MUX.

Smart MUX

Control

LVPECL/LVDS 500 MHz

Reference Divider

LVCMOS 250 MHz

REF_IN

/1 - /8

Synthesizer

Reference

Crystal: 2 MHz – 42 MHz XTAL/

Single Ended: 2 MHz - 75 MHz AUX_IN

Figure 4. CDCE62002 Input Block

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Synthesizer Block

Figure 5 presents a high-level overview of the Synthesizer Block on the CDCE62002. This block contains the

Phase lock loop, internal loop filter and dual Voltage controlled oscillators. Only one VCO is selected at a time.

The loop is closed after a Prescaler divider that feeds the output stage the feedback divider.

1.75 GHz –

2.356 GHz

SMART_MUX

AUX_IN

Input Divider

/1 - /256

SYNTH

PFD/

CP

Prescaler

/2,/3,/4,/5

70 kHz –

400 kHz

/1,/2,/5,/8,/10,/16,/20

Feedback Bypass Divider

/8 - /1280

Feedback Divider

Figure 5. CDCE62002 Synthesizer Block

Output Block

Both identical output blocks incorporate a Clock Divider Module (CDM), and a universal output array buffer

driver. If an individual clock output channel is not used, then the user should disable the CDM and Output Buffer

for the unused channel to save device power. Each channel includes 4-bit in register “0” to control the divide

ratio. The output divider supports divide ratios from divide by 1 (bypass the divider) 2,3,4,5,8,10,12,16,20,24 and

32.

Output Buffer Control

Sync

Pulse

Enable

Digital Phase Adjust (7-bits)

UxP

UxN

SYNTH

/1,2,3,4C,5lock Di/v1id-e/r8Module 0/2& 1

LVDS

LVPECL

Figure 6. CDCE62002 Output Block

6

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COMPUTING THE OUTPUT FREQUENCY

Figure 7 presents the block diagram of the CDCE62002 synthesizer highlighting the clock path for a single

output. It also identifies the following regions containing dividers comprising the complete clock path:

•

R: Is the Reference divider values.

O: The output divider value (see Output Block for more details)

I: The input divider value (see Synthesizer Block for more details)

P: The Prescaler divider value (see Synthesizer Block of more details)

F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for

more details)

R

Reference

Divider

Fin

O

Output

U0P

F_OUT

U0N

Divider 0

EXT_LFP

EXT_LFN

I

Input

Divider

P

U1P

U1N

Output

PFD/

CP

Prescaler

Divider 1

Feedback

Divider

F

Figure 7. CDCE62002 Clock Path – Synthesizer

With respect to Figure 7, any output frequency generated by the CDCE62002 relates to the input frequency

connected to the Synthesizer Block by the following equation:

F

F_OUT= F

×

IN

R ×I×O

(1)

(2)

Equation 1 holds true subject to the following constraints:

1.750GHz < O×P×F_OUT< 2.356GHz

And the comparison frequency F_COMP

40.0 kHz ≤ F_COMP≤ 40 MHz

Where:

,

F

IN

F_COMP

=

R×I

(3)

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE / UNIT

Supply voltage range VCC⁽²⁾

–0.5 V to 4.6 V

–0.5 V to VCC + 0.5 V

±20 mA

(3)

Input voltage range, V_I

(3)

Output voltage range, V_O

Input Current (V_I< 0, V_I> VCC)

Output current for LVPECL/LVCMOS Outputs (0 < V_O< V_CC

)

±50 mA

Maximum junction temperature, T_J

125°C

Storage temperature range, T_stg

–65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All supply voltages have to be supplied simultaneously.

(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

THERMAL CHARACTERISTICS

Package Thermal Resistance for QFN (RGZ) Package

Airflow (lfm)

θ_JP(°C/W)

1.13

θJA (°C/W)

35

0

JEDEC Compliant Board (3X3 VIAs on PAD)

200

400

1.13

28.3

1.13

27.2

PACKAGE

The CDCE62002 is packaged in a 32-Pin Lead Free “Green” Plastic Quad Flatpack Package with enhanced

bottom thermal pad for heat dissipation. The Texas Instruments Package Designator is; RHB (S-PQFP-N32).

Please refer to the Mechanical Data appendix at the end of this document for more information.

ELECTRICAL CHARACTERISTICS

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

POWER SUPPLY

Supply voltage, V_{CC_OUT}, V_{CC_PLLDIV}, V_{CC_PLLD}, V_{CC_IN}, and V_{CC_AUX}

Analog Supply Voltage, VCC_PLLA, & VCC_VCO

3

3.3

3.6

V

REF at 30.72MHz

P_LVPECL

850

750

800

mW

Outputs are LVPECL

Output 1 = 491.52 MHz

Output 2 = 245.76 MHz

In case of LVCMOS Outputs (1) =

245.76MHz

REF at 30.72MHz

Outputs are LVDS

P_LVDS

REF at 30.72MHz

Outputs are LVCMOS

P_LVCMOS

P_OFF

P_PD

REF at 30.72MHz

Dividers and Outputs are disabled

Device is Powered Down

450

40

mW

DIFFERENTIAL INPUT MODE (REF_IN)

Input amplitude, VINPP (V_IN+– V_IN–

)

0.1

1.0

1.3

V

Common-mode input voltage, VIC

V_CC–03

VI = VCC,

VCC = 3.6 V

I_IH

I_IL

Differential input current High (No internal Termination)

Differential input current Low (No internal Termination)

20

µA

VI = 0 V,

VCC = 3.6 V

–20

0

µA

Input Capacitance on REF_IN

3

pF

LVCMOS INPUT MODE (AUX_IN)

V_IL

Low-level input voltage LVCMOS

0.3 VCC

V

(1) All typical values are at VCC = 3.3 V, temperature = 25°C.

8

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ELECTRICAL CHARACTERISTICS (continued)

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

VCC

–1.2

UNIT

V

V_IH

V_IK

I_IH

High-level input voltage LVCMOS

LVCMOS input clamp voltage

LVCMOS input current

0.7 VCC

VCC = 3 V, II = –18 mA

V

VI = VCC, VCC = 3.6 V

VI = 0 V, VCC = 3.6 V

VI = 0 V or VCC 8

300

8

µA

pF

I_IL

LVCMOS input

–10

10

C_I

Input capacitance (LVCMOS signals)

CRYSTAL INPUT SPECIFICATIONS

Crystal Shunt Capacitance

10

50

pF

Equivalent Series Resistance (ESR)

LVCMOS INPUT MODE (SPI_CLK,SPI_MOSI,SPI_LE,PD, REF_IN)

Ω

V_IL

V_IH

V_IK

I_IH

I_IL

Low-level input voltage LVCMOS

High-level input voltage LVCMOS

LVCMOS input clamp voltage

LVCMOS input current VI =

0

0.3 VCC

VCC

–1.2

20

V

0.7 VCC

VCC = 3 V, II = –18 mA

VCC, VCC = 3.6 V

V

µA

pF

LVCMOS input (Except REF_IN)

LVCMOS input (REF_IN)

VI = 0 V, VCC = 3.6 V

VI = 0 V or VCC 3

–10

–40

I_IL

10

C_I

Input capacitance (LVCMOS signals)

3

SPI OUTPUT (MISO) / PLL

I_OHHigh-level output current

I_OL

VCC = 3.3 V,

V_O= 1.65 V

–30

33

mA

Low-level output current

V_O= 1.65 V

High-level output voltage for LVCMOS

outputs

V_OH

V_OL

VCC = 3 V,

I_OH= –100 µA

VCC–0.5

V

Low-level output voltage for LVCMOS

outputs

I_OH= 100 µA

0.3

C_O

Output capacitance o MISO

VCC = 3.3 V; V_O= 0 V or VCC

V_O= V_CC, V_O= 0 V

3

5

pF

µA

I_OZH

3-state output current

I_OZL

–5

EEPROM

EEcyc

EEret

Programming cycle of EEPROM

Data retention

100

10

1000

Cycles

Years

VBB ( INPUT BUFFER INTERNAL TERMINATION VOLTAGE REFERENCE)

V_BBInput termination voltage IBB = –0.2 mA, Depending on the setting

INPUT BUFFERS INTERNAL TERMINATION RESISTORS (REF_IN)

1.2

1.9

40

V

Termination resistance

PHASE DETECTOR

f_CPmaxCharge pump frequency

Single ended

5

kΩ

0.04

MHz

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ELECTRICAL CHARACTERISTICS (Continued)

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX UNIT

LVCMOS

f_clk

Output frequency, see Figure below

Load = 5 pF to GND

250 MHz

V

V_OH

V_OL

High-level output voltage for LVCMOS outputs V_CC= min to max I_OH= –100 µA

Low-level output voltage for LVCMOS outputs V_CC= min to max I_OL= 100 µA

VCC–0.5

0.3

V

I_OH

High-level output current

VCC = 3.3 V

VO = 1.65 V

–30

33

mA

ps

I_OL

Low-level output current

t_sko

Skew, output to output For Y0 to Y1

Both Outputs set at 122.88 MHz,

Reference = 30.72 MHz

75

C_O

Output capacitance on Y0 to Y1

Tristate LVCMOS output current

Power Down output current

LVCMOS

VCC = 3.3 V; VO = 0 V or VCC

VO = VCC

5

pF

µA

I_OZH

I_OZL

VO = 0 V

-5

I_OPDH

I_OPDL

Duty cycle

t_slew-rate

VO = VCC

25

5

VO = 0 V

45%

3.6

55%

Output rise/fall slew rate

5.2

V/ns

(1) All typical values are at VCC = 3.3 V, temperature = 25°C.

5 pF

LVCMOS

10

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ELECTRICAL CHARACTERISTICS (Continued)

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°C

PARAMETER

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX UNIT

LVDS OUTPUT

f_clk

Output frequency

Configuration Load (see Figure below)

0

800

550

50

MHz

mV

V

|VOD|

ΔV_OD

V_OS

Differential output voltage

LVDS VOD Magnitude Change

Offset Voltage

R_L= 100 Ω

270

–40°C to 85°C

1.24

40

ΔV_OS

VOS Magnitude Change

mV

mA

ps

Short Circuit Vout+ to Ground

Short Circuit Vout- to Ground

Skew, output to output For Y0 to Y1

VOUT = 0

27

t_sk(o)

Both Outputs set at 122.88 MHz

Reference = 30.72 MHz

10

5

C_O

Output capacitance on Y0 to Y1

Power Down output current

Duty Cycle

VCC = 3.3 V; VO = 0 V or VCC

VO= V_CC

pF

µA

I_OPDH

I_OPDL

25

5

VO= 0 V

45%

55%

190

t_r/ t_f

Rise and fall time

20% to 80% of Voutpp

110

160

1.7

ps

ns

LVCMOS-TO-LVDS

t_{skP_C}

Output skew between LVCMOS and LVDS outputs VCC/2 to Crosspoint

1.4

2.0

(1) All typical values are at VCC = 3.3 V, temperature = 25°C.

LVDS DC Termination Test

100Ω

Oscilloscope

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ELECTRICAL CHARACTERISTICS (Continued)

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of –40°C

to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX

UNIT

LVPECL OUTPUT

f_clk

Output frequency,

Configuration Load (see Figure below)

0

VCC –1.1

VCC –2.02

510

1175

VCC –0.88

VCC –1.48

870

MHz

V

V_OH

V_OL

|VOD|

t_sko

LVPECL high-level output voltage

LVPECL low-level output voltage

Differential output voltage

Skew, output to output For Y0 to Y1

Output capacitance on Y0 to Y1

Power Down output current

Duty Cycle

Load

V

mV

ps

Both Outputs set at 122.88 MHz

VCC = 3.3 V; VO = 0 V or VCC

VO= V_CC

15

5

pF

µA

CO

I_OPDH

25

5

I_OPDL

VO= 0 V

45%

55

55%

735

t_r/ t_f

Rise and fall time

20% to 80% of Voutpp

Crosspoint to Crosspoint

75

200

1.8

ps

ns

LVDS-TO- LVPECL

t_{skP_C}

Output skew between LVDS and LVPECL outputs

130

1.6

280

2.2

LVCMOS-TO- LVPECL

t_{skP_C}

Output skew between LVCMOS and LVPECL outputs VCC/2 to Crosspoint

LVPECL Hi-PERFORMANCE OUTPUT

V_OH

LVPECL high-level output voltage

LVPECL low-level output voltage

Differential output voltage

Rise and fall time

Load

VCC –1.11

VCC –2.06

670

VCC –0.91

VCC –1.84

950

V

V_OL

|VOD|

t_r/ t_f

mV

ps

20% to 80% of Voutpp

55

75

135

(1) All typical values are at VCC = 3.3 V, temperature = 25°C.

LVPECL AC Termination Test

LVPECL DC Termination Test

50W

Oscilloscope

50W

150W

50W

Oscilloscope

Vcc-2

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HIGH-PERFORMANCE LVPECL

LVPECL OUTPUT VOLTAGE SWING

OUTPUT VOLTAGE SWING

vs

FREQUENCY

1000

950

900

850

800

750

700

650

600

550

500

450

1200

1150

1100

1050

1000

950

T = 25°C

R = 50 Ω to VCC − 2 V

L

T = 25°C

R = 50 Ω to VCC − 2 V

L

A

VCC = 3.6 V

VCC = 3.3 V

VCC = 3.6 V

VCC = 3.3 V

900

850

800

750

VCC = 3 V

700

650

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

f − Frequency − MHz

G002

G001

Figure 8.

Figure 9.

LVDS OUTPUT VOLTAGE SWING

LVCMOS OUTPUT VOLTAGE SWING

vs

FREQUENCY

500

475

450

425

400

375

350

325

300

275

250

225

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3.0

2.9

2.8

2.7

T = 25°C

R = 100 Ω

L

T = 25°C

C = 5 pF

L

A

VCC = 3.6 V

VCC = 3.3 V

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

0

100 200 300 400 500 600 700 800 900

f − Frequency − MHz

50

100

150

200

250

300

f − Frequency − MHz

G003

G004

Figure 10.

Figure 11.

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TIMING REQUIREMENTS

over recommended ranges of supply voltage, load and operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

REF_IN REQUIREMENTS

f_{REF – Diff IN-DIV}

Maximum clock frequency applied to reference divider when (Register 0 Bit 9 = 1)

(Reg 0 RAM bit 9 = 1)

500

250

MHz

f_{REF – Diff REF_DIV}

Maximum clock frequency applied to reference divider when (Register 0 Bit 9 = 0)

(Reg 0 RAM bit 9 = 0)

f_{REF– Single}

For Single ended Inputs ( LVCMOS) on REF_IN

Duty cycle of REF_IN at V_CC/ 2

250

60%

Duty Cycle Single

Duty Cycle Diff

40%

Duty cycle of REF_IN at V_CC/ 2

AUXILARY_IN REQUIREMENTS

f_{REF – Single}

For Single ended Inputs (LVCMOS) on AUX_IN

2

75

42

MHz

f_{REF – Crystal}

PD REQUIREMENTS

t_r/ t_f

For Single ended Inputs (AT-Cut Crystal Input)

Rise and fall time of the PD signal from 20% to 80% of V_CC

4

ns

PHASE NOISE ANALYSIS

Table 2. Phase Noise for 30.72MHz External Reference

Phase Noise Specifications under following configuration: VCO = 1966.08 MHz, REF_IN = 30.72MHz,

PFD Frequency = 30.72MHz, Charge Pump Current = 1.5mA Loop BW = 400kHz at 3.3V and 25°C.

PHASE NOISE

AT

Reference

30.72MHz

LVPECL-HP

491.52MHz

LVPECL

491.52MHz

LVDS-HP

491.52MHz

LVDS

491.52MHz

LVCMOS-HP

122.88MHz

LVCMOS

122.88MHz

UNIT

10Hz

–108

–130

–134

–152

–156

–157

—

–84

–98

–84

–98

–85

–98

–85

–97

dBc/Hz

100Hz

1kHz

–110

–118

–130

–133

–143

–152

–111

–118

–130

–133

–142

–151

–106

–118

–121

–131

–146

–106

–118

–121

–131

–146

–106

–118

–121

–130

–146

–106

–118

–121

–130

–145

10kHz

100kHz

1MHz

10MHz

20MHz

—

Jitter(RMS)

10k~20MHz

195

(10k~20Mhz)

319

316

332.4

332.2

366.5

372.1

fs

Table 3. Phase Noise for 25MHz Crystal Reference

Phase Noise Specifications under following configuration: VCO = 2000.00 MHz, AUX_IN -REF = 25.00MHz,

PFD Frequency = 25.00MHz, Charge Pump Current = 1.5mA Loop BW = 400kHz 3.3V and 25°C.

Phase Noise at

Reference

25.00MHz

LVPECL-HP

500.00MHz

LVDS-HP

250.00MHz

LVCMOS-HP

125.00MHz

UNIT

10Hz

—

–72

–97

–72

–97

–79

–103

–118

–126

–130

–142

–151

443

dBc/Hz

fs

100Hz

1kHz

–111

–120

–124

–136

–147

–148

426

–111

–120

–124

–136

–147

–148

426

10kHz

100kHz

1MHz

10MHz

20MHz

Jitter(RMS)

10k~20MHz

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OUTPUT TO OUTPUT ISOLATION

Measurement Method

1. Connect output 1 to the phase noise and Spectrum analyzer.

2. Measure spurious on Outputs 1.

3. Enable aggressor channel 0

4. Measure spurious on Output 1

5. The difference between the spurious levels of Outputs 1 before and after enabling the aggressor channel determine the output-to-output

isolation performance recorded.

Table 4. Output to Output Isolation

WORST CASE SPUR

UNIT

The Output to Output Isolation was tested at 3.3V supply and 25°C ambient temperature (Default Configuration):

Output 1

Measured Channel

In LVDS Signaling at 125MHz

-70

dB

Output 0

Aggressor Channel

LVPECL 156.25MHz

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SPI CONTROL INTERFACE TIMING

t1

t4

t5

SPI_CLK

SPI_MOSI

SPI_LE

t2

t3

Bit0

Bit1

Bit29

Bit30

Bit31

t7

t6

Figure 12. Timing Diagram for SPI Write Command

t4

t5

SPI_CLK

t2

t3

Bit30

Bit31

SPI_MOSI

SPI_MISO

SPI_LE

Bit1

Bit2

Bit0

t7

t6

t8

Figure 13. Timing Diagram for SPI Read Command

Table 5. SPI Bus Timing Characteristics

SPI BUS TIMINGS

PARAMETER

MIN

TYP

MAX UNIT

f_Clock

t₁

Clock Frequency for the SPI_CLK

SPI_LE to SPI_CLK setup time

SPI_MOSI to SPI_CLK setup time

SPI_MOSI to SPI_CLK hold time

SPI_CLK high duration

20

MHz

ns

10

25

10

20

10

t₂

ns

t₃

ns

t₄

ns

t₅

SPI_CLK low duration

ns

t₆

SPI_CLK to SPI_LE Setup time

SPI_LE Pulse Width

ns

t₇

ns

t₈

SPI_MISO to SPI_CLK Data Valid (First Valid Bit after LE)

ns

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DEVICE CONFIGURATION

The Functional Description Section described four different functional blocks contained within the CDCE62002.

Figure 14 depicts these blocks along with a high-level functional block diagram of the circuit elements comprising

each block. The balance of this section focuses on a detailed discussion of each functional block from the

perspective of how to configure them.

Input

Block

Output Blocks

Synthesizer

Block

Output

Channel 0

Smart

MUX

Frequency

Synthesizer

Output

Channel 1

Interface

&

Control

Block

Interface

&

Control

Device

Registers

EEPROM

Figure 14. CDCE62002 Circuit Blocks

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INTERFACE and CONTROL BLOCK

The Interface and Control Block includes a SPI interface, four control pins, a non-volatile memory array in which

the device stores default configuration data, and an array of device registers implemented in Static RAM. This

RAM, also called the device registers, configures all hardware within the CDCE62002.

Device Registers

Register2

Static RAM

Interface

PD

Device

Hardware

SPI_ LE

SPI_ CLK

SPI_ MOSI

SPI_ MISO

&

Control

Register1

Register0

Device Registers

Register2

EEPROM

Register1

Register0

Figure 15. CDCE62002 Interface and Control Block

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SPI (Serial Peripheral Interface)

The serial interface of CDCE62002 is a simple bidirectional SPI interface for writing and reading to and from the

device registers. It implements a low speed serial communications link in a master/slave topology in which the

CDCE62002 is a slave. The SPI consists of four signals:

•

SPI_CLK: Serial Clock (Output from Master) – the CDCE62002 clocks data in and out on the rising edge of SPI_CLK. Data transitions

therefore occur on the falling edge of the clock.

•

SPI_MOSI: Master Output Slave Input (Output from Master).

SPI_MISO: Master Input Slave Output (Output from Slave)

SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high, no data transfer can take

place.

The CDCE62002 implements data fields that are 28-bits wide. In addition, it contains 3 registers, each

comprising a 28 bit data field. Therefore, accessing the CDCE62002 requires that the host program append a

4-bit address field to the front of the data field as follows:

Device Register N

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SPI Register

Address

Bits

(4)

Data Bits (28)

First In/

First Out

Last in/

Last out

19 18 17 16 15

27 26 25 24 23 22 21 20

14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

3

2

1

0

SPI Master (Host)

SPI_CLK

SPI Slave (CDCE62002)

SPI_CLK

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

SPI_MOSI

SPI_MISO

SPI_LE

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

3

2

1

0

SPI_MOSI

SPI_MISO

Figure 16. CDCE62002 SPI Communications Format

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CDCE62002 SPI Command Structure

The CDCE62002 supports four commands issued by the Master via the SPI:

•

Write to RAM

Read Command

Copy RAM to EEPROM – unlock

Copy RAM to EEPROM – lock

Table 6 provides a summary of the CDCE62002 SPI command structure. The host (master) constructs a Write to

RAM command by specifying the appropriate register address in the address field and appends this value to the

beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first. The

host must issue a Read Command to initiate a data transfer from the CDCE62002 back to the host. This

command specifies the address of the register of interest in the data field.

Table 6. CDCE62002 SPI Command Structure

Data Field (28 Bits)

Addr Field

(4 BIts)

2

7

2

6

2

5

2

4

2

3

2

1

2

0

1

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

0

Register

Operation

NVM

Yes

9

X

0

1

8

X

0

7

X

0

6

X

0

5

X

0

4

X

0

3

X

A

0

2

X

A

0

1

X

A

0

X

A

1

3

0

1

2

0

1

0

1

0

1

0

1

0

1

2

Write to RAM

Status/Control

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

X

0

1

X

0

Yes

No

Instruction Read Command

Instruction RAM EEPROM

No

Unlock

(1)

Lock

0

1

(1) CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration can

only be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed.

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Writing to the CDCE62002

Figure 17 illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit

0) occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE62002,

data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE62002 that

the transmission of the last bit in the stream (Bit 31) has occurred.

SPI_CLK

Bit0

Bit1

Bit29

Bit30

Bit31

SPI_MOSI

SPI_LE

Figure 17. CDCE62002 SPI Write Operation

Reading from the CDCE62002

Figure 18 shows how the CDCE62002 executes a Read Command. The SPI master first issues a Read

Command to initiate a data transfer from the CDCE62002 back to the host (see Table 6). This command

specifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE62002

resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and the

CDCE62002 presents the data present in the register specified in the Read Command on SPI_MISO.

SPI_CLK

Bit30

Bit31

SPI_MOSI

Bit0

Bit1

Bit2

SPI_MISO

SPI_LE

Figure 18. CDCE62002 Read Operation

Writing to EEPROM

After the CDCE62002 detects a power-up and completes a reset cycle, it copies the contents of the on-board

EEPROM into the Device Registers. Therefore, the CDCE62002 initializes into a known state predefined by the

user. The host issues one of two special commands shown in Table 6 to copy the contents of Device Registers 0

through 1 into EERPOM. They include:

•

Copy RAM to EEPROM – Unlock, Execution of this command can happen many times.

•

Copy RAM to EEPROM – Lock: Execution of this command can happen only once; after which the EEPROM is permanently locked.

After either command is initiated, power must remain stable and the host must not access the CDCE62002 for at

least 50 ms to allow the EEPROM to complete the write cycle and to avoid the possibility of EEPROM corruption.

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Device Registers: Register 0

Table 7. CDCE62002 Register 0 Bit Definitions

SPI RAM

BIT BIT

BIT

NAME

DESCRIPTION / FUNCTION

0

1

2

3

A0

A1

A2

A3

Address 0

Address 1

Address 2

Address 3

0

4

5

0

1

INBUFSELX

INBUFSELY

INBUFSELX

INBUFSELY

Input Buffer Select (LVPECL,LVDS or LVCMOS)

XY(00 ) Disabled, (01) LVPECL, (10) LVDS, (11) LVCMOS

The VBB internal Biasing will be determined from this setting

EEPROM

6

7

2

3

REFSEL

AUXSEL

Smart MUX

Bits(2,3)

See specific section for more detailed description and configuration

setup.

00 – RESERVED

EEPROM

10 – REF_IN Select

01– AUX_IN Select

11 – Auto Select ( Reference then AUX)

8

4

5

6

7

8

9

ACDCSEL

Input Buffers

If Set to “1” DC Termination, If set to “0” AC Termination

If Set to “0” Input Buffer Internal Termination Enabled

EEPROM

9

TERMSEL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

REFDIVIDE 0

REFDIVIDE 1

REFDIVIDE 2

REFDIVIDE 3

Reference Divider Settings.

See specific section for more detailed description and configuration

setup.

10 EXTFEEDBACK

11 I70TEST

External Feedback to PFD from AUX Input enabled when set to “1”

Set to “0” for Normal Operation.

TEST

12 ATETEST

TEST

Set to “0” for Normal Operation.

13 LOCKW(0)

PLL Lock

Output 0

Output 1

Output 0 & 1

Lock-detect window Bit 0

14 LOCKW(1)

Lock-detect window Bit 1

15 OUT0DIVRSEL0

16 OUT0DIVRSEL1

17 OUT0DIVRSEL2

18 OUT0DIVRSEL3

19 OUT1DIVRSEL0

20 OUT1DIVRSEL1

21 OUT1DIVRSEL2

22 OUT1DIVRSEL3

23 HIPERORMANCE

Output 0 Divider Settings.

See specific section for more detailed description and configuration

setup.

Output 1 Divider Settings.

See specific section for more detailed description and configuration

setup.

High Performance, If this Bit is set to “1”:

– Increase the Bias in the device to achieve Best Phase Noise on the

Output Divider

– It changes the LVPECL Buffer to Hi Swing in LVPECL.

– It increases the current consumption by 20mA (Typical)

28

29

30

31

24 OUTBUFSEL0X

25 OUTBUFSEL0Y

26 OUTBUFSEL1X

27 OUTBUFSEL1Y

Output 0

Output 1

Output Buffer mode select for OUTPUT “0 ”.

(X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL

EEPROM

Output Buffer mode select for OUTPUT “1 ”.

(X,Y)=00:Disabled, 01:LVCMOS, 10:LVDS, 11:LVPECL

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Table 8. Reference Input AC/DC Input Termination Table

REFERENCE INPUT

RAM BITS

VBB VOLTAGE

REF+

REF–

TERMINATION

INTERNAL

0

1

4

5

GENERATOR

5kΩ to VBB

TERMINATION

External Termination

Disabled

X

0

1

0

1

X

0

1

0

X

0

1

0

1

X

0

OFF

1.9V

1.0V

1.2V

OPEN

LVCMOS

OPEN

LVPECL-AC

LVPECL-DC

LVDS-AC

CLOSED

LVDS-DC

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Device Registers: Register 1

Table 9. CDCE62002 Register 1 Bit Definitions

SPI

BIT

RAM

BIT

BIT NAME

DESCRIPTION / FUNCTION

0

1

A0

A1

A2

A3

Address 0

1

Address 1

0

2

Address 2

0

3

Address 3

0

4

0

1

SELVCO

VCO Core

VCO Select

Input Divider Settings.

See specific section for more detailed description and configuration

setup.

EEPROM

5

SELINDIV0

SELINDIV1

SELINDIV2

SELINDIV3

SELINDIV4

SELINDIV5

SELINDIV6

SELINDIV7

SELPRESCA

SELPRESCB

6

2

7

3

8

4

9

5

10

11

12

13

14

6

7

8

9

PRESCALER Setting.

See specific section for more detailed description and configuration

setup.

10

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

SELFBDIV0

SELFBDIV1

SELFBDIV2

SELFBDIV3

SELFBDIV4

SELFBDIV5

SELFBDIV6

SELFBDIV7

SELBPDIV0

SELBPDIV1

SELBPDIV2

LFRCSEL0

LFRCSEL1

LFRCSEL2

LFRCSEL3

EELOCK

VCO Core

Status

FEEDBACK DIVIDER Setting

See specific section for more detailed description and configuration

setup.

EEPROM

BYPASS DIVIDER Setting ( 6 settings + Disable + Enable)

See specific section for more detailed description and configuration

setup.

Loop Filter & Charge Pump Control Setting

See specific section for more detailed description and configuration

setup.

If EELOCK reads "0" EEPROM is unlocked. If EELOCK reads "1," then

EEPROM is locked.

31

27

RESERVED

Status

Read Only always reads "1"

EEPROM

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Device Registers: Register 2

Table 10. CDCE62002 Register 2 Bit Definitions

SPI

BIT

RAM BIT NAME

BIT

DESCRIPTION / FUNCTION

0

1

A0

A1

A2

A3

Address 0

0

Address 1

1

2

Address 2

0

3

Address 3

0

4

0

1

2

3

4

5

6

RESERVED

PLLLOCKPIN

Diagnostics

Status

TI Test Registers. For TI Use Only

RAM

5

6

7

8

9

10

Read Only: Status of the PLL Lock Pin Driven by the device. PLL Lock

= 1

11

12

7

8

PD

Control

Power Down mode “On” when set to “0”, Off when set to “1” is normal

operation (PD bit does not load the EEPROM into RAM when set to

"1").

RAM

SYNC

If toggled “1-0-1” this bit forces “SYNC“ resynchronize the Output

Dividers.

13

14

15

16

17

9

RESERVED

VERSION0

VERSION1

VERSION2

PLLRESET

Diagnostics

Read Only

VCO Core

TI Test Registers. For TI Use Only

RAM

10

11

12

13

If toggled “0-1-0” it Resets PLL to start calibration. “0” is normal

operation.

18

19

20

21

22

23

24

25

26

27

28

29

30

31

14

15

16

17

18

19

20

21

22

23

24

25

26

27

RESERVED

TITSTCFG0

TITSTCFG1

TITSTCFG2

TITSTCFG3

RESERVED

Diagnostics

TI Test Registers. For TI Use Only

RAM

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Device Control

Figure 19 provides a conceptual explanation of the CDCE62002 Device operation. Table 11 defines how the

device behaves in each of the operational states.

Power

Applied

Power ON

Device

Reset

OFF

Delay

Finished

PLLRESET= ON

VCO

CAL

Sync = ON

Power Down = ON

Power Down

Active Mode

Sync

Sync = OFF

Figure 19. CDCE62002 Device State Control Diagram

Table 11. CDCE62002 Device State Definitions

Output

Divider

Status

Output

Buffer

Status

SPI Port

Status

PLL

Status

State

Device Behavior

Entered Via

Exited Via

Power-On

Reset

After device power supply reaches

approximately 2.35V, the contents of

EEPROM are copied into the Device

Registers, thereby initializing the device

hardware .

Power applied to the device or

upon exit from Power Down State

via the PD pin set HIGH.

Power On Reset and EEPROM

loading delays are finished OR the

PD pin is set LOW.

OFF

Disabled Disabled

OFF

VCO CAL

The voltage controlled oscillator is

calibrated based on the PLL settings

and the incoming reference clock. After

the VCO has been calibrated, the device

enters Active Mode automatically.

Delay process in the Power-On

Reset State is finished or

PLLRESET=ON

Calibration Process in completed

ON

Enabled

Disabled

OFF

Active Mode

Power Down

Normal Operation

CAL Done (VCO calibration

process finished) or Sync = OFF

(from Sync State).

Power Down or PLLRESET=ON

PD pin is pulled HIGH.

ON

Disabled

or

Enabled

Disabled or

Enabled

Used to shut down all hardware and

Resets the device after exiting the

Power Down State. Therefore, the

EEPROM contents will eventually be

copied into RAM after the Power Down

State is exited.

PD pin is pulled LOW.

Disabled Disabled

Disabled

Sync

Sync synchronizes both outputs dividers Sync Bit in device register 2 bit 8

Sync bit in device register 2 bit 8 is

set HIGH

ON

Enabled

Disabled

so that they begin counting at the same

time

is set LOW

External Control Pins

Power Down (PD)

When pulled LOW, PD activates the Power Down state which shuts down all hardware and resets the device.

Restoring PD high will cause the CDCE62002 to exit the Power Down State. This causes the device to behave

as if it has been powered up including copying the EEPROM contents into RAM. PD pin also has a shadowed

PD bit residing in Register 2 Bit 7. When asserted Low it puts the device in Power Down Mode, but it does not

load the EEPROM when the bits is disserted.

NOTE:

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The SPI_LE signal has to be high in order for the EEPROM to load correctly into RAM

on the Rising edge of PD Pin.

FACTORY DEFAULT PROGRAMMING

The CDCE62002 is factory pre-programmed to work with 25 MHz input from the reference input or from the

auxiliary input with auto switching enabled. An internal PFD of 6.25 MHz and about 400 KHz loop bandwidth.

Output 0 is pre-programmed as an LCPECL driver to output 156.25 MHz and output 1 is pre-programmed as

LVDS driver to output 125 MHz.

U0P

U0N

LVPECL

156.25 MHz

156.25Mhz

25 MHz

25Mhz

XTAL

25 MHz

25Mhz

U1P

U1N

CDCE62002

Default Programing

LVDS

125 MHz

125Mhz

EEPROM

Register Content

72A000E0

Register 0

Register 1

8389A061

Figure 20. CDCE62002 Default Factory Programming

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INPUT BLOCK

The Input Block includes one Universal Input Buffers, an Auxiliary Input, and a Smart Multiplexer.

Register 0

2

3

Smart MUX

Control

Register 0

1

0

Smart Multiplexer

Universal Input Buffers

Smart

MUX

LVPECL : 500 MHz

LVDS: 500 MHz

LVCMOS : 250 MHz

Pre-Divider

/1 or /2

Reference Divider

/1 - /8

REF_IN

XTAL/

9

8

7

6

Auxiliary Input

Register 0

Crystal: 2 MHz – 42 MHz

Single Ended : 2 MHz - 75 MHz AUX_IN

Figure 21. CDCE62002 Input Block With References to Registers

The CDCE62002 provides a Reference Divider that divides the clock exiting Reference (REF_IN) input buffer.

Table 12. CDCE62002 Reference Divider Settings

REFERENCE DIVIDER

REFDIVIDE2 REFDIVIDE1

0.8 0.7

TOTAL

DIVIDE

RATIO

BIT NAME →

REFDIVIDE3

REFDIVIDE0

REGISTER BIT →

0.9

0

1

0.6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

/1

/2

/3

/4

/5

/6

/7

/8

/2

/4

/6

/8

/10

/12

/14

/16

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Reference Input Buffer

Figure 22 shows the key elements of a Universal Input Buffer (UIB). A UIB supports multiple formats along with

different termination and coupling schemes. The CDCE62002 implements the UIB by including on board

switched termination, a programmable bias voltage generator, and a multiplexer. The CDCE62002 provides a

high degree of configurability on the UIB to facilitate most existing clock input formats.

REF_IN

Input Buffer Select

Input Buffer

Bit Name-->

INBUFSELX

INBUFSELY

Mode

Register.Bit -->

0.0

0.1

Disabled

LVPECL

LVDS

0

1

0

1

Universal Input Control

Register0

LVCMOS

1

0

PN

PP

Settings

SWITCH Status VBB

0.0

0.1

0.4

0.5

Register 0

5k

INBUFSELX

INBUFSELY ACDCSEL TERMSEL

P

N

VBB

OFF

1.2V

1.9V

1.2V

0

1

4

5

X

0

1

0

X

1

0

1

X

1

0

1

0

OFF

ON

OFF

ON

V

bb

ON ON

V

bb

0

1uF

1

0

Figure 22. CDCE62002 Universal Input Buffer

Smart Multiplexer Dividers

Register 0

2

3

Setting

REFSEL AUXSEL

Smart Mux

Mode

0.2

0

0.3

0

Smart MUX

Control

Register 0

Reserved

0

1

0

REF Select

AUX Select

Auto Select

Smart Multiplexer

0

1

Smart

MUX

Reference Divider

/1 - /8

Pre-Divider

/1 or /2

REF_IN

9

8

7

6

Register 0

XTAL/

AUX_IN

Figure 23. CDCE62002 Smart Multiplexer

In Auto Select Mode the Smart Mux switches automatically between Reference input and Auxiliary input with a

preference to the Reference input. In order for the Smart Mux to function correctly the frequency after the

reference divider and the Auxiliary Input signal frequency should be within 20% of each other or one of them

should be zero or ground. In This mode a valid frequency needs to be present on AUX_IN before the /PD is

deasserted or power is applied.

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Auxiliary Input Port

The auxiliary input on the CDCE62002 is designed to connect to an AT-Cut Crystal with a total load capacitance

of 8 pF to 18pF. One side of the crystal connects to Ground while the other side connects to the Auxiliary input of

the device. The circuit accepts crystals from 2 to 42 MHz.

Since the Auxiliary input operates between 0 and 2 Volts with a crystal, it can accept single-ended signals (e.g.,

LVCMOS). Electrically, it is equivalent to an LVCMOS input buffer with 8 pF of input capacitance.

Figure 24. CDCE62002 Auxiliary Input Port

External Feedback Mode

The auxiliary input on the CDCE62002 is to serve as an external feedback port if Bit (10) in Register 0 is set to

“1” and input smart Mux setting is set to Reference input. In addition, The Reference Divider and the input divider

have to be set to divide by 1. This feature is implemented to allow direct access to the PFD of the PLL. The

delay from Reference input to PFD and from Auxiliary Reference to PFD is not matched. However, in close loop

system where the device output is fed to close the loop the delay difference between the Reference and External

feedback path will cancel out.

Div by 1

REF_IN

FB

Div by 1

PFD/

CP

Feedback

Divider

Figure 25. CDCE62002 in External Feedback Mode

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OUTPUT BLOCK

The output block includes two identical output channels. Each output channel comprises of a clock divider

module, and a universal output buffer as shown in Figure 26.

OUTPUT 0

OUTPUT 1

Registers 0

15 16 17 18

Registers 0

19 20 21 22

Output Buffer Control

Sync

Pulse

Enable

UxP

UxN

SYNTH

Clock Divider Module 0

Clock Divider Module 1

LVDS

LVPECL

Figure 26. CDCE62002 Output Channel

Table 13. CDCE62002 Output Divider Settings

OUTPUT DIVIDERS SETTING

DIVIDER 0 →

DIVIDER 1 →

0.18

0.22

0

0.17

0.21

0

0.16

0.20

0

0.15

0.19

0

DIVIDE RATIO

Disabled

0

1

/1

/2

0

1

0

1

/3

0

1

0

/4

0

1

0

1

/5

0

1

0

/6

0

1

Disabled

/8

1

0

1

0

1

Disabled

/10

1

0

1

0

1

0

1

/20

1

0

/12

1

0

1

/24

1

0

/16

1

/32

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SYNTHESIZER BLOCK

Figure 27 provides an overview of the CDCE62002 synthesizer block. The Synthesizer Block provides a Phase

Locked Loop, a partially integrated programmable loop filter, and two Voltage Controlled Oscillators (VCO). The

synthesizer block generates an output clock called “SYNTH” and drives it onto the Internal Clock Distribution

Bus.

Loop Filter and Charge Pump

Current Settings

Input Divider Settings

Register 1

25 24 23 22

8

7

6

5

4

3

2

1

Prescaler

Register 1

9

8

1.75 GHz –

2.356 GHz

SMART_MUX

Input Divider

/1 - /256

PFD/

CP

Prescaler

/2,/3,/4,/5

SYNTH

Feedback Divider

70 kHz –

400 kHz

/1,/2,/5,/8,/10,/16,/20

/8 - /1280

Register 1

0

VCO Select

Register 1

21 20 19

18 17 16 15 14 13 12 11

Feedback Divider

Feedback Bypass Divider

Figure 27. CDCE62002 Synthesizer Block

Input Divider

The Input Divider divides the clock signal selected by the Smart Multiplexer and presents the divided signal to

the Phase Frequency Detector / Charge Pump of the frequency synthesizer.

Table 14. CDCE62002 Input Divider Settings

INPUT DIVIDER SETTINGS

DIVIDE

RATIO

SELINDIV7

SELINDIV6

SELINDIV5

SELINDIV4

SELINDIV3

SELINDIV2

SELINDIV1

SELINDIV0

1.8

0

1.7

0

1.6

0

1.5

0

1.4

0

1.3

0

1.2

0

1.1

0

1

2

0

1

0

1

0

3

0

1

4

0

1

0

1

0

5

0

1

0

1

0

1

6

–

1

256

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Feedback and Feedback Bypass Divider

Table 15 shows how to configure the Feedback divider for various divide values:

Table 15. CDCE62002 Feedback Divider Settings

FEEDBACK DIVIDER

DIVIDE

RATIO

SELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0

1.18

0

1

0

1.17

0

1

0

1

0

1

0

1

0

1

0

1

1.16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.15

0

1

0

1

0

1

0

1

0

1

1.14

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.13

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.12

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.11

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8

12

16

20

24

32

36

40

48

56

60

64

72

80

84

96

100

108

112

120

128

140

144

160

168

180

192

200

216

224

240

252

256

280

288

300

320

336

360

384

392

400

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Table 15. CDCE62002 Feedback Divider Settings (continued)

FEEDBACK DIVIDER

DIVIDE

RATIO

SELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0

1.18

0

1

0

1

0

1

0

1

1.17

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.15

1

1.14

1

0

1

0

1

0

1

0

1

0

1

1.13

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.12

1

0

1

0

1

0

1

1.11

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

420

432

448

480

500

504

512

560

576

588

600

640

672

700

720

768

784

800

840

896

960

980

1024

1120

1280

Table 16 shows how to configure the Feedback Bypass Divider.

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Table 16. CDCE62002 Feedback Bypass Divider Settings

FEEDBACK BYPASS DIVIDER

SELBPDIV2

SELBPDIV1

SELBPDIV0

DIVIDE RATIO

1.21

0

1.20

0

1.19

0

2

0

1

5

0

1

0

8

10

0

1

0

16

1

0

1

20

1

0

RESERVED

1(bypass)

1

VCO Select

Table 17 illustrates how to control the dual voltage controlled oscillators.

Table 17. CDCE62002 VCO Select

VCO SELECT

SELVCO

VCO CHARACTERISTICS

BIT NAME →

REGISTER NAME →

1.0

0

VCO RANGE

Low

Fmin (MHz)

1750

Fmax (MHz)

2046

1

High

2040

2356

Prescaler

Table 18 shows how to configure the prescaler.

Table 18. CDCE62002 Prescaler Settings

SETTINGS

SELPRESCB

SELPRESCA

DIVIDE RATIO

1.10

1.9

0

1

0

1

5

4

3

2

0

1

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Loop Filter

Figure 28 depicts the loop filter topology of the CDCE62002. It facilitates both internal and external

implementations providing optimal flexibility.

EXT_LFP

EXT_LFN

Registers 0

22

internal

external

internal

external

25 24 23

V_B

+

-

R3

PFD/

CP

C3

C1

C2

R2

Figure 28. CDCE62002 Loop Filter Topology

Internal Loop Filter Component Configuration

Figure 28 illustrates the switching between four fixed internal loop filter settings and the external loop filter

setting. Table 19 shows that the CDCE62002 has 16 settings different settings for the loop filter. Four of the

settings are internal and twelve are external.

Table 19. CDCE62002 Loop Filter Settings

Charge

LFRCSEL

3 db Corner

C3R3

Pump

Current

1.5 mA

400 µA

250 µA

150 µA

1.0 mA

2.0 mA

3.0 mA

3.75 mA

1.0 mA

2.0 mA

3.0 mA

3.75 mA

1.0 mA

2.0 mA

3.0 mA

3.75 mA

3

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Loop Filter

Internal

C1

C2

R2

4.0k

2.7k

X

R3

5k

C3

1.5 pF

473.5 pF

2.5 pF

112 pF

100 pF

64 pF

12 MHz

70 kHz

Internal

1.5 pF

473.5 pF

5k

Internal

1.5 pF

473.5 pF

5k

Internal

1.5 pF

473.5 pF

5k

External

X

20k

10k

5k

X

70 kHz

X

70 kHz

X

70 kHz

X

150 kHz

300 kHz

500 kHz

700 kHz

800 kHz

X

5k

X

5k

48 pF

X

5k

38 pF

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Lock Detect

The CDCE62002 provides a lock detect indicator circuit that can be detected on an external Pin PLL_LOCK (Pin

32) and internally by reading PLLLOCKPIN bit (6) in Register 2.

Two signals whose phase difference is less than a prescribed amount are ‘locked’ otherwise they are ‘unlocked’.

The phase frequency detector / charge pump compares the clock provided by the input divider and the feedback

divider; using the input divider as the phase reference. The lock detect circuit implements a programmable lock

detect window. Table 20 shows an overview of how to configure the lock detect feature. The PLL_LOCK pin will

possibly jitter several times between lock and out of lock until the PLL achieves a stable lock. If desired, choosing

a wide loop bandwidth and a high number of successive clock cycles virtually eliminates this characteristic.

PLL_LOCK will return to out of lock, if just one cycle is outside the lock detect window or if a cycle slip occurs.

Lock Detect Window (Max)

From Input Divider

Locked

From Feedback Divider

Unlocked

From Input Divider

From Feedback Divider

From Input Divider

PFD/

CP

From Lock Detector

Lock Detect Window Adjust

To Loop Filter

PLL_LOCK

1 = Locked

O = Unlocked

Register 0

From Feedback Divider

13 14

(b)

(c)

(a)

Figure 29. CDCE62002 Lock Detect

Table 20. CDCE62002 Lock Detect Control

LOCK DETECT

BIT NAME →

REGISTER NAME →

LOCKW(1)

LOCKW(0)

WINDOW

0.13

0.14

0

1

0

1

0

1

2.1 ns

4.6 ns

7.2 ns

19.9 ns

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Device Power Calculation and Thermal Management

The CDCE62002 is a high performance device; therefore careful attention must be paid to device configuration

and printed circuit board layout with respect to power consumption. Table 21 provides the power consumption for

the individual blocks within the CDCE62002. To estimate total power consumption, calculate the sum of the

products of the number of blocks used and the power dissipated of each corresponding block.

Table 21. CDCE62002 Power Consumption

INTERNAL BLOCK

(Power at 3.3V)

POWER DISSIPATED

PER BLOCK

NUMBER OF BLOCKS

PER DEVICE

Input Circuit

32

333

92

1

2

4

PLL and VCO Core

Output Divider

Output Buffer ( LVPECL)

Output Buffer (LVDS)

Output Buffer (LVCMOS)

150

95

62

This power estimate determines the degree of thermal management required for a specific design. Observing

good thermal layout practices enables the thermal pad on the backside of the QFN-32 package to provide a

good thermal path between the die contained within the package and the ambient air. This thermal pad also

serves as the ground connection the device; therefore, a low inductance connection to the ground plane is

essential.

Component Side

Back Side

QFN-32

Thermal Slug

(package bottom)

Solder Mask

Internal

Ground

Plane

Internal

Power

Plane

Thermal

Dissipation

Pad (back side)

Thermal Vias

No Solder Mask

Figure 30. CDCE62002 Recommended PCB Layout

CDCE62002 Power Supply Bypassing – Recommended Layout

Figure 31 shows a conceptual layout focusing on power supply bypass capacitor placement. If the capacitors are

mounted on the back side, 0402 components can be employed; however, soldering to the Thermal Dissipation

Pad can be difficult. If the capacitors are mounted on the component side, 0201 components must be used to

facilitate signal routing. In either case, the connections between the capacitor and the power supply terminal on

the device must be kept as short as possible.

Component & Back Side

Component Side

Only

Figure 31. CDCE62002 Power Supply Bypassing

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APPLICATION INFORMATION AND GENERAL USAGE HINTS

Clock Generator

The CDCE62002 can generate 1 to 4 low noise clocks from a single crystal or crystal oscillator as follows:

Feedback

XTAL/

U0P

U0N

Divider

PFD/

CP

Output

AUX_IN

Prescaler

Divider 0

Smart

MUX

Input

Divider

U1P

U1N

Output

Divider 1

Figure 32. CDCE62002 as a Clock Generator

External Feedback Option

The CDCE62002 has a limited optional external feedback path that give access to the PFD inside the device.

This option enables customers to implement complex or custom PLL designed to control the VCO inside the

CDCE62002. In addition, the External feedback allows the device to operate in a deterministic delay mode where

the reference to output delay is fixed but dependable on the routing path length from the outputs to the auxiliary

input pin. Figure 33 illustrates how the output is loopback to the Auxiliary Input in bypass mode to put the device

in fixed delay mode.

LF

U0P

REF_IN

Output

Divider 0

U0N

Div by 1

Prescaler

FB

U1P

U1N

Output

Divider 1

Div by 1

PFD/

CP

Feedback

Divider

100nF

Figure 33. CDCE62002 External Feedback Example

This function is limited by the output divider divide ratio and can be implemented when one of the outputs is set

from 10.94 MHz to 40.00MHz.

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SERDES Startup and Clock Cleaner

The CDCE62002 can serve as a SERDES device companion by providing a crystal based reference for the

SERDES device to lock to receive data stream and when the SERDES locks to the data and outputs the

recovered clock the CDCE62002 can switch and use the recovered clock and serve as a jitter cleaner.

Data

SERDES

Cleaned Clock

Recovered Clock

EXT_LFP

Reference

Divider

EXT _LFN

REF_IN

XTAL/AUX_IN

U0P

U0N

Output

Divider 0

Input

Divider

PFD/

CP

U1P

U1N

Output

Prescaler

Feedback

Divider

Divider 1

Figure 34. CDCE62002 Clocking SERDES

Since the jitter of the recovered clock can be above 100 ps (RMS) the output jitter from CDCE62002 can be as

low and 6 ps (RMS) depending on the external loop filter configuration.

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CLOCKING ADCS WITH THE CDCE62002

High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample

clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly

implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation

trend often causes engineers working in communications system design to encounter the term “clock limited

performance”. Therefore, it is important to understand the impact of clock jitter on ADC performance. The

following equation shows the relationship of data converter signal to noise ratio (SNR) to total jitter:

é

₁₀ê

ë

ù

ú

û

1

SNR_jitter= 20log

2p f_injitter_total

(4)

Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample

clock:

2

)

jitter_total

=

jitter

²+ jitter

(

_ADC) (

CLK

(5)

With respect to an ADC with N-bits of resolution, ignoring total jitter, ADC quantization error, and input noise, the

following equation shows the relationship between resolution and SNR:

SNR _ADC= 6.02N + 1.76

(6)

Figure 35 plots Equation 4 and Equation 6 for constant values of total jitter. When used in conjunction with most

ADCs, the CDCE62002 supports a total jitter performance value of <1ps.

Data Converter Jitter Requirements

140

130

120

110

100

90

26

24

22

20

18

16

14

12

10

8

100 fs

1ps

80

50 fs

70

60

350 fs

50

40

6

30

4

20

2

10

0

1

10

100

Input Bandwidth (MHz)

1000

10000

Figure 35. Data Converter Jitter Requirements

Submit Documentation Feedback

41

Product Folder Link(s): CDCE62002

CDCE62002

SCAS882A–JUNE 2009–REVISED JULY 2009.............................................................................................................................................................. www.ti.com

REVISION HISTORY

Changes from Original (June 2009) to Revision A ......................................................................................................... Page

•

Added information - The input has an internal 150-kΩ pull-up resist .................................................................................... 3

Deleted (as described in later future revisions of this document).......................................................................................... 3

Added NOTE: All VCC pins need to be connected for the device to operate properly......................................................... 3

Changed graphic input naming.............................................................................................................................................. 4

Changed graphic input naming.............................................................................................................................................. 5

Changed W to mW ................................................................................................................................................................ 8

Deleted underscore before IN+.............................................................................................................................................. 8

Deleted 6 from 8006 ............................................................................................................................................................ 11

Changed Y4 to Y1 ............................................................................................................................................................... 12

Added MIN, TYP, and MAX values...................................................................................................................................... 12

Added (Reg 0 RAM bit 9 = 1) .............................................................................................................................................. 14

Added (Reg 0 RAM bit 9 = 0) .............................................................................................................................................. 14

Changed REF into REF_IN ................................................................................................................................................. 14

Changed AUX into AUX_IN ................................................................................................................................................. 14

Deleted t9 from timing.......................................................................................................................................................... 16

Changed input naming......................................................................................................................................................... 18

Changed part number error ................................................................................................................................................. 19

Changed REFERENCE to REF_IN and AUXILARY to AUX_IN ......................................................................................... 22

Changed power to current ................................................................................................................................................... 22

Changed 0110 to 1000 ........................................................................................................................................................ 24

Changed 0001 to 0100 ........................................................................................................................................................ 25

Changed description for RAM BIT to - TI Test Registers. For TI Use Only ........................................................................ 25

Changed graphic.................................................................................................................................................................. 26

Changed table information................................................................................................................................................... 26

Changed PDDRESET to PLLRESET .................................................................................................................................. 26

Changed Power_Down to PD.............................................................................................................................................. 26

Changed PRI_IN to REF_IN................................................................................................................................................ 28

Changed PRI_IN to REF_IN................................................................................................................................................ 29

Added sentence - In This mode a valid frequency needs to be present on AUX_IN before the /PD is deasserted or

power is applied................................................................................................................................................................... 29

•

Changed PRI_IN to REF_IN................................................................................................................................................ 40

42

Submit Documentation Feedback

Product Folder Link(s): CDCE62002

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jul-2009

PACKAGING INFORMATION

Orderable Device

CDCE62002RHBR

CDCE62002RHBT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RHB

32

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

RHB

32

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Jul-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

CDCE62002RHBR

CDCE62002RHBT

QFN

RHB

32

3000

250

330.0

12.4

5.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Jul-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CDCE62002RHBR

CDCE62002RHBT

QFN

RHB

32

3000

250

340.5

333.0

20.6

Pack Materials-Page 2

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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Applications

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www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CDCE62002
厂家：	TEXAS INSTRUMENTS
描述：	Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs 四个输出时钟发生器/抖动消除器具有集成双路VCO的时钟发生器
文件：	总49页 (文件大小：1488K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CDCE62002 [TI]

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