CDCE62005 [TI]
Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs; 5分/ 10路输出时钟发生器/抖动消除器具有集成双路VCO的![CDCE62005](http://pdffile.icpdf.com/pdf1/p00144/img/icpdf/CDCE6_798777_icpdf.jpg)
型号: | CDCE62005 |
厂家: | ![]() |
描述: | Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs |
文件: | 总76页 (文件大小:2097K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862–NOVEMBER 2008
Five/Ten Output Clock Generator/Jitter Cleaner
With Integrated Dual VCOs
1
FEATURES
•
•
•
Frequency Synthesizer With PLL/VCO and
Partially Integrated Loop Filter.
•
Flexible Inputs With Innovative Smart
Multiplexer Feature:
Fully Configurable Outputs Including
Frequency, Output Format, and Output Skew.
– Two Universal Differential Inputs Accept
Frequencies up to 1500 MHz (LVPECL), 800
MHz (LVDS), or 250 MHz (LVCMOS).
Smart Input Multiplexer Automatically
Switches Between One of Three Reference
Inputs.
– One Auxiliary Input Accepts Single Ended
Clock Source or Crystal. Auxiliary Input
Accepts Crystals in the Range of 2 MHz–42
MHz or an LVCMOS Input up to 75 MHz.
•
•
Multiple Operational Modes Include Clock
Generation via Crystal, SERDES Startup Mode,
Jitter Cleaning, and Oscillator Holdover Mode
– Clock Generator Mode Using Crystal Input.
Integrated EEPROM Determines Device
Configuration at Power-up
– Smart Input Multiplexer can be Configured
to Automatically Switch Between Highest
Priority Clock Source Available Allowing
for Fail-safe Operation and Holdover
Modes.
•
•
Excellent Jitter Performance
Integrated Frequency Synthesizer including
PLL, Multiple VCOs, and Loop Filter:
•
•
Typical Power Consumption 1.7W
(See Table 44) at 3.3V
– Full Programmability Facilitates Phase
Noise Performance Optimization Enabling
Jitter Cleaner Mode.
Integrated EEPROM Stores Default Settings;
Therefore, The Device Can Power up in a
Known, Predefined State.
– Programmable Charge Pump Gain and
Loop Filter Settings
•
•
•
Offered in QFN-48 Package
– Unique Dual-VCO Architecture Supports a
Wide Tuning Range 1.750 GHz–2.356 GHz
ESD Protection Exceeds 2kV HBM
Industrial Temperature Range –40°C to 85°C
•
Universal Output Blocks Support up to 5
Differential, 10 Single-ended, or Combinations
of Differential or Single-ended:
APPLICATIONS
•
•
•
•
•
•
•
Data Converter and Data Aggregation Clocking
Wireless Infrastructure
Switches and Routers
Medical Electronics
Military and Aerospace
Industrial
Clock Generation and Jitter Cleaning
– 1 ps RMS (10 kHz to 20 MHz) Output Jitter
Performance
– Low Output Phase Noise: –130 dBc/Hz at 1
MHz offset, Fc = 491.52 MHz
– Output Frequency Ranges from 4.25 MHz to
1.175 GHz in Synthesizer Mode
– Output Frequency up to 1.5 GHz in Fan-out
Mode
– LVPECL, LVDS, LVCMOS, and Special High
Output Swing Modes
– Independent Output Dividers Support
Divide Ratios from 1–80(1)
– Independent Coarse Skew Control on all
Outputs
(1)
Non-continuous values supported.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
CDCE62005
SCAS862–NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
DESCRIPTION
The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree
of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM.
Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter
performance well under 1 ps RMS(1). It incorporates a synthesizer block with partially integrated loop filter, a
clock distribution block including programmable output formats, and an input block featuring an innovative smart
multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to
provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be
programmed to a unique output frequency (ranging from 800 kHz to 1.5 GHz (2)) and skew relationship via a
programmable delay block. If all outputs are configured in single-ended mode (e.g., LVCMOS), the CDCE62005
supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including
any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal
differential inputs which support frequencies up to 500 MHz and an auxiliary single ended input that can be
connected to a CMOS level clock or configured to connect to an external crystal via an on board oscillator block.
The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user
selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically
select between the highest priority input clock available.
Data
DSP
Cleaned Clock
SerDes
DSP Clock
Recovered Clock
CDCE62005
ADC Clock
ADC Clock
DAC Clock
Figure 1. CDCE62005 Application Example
DEVICE INFORMATION
(1) 10 kHz to 20 MHz integration bandwidth.
(2) Frequency range depends on operational mode and output format selected.
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PACKAGE
The CDCE62005 is packaged in a 48-Pin Plastic Quad Flatpack Package with enhanced bottom thermal pad for
heat dissipation. The Texas Instruments Package Designator is: RGZ (S-PQFP-N48)
36
25
37
24
Top View
Not up to Scale
48
13
12
1
Figure 2. 48-Pin QFN Package Outline
PIN FUNCTIONS
PIN
TYPE
DESCRIPTION
NAME
QFN
VCC_OUT
8, 11,
18, 21,
26, 29,
32
Power 3.3V Supply for the Output Buffers
VCC_AUXOUT
VCC1_PLL
VCC2_PLL
VCC_VCO
VCC_IN_PRI
VCC_IN_SEC
VCC_AUXIN
GND_VCO
GND
15
Power 3.3V to Power the AUX_OUT circuitry
5
A. Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required)
A. Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required)
A. Power 3.3V VCO Input Buffer and Circuitry Supply Voltage. (Filter Required)
A. Power 3.3V References Input Buffer and Circuitry Supply Voltage.
A. Power 3.3V References Input Buffer and Circuitry Supply Voltage.
A. Power 3.3V Crystal Oscillator Input Circuitry.
39, 42
34, 35
47
1
44
36
Ground Ground that connects to VCO Ground. (VCO_GND is shorted to GND)
Ground Ground is on Thermal PAD. See Layout recommendation
PAD
22
SPI_MISO
OD
In SPI Mode it is an Open Drain Output and it functions as a Master In Slave Out as a serial
Control Data Output to CDCE62005 .
SPI_LE
25
I
LVCMOS input, control Latch Enable for Serial Programmable Interface (SPI), with Hysteresis in
SPI Mode. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to
logic level “1”.
SPI_CLK
24
23
I
I
LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The input has
an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level “1”.
SPI_MOSI
LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62005 for the SPI bus
interface. The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic
level “1”.
TEST_MODE
33
I
This pin should be tied high or left unconnected.
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PIN FUNCTIONS (continued)
PIN
TYPE
DESCRIPTION
NAME
REF_SEL
QFN
31
I
If Auto Reference Select Mode is OFF this Pin acts as External Input Reference Select Pin;
The REF_SEL signal selects one of the two input clocks:
REF_SEL [1]: PRI_IN is selected; REF_SEL [0]: SEC_IN is selected;
The input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level “1”.
If Auto Reference Select Mode in ON this Pin not used.
Power_Down
12
I
Active Low. Power down mode can be activated via this pin. See Table 14 for more details. The
input has an internal 150-kΩ pull-up resistor if left unconnected it will default to logic level “1”.
SPI_LE has to be HIGH in order for the rising edge of Power_Down signal to load the EEPROM.
SYNC
14
43
13
I
I
Active Low. Sync mode can be activated via this pin. See Table 14 for more details. The input has
an internal 150-kΩ, pull-up resistor if left unconnected it will default to logic level “1”.
AUX IN
AUX OUT
Auxiliary Input is a single ended input including an on-board oscillator circuit so that a crystal may
be connected.
O
Auxiliary Output LVCMOS level that can be programmed via SPI interface to be driven by Output 2
or Output 3.
PRI REF+
PRI REF–
45
46
I
I
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference Clock,
Universal Input Buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In case of
LVCMOS signaling Ground this pin.
SEC REF+
SEC REF–
3
2
I
I
Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary Reference
Clock,
Universal Input Buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock. In
case of LVCMOS signaling Ground this pin.
TESTOUTA
REG_CAP1
REG_CAP2
VBB
30
4
Analog Analog Test Point for Use for TI Internal Testing. Pull Down to GND Via a 1kΩs Resistor.
Analog Capacitor for the internal Regulator. Connect to a 10uF Capacitor (Y5V)
Analog Capacitor for the internal Regulator. Connect to a 10uF Capacitor (Y5V)
Analog Capacitor for the internal termination Voltage. Connect to a 1uF Capacitor (Y5V)
Analog External Loop Filter Input Positive
38
48
40
41
37
EXT_LFP
EXT_LFN
PLL_LOCK
Analog External Loop Filter Input Negative.
AI/O
O
Output that indicates PLL Lock Status. See Figure 36.
U0P:U0N
U1P:U1N:
U2P:U2N
U3P:U3N
U4P:U4N
27, 28
19, 20
16,17
9, 10
6, 7
The Main outputs of CDCE62005 are user definable and can be any combination of up to 5
LVPECL outputs, 5 LVDS outputs or up to 10 LVCMOS outputs. The outputs are selectable via
SPI interface. The power-up setting is EEPROM configurable.
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FUNCTIONAL DESCRIPTION
PRI_IN
U0P
Output
Divider
0
U0N
SEC_IN
/1:/2:HiZ
/1:/2:HiZ
Reference
Divider
U1P
U1N
Output
Divider
1
XTAL /
AUX_IN
EXT_LFP
EXT_LFN
U2P
U2N
Output
Divider
2
3
Input
Divider
U3P
U3N
PFD /
CP
Output
Divider
Prescaler
Feedback
Divder
U4P
U4N
Output
Divider
4
REF_SELECT
/Power_down
/SYNC
Interface
&
Control
EEPROM
SPI_LE
SPI_CLK
AUX
OUT
SPI_MISO
SPI_MOSI
Figure 3. CDCE62005 Block Diagram
The CDCE62005 comprises of four primary blocks: the interface and control block, the input block, the output
block, and the synthesizer block. In order to determine which settings are appropriate for any specific
combination of input/output frequencies, a basic understanding of these blocks is required. The interface and
control block determines the state of the CDCE62005 at power-up based on the contents of the on-board
EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE62005 by writing directly
to the device registers after power-up. The input block selects which of the three input ports is available for use
by the synthesizer block and buffers all clock inputs. The output block provides five separate clock channels that
are fully programmable and configurable to select and condition one of four internal clock sources. The
synthesizer block multiplies and filters the input clock selected by the input block.
NOTE:
This Section of the data sheet provides a high-level description of the features of the
CDCE62005 for purpose of understanding its capabilities. For a complete description
of device registers and I/O, please refer to the Device Configuration Section.
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CDCE62005
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Interface and Control Block
The CDCE62005 is a highly flexible and configurable architecture and as such contains a number of registers so
that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM
determine device configuration at all times. On power-up, the CDCE62005 copies the contents of the EEPROM
into the RAM and the device begins operation based on the default configuration stored in the EEPROM.
Systems that do not have a host system to communicate with the CDCE62005 use this method for device
configuration. The CDCE62005 provides the ability to lock the EEPROM; enabling the designer to implement a
fault tolerant design. After power-up, the host system may overwrite the contents of the RAM via the SPI (Serial
Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62005 during system
operation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM, if the EEPROM is
unlocked.
Static RAM (Device Registers)
Register 8
Register 7
Register 6
REF_SELECT
/Power_Down
/SYNC
Register 5
Interface
&
Control
Device
Hardware
Register 4
Register 3
Register 2
Register 1
Register 0
SPI_LE
SPI_CLK
SPI_MISO
SPI_MOSI
EEPROM (Default Configuration)
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
Figure 4. CDCE62005 Interface and Control Block
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Input Block
The Input Block includes a pair of Universal Input Buffers and an Auxiliary Input. The Input Block buffers the
incoming signals and facilitates signal routing to the Internal Clock Distribution bus and the Synthesizer Block via
the smart multiplexer (called the Smart MUX). The Internal Clock Distribution Bus connects to all output blocks
discussed in the next section. Therefore, a clock signal present on the Internal Clock Distribution bus can appear
on any or all of the device outputs. The CDCE62005 routes the PRI_IN and SEC_IN inputs directly to the Internal
Clock Distribution Bus. Additionally, it can divide these signals via the dividers present on the inputs and output
of the first stage of the Smart MUX.
1500 MHz
PRI_IN
LVPECL: 1500 MHz
LVDS: 800 MHz
LVCMOS: 250 MHz
1500 MHz
SEC_IN
Smart MUX
Control
REF_SEL
Smart
/1:/2:HiZ
MUX1
Smart
MUX2
Reference Divider
/1 - /8
/1:/2:HiZ
Crystal: 2 MHz - 40 MHz
XTAL/
AUX_IN
Single Ended: 2 MHz - 75 MHz
Figure 5. CDCE62005 Input Block
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Output Block
Each of the five identical output blocks incorporates an output multiplexer, a clock divider module, and a
universal output array as shown.
Output
MUX
Output Buffer Control
Sync
Control
Enable
Pulse
PRI_IN
UxP
UxN
SEC_IN
Clock Divider Module 0 - 4
LVDS
SMART_MUX
SYNTH
LVPECL
Figure 6. CDCE62005 Output Block (1 of 5)
Clock Divider Module 0–4
The following shows a simplified version of a Clock Divider Module (CDM). If an individual clock output channel
is not used, then the user should disable the CDM and Output Buffer for the unused channel to save device
power. Each channel includes two 7-bit registers to control the divide ratio used and the clock phase for each
output. The output divider supports divide ratios from divide by 1 (bypass the divider) to divide by 80; the divider
does not support all integer values between 1 and 80. Refer to Table 23 for a complete list of divide ratios
supported.
Enable
Sync Pulse
(internally generated)
Digital Phase Adjust (7-bits)
Output Divider (7-bits)
From
Output
MUX
To
Output
Buffer
Figure 7. CDCE62005 Output Divider Module (1 of 5)
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Synthesizer Block
Figure 8 presents a high-level overview of the Synthesizer Block on the CDCE62005.
1.750 GHz –
SMART_MUX
Input Divider
/1 - /256
2.356 GHz
PFD/
CP
Prescaler
/2,/3,/4,/5
SYNTH
Feedback Divider
50 kHz –
400 kHz
/1, /2, /5, /8, /10, /15, /20
/8 - /1280
Feedback Divider
Feedback Bypass Divider
Figure 8. CDCE62005 Synthesizer Block
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COMPUTING THE OUTPUT FREQUENCY
Figure 9 presents the block diagram of the CDCE62005 in synthesizer mode highlighting the clock path for a
single output. It also identifies the following regions containing dividers comprising the complete clock path
•
R: Includes the cumulative divider values of all dividers included from the Input Ports to the output of the
Smart Multiplexer (see Input Block for more details)
•
•
•
•
O: The output divider value (see Output Block for more details)
I: The input divider value (see Synthesizer Block for more details)
P: The Prescaler divider value (see Synthesizer Block of more details)
F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block for
more details)
O
Output
Divider 0
U0P
FOUT
U0N
FIN
R
/1:/2:HiZ
/1:/2:HiZ
Reference
Divider
U1P
U1N
Output
Divider 1
EXT_LFP
EXT_LFN
U2P
U2N
Output
Divider 2
I
Input
Divider
P
U3P
U3N
PFD/
CP
Output
Divider 3
Prescaler
Feedback
Divider
F
U4P
U4N
Output
Divider 4
AUX
OUT
Figure 9. CDCE62005 Clock Path – Synthesizer Mode
With respect to Figure 9, any output frequency generated by the CDCE62005 relates to the input frequency
connected to the Synthesizer Block by Equation 1.
F
FOUT = F ´
IN
R´I´O
(1)
Equation 1 holds true when subject to the following constraints:
1.750 Ghz < O x P x FOUT< 2.356 GHz
And the comparison frequency FCOMP
,
40 kHz ≤ FCOMP < 40 MHz
Where:
F
IN
FCOMP
=
R ´I
Note: This device cannot output the frequencies between 780 MHz to 880 MHz
(2)
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
-0.5 to 4.6
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
±20
UNIT
V
VCC
VI
Supply voltage range(2)
Input voltage range(3)
Output voltage range(3)
V
VO
V
Input Current (VI < 0, VI > VCC
)
mA
mA
°C
°C
Output current for LVPECL/LVCMOS Outputs (0 < VO < VCC
)
±50
TJ
Maximum junction temperature
125
Tstg
Storage temperature range
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All supply voltages have to be supplied simultaneously.
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
THERMAL CHARACTERISTICS
Package Thermal Resistance for QFN (RGZ) Package
(1) (2)
AIRFLOW (lfm)
θJP (°C/W)(3)
θJA (°C/W)
28.9
0
JEDEC Compliant Board (6X6 VIAs on PAD)
JEDEC Compliant Board (6X6 VIAs on PAD)
Recommended Layout (7X7 VIAs on PAD)
Recommended Layout (7X7 VIAs on PAD)
2
2
2
2
100
0
20.4
27.3
100
20.3
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(2) Connected to GND with 36 thermal vias (0,3 mm diameter).
(3) θJP (Junction – Pad) is used for the QFN Package, because the main heat flow is from the Junction to the GND-Pad of the QFN.
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN
3
TYP
3.3
MAX UNIT
POWER SUPPLY
VCC
Supply voltage
3.6
3.6
V
VCC_PLL
,
VCC_IN
VCC_VCO
VCCA
,
Analog supply voltage
3
3.3
&
PLVPECL
PLVDS
REF at 30.72,MHz, Outputs are LVPECL
REF at 30.72 MHz, Outputs are LVDS
Output 1 = 491.52 MHz
1.9
W
W
Output 2 = 245.76 MHz
Output 3 = 122.88 MHz
Output 4 = 61.44 MHz
Output 5 = 30.72 MHz
In case of LVCMOS
Outputs = 245.76 MHz
1.65
PLVCMOS
REF at 30.72 MHz, Outputs are LVCMOS
REF at 30.72 MHz
1.8
W
Dividers are disabled. Outputs are
disabled.
POFF
PPD
0.75
20
W
Device is powered down
mW
DIFFERENTIAL INPUT MODE (PRI_IN, SEC_IN)
(1)
VINPP
VIC
Input amplitude (V_IN – V/IN
)
0.1
1.0
1.3
V
V
Common-mode input voltage
VCC–0.3
Differential input current high (no internal
termination)
IIH
IIL
VI = VCC, VCC = 3.6 V
VI = 0 V, VCC = 3.6 V
20
20
µA
Differential input current low (no internal
termination)
–20
µA
Input Capacitance on PRI_IN, SEC_IN
3
pF
LVCMOS INPUT MODE (AUX_IN)
VIL
VIH
Low-level input voltage LVCMOS
0
0.3 x VCC
VCC
V
V
High-level input voltage LVCMOS
VIK LVCMOS input clamp voltage
LVCMOS input current
0.7 x VCC
VCC = 3 V, II = –18 mA
VI = VCC, VCC = 3.6 V
VI = 0 V, VCC = 3.6 V
VI = 0 V or VCC
–1.2
V
IIH
IIL
CI
300
8
µA
µA
pF
LVCMOS input
–10
10
Input capacitance (LVCMOS signals)
CRYSTAL INPUT SPECIFICATIONS
Crystal shunt capacitance
20
50
pF
Equivalent series resistance (ESR)
Ω
LVCMOS INPUT MODE (SPI_CLK,SPI_MOSI,SPI_LE,PD,SYNC,REF_SEL, PRI_IN, SEC_IN )
Low-level input voltage LVCMOS,
0
0.3 x VCC
VCC
V
V
High-level input voltage LVCMOS
0.7 x VCC
VIK
IIH
LVCMOS input clamp voltage
LVCMOS input current
VCC = 3 V, II = –18 mA
VI = VCC, VCC = 3.6 V
–1.2
V
20
µA
LVCMOS input (Except PRI_IN and
SEC_IN)
IIL
VI = 0 V, VCC = 3.6 V
–10
–10
–40
10
µA
IIL
CI
LVCMOS input (PRI_IN and SEC_IN)
Input capacitance (LVCMOS signals)
VI = 0 V, VCC = 3.6 V
VI = 0 V or VCC
µA
3
pF
(1) VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of
100mV.
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued)
recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX UNIT
SPI OUTPUT (MISO) / PLL DIGITAL (OUTPUT MODE)
IOH
High-level output current
VCC = 3.3 V,
VO = 1.65 V
VO = 1.65 V
IOH = −100 µA
IOL = 100 µA
–30
33
mA
mA
V
IOL
Low-level output current
VCC = 3.3 V,
VCC = 3 V,
VCC = 3 V,
VOH
VOL
CO
High-level output voltage for LVCMOS outputs
Low-level output voltage for LVCMOS outputs
Output capacitance on MISO
VCC–0.5
0.3
V
VCC = 3.3 V; VO = 0 V or VCC
3
5
pF
IOZH
IOZL
VO = VCC
VO = 0 V
3-state output current
µA
–5
PLL ANALOG ( INPUT MODE)
High-impedance state output current for PLL
IOZH LOCK
IOZL LOCK
VT+
VO = 3.6 V (PD is set low)
VO = 0 V (PD is set low)
22
–1
µA
µA
V
LOCK output(2)
High-impedance state output current for PLL
LOCK output
Positive input threshold voltage VCC = min to
max
VCC×0.55
VCC×0.35
Negative input threshold voltage VCC c= min to
max
VT–
V
VBB
VBB
IBB = –0.2 mA, Depending on the
setting.
Termination voltage for reference inputs.
0.9
1.9
V
INPUT BUFFERS INTERNAL TERMINATION RESISTORS (PRI_IN and SEC_IN)
Termination resistance Single ended
PHASE DETECTOR
fCPmax Charge pump frequency
50
Ω
0.04
40 MHz
(1) All typical values are at VCC = 3.3 V, temperature = 25°C
(2) Lock output has a 80kΩ pull-down resistor.
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued)
recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
LVCMOS OUTPUT OR AUXILIARY OUTPUT
fclk
Output frequency, see Figure Below
Load = 5 pF to GND
0
250 MHz
High-level output voltage for LVCMOS
outputs
VOH
VCC = min to max
VCC = min to max
IOH = –100 µA
VCC –0.5
Low-level output voltage for LVCMOS
outputs
VOL
IOL =100 A
0.3
V
IOH
IOL
High-level output current
Low-level output current
VCC = 3.3 V
VCC = 3.3 V
VO = 1.65 V
VO = 1.65 V
–30
33
mA
mA
Reference (PRI_IN or SEC_IN) to Output
Phase offset
Outputs are set to 122.88 MHz, Reference
at 30.72 MHz
tpho
0.35
4
ns
ns
ps
tpd(LH)/
tpd(HL)
Propagation delay from PRI_IN or SEC_IN
to Outputs
Crosspoint to VCC/2, load In Bypass Mode
All Outputs set at 200 MHz in bypass mode
only, Reference = 200 MHz
tsk(o)
Skew, output to output For Y0 to Y4
Output capacitance on Y0 to Y4
75
CO
VCC = 3.3 V; VO = 0 V or VCC
VO = VCC
5
5
pF
µA
µA
µA
µA
IOZH
IOZL
IOPDH
IOPDL
3-State LVCMOS output current
Power Down output current
VO = 0 V
–5
VO = VCC
25
5
VO = 0 V
Duty cycle LVCMOS
45%
3.6
55%
tslew-rate
Output rise/fall slew rate
5.2
V/ns
(1) All typical values are at VCC = 3.3 V, temperature = 25°C
5 pF
LVCMOS
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued)(1)(2)(3)(4)
recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN TYP(5)
MAX UNIT
LVDS OUTPUT
fclk
Output frequency
Configuration Load
0
800 MHz
|VOD
|
Differential output voltage
LVDS VOD magnitude change
Offset Voltage
RL = 100 Ω
270
550
50
mV
mV
V
ΔVOD
VOS
–40°C to 85°C
1.24
40
ΔVOS
VOS magnitude change
Short circuit Vout+ to ground
Short circuit Vout– to ground
mV
mA
mA
ns
VOUT = 0
VOUT = 0
27
27
tpho
Reference (PRI_IN or SEC_IN) to output
phase offset
Outputs are set to 491.52 MHz
Reference at 30.72 MHz
1.65
3.1
tpd(LH)/tpd(HL) Propagation delay from PRI_IN or SEC_IN to Crosspoint to Crosspoint, load In Bypass
ns
ps
outputs
Mode
All Outputs set at 200 MHz
In Bypass Mode Only
Reference = 200 MHz
(6)
tsk(o)
Skew, output to output For Y0 to Y4
25
5
CO
IOPDH
IOPDL
Output capacitance on Y0 to Y4
Power down output current
Power down output current
Duty cycle
VCC = 3.3 V; VO = 0 V or VCC
VO = VCC
pF
µA
µA
25
5
VO = 0 V
45%
55%
190
tr / tf
Rise and fall time
20% to 80% of VOUT(PP)
VCC/2 to Crosspoint
110
160
1.4
ps
ns
LVCMOS-TO-LVDS
tskP_c
Output skew between LVCMOS and LVDS
outputs(7)
0.9
1.9
(1) This is valid only for same REF_IN clock and Y output clock frequency
(2) VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of
100mV.
(3) Lock output has a 80 kΩ pull-down resistor.
(4) The phase of LVCMOS is lagging in reference to the phase of LVDS.
(5) All typical values are at VCC = 3.3 V, temperature = 25°C
(6) The tsk(o) specification is only valid for equal loading of all outputs.
(7) Operating the LVCMOS or LVDS output above the maximum frequency will not cause a malfunction to the device, but the output signal
swing might no longer meet the output specification
LVDS DC Termination Test
100 Ω
Oscilloscope
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ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (Continued)
recommended operating conditions for the CDCE62005 device for under the specified Industrial temperature range of –40°C
to 85°C
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
LVPECL OUTPUT
fclk
Output frequency, Configuration load
LVPECL high-level output voltage load
LVPECL low-level output voltage load
Differential output voltage
0
1500
VCC –0.88
VCC–1.58
970
MHz
V
VOH
VOL
|VOD
VCC –1.06
VCC–2.02
610
V
|
mV
Outputs are set to 491.52 MHz,
Reference at 30.72 MHz
tpho
Reference to Output Phase offset
1.47
3.4
ns
ns
tpd(LH)
tpd(HL)
/
Crosspoint to Crosspoint, load In
Bypass Mode
Propagation delay from PRI_IN or SEC_IN to outputs
All Outputs set at 200 MHz
In Bypass Mode Only
Reference = 200MHz
tsk(o)
Skew, output to output For Y0 to Y4
25
5
ps
CO
Output capacitance on Y0 to Y4
Power Down output current
VCC = 3.3 V; VO = 0 V or VCC
VO = VCC
pF
µA
µA
IOPDH
IOPDL
25
5
VO = 0 V
Duty Cycle
45%
55
55%
135
tr / tf
Rise and fall time
20% to 80% of VOUT(PP)
Crosspoint to Crosspoint
VCC/2 to Crosspoint
75
1.1
ps
ns
ps
LVDS-TO-LVPECL
tskP_C
Output skew between LVDS and LVPECL outputs
0.9
1.3
LVCMOS-TO-LVPECL
tskP_C
Output skew between LVCMOS and LVPECL outputs
–150
260
700
LVPECL HI-PERFORMANCE OUTPUT
VOH
VOL
LVPECL high-level output voltage load
VCC –1.11
VCC –2.06
760
VCC –0.87
VCC –1.73
1160
V
V
LVPECL low-level output voltage load
Differential output voltage
Rise and fall time
|VOD
|
mV
ps
tr / tf
20% to 80% of VOUT(PP)
55
75
135
(1) All typical values are at VCC = 3.3 V, temperature = 25°C
LVPECL AC Termination Test
LVPECL DC Termination Test
50 Ω
Oscilloscope
50 Ω
150 Ω
150 Ω
50 Ω 50 Ω
Oscilloscope
Vcc-2
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LVPECL OUTPUT SWING
HI SWING LVPECL OUTPUT SWING
vs
vs
FREQUENCY
FREQUENCY
V
Figure 10.
Figure 11.
LVDS OUTPUT SWING
LVCMOS OUTPUT SWING
vs
vs
FREQUENCY
FREQUENCY
Figure 12.
Figure 13.
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TIMING REQUIREMENTS
over recommended ranges of supply voltage, load and operating free air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
PRI_IN/SEC_IN_IN REQUIREMENTS
Maximum Clock Frequency Applied to PRI_IN & SEC_IN in fan-out mode
Maximum Clock Frequency Applied to Smart Multiplexer input Divider
Maximum Clock Frequency Applied to Reference Divider
For Single ended Inputs ( LVCMOS) on PRI_IN and SEC_IN
Single duty cycle of PRI_IN or SEC_IN at VCC / 2
1500
500
MHz
MHz
MHz
MHz
fmax
250
250
40%
40%
60%
60%
Differential duty cycle of PRI_IN or SEC_IN at VCC / 2
AUXILARY_IN REQUIREMENTS
fREF
fREF
Single ended Inputs (LVCMOS) on AUX_IN
2
2
75
42
MHz
MHz
Crystal single ended Inputs (AT-Cut Crystal Input)
PD, SYNC, REF_SEL REQUIREMENTS
tr/ tf
Rise and fall time of the PD, SYNC, REF_SEL signal from 20% to 80% of VCC
4
ns
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PHASE NOISE ANALYSIS
Table 1. Device Output Phase Noise for 30.72 MHz External Reference
Phase Noise Specifications under following configuration: VCO = 1966.08 MHz, REF = 30.72 MHz,
PFD Frequency = 30.72 MHz, Charge Pump Current = 1.5 mA Loop BW = 400 kHz at 3.3 V and 25°C
Phase Noise
Reference 30.72
MHz
LVPECL 491.52
MHz
LVDS
491.52 MHz
LVCMOS
122.88
MHz
Unit
10 Hz
-108
-130
-134
-152
-156
-157
—
–81
–94
–81
–96
–92
–108
–118
–132
–134
–143
–150
–150
377
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
100 Hz
1 kHz
–106
–119
–121
–131
–145
–145
307
–106
–119
–122
–131
–144
–144
315
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
—
Jitter(RMS)
193
10k~20 MHz
Table 2. Device Output Phase Noise for 25 MHz Crystal Reference
Phase Noise Specifications under following configuration: VCO = 2000.00 MHz, AUX-REF = 25.00
MHz,
PFD Frequency = 25.00 MHz, Charge Pump Current = 1.5 mA Loop BW = 400 kHz at 3.3 V and 25°C
Phase Noise Referenc LVPECL 500 MHz
e 25 MHz
LVDS 250 MHz
LVCMOS 125 MHz
Unit
10 Hz
—
—
—
—
—
—
—
—
-57
-90
-62
-95
-68
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
100 Hz
1 kHz
-102
-119
-128
-130
-143
-150
-150
437
-107
-115
-118
-130
-145
-145
389
-113
-122
-124
-137
-147
-147
405
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Jitter(RMS)
10k~20 MHz
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OUTPUT TO OUTPUT ISOLATION
Measurement Method
1. Connect output 2 to a spectrum analyzer. Disable Outputs 0, 1, 3, 4.
2. Measure spurious on Output 2.
3. Enable aggressor channels individually per Table 3.
4. Measure spurious on Output 2.
5. The difference between the spurious levels of Output 2 before and after enabling the aggressor channels
determine the output-to-output isolation performance recorded.
Table 3. Output to Output Isolation
M SPUR
Unit
The Output to Output Isolation was tested under following settings are 25°C
Output 2
Output 2
Output 2
Output 0
Output 1
Output 3
Output 4
Measured Channel
Measured Channel
Measured Channel
Aggressor Channel
Aggressor Channel
Aggressor Channel
Aggressor Channel
In LVPECL Signaling 15.5 MHz
In LVPECL Signaling 93 MHz
In LVPECL Signaling 930 MHz
LVPECL 22.14 MHz
–67
–60
–59
db
db
db
LVPECL 22.14 MHz
LVPECL 22.14 MHz
LVPECL 22.14 MHz
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SPI CONTROL INTERFACE TIMING
t1
t4
t5
SPI _CLK
SPI _MOSI
SPI _ LE
t2
t3
Bit0
Bit1
Bit29
Bit30
Bit31
t7
t6
Figure 14. Timing Diagram for SPI Write Command
t4
t5
SPI _CLK
t2
t3
Bit30
Bit31
SPI _MOSI
SPI _MISO
SPI _ LE
t9
Bit1
Bit2
Bit0
t7
t6
t8
Figure 15. Timing Diagram for SPI Read Command
SPI Bus Timing Characteristics
PARAMETER
MIN
TYP
MAX
20
UNIT
MHz
ns
fClock
t1
Clock Frequency for the SPI_CLK
SPI_LE to SPI_CLK setup time
SPI_MOSI to SPI_CLK setup time
SPI_MOSI to SPI_CLK hold time
SPI_CLK high duration
10
10
10
25
25
10
20
10
t2
ns
t3
ns
t4
ns
t5
SPI_CLK low duration
ns
t6
SPI_CLK to SPI_LE Setup time
SPI_LE Pulse Width
ns
t7
ns
t8
SPI_MISO to SPI_CLK Data Valid (First Valid Bit after LE)
ns
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DEVICE CONFIGURATION
The Functional Description Section described four different functional blocks contained within the CDCE62005.
Figure 16 depicts these blocks along with a high-level functional block diagram of the circuit elements comprising
each block. The balance of this section focuses on a detailed discussion of each functional block from the
perspective of how to configure them.
Output Blocks
Synthesizer
Block
Output
Channel 0
Smart
MUX
Frequency
Output
Synthesizer
Channel 1
Input
Block
Output
Channel 2
Interface
&
Interface
&
Device
Control
Block
Registers
Control
Output
Channel 3
Output
Channel 4
EEPROM
Figure 16. CDCE62005 Circuit Blocks
Throughout this section, references to Device Register memory locations follow the following convention:
Register 5
RAM Bit Number (s)
5
4
3
2
Register Number (s)
5.2
Figure 17. Device Register Reference Convention
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INTERFACE AND CONTROL BLOCK
The Interface & Control Block includes a SPI interface, four control pins, a non-volatile memory array in which
the device stores default configuration data, and an array of device registers implemented in Static RAM. This
RAM, also called the device registers, configures all hardware within the CDCE62005.
Static RAM (Device Registers)
Register 8
Register 7
Register 6
REF_SELECT
/Power_Down
/SYNC
Register 5
Interface
&
Control
Device
Hardware
Register 4
Register 3
Register 2
Register 1
Register 0
SPI_LE
SPI_CLK
SPI_MISO
SPI_MOSI
EEPROM (Default Configuration)
Register 7
Register 6
Register 5
Register 4
Register 3
Register 2
Register 1
Register 0
Figure 18. CDCE62005 Interface and Control Block
SPI (Serial Peripheral Interface)
The serial interface of CDCE62005 is a simple bidirectional SPI interface for writing and reading to and from the
device registers. It implements a low speed serial communications link in a master/slave topology in which the
CDCE62005 is a slave. The SPI consists of four signals:
•
SPI_CLK: Serial Clock (Output from Master) – the CDCE62005 clocks data in and out on the rising edge of
SPI_CLK. Data transitions therefore occur on the falling edge of the clock.
•
•
•
SPI_MOSI: Master Output Slave Input (Output from Master) .
SPI_MISO: Master Input Slave Output (Output from Slave)
SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high,
no data transfer can take place.
The CDCE62005 implements data fields that are 28-bits wide. In addition, it contains 9 registers, each
comprising a 28 bit data field. Therefore, accessing the CDCE62005 requires that the host program append a
4-bit address field to the front of the data field as follows:
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Device Register N
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SPI Register
Address
Bits
(4)
Data Bits (28)
First In/
First Out
Last in/
Last out
19 18 17 16 15
27 26 25 24 23 22 21 20
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
3
2
1
0
SPI Master (Host)
SPI_CLK
SPI Slave (CDCE62005)
SPI_CLK
SPI_LE
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_LE
SPI_MOSI
SPI_MISO
SPI_LE
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
3
2
1
0
SPI_MOSI
SPI_MISO
Figure 19. CDCE62005 SPI Communications Format
CDCE62005 SPI Command Structure
The CDCE62005 supports four commands issued by the Master via the SPI:
•
•
•
•
Write to RAM
Read Command
Copy RAM to EEPROM – unlock
Copy RAM to EEPROM – lock
Table 4 provides a summary of the CDCE62005 SPI command structure. The host (master) constructs a Write to
RAM command by specifying the appropriate register address in the address field and appends this value to the
beginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first. The
host must issue a Read Command to initiate a data transfer from the CDCE62005 back to the host. This
command specifies the address of the register of interest in the data field.
Table 4. CDCE62005 SPI Command Structure
Data Field (28 Bits)
Addr Field
(4 Bits)
Register
Operation
NVM
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
3
2
1
0
0
Write to RAM
Write to RAM
Write to RAM
Write to RAM
Write to RAM
Write to RAM
Write to RAM
Write to RAM
Status/Control
Read Command
RAM EEPROM
RAM EEPROM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
A
0
X
X
X
X
X
X
X
X
X
A
0
X
X
X
X
X
X
X
X
X
A
0
X
X
X
X
X
X
X
X
X
A
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
2
3
4
5
6
7
8
Instruction
Instruction
Instruction
No
Unlock
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1)
Lock
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
(1) CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration can
only be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed
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The CDCE62005 on-board EEPROM has been factory preset to the default settings listed in the table below.
REGISTER
REG0000
DEFAULT SETTING
8184032
REG0001
8184030
REG0002
8186030
REG0003
EB86030
REG0004
0186031
REG0005
101C0BE
04BE19A
BD0037F
80005DD
REG0006
REG0007
REG0008 (RAM)
The Default configurations programmed in the device is set to: Primary and Secondary are set to LVPECL AC
termination and the Auxiliary input is enabled. The Smart Mux is set to auto select among Primary, Secondary
and Auxiliary. Reference is set at 25MHz and the dividers are selected to run the VCO at 1875MHz.
Output 0 & 1 are set to output 156.25MHz with LVPECL signaling
Output 2 is set to output 125MHz/ LVPECL
Output 3 is set to output 125MHz/ LVDS
Output 4 is set to output 125MHz/ LVCMOS
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CDCE62005
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Writing to the CDCE62005
Figure 20 illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit
0) occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE62005,
data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE62005 that
the transmission of the last bit in the stream (Bit 31) has occurred.
SPI_CLK
Bit0
Bit1
Bit29
Bit30
Bit31
SPI_MOSI
SPI_LE
Figure 20. CDCE62005 SPI Write Operation
Reading from the CDCE62005
Figure 21 shows how the CDCE62005 executes a Read Command. The SPI master first issues a Read
Command to initiate a data transfer from the CDCE62005 back to the host (see Table 6). This command
specifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE62005
resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and the
CDCE62005 presents the data present in the register specified in the Read Command on SPI_MISO.
SPI_CLK
Bit30
Bit31
SPI_MOSI
Bit0
Bit1
Bit2
SPI_MISO
SPI_LE
Figure 21. CDCE62005 Read Operation
Writing to EEPROM
After the CDCE62005 detects a power-up and completes a reset cycle, it copies the contents of the on-board
EEPROM into the Device Registers. Therefore, the CDCE62005 initializes into a known state pre-defined by the
user. The host issues one of two special commands shown in Table 6 to copy the contents of Device Registers 0
through 7 (a total of 184 bits) into EERPOM. They include:
•
•
Copy RAM to EEPROM – Unlock, Execution of this command can happen many times.
Copy RAM to EEPROM – Lock: Execution of this command can happen only once; after which the EEPROM
is permanently locked.
After either command is initiated, power must remain stable and the host must not access the CDCE62005 for at
least 50 ms to allow the EEPROM to complete the write cycle and to avoid the possibility of EEPROM corruption.
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Device Registers: Register 0
Table 5. CDCE62005 Register 0 Bit Definitions
SPI RAM BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
BIT
BIT
0
A0
Address 0
Address 1
Address 2
Address 3
0
1
A1
0
2
A2
0
3
A3
0
4
0
1
DIV2PRIX
Pre-Divider Selection for the Primary Reference
(X,Y)=00:3-state, 01:Divide by “1”, 10:Divide by “2”, 11:Reserved
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Primary
Reference
5
DIV2PRIY
6
2
RESERVED
RESERVED
OUTMUX0SELX
OUTMUX0SELY
PH0ADJC0
PH0ADJC1
PH0ADJC2
PH0ADJC3
PH0ADJC4
PH0ADJC5
PH0ADJC6
OUT0DIVRSEL0
OUT0DIVRSEL1
OUT0DIVRSEL2
OUT0DIVRSEL3
OUT0DIVRSEL4
OUT0DIVRSEL5
OUT0DIVRSEL6
Used in Test Mode
Used in Test Mode
7
3
8
4
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
Output 0
OUTPUT MUX “0” Select. Selects the Signal driving Output Divider”0”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
9
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
6
7
8
9
Coarse phase adjust select for output divider “0”
10
11
12
13
14
15
16
17
18
19
OUTPUT DIVIDER “0” Ratio Select
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
24
20
OUT0DIVSEL
Output 0
EEPROM
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
25
21
HiSWINGLVPECL0
Output 0
EEPROM
26
27
28
29
30
22
23
24
25
26
CMOSMODE0PX
CMOSMODE0PY
CMOSMODE0NX
CMOSMODE0NY
OUTBUFSEL0X
Output 0
Output 0
Output 0
Output 0
Output 0
LVCMOS mode select for OUTPUT “0” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
LVCMOS mode select for OUTPUT “0” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
OUTPUT TYPE
RAM BITS
22 23
24
0
25
0
26
0
27
1
LVPECL
0
0
0
1
LVDS
0
1
1
1
31
27
OUTBUFSEL0Y
Output 0
EEPROM
LVCMOS
Output Disabled
See Settings Above*
0
0
0
1
0
1
1
0
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
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Device Registers: Register 1
Table 6. CDCE62005 Register 1 Bit Definitions
SPI RA BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
BIT
M
BIT
0
1
A0
Address 0
Address 1
Address 2
Address 3
1
A1
0
2
A2
0
3
A3
0
4
0
1
2
3
4
5
6
7
8
9
DIV2SECX
DIV2SECY
RESERVED
RESERVED
OUTMUX1SELX
OUTMUX1SELY
PH1ADJC0
PH1ADJC1
PH1ADJC2
PH1ADJC3
Pre-Divider Selection for the Secondary Reference
(X,Y)=00:3-state, 01:Divide by “1”, 10:Divide by “2”, 11:Reserved
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Secondary
Reference
5
6
Used in Test Mode
Used in Test Mode
7
8
Output 1 OUTPUT MUX “1” Select. Selects the Signal driving Output Divider”1”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
9
Output 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Output 1
Output 1
Output 1
Output 1 Coarse phase adjust select for output divider “1”
10 PH1ADJC4
Output 1
11 PH1ADJC5
Output 1
12 PH1ADJC6
Output 1
13 OUT1DIVRSEL0
14 OUT1DIVRSEL1
15 OUT1DIVRSEL2
16 OUT1DIVRSEL3
17 OUT1DIVRSEL4
18 OUT1DIVRSEL5
19 OUT1DIVRSEL6
Output 1
Output 1
Output 1
Output 1 OUTPUT DIVIDER “1” Ratio Select
Output 1
Output 1
Output 1
When set to “0”, the divider is disabled
Output 1
24
20 OUT1DIVSEL
EEPROM
When set to “1”, the divider is enabled
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
25
21 HiSWINGLVPECL1
Output 1
EEPROM
26
27
28
29
30
22 CMOSMODE1PX
23 CMOSMODE1PY
24 CMOSMODE1NX
25 CMOSMODE1NY
26 OUTBUFSEL1X
Output 1 LVCMOS mode select for OUTPUT “1” Positive Pin.
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
Output 1
Output 1 LVCMOS mode select for OUTPUT “1” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
Output 1
Output 1
OUTPUT TYPE
RAM BITS
22
0
23
0
24
0
25 26 27
LVPECL
0
1
0
1
0
1
1
1
0
0
LVDS
0
1
0
31
27 OUTBUFSEL1Y
Output 1
EEPROM
LVCMOS
Output Disabled
See Settings Above*
0
1
0
1
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
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Device Registers: Register 2
Table 7. CDCE62005 Register 2 Bit Definitions
SPI RA BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
BIT
M
BIT
0
1
A0
Address 0
0
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
0
4
0
1
2
3
4
5
6
7
8
9
REFDIV0
REFDIV1
RESERVED
RESERVED
OUTMUX2SELX
OUTMUX2SELY
PH2ADJC0
PH2ADJC1
PH2ADJC2
PH2ADJC3
Reference Divider Bit “0”
Reference Divider Bit “1”
Used in Test Mode
Used in Test Mode
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
Reference
Divider
5
6
7
8
Output 2 OUTPUT MUX “2” Select. Selects the Signal driving Output Divider”2”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
9
Output 2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Output 2
Output 2
Output 2
Output 2 Coarse phase adjust select for output divider “2”
10 PH2ADJC4
Output 2
11 PH2ADJC5
Output 2
12 PH2ADJC6
Output 2
13 OUT2DIVRSEL0
14 OUT2DIVRSEL1
15 OUT2DIVRSEL2
16 OUT2DIVRSEL3
17 OUT2DIVRSEL4
18 OUT2DIVRSEL5
19 OUT2DIVRSEL6
Output 2
Output 2
Output 2
Output 2 OUTPUT DIVIDER “2” Ratio Select
Output 2
Output 2
Output 2
When set to “0”, the divider is disabled
Output 2
24
20 OUT2DIVSEL
EEPROM
When set to “1”, the divider is enabled
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
25
21 HiSWINGLVPEC2
Output 2
EEPROM
26
27
28
29
30
22 CMOSMODE2PX
23 CMOSMODE2PY
24 CMOSMODE2NX
25 CMOSMODE2NY
26 OUTBUFSEL2X
Output 2 LVCMOS mode select for OUTPUT “2” Positive Pin.
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
Output 2
Output 2 LVCMOS mode select for OUTPUT “2” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
Output 2
Output 2
OUTPUT TYPE
RAM BITS
22
0
23
0
24
0
25 26 27
LVPECL
0
1
0
1
0
1
1
1
0
0
LVDS
0
1
0
31
27 OUTBUFSEL2Y
Output 2
EEPROM
LVCMOS
Output Disabled
See Settings Above*
0
1
0
1
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
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CDCE62005
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Device Registers: Register 3
Table 8. CDCE62005 Register 3 Bit Definitions
SPI RAM BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
BIT
BIT
0
A0
A1
A2
A3
Address 0
Address 1
Address 2
Address 3
1
1
0
0
1
2
3
Reference
Divider
4
0
REFDIV2
Reference Divider Bit “2”
EEPROM
5
1
2
RESERVED
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
6
RESERVED
Used in Test Mode
Used in Test Mode
7
3
RESERVED
8
4
OUTMUX3SELX
OUTMUX3SELY
PH3ADJC0
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
Output 3
OUTPUT MUX “3” Select. Selects the Signal driving Output Divider”3”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
9
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
6
7
PH3ADJC1
8
PH3ADJC2
9
PH3ADJC3
Coarse phase adjust select for output divider “3”
10
11
12
13
14
15
16
17
18
19
PH3ADJC4
PH3ADJC5
PH3ADJC6
OUT3DIVRSEL0
OUT3DIVRSEL1
OUT3DIVRSEL2
OUT3DIVRSEL3
OUT3DIVRSEL4
OUT3DIVRSEL5
OUT3DIVRSEL6
OUTPUT DIVIDER “3” Ratio Select
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
24
20
OUT3DIVSEL
Output 3
EEPROM
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
25
21
HiSWINGLVPEC3
Output 3
EEPROM
26
27
28
29
30
22
23
24
25
26
CMOSMODE3PX
CMOSMODE3PY
CMOSMODE3NX
CMOSMODE3NY
OUTBUFSEL3X
Output 3
Output 3
Output 3
Output 3
Output 3
LVCMOS mode select for OUTPUT “3” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
LVCMOS mode select for OUTPUT “3” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
OUTPUT TYPE
RAM BITS
22 23 24
25
0
26
0
27
1
LVPECL
0
0
0
1
0
0
LVDS
1
1
1
31
27
OUTBUFSEL3Y
Output 3
EEPROM
LVCMOS
Output Disabled
See Settings Above*
0
0
0
1
0
1
1
0
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
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Device Registers: Register 4
Table 9. CDCE62005 Register 4 Bit Definitions
SPI RAM BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
BIT
BIT
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
1
0
3
A3
Address 3
4
0
1
RESERVED
—
This bit must be set to a “0”
0 (default): normal operation,
EEPROM
5
ATETEST
TI Test Bit
EEPROM
1: outputs have deterministic delay relative to low-to-high edge of SYNC pin
6
2
3
RESERVED
Used in Test Mode
Used in Test Mode
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
7
RESERVED
8
4
OUTMUX4SELX
OUTMUX4SELY
PH4ADJC0
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
Output 4
OUTPUT MUX “4” Select. Selects the Signal driving Output Divider”4”
(X,Y) = 00: PRI_IN, 01:SEC_IN, 10:SMART_MUX, 11:VCO_CORE
9
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
6
7
PH4ADJC1
8
PH4ADJC2
9
PH4ADJC3
Coarse phase adjust select for output divider “4”
10
11
12
13
14
15
16
17
18
19
PH4ADJC4
PH4ADJC5
PH4ADJC6
OUT4DIVRSEL0
OUT4DIVRSEL1
OUT4DIVRSEL2
OUT4DIVRSEL3
OUT4DIVRSEL4
OUT4DIVRSEL5
OUT4DIVRSEL6
OUTPUT DIVIDER “4” Ratio Select
When set to “0”, the divider is disabled
When set to “1”, the divider is enabled
24
20
OUT4DIVSEL
Output 4
EEPROM
High Swing LVPECL When set to “1” and Normal Swing when set to “0”
– If LVCMOS or LVDS is selected the Output swing will stay at the same level.
– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to “1”
and Normal LVPECL if it is set to “0”.
25
21
HiSWINGLVPEC4
Output 4
EEPROM
26
27
28
29
30
22
23
24
25
26
CMOSMODE4PX
CMOSMODE4PY
CMOSMODE4NX
CMOSMODE4NY
OUTBUFSEL4X
Output 4
Output 4
Output 4
Output 4
Output 4
LVCMOS mode select for OUTPUT “4” Positive Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
LVCMOS mode select for OUTPUT “3” Negative Pin.
(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State
OUTPUT TYPE
RAM BITS
22 23 24
25
0
26
0
27
1
LVPECL
0
0
0
1
0
0
LVDS
1
1
1
31
27
OUTBUFSEL4Y
Output 4
EEPROM
LVCMOS
Output Disabled
See Settings Above*
0
0
0
1
0
1
1
0
* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs
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Device Registers: Register 5
Table 10. CDCE62005 Register 5 Bit Definitions
SPI
BIT
RAM BIT NAME
BIT
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
1
2
3
A0
A1
A2
A3
Address 0
Address 1
Address 2
Address 3
1
0
1
0
Input Buffer Select (LVPECL,LVDS or LVCMOS)
XY(01 ) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin
4
0
INBUFSELX
INBUFSELX
INBUFSELY
EEPROM
5
6
7
1
2
3
INBUFSELY
PRISEL
EEPROM
EEPROM
EEPROM
WHEN EECLKSEL = 1;
Bit (6,7,8) 100 – PRISEL, 010 – SECSEL , 001 – AUXSEL
110 – Auto Select ( PRI then SEC)
111 – Auto Select ( PRI then SEC and then AUX)
When EECLKSEL = 0, REF_SEL pin determines the Reference Input to the Smart Mux
circuitry.
SECSEL
Smart MUX
8
4
5
AUXSEL
EEPROM
EEPROM
If EEPROM Clock Select Input is set to “1” The Clock selections follows internal EEPROM
Smart MUX settings and ignores REF_SEL Pin status, when Set to “0” REF_SEL is used to control
the Mux, Auto Select Function is not available and AUXSEL is not available.
9
EECLKSEL
10
6
7
ACDCSEL
HYSTEN
Input Buffers If Set to “1” DC Termination, If set to “0” AC Termination
EEPROM
EEPROM
Input Buffers If Set to “1” Input Buffers Hysteresis Enabled. It is not recommended that Hysteresis be
disabled.
11
12
If Set to “0” Primary Input Buffer Internal Termination Enabled
Input Buffers
8
PRI_TERMSEL
EEPROM
If set to “1” Primary Internal Termination circuitry Disabled
13
14
9
PRIINVBB
SECINVBB
Input Buffers If Set to “1” Primary Input Negative Pin Biased with Internal VBB Voltage.
Input Buffers If Set to “1” Secondary Input Negative Pin Biased with Internal VBB Voltage
EEPROM
EEPROM
10
If Set to “1” Fail Safe is Enabled for all Input Buffers configured as LVDS, DC Coupling
15
11
FAILSAFE
Input Buffers
only.
EEPROM
16
17
18
19
20
21
22
23
24
25
26
27
28
29
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RESERVED
RESERVED
SELINDIV0
SELINDIV1
SELINDIV2
SELINDIV3
SELINDIV4
SELINDIV5
SELINDIV6
SELINDIV7
LOCKW(0)
LOCKW(1)
LOCKW(2)
LOCKW(3)
Must be set to “0”
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
--------
Must be set to “0”
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
PLL Lock
INPUT DIVIDER Settings
LOCKW(3:0): Lock-detect Window Width
= 0000 (narrow window),
= 0001,0010,0100,0101 …..
= 1110 (widest window)
= XX11 (RESERVED)
Number of coherent lock events. If set to “0” it triggers after the first lock detection if set to
“1” it triggers lock after 64 cycles of lock detections.
30
31
26
27
LOCKDET
ADLOCK
PLL Lock
PLL Lock
EEPROM
EEPROM
Selects Digital PLL_LOCK “0” ,Selects Analog PLL_LOCK “1”
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CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862–NOVEMBER 2008
Device Registers: Register 6
Table 11. CDCE62005 Register 6 Bit Definitions
SPI
BIT
RAM BIT NAME
BIT
RELATED
BLOCK
DESCRIPTION/FUNCTION
0
1
A0
A1
A2
A3
Address 0
0
Address 1
1
2
Address 2
1
3
Address 3
0
4
0
1
SELVCO
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
—
VCO Select, 0:VCO1(low range), 1:VCO2(high range)
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
5
SELPRESCA
SELPRESCB
SELFBDIV0
SELFBDIV1
SELFBDIV2
SELFBDIV3
SELFBDIV4
SELFBDIV5
SELFBDIV6
SELFBDIV7
RESERVED
PRESCALER Setting.
6
2
7
3
8
4
9
5
10
11
12
13
14
15
6
FEEDBACK DIVIDER Setting
7
8
9
10
11
Must be set to “0”
If Set to “0” Secondary Input Buffer Internal Termination Enabled
If set to “1” Secondary Internal Termination circuitry Disabled
16
12
SEC_TERMSEL
Input Buffers
EEPROM
17
18
19
20
21
22
23
24
25
13
14
15
16
17
18
19
20
21
SELBPDIV0
SELBPDIV1
SELBPDIV2
ICPSEL0
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
VCO Core
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
BYPASS DIVIDER Setting ( 6 settings + Disable + Enable)
ICPSEL1
CHARGE PUMP Current Select
ICPSEL2
ICPSEL3
RESERVED
CPPULSEWIDTH
Must be set to “0”
If set to 1=wide pulse, 0=narrow pulse
Enable VCO Calibration Command. To execute this command a rising edge must be
generated (i.e. Write a LOW followed by a high to this bit location). This will initiate a
VCO calibration sequence only if Calibration Mode = Manual Mode (i.e. Register 6 bit 27
is HIGH).
26
22
ENCAL
VCO Core
EEPROM
27
28
23
24
RESERVED
AUXOUTEN
—
Must be set to “0”
EEPROM
EEPROM
Output AUX Enable Auxiliary Output when set to “1”
Select the Output that will driving the AUX Output;
Output AUX
29
30
25
26
AUXFEEDSEL
EXLFSEL
EEPROM
EEPROM
Low for Selecting Output Divider “2” and High for Selecting Output Divider “3”
When Set to “1” External Loop filter is used.
VCO Core
When Set to “0” Internal Loop Filter is used.
1: Calibration Mode = Manual Mode. In this mode, a calibration will be initiated if a rising
edge is asserted on ENCAL (Register 6 Bit 22).
0: Calibration Mode = Startup Mode.
PLL
Calibration
31
27
ENCAL_MODE
EEPROM
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Device Registers: Register 7
Table 12. CDCE62005 Register 7 Bit Definitions
SPI RAM BIT NAME
RELATED DESCRIPTION/FUNCTION
BLOCK
BIT
BIT
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
1
3
A3
Address 3
0
4
0
1
2
3
4
5
6
7
8
9
LFRCSEL0
LFRCSEL1
LFRCSEL2
LFRCSEL3
LFRCSEL4
LFRCSEL5
LFRCSEL6
LFRCSEL7
LFRCSEL8
LFRCSEL9
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
VCO Core Loop Filter Control Setting
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
10 LFRCSEL10
11 LFRCSEL11
12 LFRCSEL12
13 LFRCSEL13
14 LFRCSEL14
15 LFRCSEL15
16 LFRCSEL16
17 LFRCSEL17
18 LFRCSEL18
19 LFRCSEL19
20 LFRCSEL20
21 RESERVED
22 TESTMUX1
—
Must be set to "0"
Diagnostics Set to “1”
If set to “0” it enables short delay for fast operation
If Set to “1” Long Delay recommended for Input References below 150MHz.
Diagnostics Set to “1”
27
28
29
23 SEL_DEL2
24 TEXTMUX2
25 SEL_DEL1
Smart Mux
EEPROM
EEPROM
EEPROM
If set to “0” it enables short delay for fast operation
If Set to “1” Long Delay recommended for Input References below 150MHz.
Smart Mux
Read Only
If EPLOCK reads “0” EEPROM is unlocked. If EPLOCK reads “1”, then the
EEPROM is locked (see Table 4 for how to lock the EEPROM – this can only
be executed once after which the EEPROM is locked permanently).
30
31
26 EPLOCK
Status
Status
EEPROM
EEPROM
27 RESERVED
Read Only Always reads “1”
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Device Registers: Register 8
Table 13. CDCE62005 Register 8 Bit Definitions
SPI RAM BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
BIT
BIT
0
A0
Address 0
Address 1
Address 2
Address 3
0
1
A1
0
2
A2
0
3
A3
1
4
0
1
2
3
4
5
6
7
CALWORD0
CALWORD1
CALWORD2
CALWORD3
CALWORD4
CALWORD5
PLLLOCKPIN
/SLEEP
Status
Status
Status
Status
Status
Status
Status
Status
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
5
6
“VCO Calibration Word” read back from device
7
8
9
10
11
Read Only: Status of the PLL Lock Pin Driven by the device.
Set Device Sleep mode On when set to “0”, Normal Mode when set to “1”
If set to “0” this bit forces “/SYNC ; Set to “1” to exit the Synchronization
State.
12
8
/SYNC
Status
RAM
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
9
RESERVED
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
10 VERSION0
Silicon Revision
Silicon Revision
Silicon Revision
Must be set to “0”
11 VERSION1
12 VERSION2
13 RESERVED
14 CALWORD_IN0
15 CALWORD_IN1
16 CALWORD_IN2
17 CALWORD_IN3
18 CALWORD_IN4
19 CALWORD_IN5
20 RESERVED
21 TITSTCFG0
22 TITSTCFG1
23 TITSTCFG2
24 TITSTCFG3
25 PRIACTIVITY
26 SECACTIVITY
—
Diagnostics
Diagnostics
Diagnostics
Diagnostics
Diagnostics
Diagnostics
—
TI Test Registers. For TI Use Only
Must be set to “0”
Diagnostics
Diagnostics
Diagnostics
Diagnostics
Status
TI Test Registers. For TI Use Only
Synthesizer Source Indicator (27:25)
0 0 1 Primary Input
0 1 0 Secondary Input
Status
31
27 AUXACTIVITY
Status
RAM
1 0 0 Auxiliary Input
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Device Control
Figure 22 provides a conceptual explanation of the CDCE62005 Device operation. Table 14 defines how the
device behaves in each of the operational states.
Power
Applied
Power ON
Reset
Device
OFF
Delay Finished
Calibration
Hold
Sleep
Sleep = OFF
CAL_Enabled
Sleep = ON
VCO
CAL
Manual
Recalibration = ON
CAL Done
Sync = ON
Power Down = ON
Power Down
Active Mode
Sync
Sync = OFF
Figure 22. CDCE62005 Device State Control Diagram
Table 14. CDCE62005 Device State Definitions
Status
Output
State
Device Behavior
Entered Via
Exited Via
Output
Buffer
SPI Port
PLL
Divider
After device power supply reaches
approximately 2.35 V, the contents
of EEPROM are copied into the
Device Registers, thereby initializing
the device hardware.
Power applied to the device or upon
exit from Power Down State via the
Power_Down pin set HIGH.
Power On Reset and EEPROM loading
delays are finished OR the Power_Down
pin is set LOW.
OFF
Disabled
Disabled
OFF
Power-On
Reset(1)
The device waits until either
Delay process in the Power-On Reset The device waits until either
ON
ON
Enabled
Enabled
Disabled
Disabled
OFF
ENCAL_MODE (Device Register 6
bit 27) is low (Start up calibration
enabled) or both ENCAL_MODE is
high (Manual Calibration Enabled)
AND ENCAL (Device Register 6 bit
22) transitions from a low to a high
signaling the device.
State is finished or Sleep Mode (Sleep ENCAL_MODE (Device Register 6 bit 27)
bit is in Register 8 bit 7) is turned OFF is low (Start up calibration enabled) or
while in the Sleep State. Power Down both ENCAL_MODE is high (Manual
Calibration
Hold
must be OFF to enter the Calibration
Hold State.
Calibration Enabled) AND ENCAL (Device
Register 6 bit 22) transitions from a low to
a high signaling the device
The voltage controlled oscillator is
Calibration Hold: CAL Enabled
Calibration Process in completed
OFF
calibrated based on the PLL settings becomes true when either
and the incoming reference clock.
After the VCO has been calibrated,
the device enters Active Mode
automatically.
ENCAL_MODE (Device Register 6 bit
27) is low or both ENCAL_MODE is
high AND ENCAL (Device Register 6
bit 22) transitions from a low to a high.
Active Mode: A Manual Recalibration
is requested. This is initiated by
setting ENCAL_MODE to HIGH
(Manual Calibration Enabled) AND
initiating a calibration sequence by
applying a LOW to HIGH transition on
ENCAL.
VCO CAL
Normal Operation
CAL Done (VCO calibration process
finished) or Sync = OFF (from Sync
State).
Sync, Power Down, Sleep, or Manual
Recalibration activated.
ON
Enabled
Disabled Disabled
Active Mode
or
or
Enabled
Enabled
(1) To ensure proper operation, independently from power supply ramp up, Power_Down pin should be held LOW for 50 µs after power
supply is stable.
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Table 14. CDCE62005 Device State Definitions (continued)
Status
State
Device Behavior
Entered Via
Exited Via
Output
Divider
Output
Buffer
SPI Port
PLL
Used to shut down all hardware and Power_Down pin is pulled LOW.
Resets the device after exiting the
Power_Down pin is pulled HIGH.
ON
Disabled
Disabled Disabled
Power
Power Down State. Therefore, the
Down
EEPROM contents will eventually be
copied into RAM after the Power
Down State is exited.
Identical to the Power Down State
except the EEPROM contents are
not copied into RAM.
Sleep bit in device register 8 bit 7 is
set LOW.
Sleep bit in device register 8 bit 7 is set
HIGH.
ON
ON
Disabled
Enabled
Disabled Disabled
Disabled Disabled
Sleep
Sync synchronizes all output
dividers so that they begin counting
at the same time. Note: this
operation is performed automatically
each time a divider register is
accessed.
Sync Bit in device register 8 bit 8 is
set LOW or Sync pin is pulled LOW
Sync Bit in device register 8 bit 8 is set
HIGH or Sync pin is pulled HIGH
Sync
External Control Pins
REF_SEL
REF_SEL provides a way to switch between the primary and secondary reference inputs (PRI_IN and SEC_IN)
via an external signal. It works in conjunction with the smart multiplexer discussed in the Input Block section.
Power_Down
The Power_Down pin places the CDCE62005 into the power down state . Additionally, the CDCE62005 loads
the contents of the EEPROM into RAM after the Power_Down pin is de-asserted; therefore, it is used to initialize
the device after power is applied. SPI_LE signal has to be HIGH in order for EEPROM to load correctly during
the rising edge of Power_Down.
SYNC
The SYNC pin (Active LOW) has a complementary register location located in Device Register 8 bit 8. When
enabled, Sync synchronizes all output dividers so that they begin counting simultaneously. Further, SYNC
disables all outputs when in the active. State.
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INPUT BLOCK
The Input Block includes two Universal Input Buffers, an Auxiliary Input, and a Smart Multiplexer. The Input Block
drives three different clock signals onto the Internal Clock Distribution Bus: buffered versions of both the primary
and secondary inputs (PRI_IN and SEC_IN) and the output of the Smart Multiplexer.
Universal Input Buffers
1500 MHz
PRI_IN
LVPECL : 1500 MHz
LVDS : 800 MHz
LVCMOS : 250 MHz
Register 6
12
Register 5
9
8
6
1
0
1500 MHz
SEC_IN
Register 5
5
4
3
2
Smart MUX
Control
REF_SEL
Register 0
Smart Multiplexer
1
0
Smart
MUX1
/1:/2:HiZ
250 MHz
250 MHz
Smart
MUX2
Reference Divider
/1 - /8
Register 1
1
0
Auxiliary Input
XTAL/
AUX_IN
Register 3 Register 2
/1:/2:HiZ
0
1
0
Crystal : 2 MHz – 42 MHz
Single Ended : 2 MHz – 75 MHz
Figure 23. CDCE62005 Input Block With References to Registers
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Universal Input Buffers (UIB)
Figure 24 shows the key elements of a universal input buffer. A UIB supports multiple formats along with different
termination and coupling schemes. The CDCE62005 implements the UIB by including on board switched
termination, a programmable bias voltage generator, and an output multiplexer. The CDCE62005 provides a high
degree of configurability on the UIB to facilitate most existing clock input formats.
PRI_IN
Settings
5.1
5.0
5.6
INBUFSELY INBUFSELX ACDCSEL
Nominal
Vbb
PINV
Universal Input Control
1
1
1
1
0
0
1
1
0
1
0
1
1.9V
1.2V
PN
PP
1.2V
1.2V
50 Ω
50 Ω
Register 6
12
Vbb
Register 5
Vbb
1 mF
10
9
8
7
6
1
0
50 Ω
SN
50 Ω
SP
SINV
Settings
SWITCH Status
5.0
INBUFSELX
5.1
INBUFSELY
5.8, 6.12
TERMSEL
5.9,5.10
INVBB
P
N
INV
OFF
OFF
ON
SEC_IN
0
X
X
X
0
X
1
1
X
1
0
0
X
X
0
OFF
OFF
ON
OFF
OFF
ON
1
ON
ON
OFF
Figure 24. CDCE62005 Universal Input Buffer
Table 15 lists several settings for many possible clock input scenarios. Note that the two universal input buffers
share the Vbb generator. Therefore, if both inputs use internal termination, they must use the same configuration
mode (LVDS, LVPECL, or LVCMOS). If the application requires different modes (e.g. LVDS and LVPECL) then
one of the two inputs must implement external termination.
Table 15. CDCE62005 Universal Input Buffer Configuration Matrix
PRI_IN CONFIGURATION MATRIX
SETTINGS
CONFIGURATION
Register.Bit →
Bit Name →
5.7
5.1
5.0
5.8
5.9
5.6
HYSTEN
INBUFSELY
INBUFSELX
PRI_TERMSEL
PRIINVBB
ACDCSEL Hysteresis
Mode
LVCMOS
LVPECL
LVPECL
LVPECL
LVDS
Coupling
DC
AC
Termination
Vbb
—
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
X
X
X
0
0
1
0
0
1
X
X
X
0
X
0
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
OFF
N/A
Internal
Internal
External
Internal
Internal
External
—
1.9V
1.2V
—
0
1
DC
—
X
0
X
0
AC
1.2V
1.2V
—
0
1
LVDS
DC
—
X
X
X
X
X
X
LVDS
—
—
—
ENABLED
—
—
—
—
SEC_IN CONFIGURATION MATRIX
SETTINGS
CONFIGURATION
Register.Bit →
Bit Name →
5.7
HYSTEN
1
5.1
INBUFSELY
0
5.0
INBUFSELX
0
6.12
5.10
SECINVBB
X
5.6
SEC_TERMSEL
ACDCSEL Hysteresis
ENABLED
Mode
Coupling
Termination
Vbb
X
X
LVCMOS
DC
N/A
—
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Table 15. CDCE62005 Universal Input Buffer Configuration Matrix (continued)
PRI_IN CONFIGURATION MATRIX
SETTINGS
CONFIGURATION
Register.Bit →
Bit Name →
5.7
5.1
5.0
5.8
5.9
5.6
HYSTEN
INBUFSELY
INBUFSELX
PRI_TERMSEL
PRIINVBB
ACDCSEL Hysteresis
Mode
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVDS
—
Coupling
AC
Termination
Vbb
1.9V
1.2V
—
1
1
1
1
1
1
0
1
1
1
1
1
1
1
X
X
0
0
0
1
1
1
X
X
0
0
1
0
0
1
X
X
0
0
0
1
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
ENABLED
OFF
Internal
Internal
External
Internal
Internal
External
—
DC
—
X
0
X
0
AC
1.2V
1.2V
—
0
1
DC
—
X
X
X
X
X
X
—
—
ENABLED
—
—
—
—
LVDS Fail Safe Mode
Differential data line receivers can switch on noise in the absence of an input signal. This occurs when the bus
driver is turned off or the interconnect is damaged or missing. Traditionally the solution to this problem involves
incorporating an external resistor network on the receiver input. This network applies a steady-state bias voltage
to the input pins. The additional cost of the external components notwithstanding, the use of such a network
lowers input signal magnitude and thus reduces the differential noise margin. The CDCE62005 provides internal
failsafe circuitry on all LVDS inputs if enabled as shown in Table 16 for DC termination only.
Table 16. LVDS Failsafe Settings
Bit Name →
Register.Bit →
FAILSAFE
5.11
LVDS Failsafe
0
1
Disabled for all inputs
Enabled for all inputs
Smart Multiplexer Controls
The smart multiplexer implements a configurable switching mechanism suitable for many applications in which
fault tolerance is a design consideration. It includes the multiplexer itself along with three dividers. With respect to
the multiplexer control, Table 17 provides an overview of the configurations supported by the CDCE62005.
Table 17. CDCE62005 Smart Multiplexer Settings
REGISTER 5 SETTINGS
EECLKSEL
AUXSEL
SECSEL
PRISEL
SMART MULTIPLEXER MODE
5.5
1
5.4
0
5.3
0
5.2
1
Manual Mode: PRI_IN selected
1
0
1
0
Manual Mode: SEC_IN selected
1
1
0
0
Manual Mode: AUX_IN selected
1
0
1
1
Auto MOde: PRI_IN then SEC_IN
1
1
1
1
Auto Mode: PRI_IN then SEC_IN then AUX_IN
REF_SEL pin selects PRI_IN or SEC_IN
0
X
1
1
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Smart Multiplexer Auto Mode
Smart Multiplexer Auto Mode switches automatically between clock inputs based on a prioritization scheme
shown in Table 17. If using the Smart Multiplexer Auto Mode, the frequencies of the clock inputs may differ by up
to 20%. The phase relationship between clock inputs has no restriction. The smart multiplexer includes signal
conditioning that provides glitch suppression(1).
Upon the detection of a loss of signal on the highest priority clock, the smart multiplex switches its output to the
next highest priority clock on the first incoming rising edge of the next highest priority clock. During this switching
operation, the output of the smart multiplexer is low. Upon restoration of the higher priority clock, the smart
multiplexer waits until it detects four complete cycles from the higher priority clock prior to switching the output of
the smart multiplexer back to the higher priority clock. During this switching operation, the output of the smart
multiplexer remains high until the next falling edge as shown in Figure 25.
PRI _ REF
SEC _ REF
Internal
Reference Clock
Secondary Clock
Primary Clock
Primary Clock
Figure 25. CDCE62005 Smart Multiplexer Timing Diagram
Smart Multiplexer Dividers
Register 5
5
4
3
2
Smart MUX
Control
REF_SEL
Register 0
1
0
Smart Multiplexer
Smart
MUX1
/1:/2:HiZ
PRI_IN
Smart
MUX2
Reference Divider
/1 - /8
Register 1
Universal Input Buffers
SEC_IN
1
0
Register 3 Register 2
/1:/2:HiZ
0
1
0
XTAL/
AUX_IN
Auxiliary Input
Figure 26. CDCE62005 Smart Multiplexer
The CDCE62005 Smart Multiplexer Block provides the ability to divide the primary and secondary UIB or to
disconnect a UIB from the first state of the smart multiplexer altogether.
Table 18. CDCE62005 Pre-Divider Settings
Primary Pre-Divider
Secondary Pre-Divider
Bit Name →
Register.Bit →
DIV2PRIY
0.1
DIV2PRIX
0.0
Bit Name →
Register.Bit →
DIV2SECY
1.1
DIV2SECX
1.0
Divide Ratio
Divide Ratio
0
0
0
1
Hi-Z
/2
0
0
0
1
Hi-Z
/2
(1) This implementation does not include a phase build-out mechanism.
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Table 18. CDCE62005 Pre-Divider Settings (continued)
Primary Pre-Divider
Secondary Pre-Divider
Bit Name →
Register.Bit →
DIV2PRIY
0.1
DIV2PRIX
0.0
Bit Name →
Register.Bit →
DIV2SECY
1.1
DIV2SECX
1.0
Divide Ratio
/1
Divide Ratio
/1
1
1
0
1
1
1
0
1
Reserved
Reserved
The CDCE62005 provides a Reference Divider that divides the clock exiting the first multiplexer stage; thus
dividing the primary (PRI_IN) or the secondary input (SEC_IN).
Table 19. CDCE62005 Reference Divider Settings
Reference Divider
Bit Name →
Register.Bit →
REFDIV2
3.0
REFDIV1
2.1
REFDIV0
2.0
Divide Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
/1
/2
/3
/4
/5
/6
/7
/8
Auxiliary Input Port
The auxiliary input on the CDCE62005 is designed to connect to an AT-Cut Crystal with a total load
capacitance(CL) of 0 to 10pF. One side of the crystal connects to Ground while the other side connects to the
Auxiliary input of the device. The circuit works optimally between 20 to 40MHz but it can accept crystals from 2 to
42MHz.
Since the Auxiliary input operates between 0 and 2 V with a crystal, it can accept single-ended signals (e.g.
LVCMOS). Electrically, it is equivalent to an LVCMOS input buffer with 10pf of input capacitance.
8 pF
CL
Figure 27. CDCE62005 Auxiliary Input Port
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OUTPUT BLOCK
The output block includes five identical output channels. Each output channel comprises an output multiplexer, a
clock divider module, and a universal output buffer as shown in Figure 28.
Registers 0 - 4
Registers 0 - 4
5
4
27 26 25 24 23 22 21
Output
MUX
Control
Output Buffer Control
Sync
Pulse
Enable
PRI_IN
UxP
UxN
SEC_IN
Clock Divider Module 0 - 4
LVDS
SMART_MUX
SYNTH
LVPECL
Figure 28. CDCE62005 Output Channel
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Output Multiplexer Control
The Clock Divider Module receives the clock selected by the output multiplexer. The output multiplexer selects
from one of four clock sources available on the Internal Clock Distribution. For a description of PRI_IN, SEC_IN,
and SMART_MUX, see Figure 23. For a description of SYNTH, see Figure 33.
Table 20. CDCE62005 Output Multiplexer Control Settings
OUTPUT MULTIPLEXER CONTROL
Register n (n = 0,1,2,3,4)
OUTMUXnSELX
n.4
OUTMUXnSELY
n.5
CLOCK SOURCE SELECTED
0
0
1
1
0
1
0
1
PRI_IN
SEC_IN
SMART_MUX
SYNTH
Output Buffer Control
Each of the five output channels includes a programmable output buffer; supporting LVPECL, LVDS, and
LVCMOS modes. Table 21 lists the settings required to configure the CDCE62005 for each output type.
Registers 0 through 4 correspond to Output Channels 0 through 4 respectively.
Table 21. CDCE62005 Output Buffer Control Settings
OUTPUT BUFFER CONTROL
Register n (n = 0,1,2,3,4)
OUTPUT TYPE
CMOSMODEnPX
CMOSMODEnPY
CMOSMODEnNX
CMOSMODEnNY
OUTBUFSELnX
OUTBUFSELnY
n.22
n.23
n.24
n.25
n.26
n.27
0
0
0
1
0
0
0
1
0
1
0
1
1
1
0
0
LVPECL
LVDS
See LVCMOS Output Buffer Configuration Settings
LVCMOS
OFF
0
1
0
1
Output Buffer Control – LVCMOS Configurations
A LVCMOS output configuration requires additional configuration data. In the single ended configuration, each
Output Channel provides a pair of outputs. The CDCE62005 supports four modes of operation for single ended
outputs as listed in Table 22.
Table 22. LVCMOS Output Buffer Configuration Settings
OUTPUT BUFFER CONTROL – LVCMOS CONFIGURATION
Register n (n = 0,1,2,3,4)
Output
Pin
Output Mode
Type
CMOSMODEnPX
CMOSMODEnPY
CMOSMODEnNX
CMOSMODEnNY
OUTBUFSELnX
OUTBUFSELnY
n.22
X
n.23
X
n.24
0
n.25
0
n.26
0
n.27
0
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Negative Active – Non-inverted
Negative Hi-Z
X
X
0
1
0
0
X
X
1
0
0
0
Negative Active – Non-inverted
Negative Low
X
X
1
1
0
0
0
0
X
X
0
0
Positive
Positive
Positive
Positive
Active – Non-inverted
0
1
X
X
0
0
Hi-Z
1
0
X
X
0
0
Active – Non-inverted
Low
1
1
X
X
0
0
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Output Dividers
Figure 29 shows that each output channel provides a 7-bit divider and digital phase adjust block. Table 23 lists
the divide ratios supported by the output divider for each output channel. Figure 30 illustrates the output divider
architecture in detail. The Prescaler provides an array of low noise dividers with duty cycle correction. The
Integer Divider includes a final divide by two stage which is used to correct the duty cycle of the /1–/8 stage. The
output divider’s maximum input frequency is limited to 1.175GHz. If the divider is bypassed (divide ratio = 1) then
the maximum frequency of the output channel is 1.5GHz.
Registers 0 - 4
12 11 10
Registers 0 - 4
20
9
8
7
6
Enable
Sync
Pulse
(internally generated )
Digital Phase Adjust (7-bits)
Output Divider (7-bits)
To
Output
Buffer
From
Output
MUX
Registers 0 - 4
19 18 17 16 15 14 13
Figure 29. CDCE62005 Output Divider and Phase Adjust
Registers 0 - 4
Registers 0 - 4
14 13
Registers 0 - 4
17 16 15
19 18
From
Output
MUX
0 0
/2-/5
/1 - /8
/2
To
Output
Buffer
Prescaler
Integer Divider
1 0
0 1
Figure 30. CDCE62005 Output Divider Architecture
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Table23. CDCE62005 Output Divider Settings
OUTPUT DIVIDER n SETTINGSRegister n (n = 0,1,2,3,4)
Output Phase*
Output Divide Ratio
Multiplexer
Integer Divider
Prescaler
Output
Channels
0-4
OFF
1
Auxiliary
Output
OFF
4
n.19
X
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.18
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.17
n.16
X
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
n.15
n.14
X
0
0
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
n.13
X
0
0
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
n.20
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles Degree
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
1
1
0
0
0
0
1
1
OFF
0
OFF
0
–
2
3
4
5
3
4
5
3
4
5
3
4
5
4
5
5
3
4
5
2
3
4
5
4
5
–
–
0.5
0
180
2**
3**
4
4
–
0
6
–
0.5
0
180
8
–
0
5
10
6
2
21
7560
10260
12500
8640
11700
14400
9720
13140
16200
14580
18000
19800
12960
17460
21600
9540
14040
18900
23400
20340
25200
6
2
28.5
35
8
8
2
10
12
16
20
18
24
30
32
40
50
36
48
60
28
42
56
70
64
80
10
12
16
20
18
24
30
32
40
50
36
48
60
28
42
56
70
64
80
4
24
4
32.5
40
4
6
27
6
36.5
45
6
8
40.5
50
8
10
12
12
12
14
14
14
14
16
16
55
36
48.5
60
25.5
39
52.5
65
56.5
70
*These columns show that the output divider generates a unique phase lag in the output clock (relative to the clock from the output multiplexer) determined by the
divide ratio used.
**Output channel 2 or 3 determine the auxiliary output divide ratio. For example, if the auxiliary output is programmed to drive via output 2 and output 2 divider is
programmed to divide by 3, then the divide ratio for the auxiliary output will be 6.
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Digital Phase Adjust
Figure 31 provides an overview of the Digital Phase Adjust feature. The output divider includes a coarse phase
adjust that shifts the divided clock signal that drives the output buffer. Essentially, the Digital Phase Adjust timer
delays when the output divider starts dividing; thereby shifting the phase of the output clock. The phase adjust
resolution is a function of the divide function. Coarse phase adjust parameters include:
•
Number of Phase Delay Steps – the number of phase delay steps available is equal to the divide ratio
selected. For example, if a Divide by 4 is selected, then the Digital Phase Adjust can be programmed to
select when the output divider changes state based upon selecting one of the four counts on the input.
Figure 31 shows an example of divide by 16 in which there are 16 rising edges of Clock IN at which the
output divider changes state (this particular example shows the fourth edge shifting the output by one fourth
of the period of the output).
•
Phase Delay Step Size – the step size is determined by the number of phase delay steps according to the
following equations:
360 degrees
Stepsize(deg) =
OutputDivideRatio
(3)
1
fClockIN
Stepsize(sec) =
OutputDivideRatio
(4)
Clock
IN
(from Smart MUX )
Start Divider
Digital Phase Adjust (7-bits)
To Output Buffer
/1 - /80
Clock IN
Output Divider (no adjust )
Output Divider (phase adjust )
Figure 31. CDCE62005 Phase Adjust
Phase Adjust example
Given:
Output Frequency: 30.72 MHz
VCO Operating Frequency: 1966.08 MHz
Prescaler Divider Setting: 2
Output Divider Setting: 32
360
Stepsize(deg) =
=11.25° / Step
32
(5)
The tables that follow provide a list of valid register settings for the digital phase adjust blocks.
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Table 24. CDCE62005 Output Coarse Phase Adjust Settings (1)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6 (radian)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6 (radian)
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
(2π/18)
(2π/2)
2(2π/18)
3(2π/18)
4(2π/18)
5(2π/18)
6(2π/18)
7(2π/18)
8(2π/18)
9(2π/18)
10(2π/18)
11(2π/18)
12(2π/18)
13(2π/18)
14(2π/18)
15(2π/18)
16(2π/18)
17(2π/18)
0
3
4
0
(2π/3)
2(2π/3)
0
(2π/4)
2(2π/4)
3(2π/4)
0
5
6
(2π/5)
2(2π/5)
3(2π/5)
4(2π/5)
0
(2π/6)
2(2π/6)
3(2π/6)
4(2π/6)
5(2π/6)
0
20
(2π/20)
2(2π/20)
3(2π/20)
4(2π/20)
5(2π/20)
6(2π/20)
7(2π/20)
8(2π/20)
9(2π/20)
10(2π/20)
11(2π/20)
12(2π/20)
13(2π/20)
14(2π/20)
15(2π/20)
16(2π/20)
17(2π/20)
18(2π/20)
19(2π/20)
0
8
(2π/8)
2(2π/8)
3(2π/8)
4(2π/8)
5(2π/8)
6(2π/8)
7(2π/8)
0
10
(2π/10)
2(2π/10)
3(2π/10)
4(2π/10)
5(2π/10)
6(2π/10)
7(2π/10)
8(2π/10)
9(2π/10)
0
24
12
(2π/24)
(2π/12)
2(2π/12)
3(2π/12)
4(2π/12)
5(2π/12)
6(2π/12)
7(2π/12)
8(2π/12)
9(2π/12)
10(2π/12)
11(2π/12)
0
2(2π/24)
3(2π/24)
4(2π/24)
5(2π/24)
6(2π/24)
7(2π/24)
8(2π/24)
9(2π/24)
10(2π/24)
11(2π/24)
12(2π/24)
13(2π/24)
14(2π/24)
15(2π/24)
16(2π/24)
17(2π/24)
18(2π/24)
19(2π/24)
20(2π/24)
21(2π/24)
22(2π/24)
23(2π/24)
16
(2π/16)
2(2π/16)
3(2π/16)
4(2π/16)
5(2π/16)
6(2π/16)
7(2π/16)
8(2π/16)
9(2π/16)
10(2π/16)
11(2π/16)
12(2π/16)
13(2π/16)
14(2π/16)
15(2π/16)
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Table 25. CDCE62005 Output Coarse Phase Adjust Settings (2)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
n.7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
n.6 (radian)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
n.6 (radian)
28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
(2π/28)
(2π/32)
2(2π/28)
3(2π/28)
4(2π/28)
5(2π/28)
6(2π/28)
7(2π/28)
8(2π/28)
9(2π/28)
10(2π/28)
11(2π/28)
12(2π/28)
13(2π/28)
14(2π/28)
15(2π/28)
16(2π/28)
17(2π/28)
18(2π/28)
19(2π/28)
20(2π/28)
21(2π/28)
22(2π/28)
23(2π/28)
24(2π/28)
25(2π/28)
26(2π/28)
27(2π/28)
0
2(2π/32)
3(2π/32)
4(2π/32)
5(2π/32)
6(2π/32)
7(2π/32)
8(2π/32)
9(2π/32)
10(2π/32)
11(2π/32)
12(2π/32)
13(2π/32)
14(2π/32)
15(2π/32)
16(2π/32)
17(2π/32)
18(2π/32)
19(2π/32)
20(2π/32)
21(2π/32)
22(2π/32)
23(2π/32)
24(2π/32)
25(2π/32)
26(2π/32)
27(2π/32)
28(2π/32)
29(2π/32)
30(2π/32)
31(2π/32)
0
30
(2π/30)
2(2π/30)
3(2π/30)
4(2π/30)
5(2π/30)
6(2π/30)
7(2π/30)
8(2π/30)
9(2π/30)
10(2π/30)
11(2π/30)
12(2π/30)
13(2π/30)
14(2π/30)
15(2π/30)
16(2π/30)
17(2π/30)
18(2π/30)
19(2π/30)
20(2π/30)
21(2π/30)
22(2π/30)
23(2π/30)
24(2π/30)
25(2π/30)
26(2π/30)
27(2π/30)
28(2π/30)
29(2π/30)
36
(2π/36)
2(2π/36)
3(2π/36)
4(2π/36)
5(2π/36)
6(2π/36)
7(2π/36)
8(2π/36)
9(2π/36)
10(2π/36)
11(2π/36)
12(2π/36)
13(2π/36)
14(2π/36)
15(2π/36)
16(2π/36)
17(2π/36)
18(2π/36)
19(2π/36)
20(2π/36)
21(2π/36)
22(2π/36)
23(2π/36)
24(2π/36)
25(2π/36)
26(2π/36)
27(2π/36)
28(2π/36)
29(2π/36)
30(2π/36)
31(2π/36)
32(2π/36)
33(2π/36)
34(2π/36)
35(2π/36)
Copyright © 2008, Texas Instruments Incorporated
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49
Product Folder Link(s) :CDCE62005
CDCE62005
SCAS862–NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Table 26. CDCE62005 Output Coarse Phase Adjust Settings (3)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
n.6 (radian)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6 (radian)
40
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
48
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(2π/40)
(2π/48)
2(2π/40)
3(2π/40)
4(2π/40)
5(2π/40)
6(2π/40)
7(2π/40)
8(2π/40)
9(2π/40)
10(2π/40)
11(2π/40)
12(2π/40)
13(2π/40)
14(2π/40)
15(2π/40)
16(2π/40)
17(2π/40)
18(2π/40)
19(2π/40)
20(2π/40)
21(2π/40)
22(2π/40)
23(2π/40)
24(2π/40)
25(2π/40)
26(2π/40)
27(2π/40)
28(2π/40)
29(2π/40)
30(2π/40)
31(2π/40)
32(2π/40)
33(2π/40)
34(2π/40)
35(2π/40)
36(2π/40)
37(2π/40)
38(2π/40)
39(2π/40)
0
2(2π/48)
3(2π/48)
4(2π/48)
5(2π/48)
6(2π/48)
7(2π/48)
8(2π/48)
9(2π/48)
10(2π/48)
11(2π/48)
12(2π/48)
13(2π/48)
14(2π/48)
15(2π/48)
16(2π/48)
17(2π/48)
18(2π/48)
19(2π/48)
20(2π/48)
21(2π/48)
22(2π/48)
23(2π/48)
24(2π/48)
25(2π/48)
26(2π/48)
27(2π/48)
28(2π/48)
29(2π/48)
30(2π/48)
31(2π/48)
32(2π/48)
33(2π/48)
34(2π/48)
35(2π/48)
36(2π/48)
37(2π/48)
38(2π/48)
39(2π/48)
40(2π/48)
41(2π/48)
42(2π/48)
43(2π/48)
44(2π/48)
45(2π/48)
46(2π/48)
47(2π/48)
42
(2π/42)
2(2π/42)
3(2π/42)
4(2π/42)
5(2π/42)
6(2π/42)
7(2π/42)
8(2π/42)
9(2π/42)
10(2π/42)
11(2π/42)
12(2π/42)
13(2π/42)
14(2π/42)
15(2π/42)
16(2π/42)
17(2π/42)
18(2π/42)
19(2π/42)
20(2π/42)
21(2π/42)
22(2π/42)
23(2π/42)
24(2π/42)
25(2π/42)
26(2π/42)
27(2π/42)
28(2π/42)
29(2π/42)
30(2π/42)
31(2π/42)
32(2π/42)
33(2π/42)
34(2π/42)
35(2π/42)
36(2π/42)
37(2π/42)
38(2π/42)
39(2π/42)
40(2π/42)
41(2π/42)
50
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005
CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862–NOVEMBER 2008
Table 27. CDCE62005 Output Coarse Phase Adjust Settings (4)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
n.6 (radian)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6 (radian)
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
56
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(2π/50)
(2π/56)
2(2π/50)
2(2π/56)
3(2π/50)
3(2π/56)
4(2π/50)
4(2π/56)
5(2π/50)
5(2π/56)
6(2π/50)
6(2π/56)
7(2π/50)
7(2π/56)
8(2π/50)
8(2π/56)
9(2π/50)
9(2π/56)
10(2π/50)
11(2π/50)
12(2π/50)
13(2π/50)
14(2π/50)
15(2π/50)
16(2π/50)
17(2π/50)
18(2π/50)
19(2π/50)
20(2π/50)
21(2π/50)
22(2π/50)
23(2π/50)
24(2π/50)
25(2π/50)
26(2π/50)
27(2π/50)
28(2π/50)
29(2π/50)
30(2π/50)
31(2π/50)
32(2π/50)
33(2π/50)
34(2π/50)
35(2π/50)
36(2π/50)
37(2π/50)
38(2π/50)
39(2π/50)
40(2π/50)
41(2π/50)
42(2π/50)
43(2π/50)
44(2π/50)
45(2π/50)
46(2π/50)
47(2π/50)
48(2π/50)
49(2π/50)
10(2π/56)
11(2π/56)
12(2π/56)
13(2π/56)
14(2π/56)
15(2π/56)
16(2π/56)
17(2π/56)
18(2π/56)
19(2π/56)
20(2π/56)
21(2π/56)
22(2π/56)
23(2π/56)
24(2π/56)
25(2π/56)
26(2π/56)
27(2π/56)
28(2π/56)
29(2π/56)
30(2π/56)
31(2π/56)
32(2π/56)
33(2π/56)
34(2π/56)
35(2π/56)
36(2π/56)
37(2π/56)
38(2π/56)
39(2π/56)
40(2π/56)
41(2π/56)
42(2π/56)
43(2π/56)
44(2π/56)
45(2π/56)
46(2π/56)
47(2π/56)
48(2π/56)
49(2π/56)
50(2π/56)
51(2π/56)
52(2π/56)
53(2π/56)
54(2π/56)
55(2π/56)
Copyright © 2008, Texas Instruments Incorporated
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51
Product Folder Link(s) :CDCE62005
CDCE62005
SCAS862–NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Table 28. CDCE62005 Output Coarse Phase Adjust Settings (5)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
n.6 (radian)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n.7
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
n.6 (radian)
60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
(2π/60)
(2π/64)
2(2π/60)
2(2π/64)
3(2π/60)
3(2π/64)
4(2π/60)
4(2π/64)
5(2π/60)
5(2π/64)
6(2π/60)
6(2π/64)
7(2π/60)
7(2π/64)
8(2π/60)
8(2π/64)
9(2π/60)
9(2π/64)
10(2π/60)
11(2π/60)
12(2π/60)
13(2π/60)
14(2π/60)
15(2π/60)
16(2π/60)
17(2π/60)
18(2π/60)
19(2π/60)
20(2π/60)
21(2π/60)
22(2π/60)
23(2π/60)
24(2π/60)
25(2π/60)
26(2π/60)
27(2π/60)
28(2π/60)
29(2π/60)
30(2π/60)
31(2π/60)
32(2π/60)
33(2π/60)
34(2π/60)
35(2π/60)
36(2π/60)
37(2π/60)
38(2π/60)
39(2π/60)
40(2π/60)
41(2π/60)
42(2π/60)
43(2π/60)
44(2π/60)
45(2π/60)
46(2π/60)
47(2π/60)
48(2π/60)
49(2π/60)
50(2π/60)
51(2π/60)
52(2π/60)
53(2π/60)
54(2π/60)
55(2π/60)
56(2π/60)
57(2π/60)
58(2π/60)
59(2π/60)
10(2π/64)
11(2π/64)
12(2π/64)
13(2π/64)
14(2π/64)
15(2π/64)
16(2π/64)
17(2π/64)
18(2π/64)
19(2π/64)
20(2π/64)
21(2π/64)
22(2π/64)
23(2π/64)
24(2π/64)
25(2π/64)
26(2π/64)
27(2π/64)
28(2π/64)
29(2π/64)
30(2π/64)
31(2π/64)
32(2π/64)
33(2π/64)
34(2π/64)
35(2π/64)
36(2π/64)
37(2π/64)
38(2π/64)
39(2π/64)
40(2π/64)
41(2π/64)
42(2π/64)
43(2π/64)
44(2π/64)
45(2π/64)
46(2π/64)
47(2π/64)
48(2π/64)
49(2π/64)
50(2π/64)
51(2π/64)
52(2π/64)
53(2π/64)
54(2π/64)
55(2π/64)
56(2π/64)
57(2π/64)
58(2π/64)
59(2π/64)
60(2π/64)
61(2π/64)
62(2π/64)
63(2π/64)
52
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :CDCE62005
CDCE62005
www.ti.com........................................................................................................................................................................................... SCAS862–NOVEMBER 2008
Table 29. CDCE62005 Output Coarse Phase Adjust Settings (6)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
n.6 (radian)
n.12 n.11 n.10 n.9
n.8
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
n.7
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
n.6 (radian)
70
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
80
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
(2π/70)
(2π/80)
2(2π/70)
2(2π/80)
3(2π/70)
3(2π/80)
4(2π/70)
4(2π/80)
5(2π/70)
5(2π/80)
6(2π/70)
6(2π/80)
7(2π/70)
7(2π/80)
8(2π/70)
8(2π/80)
9(2π/70)
9(2π/80)
10(2π/70)
11(2π/70)
12(2π/70)
13(2π/70)
14(2π/70)
15(2π/70)
16(2π/70)
17(2π/70)
18(2π/70)
19(2π/70)
20(2π/70)
21(2π/70)
22(2π/70)
23(2π/70)
24(2π/70)
25(2π/70)
26(2π/70)
27(2π/70)
28(2π/70)
29(2π/70)
30(2π/70)
31(2π/70)
32(2π/70)
33(2π/70)
34(2π/70)
35(2π/70)
36(2π/70)
37(2π/70)
38(2π/70)
39(2π/70)
40(2π/70)
41(2π/70)
42(2π/70)
43(2π/70)
44(2π/70)
45(2π/70)
46(2π/70)
47(2π/70)
48(2π/70)
49(2π/70)
50(2π/70)
51(2π/70)
52(2π/70)
53(2π/70)
54(2π/70)
55(2π/70)
56(2π/70)
57(2π/70)
58(2π/70)
59(2π/70)
60(2π/70)
61(2π/70)
62(2π/70)
63(2π/70)
64(2π/70)
65(2π/70)
66(2π/70)
67(2π/70)
68(2π/70)
69(2π/70)
10(2π/80)
11(2π/80)
12(2π/80)
13(2π/80)
14(2π/80)
15(2π/80)
16(2π/80)
17(2π/80)
18(2π/80)
19(2π/80)
20(2π/80)
21(2π/80)
22(2π/80)
23(2π/80)
24(2π/80)
25(2π/80)
26(2π/80)
27(2π/80)
28(2π/80)
29(2π/80)
30(2π/80)
31(2π/80)
32(2π/80)
33(2π/80)
34(2π/80)
35(2π/80)
36(2π/80)
37(2π/80)
38(2π/80)
39(2π/80)
40(2π/80)
41(2π/80)
42(2π/80)
43(2π/80)
44(2π/80)
45(2π/80)
46(2π/80)
47(2π/80)
48(2π/80)
49(2π/80)
50(2π/80)
51(2π/80)
52(2π/80)
53(2π/80)
54(2π/80)
55(2π/80)
56(2π/80)
57(2π/80)
58(2π/80)
59(2π/80)
60(2π/80)
61(2π/80)
62(2π/80)
63(2π/80)
64(2π/80)
65(2π/80)
66(2π/80)
67(2π/80)
68(2π/80)
69(2π/80)
70(2π/80)
71(2π/80)
72(2π/80)
73(2π/80)
74(2π/80)
75(2π/80)
76(2π/80)
77(2π/80)
78(2π/80)
79(2π/80)
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Auxiliary Output
Figure 32 shows the auxiliary output port. Table 30 lists how the auxiliary output port is controlled. The output
buffer supports a maximum output frequency of 250 MHz and drives at LVCMOS levels. Refer to Table 23 for the
list of divider settings that establishes the output frequency.
Output Divider 2
AUX
OUT
Output Divider 3
Register 6
25
Register 6
24
Figure 32. CDCE62005 Auxiliary Output
Table 30. CDCE62005 Auxiliary Output Settings
Bit Name →
AUXFEEDSEL
AUXOUTEN
AUX OUTPUT SOURCE
Register.Bit →
6.25
X
6.24
0
1
1
OFF
0
Divider 2
Divider 3
1
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SYNTHESIZER BLOCK
Figure 33 provides an overview of the CDCE62005 synthesizer block. The Synthesizer Block provides a Phase
Locked Loop, a partially integrated programmable loop filter, and two Voltage Controlled Oscillators (VCO). The
synthesizer block generates an output clock called “SYNTH” and drives it onto the Internal Clock Distribution
Bus.
Charge Pump Current
Register 6
Loop Filter Settings
Register 7
Input Divider Settings
Register 5
19 18 17 16
7
6
5
4
3
2
1
9
0
8
15 14 13 12 11 10
21 20 19 18 17 16 15 14
20 19 18 17 16
Prescaler
Register 6
2
1
1.75 GHz –
2.356 GHz
SMART_MUX
Input Divider
/1 - /256
PFD/
CP
Prescaler
/2,/3,/4,/5
SYNTH
Feedback Divider
50 kHz –
400 kHz
/1,/2,/5,/8,/10,/16,/20
/8 - /1280
Register 6
0
VCO Select
Register 6
10
Register 6
15 14 13
9
8
7
6
5
4
3
Feedback Divider
Feedback Bypass Divider
Figure 33. CDCE62005 Synthesizer Block
Input Divider
The Input Divider divides the clock signal selected by the Smart Multiplexer (see Table 17) and presents the
divided signal to the Phase Frequency Detector / Charge Pump of the frequency synthesizer.
Table 31. CDCE62005 Input Divider Settings
INPUT DIVIDER SETTINGS
DIVIDE
RATIO
SELINDIV7
SELINDIV6
SELINDIV5
SELINDIV4
SELINDIV3
SELINDIV2
SELINDIV1
SELINDIV0
5.21
5.20
5.19
5.18
5.17
5.16
5.15
5.14
0
0
0
0
0
0
•
0
0
0
0
0
0
•
0
0
0
0
0
0
•
0
0
0
0
0
0
•
0
0
0
0
0
0
•
0
0
0
0
1
1
•
0
0
1
1
0
0
•
0
1
0
1
0
1
•
1
2
3
4
5
6
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
256
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Feedback and Feedback Bypass Divider
Table 32 shows how to configure the Feedback divider for various divide values
Table 32. CDCE62005 Feedback Divider Settings
FEEDBACK DIVIDER
DIVIDE
RATIO
SELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0
6.10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
6.9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
1
1
1
9.8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
1
6.7
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6.6
0
0
0
0
0
0
1
0
1
1
1
1
0
1
1
0
0
1
1
0
1
1
0
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
1
0
6.5
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
6.4
0
0
1
1
0
1
0
1
1
0
1
1
0
1
0
1
1
0
1
1
1
1
0
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
0
1
6.3
0
1
0
1
1
0
1
1
0
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
1
0
1
0
0
1
8
12
16
20
24
32
36
40
48
56
60
64
72
80
84
96
100
108
112
120
128
140
144
160
168
180
192
200
216
224
240
252
256
280
288
300
320
336
360
384
392
400
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Table 32. CDCE62005 Feedback Divider Settings (continued)
FEEDBACK DIVIDER
DIVIDE
RATIO
SELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0
6.10
0
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
6.9
1
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
0
0
1
0
1
1
1
1
9.8
0
1
1
0
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
6.7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6.6
1
0
1
1
0
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
6.5
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
6.4
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6.3
1
1
0
1
1
1
0
1
0
1
1
1
0
1
1
0
0
1
1
0
1
1
0
1
1
420
432
448
480
500
504
512
560
576
588
600
640
672
700
720
768
784
800
840
896
960
980
1024
1120
1280
Table 33 shows how to configure the Feedback Bypass Divider.
Table 33. CDCE62005 Feedback Bypass Divider Settings
FEEDBACK BYPASS DIVIDER
SELBPDIV2
SELBPDIV1
SELBPDIV0
DIVIDE RATIO
6.15
0
6.14
0
6.13
0
2
0
0
1
5
0
1
0
8
10
0
1
1
1
0
0
16
1
0
1
20
1
1
0
RESERVED
1(bypass)
1
1
1
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VCO Select
Table 34 illustrates how to control the dual voltage controlled oscillators.
Table 34. CDCE62005 VCO Select
VCO Select
SELVCO
VCO CHARACTERISTICS
Bit Name →
Register.Bit →
6.0
0
VCO Range
Low
Fmin (MHz)
1750
Fmax (MHz)
2046
1
High
2040
2356
Prescaler
Table 35 shows how to configure the prescaler.
Table 35. CDCE62005 Prescaler Settings
SETTINGS
SELPRESCB
SELPRESCA
DIVIDE RATIO
6.2
0
6.1
0
5
4
3
2
0
1
1
0
1
1
Charge Pump Current Settings
Table 36 provides the settings for the charge pump:
Table 36. CDCD62005 Charge Pump Settings
CHARGE PUMP SETTINGS
CHARGE PUMP
CURRENT
ICPSEL3
ICPSEL2
ICPSEL1
ICPSEL0
Bit Name →
Register.Bit →
6.19
0
6.18
0
6.17
0
6.16
0
50 µA
100 µA
150 µA
200 µA
300 µA
400 µA
600 µA
750 µA
1 mA
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1.25 mA
1.5 mA
2 mA
1
0
1
0
1
0
1
1
1
1
0
0
2.5 mA
3 mA
1
1
0
1
1
1
1
0
3.5 mA
3.75 mA
1
1
1
1
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Loop Filter
Figure 34 depicts the loop filter topology of the CDCE62005. It facilitates both internal and external
implementations providing optimal flexibility.
C2
R2
C1
EXT_LFP
EXT_LFN
internal
external
internal
external
VB
+
-
R3
PFD/
CP
C3
C1
C2
R2
Figure 34. CDCE62005 Loop Filter Topology
Internal Loop Filter Component Configuration
Figure 34 contains five different loop filter components with programmable values: C1, C2, R2, R3, and C3.
Table 37 shows that the CDCE62005 uses one of four different types of circuit implementation (shown in
Figure 35) for each of the internal loop filter components.
Table 37. CDCE62005 Loop Filter Component Implementation Type
Implementation Type
Component
Control Bits Used
(see Figure 35)
C1
C2
R2
R3
C3
5
5
5
2
4
a
a
c
d
b
Ceq
Ceq
c.3
c.2
c.1
c.0
c.4
c.3
c.2
c.1
c.0
(a)
(b)
Req
Req
r.base
r.1
r.0
r.4
r.3
r.2
r.1
r.0
(c)
(d)
Figure 35. CDCE62005 Internal Loop Filter Component Schematics
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Table 38. CDCE62005 Internal Loop Filter – C1 Settings
C1 SETTINGS
Bit Name →
EXLFSEL
LFRCSEL14
LFRCSEL13
LFRCSEL12 LFRCSEL11 LFRCSEL10
Capacitor Value →
Register.Bit →
—
6.26
1
37.5 pF
21.5 pF
10 pF
6.5 pF
1.5 pF
7.14
X
0
7.13
X
0
7.12
X
0
7.11
X
0
7.10
X
0
Capacitor Value
External Loop Filter
0 pF
0
0
0
0
0
0
1
1.5 pF
0
0
0
0
1
0
6.5 pF
0
0
0
0
1
1
8 pF
0
0
0
1
0
0
10 pF
0
0
0
1
0
1
11.5 pF
16.5 pF
18 pF
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
0
21.5 pF
23 pF
0
0
1
0
0
1
0
•
•
•
•
•
•
0
1
1
1
0
0
69 pF
0
1
1
1
0
1
70.5 pF
75.5 pF
77 pF
0
1
1
1
1
0
0
1
1
1
1
1
Table 39. CDCE62005 Internal Loop Filter – C2 Settings
C2 SETTINGS
Bit Name →1
EXLFSEL
LFRCSEL4 LFRCSEL3 LFRCSEL2 LFRCSEL1 LFRCSEL0
Capacitor Value →
Register.Bit 1→
—
6.26
1
226 pF
123 pF
87 pF
25 pF
12.5 pF
7.4
0
0
0
0
0
0
0
0
0
0
0
•
7.3
0
0
0
0
0
0
0
0
0
1
1
•
7.2
0
0
0
0
0
1
1
1
1
0
0
•
7.1
0
0
0
1
1
0
0
1
1
0
0
•
7.0
0
0
1
0
1
0
1
0
1
0
1
•
Capacitor Value
External Loop Filter
0 pF
0
0
12.5 pF
25 pF
0
0
37.5 pF
87 pF
0
0
99.5 pF
112 pF
0
0
124.5 pF
123 pF
0
0
135.5 pF
•
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
436 pF
0
448.5 pF
461 pF
0
0
473.5 pF
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Table 40. CDCE62005 Internal Loop Filter – R2 Settings
R2 SETTINGS
Bit Name →
EXLFSEL
LFRCSEL9 LFRCSEL8 LFRCSEL7 LFRCSEL6 LFRCSEL5
Resistor Value →
Register.Bit →
—
6.26
1
56.4 k
38.2 k
20 k
7.7
X
0
9 k
7.6
X
0
4 k
7.5
X
0
7.9
X
0
0
0
0
0
0
0
0
0
0
•
7.8
X
0
0
0
0
0
0
0
0
1
1
•
Resistor Value (kΩ)
External Loop Filter
0
127.6
123.6
118.6
114.6
107.6
103.6
98.6
94.6
89.4
85.4
•
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
1
0
•
•
•
0
1
1
1
1
1
1
1
1
1
0
0
13
0
1
0
1
9
0
1
1
0
4
0
1
1
1
0
Table 41. CDCE62005 Internal Loop Filter – C3 Settings
C3 SETTINGS
Bit Name →
EXLFSEL
LFRCSEL18 LFRCSEL17 LFRCSEL16 LFRCSEL15
Capacitor Value →
Register.Bit →
—
6.26
1
85 pF
19.5 pF
5.5 pF
2.5 pF
7.18
X
0
7.17
X
0
7.16
X
0
7.15
X
0
Capacitor Value
External Loop Filter
0 pF
0
0
0
0
0
1
2.5 pF
0
0
0
1
0
5.5 pF
0
0
0
1
1
8 pF
0
0
1
0
0
19.5 pF
22 pF
0
0
1
0
1
0
0
1
1
0
25 pF
0
0
1
1
1
27.5 pF
85 pF
0
1
0
0
0
0
1
0
0
1
87.5 pF
•
0
•
•
•
•
0
1
1
1
0
104.5 pF
107 pF
0
1
1
1
1
0
1
1
1
0
110 pF
0
1
1
1
1
112.5 pF
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Table 42. CDCE62005 Internal Loop Filter – R3 Settings
R3 SETTINGS
Bit Name →
EXLFSEL
LFRCSEL20
LFRCSEL19
Resistor Value →
Register.Bit →
—
6.26
1
10 k
7.20
X
5 k
7.19
X
Resistor Value (kΩ)
External Loop Filter
0
0
0
20
15
10
5
0
0
1
0
1
0
0
1
1
External Loop Filter Component Configuration
To implement an external loop filter, set EXLFSEL bit (6.26) high. Setting all of the control switches low that
control capacitors C1 and C2 (see Table 40) remove them from the loop filter circuit. This is necessary for an
external loop filter implementation.
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Lock Detect
Digital Lock Detect
The CDCE62005 provides both an analog and a digital lock detect circuit. With respect to lock detect, two signals
whose phase difference is less than a prescribed amount are ‘locked’ otherwise they are ‘unlocked’. The phase
frequency detector / charge pump compares the clock provided by the input divider and the feedback divider;
using the input divider as the phase reference. The digital lock detect circuit implements a programmable lock
detect window. Table 43 shows an overview of how to configure the digital lock detect feature. When selecting
the digital PLL lock option, the PLL_LOCK pin will possibly jitter several times between lock and out of lock until
the PLL achieves a stable lock. If desired, choosing a wide loop bandwidth and a high number of successive
clock cycles virtually eliminates this characteristic. PLL_LOCK will return to out of lock, if just one cycle is outside
the lock detect window or if a cycle slip occurs.
Lock Detect Window (Max)
From Input Divider
Locked
From Feedback Divider
Unlocked
From Input Divider
From Feedback Divider
From Input Divider
From Digital
Lock Detector
PFD/
CP
Lock Detect Window Adjust
PLL_LOCK
To Loop Filter
1 = Locked
O = Unlocked
Register 5
From Feedback Divider
27 26
25 24 23 22
(a)
(b)
(c)
Figure 36. CDCE62005 Digital Lock Detect
Table 43. CDCE62005 Digital Lock Detect Control
DIGITAL LOCK DETECT
Bit Name →
ADLOCK
LOCKDET
LOCKW(3)
LOCKW(2)
LOCKW(1)
LOCKW(0)
Register.Bit →
5.27
1
5.26
X
5.25
X
5.24
X
5.23
X
5.22
X
Lock Detect Window
Analog Lock
X
0
X
X
X
X
1 cycle in lock window triggers a lock
64 continuous cycles in lock window triggers a
lock
X
1
X
X
X
X
0
0
0
0
0
•
X
X
X
X
X
•
0
0
0
0
0
•
0
0
0
1
1
•
0
0
1
0
0
•
0
1
0
0
1
•
Narrow Window
One step wider than narrow window
Two steps wider than narrow window
Three steps wider than narrow window
Four steps wider than narrow window
•
0
0
X
X
1
X
1
X
1
1
0
1
Widest Window
Reserved
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Analog Lock Detect
Figure 37 shows the Analog Lock Detect circuit. Depending upon the phase relationship of the two signals
presented at the PFD/CP inputs, the lock detect circuit either charges (if the PLL is locked) or discharges (if PLL
is unlocked) the circuit shown via 100µA current sources. An external capacitor determines the sensitivity of the
lock detect circuit. The value of the capacitor determines the rate of change of the voltage presented on the
output pin PLL_LOCK and hence how quickly the PLL_LOCK output toggles based on a change of PLL locked
status. The PLL_LOCK pin is an analog output in analog lock detect mode.
1
Vout = ´ i´ t
C
(6)
Solving for t yields:
Vout ´C
t =
i
(7)
VH = 0.55 × VCC
VL = 0.35 × VCC
For Example, let:
C =10 nF
Vcc = 3.3 V\VH @ 1.8 V = VOut
1.8´10n
110 μ
t =
@ 164 μs
Vcc
110 uA
Locked
PLL_LOCK
5 pF
Lock_I
To Host
Unlocked
110 uA
C
80k
From Input Divider
PFD/
CP
From Feedback Divider
Figure 37. CDCE62005 Analog Lock Detect
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DEVICE POWER CALCULATION AND THERMAL MANAGEMENT
The CDCE62005 is a high performance device, therefore careful attention must be paid to device configuration
and printed circuit board layout with respect to power consumption. Table 44 provides the power consumption for
the individual blocks within the CDCE62005. To estimate total power consumption, calculate the sum of the
products of the number of blocks used and the power dissipated of each corresponding block.
Table 44. CDCE62005 Power Consumption
Internal Block (Power at 3.3V)
Input Circuit
Power Dissipated per Block
Number of Blocks per Device
18 mW
746 mW
185 mW
116 mW
76 mW
1
1
PLL and VCO Core
Output Divider
5
Output Buffer ( LVPECL)
Output Buffer (LVDS)
Output Buffer (LVCMOS)
5
5
86 mW
10
This power estimate determines the degree of thermal management required for a specific design. Employing the
thermally enhanced printed circuit board layout shown in Figure 39 insures that the thermal performance curves
shown in Figure 38 apply. Observing good thermal layout practices enables the thermal pad on the backside of
the QFN-48 package to provide a good thermal path between the die contained within the package and the
ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance
connection to the ground plane is essential.
Figure 39 shows a layout optimized for good thermal performance and a good power supply connection as well.
The 7×7 filled via patter facilitates both considerations. Finally, the recommended layout achieves θJA
=
27.3°C/W in still air and 20.3°C/W in an environment with 100 LFM airflow if implemented on a JEDEC compliant
thermal test board..
Die Temperature vs Total Device Power
RL 0 LFM 85 C
125
JEDEC 0 LFM 25 C
JEDEC 100 LFM 25 C
RL 0 LFM 25 C
JDEC 0 LFM 85 C
JEDEC 0 LFM 25 C
100
JEDEC 100 LFM 25 C
RL 0 LFM 25 C
RL 100 LFM 85 C
JEDEC 100 LFM 85 C
RL 100 LFM 25 C
75
50
25
0
RL 100 LFM 25 C
JEDEC 0 LFM 85 C
JEDEC 100 LFM 85 C
RL 0 LFM 85 C
RL 100 LFM 85 C
0
1
2
3
4
Power (W)
Figure 38. CDCE62005 Die Temperature vs Device Power
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Component Side
QFN-48
Solder Mask
Thermal Slug
(package bottom)
Internal
Ground
Plane
Internal
Power
Plane
Thermal
Dissipation
Pad (back side)
Thermal Vias
No Solder Mask
Back Side
Figure 39. CDCE62005 Recommended PCB Layout
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CDCE62005 Power Supply Bypassing – Recommended Layout
Figure 40 shows two conceptual layouts detailing recommended placement of power supply bypass capacitors. If
the capacitors are mounted on the back side, 0402 components can be employed; however, soldering to the
Thermal Dissipation Pad can be difficult. For component side mounting, use 0201 body size capacitors to
facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the
device as short as possible. Ground the other side of the capacitor using a low impedance connection to the
ground plane.
Component Side
Back Side
Figure 40. CDCE62005 Power Supply Bypassing
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APPLICATION INFORMATION AND GENERAL USAGE HINTS
Fan-out Buffer
Each output of the CDCE62005 can be configured as a fan-out buffer (divider bypassed) or fan-out buffer with
divide and skew control functionality.
PRI_IN
U0P
Divide by 1: Up to 1500 MHz
Otherwise: Up to 1175 MHz
/1 - /80
U0N
SEC_IN
Up to 5 Outputs:
LVPECL or LVDS
Up to 10 Outputs:
LVCMOS
U4P
U4N
/1 - /80
Figure 41. CDCE62005 Fan-out Buffer Mode
Clock Generator
The CDCE62005 can generate 5–10 low noise clocks from a single crystal or crystal oscillator as follows:
Feedback
XTAL/
U0P
U0N
Divider
PFD/
CP
Output
AUX_IN
Prescaler
Divider 0
Smart
MUX
Input
Divider
U4P
U4N
Output
Divider 4
Figure 42. CDCE62005 Clock Generator Mode
Jitter Cleaner – Mixed Mode (1)
The following table presents a common scenario. The CDCE62005 must generate several integer-related clocks
from a reference that has traversed a backplane. In order for jitter cleaning to take place, the phase noise of the
on-board clock path must be better than that of the incoming clock. The designer must pay attention to the
optimization of the loop bandwidth of the synthesizer and understand the phase noise profiles of the oscillators
involved. Further, other devices on the card require clocks at frequencies not related to the backplane clock. The
system requires combinations of differential and single-ended clocks in specific formats with specific phase
(1)
relationships.
CLOCK FREQUENCY
10.000 MHz
30.72 MHz
INPUT/OUTPUT
Input
FORMAT
LVDS
NUMBER
CDCE62005 PORT
COMMENT
Low end crystal oscillator
Reference from backplane
SERDES Clock
ASIC
1
1
1
1
1
2
2
SEC_IN
PRI_IN
U0
Input
LVDS
122.88 MHz
491.52 MHz
245.76 MHz
30.72 MHz
Output
LVDS
Output
LVPECL
LVPECL
LVCMOS
LVCMOS
U1
Output
U2
FPGA
Outputs
Outputs
U3
ASIC
10.000 MHz
U4
CPU, DSP
(1) Pay special attention when using the universal inputs with two different clock sources. Two clocks derived from the same source may
use the internal bias generator and internal termination network without jitter performance degradation. However, if their origin is from
different sources (e.g. two independent oscillators) then sharing the internal bias generator can degrade jitter performance significantly.
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30.72 MHz
Output
122.88 MHz
Divider 0
10.00 MHz
/1:/2:HiZ
/1:/2:HiZ
Reference
Divider
Output
491.52 MHz
245.76 MHz
Divider 1
Output
Divider 2
Input
30.72 MHz
30.72 MHz
Divider
PFD/
CP
Output
Prescaler
Feedback
Divider
Divider 3
10 MHz
10 MHz
Output
Divider 4
Figure 43. CDCE62005 Jitter Cleaner Example
Clocking ADCs with the CDCE62005
High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sample
clock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularly
implement receiver chains that take advantage of the characteristics of bandpass sampling. This implementation
trend often causes engineers working in communications system design to encounter the term clock limited
performance. Therefore, it is important to understand the impact of clock jitter on ADC performance. Equation 8
shows the relationship of data converter signal to noise ratio (SNR) to total jitter.
é
ê
ë
ù
ú
û
1
SNRjitter = 20log10
2πfin jittertotal
(8)
Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sample
clock:
2
)
jittertotal
=
jitter
2 + jitter
(
ADC ) (
CLK
(9)
With respect to an ADC with N-bits of resolution, ignoring total jitter, DNL, and input noise, the following equation
shows the relationship between resolution and SNR:
SNRADC = 6.02N+1.76
(10)
Figure 44 plots Equation 8 and Equation 10 for constant values of total jitter. When used in conjunction with most
ADCs, the CDCE62005 supports a total jitter performance value of <1 ps.
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Data Converter Jitter Requirements
140
130
120
110
100
90
26
24
22
20
18
16
14
12
10
8
100 fs
50 fs
80
70
60
50
1 ps
40
6
30
350 fs
4
20
2
10
0
0
1
10
100
1000
10000
Figure 44. Data Converter Jitter Requirements
CDCE62005 SERDES Startup Mode
A common scenario involves a host communicating to a satellite system via a high-speed wired communications
link. Typical communications media might be a cable, backplane, or fiber. The reference clock for the satellite
system is embedded in the high speed link. This reference clock must be recovered by the SERDES, however,
the recovered clock contains unacceptable levels of jitter due to a degradation of SNR associated with
transmission over the media. At system startup, the satellite system must self-configure prior to the recovery and
cleanup of the reference clock provided by the host. Furthermore, upon loss of the communication link with the
host, the satellite system must continue to operate albeit with limited functionality. Figure 45 shows a block
diagram of an optical based system with such a mechanism that takes advantage of the features of the
CDCE62005:
Data
Cleaned Clock
SERDES
ASIC
ASIC Clock
Recovered Clock
CDCE62005
Figure 45. CDCE62005 SERDES Startup Overview
The functionality provided by the Smart Multiplexer provides a straightforward implementation of a SERDES
clock link. The Auxiliary Input provides a startup clock because it connects to a crystal. The on-chip EEPROM
determines the default configuration at power-up; therefore, the CDCE62005 requires no host communication to
begin cleaning the recovered clock once it is available. The CDCE62005 immediately begins clocking the
satellite components including the SERDES using the crystal as a clock source and a frequency reference. After
the SERDES recovers the clock, the CDCE62005 removes the jitter via the on-chip synthesizer/loop filter. The
recovered clock from the communications link becomes the frequency reference for the satellite system after the
smart multiplexer automatically switches over to it. The CDCE62005 applies the cleaned clock to the recovered
clock input on the SERDES; thereby establishing a reliable communications link between host and satellite
systems.
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Cleaned Clock
Output Blocks
Synthesizer
Block
SERDES
Recovered Clock
Output
Channel
0
1
2
3
4
Start-up/
Back-up
Clock
Smart
MUX
Frequency
Synthesizer
Output
Channel
Input
Block
Output
Channel
Interface
&
To Satellite
System
Interface
&
Control
Device
Control
Block
Components
Registers
Output
Channel
Output
Channel
EEPROM
Figure 46. CDCE62005 SERDES Startup Mode
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
QFN
QFN
Drawing
CDCE62005RGZR
CDCE62005RGZT
ACTIVE
ACTIVE
RGZ
48
48
2500
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
RGZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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