CDCE421YS [TI]
Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator; 完全集成的宽电压范围，低抖动，晶体振荡器时钟发生器
| 型号： | CDCE421YS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator |
| 文件： | 总30页 (文件大小：1004K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCE421
www.ti.com
SCAS842–APRIL 2007
Fully Integrated Wide-Range, Low-Jitter, Crystal-Oscillator Clock Generator
FEATURES
•
Differential Low-Voltage Positive
Emitter-Coupled Logic (LVPECL) Output,
10.9-MHz to 1.175-GHz Frequency Range
•
Single 3.3V Supply
•
High-Performance Clock Generator
Incorporating Crystal-Oscillator Circuitry With
Integrated Frequency Synthesizer
•
Two Fully Integrated Voltage-Controlled
Oscillators (VCOs) Support Wide Output
Frequency Range
•
•
Low-Output Jitter, as Low as 380 fs (rms
Integrated Between 10 kHz–20 MHz)
•
•
Fully Integrated Programmable Loop Filter
Typical Power Consumption 240 mW in LVDS
Mode and 300 mW in LVPECL Mode
Low Phase Noise at High Frequency; at 708
MHz It Is Less Than –109 dBc/Hz at 10-kHz
and –146 dBc/Hz at 10-MHz Offset From the
Carrier
•
•
Chip-Enable Control Pin
Simple Serial Interface Allows Programming
After Manufacturing
•
•
Supports Crystal Frequencies Between
27.35 MHz to 38.33 MHz
•
Integrated On-Chip Non-Volatile Memory
(EEPROM) to Store Settings Without the Need
to Apply High Voltage to the Device
Output Frequency Ranges From 10.9 MHz up
to 766.7 MHz and From 875.2 MHz up to
1175 MHz
•
•
•
Die or QFN24 Package
•
Low-Voltage Differential Signaling (LVDS)
ESD Protection Exceeds 2 kV HBM
Industrial Temperature Range –40°C to 85°C
Output, 100-Ω Differential Off-Chip
Termination, 10.9-MHz to 400-MHz Frequency
Range
APPLICATIONS
A
A
A
•
Low-Cost, High-Frequency Crystal Oscillator
CE
SDATA
Output Enable/Programming Interface and EEPROM for Configuration Settings
Loop Filter
Crystal
Oscillator
Input
CLK
X-tal
VCO 1
VCO 2
Feedback
Divider
NCLK
B0216-01
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
CDCE421
www.ti.com
SCAS842–APRIL 2007
DESCRIPTION
The CDCE421 is a high-performance, low-phase-noise clock generator. It has two fully integrated, low-noise,
LC-based voltage controlled oscillators (VCOs) that operate in the 1.750-GHz–2.350-GHz frequency range. It
has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a
stable frequency reference for the PLL-based frequency synthesizer.
The output frequency (fout) is proportional to the frequency of the input crystal (fxtal). The prescaler divider,
feedback divider, output divider, and VCO selection are what set (fout) with respect to (fxtal). For a desired
frequency (fout), look in Table 1 and find the corresponding settings in the same row. Use Equation 1 to calculate
the exact crystal oscillator frequency needed for the desired output.
OutputDivider
FeedbackDivider
+ ǒ
Ǔ
f
f
out
xtal
(1)
Output divider(1) = 1, 2, 4, 8, 16, or 32
Feedback divider(2) = 12, 16, 20, or 32
(1)Output divider and feedback divider should be from the same row in Table 1.
(2)Feedback divider is set automatically with respect to the prescaler setting in Table 1.
A high-level block diagram of the CDCE421 is shown in Figure 1.
The CDCE421 supports one differential LVDS clock output or one differential LVPECL output.
All device settings are programmable through a Texas Instruments proprietary simple serial interface.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to 85°C.
The CDCE421 is available in die form or in a QFN-24 package.
XIN 1
Crystal
Oscillator
Loop Filter
VCO 1 VCO 2
1890 2200
XIN 2
PFD/
Charge Pump
Feedback
Divider
12, 16, 20 and 32
LVPCL
Prescaler
2, 3, 4 and 5
CE
LVDS
1-Pin
EEPROM
Interface
and
Control
Output
Divider
1, 2, 4, 8, 16 and 32
SDATA
B0217-01
Figure 1. High-Level Block Diagram of the CDCE421
In the CDCE421, the feedback divider is set automatically with respect to the prescaler setting. The product of
the prescaler and the feedback divider will be either 60 or 64, as shown in Table 1, to keep the control loop
stable.
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SCAS842–APRIL 2007
DEVICE SETUP AND CONFIGURATION
Table 1. Crystal Frequency Selection and Device Settings
REQUIRED INPUT
CRYSTAL
FREQUENCY (MHz)
DESIRED OUTPUT
FREQUENCY (MHz)
VCO
SELECTION
OUTPUT
DIVIDER
PRESCALER
SETTING
FEEDBACK
DIVIDER(1)
From
To
From
31.875
27.351
32.500
29.174
31.875
27.351
34.000
29.174
34.000
29.174
31.875
27.351
34.000
29.174
34.000
29.174
31.875
27.351
34.000
29.174
34.000
29.174
31.875
27.351
34.000
29.174
34.000
29.174
31.875
27.351
34.000
29.174
34.000
29.174
31.875
27.351
34.000
29.174
To
1020.0
1175.0
1020.0
36.719
31.875
38.333
32.500
36.719
31.875
38.333
34.000
38.333
34.000
36.719
31.875
38.333
34.000
38.333
34.000
36.719
31.875
38.333
34.000
38.333
34.000
36.719
31.875
38.333
34.000
38.333
34.000
36.719
31.875
38.333
34.000
38.333
34.000
36.719
31.875
38.333
34.000
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
VCO 2
VCO 1
1
1
2
2
3
3
4
4
5
5
3
3
4
4
5
5
3
3
4
4
5
5
3
3
4
4
5
5
3
3
4
4
5
5
3
3
4
4
5
5
32
32
20
20
16
16
12
12
20
20
16
16
12
12
20
20
16
16
12
12
20
20
16
16
12
12
20
20
16
16
12
12
20
20
16
16
12
12
(2)
875.2
650.0
(2)
766.7
650.0
1
583.5
510.0
437.6
408.0
350.1
340.0
291.7
255.0
218.8
204.0
175.0
170.0
145.9
127.5
109.4
102.0
87.5
1
587.5
510.0
460.0
408.0
383.3
340.0
293.8
255.0
230.0
204.0
191.7
170.0
146.9
127.5
115.0
102.0
95.8
1
1
1
1
2
2
2
2
2
2
4
4
4
4
4
4
85.0
8
72.9
85.0
8
63.8
73.4
8
54.7
63.8
8
51.0
57.5
8
43.8
51.0
8
42.5
47.9
16
16
16
16
16
16
32
32
32
32
32
32
36.5
42.5
31.9
36.7
27.4
31.9
25.5
28.8
21.9
25.5
21.3
24.0
18.2
21.3
15.9
18.4
13.7
15.9
12.8
14.4
10.9
12.8
(1) The feedback divider is set automatically with respect to the prescaler setting.
(2) Discontinuity in frequency range
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SCAS842–APRIL 2007
DEVICE SETUP EXAMPLE
The following example illustrates the procedure to calculate the required AT-cut crystal frequency needed to
generate a desired output frequency.
Assuming the requirement to generate an output frequency of 622.08 MHz, Table 1 shows that the desired
output frequency lies between 583.5 and 680 MHz.
REQUIRED INPUT
CRYSTAL
FREQUENCY (MHz)
DESIRED OUTPUT
FREQUENCY (MHz)
VCO
SELECTION
OUTPUT
DIVIDER
PRESCALER
SETTING
FEEDBACK
DIVIDER(1)
From
650.0
583.5
510.0
To
From
32.500
29.174
31.875
To
766.7
650.0
587.5
38.333
32.500
36.719
VCO 2
VCO 1
VCO 2
1
1
1
3
3
4
20
20
16
(1) The feedback divider is set automatically with respect to the prescaler setting.
So this means that the device must be configured with:
VCO = VCO 1
Output divider = 1
Prescaler setting = 3
To determine the right crystal frequency needed to get 622.08 MHz with these settings, substitute values into
Equation 1.
OutputDivider
FeedbackDivider
1
20
+ ǒ Ǔ
+ ǒ
Ǔ
f
f
f
622.08 + 31.154 MHz
out
xtal
xtal
(2)
The AT-cut frequency should be 31.154 MHz (between 29.174 MHz and 32.500 MHz. as shown in Table 1) .
SERIAL INTERFACE AND CONTROL
The CDCE421 uses a unique Texas Instruments proprietary interface protocol that can be configured and
programmed via a single input pin to the device. The architecture enables only writing to the device from this
input pin. Reading the content of a register can be achieved by sending a read command on the input pin and
monitoring the output pins (LVDS or LVPECL). In a case where the output pins cannot be used to read the
content, the software controlling the interface must account for what is written to the EEPROM and when it is
programmed. Monitoring the outputs verifies the programming modes, and cycling power on the device verifies
that the EEPROM is holding the proper configuration.
The CDCE421 can be configured and programmed via the SDATA input pin. For this purpose, a square-wave
programming sequence must be written to the device as described in the following section. During the EEPROM
programming phase, the device requires a stable VCC of 3.3 V ± 100 mV for secure writing of the EEPROM
cells. After each Write to WordX, the written data is latched, made effective, and offers look-ahead before the
actual data is stored into the EEPROM.
The following table summarizes all valid programming commands.
SDATA
00 1100
FUNCTION
Enter Programming Mode (State 1 → State 2); bits must be sent in the specified order with the specified timing.
Otherwise, a time-out occurs.
11 1011
Enter Register Read Back Mode; bits must be sent in the specified order with the specified timing. Otherwise, a
time-out occurs.
000 xxxx xxxx
100 xxxx xxxx
010 xxxx xxxx
110 xxxx xxxx
Write to Word0 (State 2)(1)(2)(3)
Write to Word1 (State 2)(1) (2) (3)
Write to Word2 (State 2)(1) (2) (3)
Write to Word3 (State 2)(1) (2) (3)
(1) Each rising edge causes a bit to be latched.
(2) Between the bits, some longer time delays can occur, but this has no effect on the data.
(3) A Write to WordX is expected to be 10 bits long. After the 10th bit, the respective word is latched and its effect can be observed as
look-ahead function.
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SDATA
001 xxxx xxxx
101 xxxx xxxx
111 xxxx xxxx
111 0101 0101
111 1111 0000
111 0000 0000
FUNCTION
Write to Word4 (State 2)(1) (2) (3)
Write to Word5 (State 2)(1) (2) (3)
State machine jump: All other patterns not defined as follows cause an exit to normal mode.
Jump: Enter EEPROM programming with EEPROM lock (State 2 → State 3)
Jump: Enter EEPROM programming without EEPROM lock (State 2 → State 4)
Jump: Exit EEPROM programming (State 3 or State 4 → State 1)
Power Up:
Read
EEPROM &
Configure
Write
WORD 0
Power Up Reset
Completed
th
11 Bit
Write
WORD 1
Written
SDATA =
State 1: IDLE
Normal
Operation
SDATA = 111011
SDATA =
100 xxxx xxxx
000 xxxx xxxx
th
11 Bit
Written
Write
WORD 2
SDATA =
111 1111 1111
State 5:
Read Back
Mode
SDATA =
60th Clock Applied
010 xxxx xxxx
th
11 Bit
State 2:
Programming
Mode
Written
SDATA = 001100
SDATA =
110 xxxx xxxx
th
11 Bit
Write
WORD 3
Written
SDATA =
001 xxxx xxxx
SDATA =
101 xxxx xxxx
th
11 Bit
SDATA =
111 1111 0000
SDATA =
Written
111 0101 0101
Write
WORD 4
th
11 Bit
SDATA =
111 0000 0000
Written
SDATA =
111 0000 0000
Write
WORD 5
State 3:
State 4:
Programming
EEPROM
Locking
Programming
EEPROM
No Locking
F0016-02
NOTE: In States 2, 3, 4, and 5, the signal pin CE is disregarded and has no influence on power down.
Figure 2. State Flow-Diagram of Single-Pin Interface
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Enter Programming Mode
Figure 3 shows the timing behavior of data to be written into SDATA. The sequence shown is 00 1100. If the
high period is as short as t1, this is interpreted as 0. If the high period is as long as t3, this is interpreted as a 1.
This behavior is achieved by shifting the incoming signal SDATA by time t5 into signal SDATA_DELAYED. As
can be seen in Figure 3, SDATA_DELAYED can be used to latch (or strobe) SDATA. The timing specifications
for t1–t7, tr, and tf are shown in Figure 3.
t7
CE
t6
t2
t4
tr
t1
tf
t3
SDATA
t5
SDATA
DELAYED
DATA
0
0
1
1
0
0
T0042-05
MIN
TYP
70
MAX
UNIT
kHz
ms
ms
ms
ms
ms
ms
µs
fSDATACLK
Repeat frequency of programming
LOW signal: high-pulse duration
60
80
t1
t2
t2
t3
t4
t4
t6
0.2 t
0.8 t
0.8 t
0.8 t
0.2 t
0.2 t
LOW signal: low-pulse duration while entering programming sequence
LOW signal: low-pulse duration while programming bits
HIGH signal: high-pulse duration
HIGH signal: low-pulse duration while entering programming sequence
HIGH signal: low-pulse duration while programming bits
Time-out during Entering Programming Mode and Enter Read Back Mode
16
3 t
until next bit must turn on
t7
CE-high time before first SDATA can be clocked in
Rise Time and Fall Time
ms
ns
tr and tf
2
t = 1 / fSDATACLK
Figure 3. SDATA/CE Timing
EEPROM PROGRAMMING
Load all the registers in RAM by writing Word0 through Word5, and after going back to State 2, then going to
State 3 (programming EEPROM, no locking) or State 4 (programming EEPROM with locking), the contents of
Word0–Word5 are saved in the EEPROM. Wait 10 ms in State 3 or State 4 when programming the EEPROM
before moving to State 2 (the idle state).
NOTE:
When writing to the device for functionality testing and verification via the serial bus,
only the RAM is being accessed.
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SCAS842–APRIL 2007
EXAMPLE: Programming Cycle of Six Words and Programming Into EEPROM
The following sequence shows how to enter programming mode and how the different words can be written. The
addressing of Word0 … Word5 is shown in bold. After the word address, the payload for the respective word is
clocked in. In this example, this is followed by a jump from State 2 → State 3 into enter EEPROM programming
with EEPROM lock. In the EEPROM-programming state, it is necessary to wait at least 10 ms for safe
programming. The last command is a jump from State 3 into State 1 (normal operation). Cycle power and verify
that the device functions as programmed.
Enter Programming Sequence
Word0
Payload
After 8 bits, the payload
data is transferred to
the RAM and is active.
Word1
Payload
·
·
·
·
·
·
Word5
Payload
Wait for at least
10 ms before
exiting EEPROM
write phase, for
safe operation.
State
Machine
Jump
State 2 ® State 3
State
Machine
Jump
State 3 ® State 1
T0043-03
Figure 4. Programming Cycle of Six Words and Programming Into EEPROM
Enter Register Readback Mode and Related Timing Diagram
Similar to the enter programming mode sequence, the enter register read back mode is written into SDATA.
After the command has been issued, the SDATA input is reconfigured as clock input. By applying one clock, the
EEPROM content is read into shift registers. Now, by further applying clocks at SDATA, the EEPROM content
can be clocked out and observed at OUTP/OUTN. There are 59 bits to be clocked out. With the 61st rising clock
edge, the OUTP/OUTN pins are reconfigured back into normal operation.
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SDATA
FOUT
1
1
1
0
1
1
Output Oscillation
Output Oscillation
0
1
2
56
57
58
60th Falling Edge
Switches Back Into
Normal Operation
Enter Register
Read-Back Mode
Fetch
EEPROM
Content With
1st CLK
EEPROM Content
1st Bit Available After
1st Falling Edge
T0044-03
In the following table, the content of the output bit stream is summarized. Important to notice: bit 0 is clocked out
first.
OUTPUT BIT STREAM
Bits[0:2]
FUNCTION
Revision identifier (MSB first)
VCO calibration word
Bits[3:8]
Bit[9]
EEPROM status:
0 = EEPROM has never been written
1 = EEPROM has been programmed before
Bit[10]
EEPROM lock:
0 = EEPROM can be rewritten
1 = EEPROM is locked, rewriting to the EEPROM is not possible any more
Bits[11:18]
Bits[19:26]
Bits[27:34]
Bits[35:42]
Bits[43:50]
Bits[51:58]
Storage value, Word5 (MSB first)
Storage value, Word4 (MSB first)
Storage value, Word3 (MSB first)
Storage value, Word2 (MSB first)
Storage value, Word1 (MSB first)
Storage value, Word0 (MSB first)
REGISTER DESCRIPTION
Word 0:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
RECOMMENDED
VALUE
0
1
C0
C1
C2
Register selection
Register selection
Register selection
W
W
W
W
W
W
W
W
W
W
W
0
0
2
0
3
SELVCO
SELPRESC
SELPRESC
OUTSEL
OUTSEL
OUTSEL
DRVSEL
ILFSEL
VCO select, 0 = VCO1, 1 = VCO2
Prescaler setting, bit 0
User
User
User
User
User
User
User
0
4
5
Prescaler setting, bit 1
6
Output divider select, bit 0
Output divider select, bit1
Output divider select, bit 2
Driver select, 0 = LVDS, 1 = PECL
Loop filter bias select
7
8
9
10
4
Divide by value (SELPRESC 1, SELPRESC 0)
Divide by 5 = (00), 3 = (01), 4 = (10), 2 = (11)
5
6
7
8
Output divider (OUTSEL2, OUTSEL1, OUTSEL0)
Divide by 1 = (000), 2 = (001), 4 = (010), 8 = (011), 16 = (100), 32 = (101)
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Word 1:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
RECOMMENDED
VALUE
0
1
C0
C1
C2
Register selection
Register selection
Register selection
W
W
W
W
W
W
W
W
W
W
W
1
0
0
1
1
1
1
1
0
1
0
2
3
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
Loop filter control settings, bit 0
Loop filter control settings, bit 1
Loop filter control settings, bit 2
Loop filter control settings, bit 3
Loop filter control settings, bit 4
Loop filter control settings, bit 5
Loop filter control settings, bit 6
Loop filter control settings, bit 7
4
5
6
7
8
9
10
Word 2:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
RECOMMENDED
VALUE
0
1
C0
Register selection
W
W
W
W
W
W
W
W
W
W
W
0
1
0
1
1
0
0
0
0
0
0
C1
Register selection
2
C2
Register selection
3
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
LFRCSEL
Loop filter control settings, bit 8
Loop filter control settings, bit 9
Loop filter control settings, bit 10
Loop filter control settings, bit 11
Loop filter control settings, bit 12
Loop filter control settings, bit 13
Loop filter control settings, bit 14
Loop filter control settings, bit 15
4
5
6
7
8
9
10
Word 3:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
RECOMMENDED
VALUE
0
1
C0
Register selection
W
W
W
W
W
W
W
W
W
W
W
1
1
0
0
0
0
1
1
1
1
0
C1
Register selection
2
C2
Register selection
3
LFRCSEL
LFRCSEL
LFRCSEL
ICPSEL
ICPSEL
ICPSEL
ICPSEL
Not Used
Loop filter control settings, bit 16
Loop filter control settings, bit 17
Loop filter control settings, bit 18
Charge pump current sel, bit 0
Charge pump current sel, bit 1
Charge pump current sel, bit 2
Charge pump current sel, bit 3
4
5
6
7
8
9
10
9
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Word 4:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
RECOMMENDED
VALUE
0
1
C0
Register selection
Register selection
Register selection
W
W
W
W
W
W
W
W
W
W
W
0
0
1
0
0
0
0
0
0
0
1
C1
2
C2
3
CALWRD
CALWRD
CALWRD
CALWRD
CALWRD
CALWRD
CALOVR
ENCAL
VCO calibration word, bit 0
VCO calibration word, bit 1
VCO calibration word, bit 2
VCO calibration word, bit 3
VCO calibration word, bit 4
VCO calibration word, bit 5
VCO calibration override
Enable VCO calibration
4
5
6
7
8
9
10
Word 5:
BIT
NAME
DESCRIPTION/FUNCTION
TYPE
RECOMMENDED
VALUE
0
1
C0
Register selection
Register selection
Register selection
TI test use, bit 0
TI test use, bit 1
TI test use, bit 2
TI test use, bit 3
W
W
W
W
W
W
W
W
W
W
W
1
0
1
0
0
0
0
0
0
0
0
C1
2
C2
3
TITSTCFG
TITSTCFG
TITSTCFG
TITSTCFG
Not used
Not used
Not used
Not used
4
5
6
7
8
9
10
10
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PACKAGE (DIE)
The CDCE421 is available in die form or in a QFN 24-pin package. The die version pad locations and numbers
are shown in Figure 5.
10
9
8 7
vcc
GND
11
12
13
SIGNALS
TI TEST ONLY
14
15
16
17
6
5
4
3
PAD1
2
M0070-01
Figure 5. Pinout of the CDCE421 Die
PAD DESCRIPTION
Table 2 shows the pin description for the CDCE421 die.
Table 2. Pad Description of CDCE421 (See Appendix B for More Information)
TERMINAL
NAME
ESD
Protection
PAD NO.
TYPE
Description
CE
1
O
Y
Chip enable
CE = 1: enable the device and the outputs.
CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z; in
LVPECL mode, LVPECLP = LVPECLN = Hi-Z.
OUTN
OUTP
3
6
2
O
O
I
Y
Y
Y
High-speed negative differential LVPECL or LVDS outputs. (Outputs are enabled
by CE and selected by the EEPROM configuration registers.)
High-speed positive differential LVPECL or LVDS outputs. (Outputs are enabled by
CE and selected by the EEPROM configuration registers.)
SDATA
Programming pin using TI proprietary interface protocol
Do not connect (TI Manufacturing test pins).
Test pins
7, 8, 11–13,
16, 17
VCC
9, 10
4, 5
14
Power
Y
Y
Y
N
3.3-V power supply
VSS
GND
Ground
XIN 1
XIN 2
I
I
Connect XIN1 to one end of the crystal and XIN2 to the other end of the crystal.
15
11
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PACKAGE (QFN24)
The CDCE421 is also packaged in a QFN 24-pin package. The QFN package footprint is shown. Pad locations
and numbers are shown in Figure 6.
RGE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
18
17
16
15
14
13
CE
NC
NC
VCC
VCC
NC
SDATA
NC
CDCE421
NC
NC
NC
NC
P0024-05
Figure 6. Pinout of the CDCE421 QFN-24 Package
PIN DESCRIPTION
Table 3 shows the pin description for the CDCE421 QFN-24 Package.
Table 3. Pinout Description of CDCE421
TERMINAL
NAME
TERMINAL
NO.
ESD
Protection
TYPE
Description
CE
1
I
Y
Chip enable
CE = 1: enable the device and the outputs.
CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z;
in LVPECL mode, LVPECLP = LVPECLN = Hi-Z.
GND
8, 9
GND
Y
Ground
No connect
2, 4–6,
11–15,
Do not connect these pins. Leave them floating.
18–20, 23,24
OUTN
OUTP
7
O
O
Y
Y
High-speed negative differential LVPECL or LVDS outputs. (Outputs are
enabled by CE and selected by the EEPROM configuration registers.)
10
High-speed positive differential LVPECL or LVDS outputs. (Outputs are
enabled by CE and selected by the EEPROM configuration registers.)
SDATA
VCC
3
16, 17
21
I
Y
Y
Y
N
Programming pin using TI proprietary interface protocol
3.3-V power supply
Power
I
XIN 1
XIN 2
In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the
other end of the crystal. In LVCMOS input single-ended driven mode, XIN1
(pin 21) acts as input reference and XIN2 should connect to GND.
22
GND
12
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OUTPUTS (LVPECL OR LVDS)
The CDCE421 device has two sets of output drivers, LVPECL and LVDS, where the outputs are wire-ORed
together. Only one output can be selected at a time; the other goes to the high-impedance state (Hi-Z).
If the device is configured for an LVPECL, the output buffers go to Hi-Z and the termination resistors determine
the state of the output (LVPECLP = LVPECLN = Hi-Z) in the device disable mode (CE = L). If the device is
configured in LVDS mode, the outputs go to Hi-Z if the device is disabled (CE = L).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.5 to 4.6
–0.5 to VCC + 0.5
–50
UNIT
V
VCC
VI
Supply voltage(2)
Voltage range for all other input pins(2)
V
IO
Output current for LVPECL
mA
kV
°C
°C
°C
Electrostatic discharge (HBM)
Characterized free-air temperature range (no airflow)
Maximum junction temperature
Storage temperature range
2
TA
–40 to 85
125
TJ
Tstg
–65 to 150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
3
TYP
MAX
3.6
UNIT
V
VCC
TA
Supply voltage
3.3
Ambient temperature (no airflow, no heat sink)
–40
85
°C
ELECTRICAL CHARACTERISTICS
recommended operating conditions for CDCE421 device
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.6
UNIT
V
VCC
Supply voltage
Total current
3
3.3
73
91
IVCC(LVDS)
LVDS mode, 3.3 V, 366 MHz
LVPECL mode, 3.3 V, 366 MHz
93
mA
mA
IVCC(LVPECL) Total current consumption
110
LVDS OUTPUT MODE (see Figure 10)
fCLK
Output frequency
10.9
240
400
454
50
MHz
mV
mV
V
|VOD
|
LDVS differential output voltage
LVDS VOD magnitude change
Offset voltage
RL = 100 Ω
400
1.1
∆VOD
VOS
∆VOS
tr
–40°C to 85°C
0.84
1.39
25
VOS magnitude change
Output rise time
mV
ps
20% to 80% of VOUTpp
80% to 20% of VOUTpp
Short Vout+ to ground
Short Vout– to ground
170
170
tf
Output fall time
ps
–20
20
mA
mA
IOS
Duty cycle of the output waveform
46%
50%
53%
13
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ELECTRICAL CHARACTERISTICS (continued)
recommended operating conditions for CDCE421 device
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVPECL OUTPUT MODE (see Figure 11)
fCLK
VOH
VOL
|VOD
tr
Output frequency
10.9
VCC – 1.2
VCC – 2.17
407
1175
VCC – 0.81
VCC – 1.36
1076
MHz
V
LVPECL high-level output voltage
LVPECL low-level output voltage
LVPECL differential output voltage
Output rise time
V
|
mV
ps
20% to 80% of VOUTpp
80% to 20% of VOUTpp
170
170
tf
Output fall time
ps
Duty cycle of the output waveform
Duty cycle exception
45%
43%
55%
57%
630 MHz to 650 MHz
LVCMOS INPUT
VIL,CMOS
VIH,CMOS
IL,CMOS
Low-level CMOS input voltage
VCC = 3.3 V
0.3 VCC
V
V
High-level CMOS input voltage
Low- level CMOS input current
High-level CMOS input current
VCC = 3.3 V
0.7 VCC
VCC = VCC max, VIL = 0 V
VCC = VCC min, VIH = 3.7 V
–200
200
µA
µA
IH,CMOS
14
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JITTER CHARACTERISTICS IN INPUT CLOCK MODE
The jitter characterization test is performed using an LVCMOS input signal driving a CDCE421 device packaged
in the QFN-24 package.
0.1 mF
Phase Noise
Analyzer
XIN 1
CDCE421
50 W
XIN 2
100 pF
150 W
150 W
150 W
S0246-01
Figure 7. Jitter Test Configuration for an LVTTL Input Driving the CDCE421
Table 4. Measured Output Jitter
LVPECL (Typical Measured Output
Jitter), ps
LVDS (Typical Measured Output
Jitter), ps
Output
Input
JRMS (12
kHz to 20
MHz)
Dj (Deter-
ministic
Jitter)
JRMS (12
kHz to 20
MHz)
Dj (Deter-
ministic
Jitter)
Pre-
scaler
Tj (Total
Jitter)
Tj (Total
Jitter)
Frequency Frequency VCO
(MHz)
Divider
(MHz)
33.3333
35.4167
31.25
100
1
2
1
1
2
1
1
1
1
2
1
5
5
4
3
5
4
3
5
5
3
2
4
4
4
4
2
2
2
1
1
1
1
0.507
0.53
35.33
30.39
47.47
31.54
33.96
36.98
29.82
29.6
11.54
11
0.552
0.564
0.561
0.482
0.523
0.525
0.45
41.86
35.38
74.14
42.31
58.45
87.5
21.4
106.25
16.01
53.51
23.33
37.84
67.35
47.49
51.2
125
156.25
212.5
250
0.529
0.472
0.512
0.42
25.2
31.25
9.12
35.4167
31.25
13.78
18.52
11
312.5
370
31.25
0.378
0.369
0.377
0.438
0.456
66.44
69.77
69.75
30.8333
33.3333
35.4
12.05
11.48
14.84
19.66
0.439
0.501
400
28.1
51.87
708
31.65
40.34
1000
31.25
15
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For the case of a CDCE421 being referenced by an external and cleaner LVCMOS input of 35.42 MHz, Figure 8
shows the SSB phase noise plot of the output at 708 MHz from 100 Hz to 40 MHz from the carrier. Note the
dependence of output jitter on the input reference jitter. See Figure 13 for test setup.
0
−20
−40
−60
−80
−100
−120
−140
−160
10
100
1k
10k
100k
1M
10M
100M
f − Single-Sideband Frequency − Hz
G001
Figure 8. Phase Noise Plot for LVPECL Output at 708 MHz
Table 5. Phase Noise Parameters With LVCMOS Input of 35.4 MHz and LVPECL Output at 708 MHz
Phase noise specifications under following assumptions: input frequency f = 35.42 MHz (VCO = 2, prescaler = 3, output divider =
1), fout = 708 MHz (driver mode = LVPECL)
PARAMETER
MIN
TYP
–95
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
–105
–109
–114
–126
–146
–146
438
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
RMS jitter integrated from 12 kHz to 20 MHz
16
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SCAS842–APRIL 2007
For the case of CDCE421 being referenced by a clean external LVCMOS input of 33.33 MHz, Figure 9 shows
the SSB phase noise plot of the output at 400 MHz from 100 Hz to 40 MHz from carrier. See Figure 12 for test
setup.
0
−20
−40
−60
−80
−100
−120
−140
−160
10
100
1k
10k
100k
1M
10M
100M
f − Single-Sideband Frequency − Hz
G002
Figure 9. Phase Noise Plot for LVDS Output at 400 MHz
Table 6. Phase Noise Parameters With LVCMOS Input of 33.33 MHz and LVDS Output at 400 MHz
Phase noise specifications under following assumptions: input frequency f = 33.33 MHz (VCO = 1, prescaler = 5, output divider =
1), fout = 400 MHz (driver mode = LVDS)
PARAMETER
MIN
TYP
–99
MAX
UNIT
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
phn100
phn1k
Phase noise at 100 Hz
Phase noise at 1 kHz
Phase noise at 10 kHz
Phase noise at 100 kHz
Phase noise at 1 MHz
Phase noise at 10 MHz
Phase noise at 20 MHz
–107
–115
–119
–128
–144
–145
501
phn10k
phn100k
phn1M
phn10M
phn20M
JRMS
RMS jitter integrated from 12 kHz to 20 MHz
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SCAS842–APRIL 2007
APPENDIX A: TEST CONFIGURATIONS
Test setups are used to characterize the CDCE421 device in ac and dc terminations. The following figures
illustrate all four setups used to terminate the clock signal driven by the device under test.
LVDS
100 W
LVDS
S0248-01
Figure 10. LVDS DC Termination Test Configuration
LVPECL
LVPECL
50 W
50 W
VCC – 2V
S0249-01
Figure 11. LVPECL DC Termination Test Configuration
Phase Noise
Analyzer
LVDS
50 W
S0250-01
Figure 12. LVDS AC Termination Test Configuration
Phase Noise
Analyzer
LVPECL
150 W
150 W
50 W
S0251-01
Figure 13. LVPECL AC Termination Test Configuration
18
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SCAS842–APRIL 2007
APPENDIX B: PACKAGE
Packaging and bond wiring the CDCE421 is the responsibility of the oscillator vendor.
Scribe (8~52 mm)
10
9
8 7
Scribe (8~52 mm)
11
12
13
Pad Legend
#1 = CE
#2 = SDATA
#3 = OUTN
#4 = GND
#5 = GND
#6 = OUTP
#7 = NC
#8 = TEST
#9 = VCC
#10 = VCC
#11 = TEST
#12 = TEST
#13 = TEST
#14 = XIN 1
14
15
16
1732 mm
17
6
5
4
3
PAD1
2
#15 = XIN 2 (XIN 2 for XO)
#16 = NC
#17 = TEST
2032 mm
M0071-01
PAD
1
X1
Y1
X2
Y2
41.85
198.65
48.65
111.85
1060.07
1988.35
1987.93
1992.2
1987.86
784.86
665.74
462.97
268.04
111.9
268.65
118.65
307.28
425.14
526.66
643.58
1689.99
1690.25
1691.07
1690.76
1539.91
1380.51
1224.46
1063.15
951.73
841.71
687.6
2
990.07
1918.35
1917.93
1922.2
1917.86
714.86
595.74
392.97
198.04
41.9
3
237.28
355.14
456.66
573.58
1619.99
1620.25
1621.07
1620.76
1469.91
1310.51
1154.46
993.15
881.73
771.71
617.6
4
5
6
7
8
9
10
11
12
13
14
15
16
17
42.19
112.19
112.35
111.97
112.84
111.87
111.87
42.35
41.97
42.84
41.87
41.87
The CDCE421 is designed to be mounted in a commonly used 6-pin oscillator package, where pin 2 (N/C) is the
programming pin, in conjunction with CE for the XO design.
19
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PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
CDCE421RGER
CDCE421RGERG4
CDCE421RGET
CDCE421RGETG4
CDCE421YS
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGE
24
24
24
24
0
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
RGE
RGE
RGE
YS
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
XCEPT
30635 Green (RoHS &
no Sb/Br)
Call TI
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
MLA
MLA
Reel
Diameter Width
(mm)
Reel
A0 (mm)
4.3
B0 (mm)
4.3
K0 (mm)
1.5
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
CDCE421RGER
CDCE421RGET
RGE
RGE
24
24
330
12
12
12
12 PKGORN
T2TR-MS
P
180
12
4.3
4.3
1.5
12 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
CDCE421RGER
CDCE421RGET
RGE
RGE
24
24
MLA
MLA
346.0
190.0
346.0
212.7
29.0
31.75
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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