TC7129CPL [TELCOM]
4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS; 4-1 / 2位ANALOG -TO -DIGITAL具有片上LCD驱动器转换器
| 型号： | TC7129CPL |
| 厂家： | 
TELCOM SEMICONDUCTOR, INC |
| 描述： | 4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS |
| 文件： | 总15页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3
TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
WITH ON-CHIP LCD DRIVERS
FEATURES
GENERAL DESCRIPTION
■ Count Resolution......................................... ±19,999
■ Resolution on 200 mV Scale.......................... 10 µV
■ True Differential Input and Reference
■ Low Power Consumption ...................500 µA at 9V
■ Direct LCD Driver for 4-1/2 Digits, Decimal Points,
Low-Battery Indicator, and Continuity Indicator
■ Overrange and Underrange Outputs
■ Range Select Input ............................................ 10:1
■ High Common-Mode Rejection Ratio ......... 110 dB
■ External Phase Compensation Not Required
The TC7129 is a 4-1/2 digit analog-to-digital converter
(ADC) that directly drives a multiplexed liquid crystal dis-
play (LCD). Fabricated in high-performance, low-power
CMOS, the TC7129 ADC is designed specifically for high-
resolution, battery-powered digital multimeter applications.
The traditional dual-slope method of A/D conversion has
been enhanced with a successive integration technique to
produce readings accurate to better than 0.005% of full
scale, and resolution down to 10 µV per count.
The TC7129 includes features important to multimeter
applications. It detects and indicates low-battery condition.
Acontinuityoutputdrivesanannunciatoronthedisplay, and
can be used with an external driver to sound an audible
alarm. Overrange and underrange outputs and a range-
change input provide the ability to create auto-ranging
instruments. For snapshot readings, the TC7129 includes a
latch-and-hold input to freeze the present reading. This
combination of features makes the TC7129 the ideal
choice for full-featured multimeter and digital measurement
applications.
ORDERING INFORMATION
Pin
Layout
Temperature
Range
Part No.
Package
TC7129CKW
TC7129CLW
TC7129CPL
Formed
—
44-Pin PQFP
44-Pin PLCC
40-Pin PDIP
0°C to +70°C
0°C to +70°C
0°C to +70°C
Normal
TYPICAL OPERATING CIRCUIT
LOW BATTERY
CONTINUITY
+
V
5 pF
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
120 kHz
TC7129
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
330 kΩ
*
0.1 µF
10 pF
0.1
+
µF
20
0.1 µF
1 µF
150 kΩ
kΩ
TC04
+
V
10 kΩ
+
100 kΩ
9V
+
–
V
IN
NOTE:
RC network between pins 26 and 28 is not required.
*
TC7129-5 10/18/96
TELCOM SEMICONDUCTOR, INC.
3-231
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
Storage Temperature Range ................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V+ to V–)............................................15V
Reference Voltage (REF HI or REF LO) .............. V+ to V–
Input Voltage (IN HI or IN LO) (Note 1) ................ V+ to V–
VDISP ................................................V+ to (DGND – 0.3V)
Digital Input, Pins
Notes: Input voltages may exceed supply voltages, provided input current
is limited to ±400 µA. Currents above this value may result in invalid display
readings but will not destroy the device if limited to ±1 mA.
Dissipation ratings assume device is mounted with all leads soldered to
printed circuit board.
1, 2, 19, 20, 21, 22, 27, 37, 39, 40.......... DGND to V+
Analog Input, Pins 25, 29, 30 ............................... V+ to V–
Package Power Dissipation (TA ≤ 70°C)
Plastic DIP ........................................................1.23W
PLCC ................................................................1.23W
Plastic QFP.......................................................1.00W
Operating Temperature Range .................... 0°C to +70°C
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS: V+ to V– = 9V, VREF = 1V, TA = +25°C, fCLK = 120 kHz, unless otherwise
indicated. Pin numbers refer to 40-pin DIP.
Symbol
Input
Parameter
Test Conditions
Min
Typ
Max Unit
Zero Input Reading
Zero Reading Drift
VIN = 0V, 200 mV Scale
– 0000 0000
+0000 Counts
VIN = 0V, 0°C < TA < +70°C
VIN = VREF = 1000 mV, Range = 2V
—
±0.5
—
µV/°C
Ratiometric Reading
Range Change Accuracy
9997
9999
10000 Counts
VIN = 0.1V on Low Range
0.9999 1.0000 1.0001 Ratio
ϬVIN = 1V on High Range
RE
Roll-Over Error
–VIN = +VIN = 199 mV
200 mV Scale
—
—
—
1
1
2
Counts
Counts
dB
NL
Linearity Error
—
—
CMRR
CMVR
Common-Mode Rejection Ratio
Common-Mode Voltage Range
VCM = 1V, VIN = 0V, 200 mV Scale
110
VIN = 0V
200 mV Scale
—
—
(V–) +1.5
—
—
V
V
(V+) –1
eN
IIN
Noise (Peak-to-Peak Value Not
Exceeded 95% of Time)
VIN = 0V
200 mV Scale
—
14
—
µVP-P
Input Leakage Current
VIN = 0V, Pins 32, 33
—
—
1
2
10
7
pA
Scale Factor Temperature
Coefficient
VIN = 199 mV, 0°C < TA < +70°C
ppm/°C
External VREF = 0 ppm/°C
Power
VCOM
Common Voltage
V+ to Pin 28
2.8
3.2
3.5
V
Common Sink Current
Common Source Current
∆Common = +0.1V
∆Common = –0.1V
—
—
0.6
10
—
—
mA
µA
DGND
Digital Ground Voltage
Sink Current
V+ to Pin 36, V+ to V– = 9V
∆DGND = +0.5V
V+ to V–
4.5
—
6
5.3
1.2
9
5.8
—
V
mA
V
Supply Voltage Range
Supply Current Excluding Common Current
Clock Frequency
12
IS
V+ to V– = 9V
—
—
—
6.3
0.8
120
50
1.3
360
—
mA
kHz
kΩ
V
fCLK
VDISP Resistance
VDISP to V+
V+ to V–
Low-Battery Flag Activation Voltage
7.2
7.7
Digital
Continuity Comparator
Threshold Voltages
VOUT Pin 27 = High
VOUT Pin 27 = Low
100
—
200
200
—
400
mV
mV
Pull-Down Current
Pins 37, 38, 39
—
2
10
µA
3-232
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3
TC7129
ELECTRICAL CHARACTERISTICS: V+ to V– = 9V, VREF = 1V, TA = +25°C, fCLK = 120 kHz, unless otherwise
indicated. Pin numbers refer to 40-pin DIP.
Symbol
Parameter
Test Conditions
Min
Typ
Max Unit
"Weak Output" Current
Sink/Source
Pins 20, 21 Sink/Source
Pin 27 Sink/Source
—
—
3/3
3/9
—
—
µA
µA
Pin 22 Source Current
Pin 22 Sink Current
—
—
40
3
—
—
µA
µA
PIN CONFIGURATIONS
40-Pin PDIP
OSC
OSC
40 OSC
2
1
2
1
39 DP
1
3
ANNUNICATOR DRIVE
B , C , CONT
38 DP
2
3
37
4
RANGE
1
1
A , G , D
5
36 DGND
1
1
1
1
F , E , DP
6
REF LO
REF HI
IN HI
35
34
33
32
1
1
B , C , LO BATT
7
2
2
A , G , D
8
2
2
2
F , E , DP
9
IN LO
2
2
2
31 BUFF
–
10
11
12
13
14
15
16
17
18
19
20
B , C MINUS
3
3,
TC7129CPL
DISPLAY
OUTPUT
LINES
A , G , D
C
C
30
29
28
3
3
3
3
5
4
4
REF
+
REF
F , E , DP
3
3
B , C BC
4,
COM
4
A , G , D
27 CONT
4
4
F , E , DP
26 INT OUT
4
4
25 INT IN
+
BP
BP
BP
3
2
1
24
23
22
V
V
–
V
LATCH/HOLD
DISP
DP /OR
21 DP /UR
3
4
44-Pin QFP
44-Pin PLCC
6
5
4
3
2
1
44 43 42 41 40
44 43 42 41 40 39 38 37 36 35 34
F , E , DP
F , E , DP
1
REF LO
39
33
32
31
30
29
28
27
26
25
24
23
7
1
2
3
4
REF LO
REF HI
1
1
1
1
1
8
38 REF HI
IN HI
B , C , BATT
B , C , BATT
2 2
A , G , D
2 2 2
2
2
A , G , D
9
37
36 IN LO
IN HI
IN LO
BUFF
NC
2
2
2
F , E , DP
F , E , DP
2 2 2
10
11
12
13
14
15
16
17
2
2
2
B , C MINUS
B , C MINUS
3,
35
34
33
32
31
30
29
BUFF
NC
–
REF
5
6
3
3,
3
NC
NC
TC7129CKW
TC7129CLW
–
REF
A , G , D
A , G , D
3 3
C
C
7
3
3
3
3
+
REF
+
REF
F , E , DP
F , E , DP
3 3
C
8
C
3
3
3
3
B , C BC
B , C BC
9
COM
COM
4
4,
5
4
4,
5
A , G , D
A , G , D
CONT
INT OUT
10
11
CONT
INT OUT
4
4
4
4
4
4
F , E , DP
F , E , DP
4 4
4
4
4
4
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
TELCOM SEMICONDUCTOR, INC.
3-233
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
PIN DESCRIPTIONS
Pin No.
40-Pin
TC7129CPL
Pin No.
Pin No.
44-Pin
TC7129CLW Symbol
44-Pin
TC7129CKW
Function
1
2
40
41
2
3
OSC1
OSC3
Input to first clock inverter.
Output of second clock inverter.
Backplane square-wave output for driving annunciators.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Backplane #3 output to display.
Backplane #2 output to display.
Backplane #1 output to display.
Negative rail for display drivers.
3
ANNUNCIATOR
B1, C1, CONT
A1, G1, D1
F1, E1, DP1
B2, C2, LO BATT
A2, G2, D2
F2, E2, DP2
B3, C3, MINUS
A3, G3, D3
F3, E3, DP3
B4, C4, BC5
A4, D4, G4
F4, E4, DP4
BP3
4
43
44
1
5
5
6
6
7
7
2
8
8
3
9
9
4
10
11
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
5
7
8
9
10
11
12
13
14
15
16
BP2
BP1
VDISP
DP4/OR
Input: When HI, turns on most significant decimal point.
Output: Pulled HI when result count exceeds ±19,999.
21
22
18
19
24
25
DP3/UR
Input: Second most significant decimal point on when HI.
Output: Pulled HI when result count is less than ±1000.
LATCH/HOLD
Input: When floating, ADC operates in the free-run mode.
When pulled HI, the last displayed reading is held. When
pulled LO, the result counter contents aren shown
inincrementing during the deintegrate phase of cycle.
Output: Negative-going edge occurs when the data latches
are updated. Can be used for converter status signal.
23
24
20
26
27
V–
V+
Negative power supply terminal.
Positive power supply terminal and positive rail for display
drivers.
25
26
27
21
23
24
28
29
30
INT IN
INT OUT
Input to integrator amplifier.
Output of integrator amplifier.
CONTINUITY
Input: When LO, continuity flag on the display is OFF.
When HI, continuity flag is ON.
Output: HI when voltage between inputs is less than +200
mV. LO when voltage between inputs is more than +200
mV.
28
25
31
COMMON
C+REF
Sets common-mode voltage of 3.2V below V+ for DE,
10X, etc. Can be used as preregulator for external
reference.
29
30
31
32
33
26
27
29
30
31
32
33
35
36
37
Positive side of external reference capacitor.
Negative side of external reference capacitor.
Output of buffer amplifier.
–
CREF
BUFFER
IN LO
Negative input voltage terminal.
IN HI
Positive input voltage terminal.
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TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3
TC7129
PIN DESCRIPTIONS
Pin No.
40-Pin
TC7129CPL
Pin No.
44-Pin
TC7129CKW
Pin No.
44-Pin
TC7129CLW
Symbol
Function
34
35
36
32
33
34
38
39
40
REF HI
REF LO
DGND
Positive reference voltage in
Negative reference voltage
Internal ground reference for digital section. See "±5V Power
Supply" paragraph.
37
35
41
RANGE
3 µA pull-down for 200 mV scale. Pulled HI externally for 2V
scale.
38
39
40
36
37
38
42
43
44
DP2
DP1
Internal 3 µA pull-down. When HI, decimal point 2 will be on.
Internal 3 µA pull-down. When HI, decimal point 1 will be on.
Output of first clock inverter. Input of second clock inverter.
OSC2
6,17, 28, 39
12, 23, 34,1
NC
No Connection
COMPONENT SELECTION
(All pin designations refer to 40-Pin Dip)
The TC7129 is designed to be the heart of a high-
resolution analog measurement instrument. The only addi-
tional components required are a few passive elements, a
voltage reference, an LCD, and a power source. Most
componentvaluesarenotcritical;substitutescanbechosen
based on the information given below.
The basic circuit for a digital multimeter application is
shown in Figure 1. See "Special Applications" for variations.
Typicalvaluesforeachcomponentareshown. Thesections
below give component selection criteria.
The resistor and capacitor values are not critical; those
shown work for most applications. In some situations, the
capacitorvaluesmayhavetobeadjustedtocompensatefor
parasitic capacitance in the circuit. The capacitors can be
low-cost ceramic devices.
SomeapplicationscanuseasimpleRCnetworkinstead
of a crystal oscillator. The RC oscillator has more potential
for jitter, especially in the least significant digit. See "RC
Oscillator."
Integrating Resistor (RINT
)
Oscillator (XOSC, CO1, CO2, RO)
The integrating resistor sets the charging current for
the integrating capacitor. Choose a value that provides a
current between 5 µA and 20 µA at 2V, the maximum full-
scale input. The typical value chosen gives a charging
current of 13.3 µA:
The primary criterion for selecting the crystal oscillator
is to chose a frequency that achieves maximum rejection of
line-frequency noise. To do this, the integration phase
should last an integral number of line cycles. The integration
phase of the TC7129 is 10,000 clock cycles on the 200 mV
range and 1000 clock cycles on the 2V range. One clock
cycleisequaltotwooscillatorcycles.For60Hzrejection,the
oscillator frequency should be chosen so that the period of
one line cycle equals the integration time for the 2V range:
2V
ICHARGE
=
13.3 µA
150 kΩ
Too high a value for RINT increases the sensitivity to
noise pickup and increases errors due to leakage current.
Too low a value degrades the linearity of the integration,
leading to inaccurate readings.
1/60 second = 16.7 msec =
1000 clock cycles 2 osc cycles/clock cycle
*
,
oscillator frequency
giving an oscillator frequency of 120 kHz. A similar calcula-
tion gives an optimum frequency of 100 kHz for 50 Hz
rejection.
TELCOM SEMICONDUCTOR, INC.
3-235
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
LOW BATTERY
CONTINUITY
+
V
C
5 pF
O1
20
9
8
7
6
5
4
3
2
1
19 18 17 16 15 14 13 12 11 10
DISPLAY DRIVE OUTPUTS
TC7129
120
kHz
CRYSTAL
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
330 kΩ
R
O
10 pF
C
0.1
µF
INT
C
O2
+
R
D
C
0.1
µF
REF
20
kΩ
REF
REF
1 µf
C
+
RF
0.1 µF
V
150 kΩ
TC04
C
IF
R
INT
10 kΩ
+
R
R
IF
100 kΩ
BIAS
9V
–
+
V
IN
Figure 1. Standard Circuit
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4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3
TC7129
Integrating Capacitor (CINT
)
Voltage Reference (DREF, RREF, RBIAS, CRF)
The charge stored in the integrating capacitor during
the integrate phase is directly proportional to the input
voltage. The primary selection criterion for CINT is to choose
a value that gives the highest voltage swing while remain-
ing within the high-linearity portion of the integrator output
range. An integrator swing of 2V is the recommended
value. The capacitor value can be calculated from the
equation:
A TC04 band-gap reference provides a high-stability
voltage reference of 1.25V. The reference potentiometer
(RREF) provides an adjustment for adjusting the reference
voltage; any value above 20 kΩ is adequate. The bias
resistor (RBIAS) limits the current through DREF to less than
150 µA. The reference filter capacitor (CRF) forms an RC
filter with RBIAS to help eliminate noise.
Input filter (RIF, CIF)
tINT x IINT
CINT
=
,
For added stability, an RC input noise filter is usually
included in the circuit. The input filter resistor value should
not exceed 100 kΩ. A typical RC time constant value is
16.7msec to help reject line-frequency noise. The input filter
capacitor should have low leakage for a high-impedance
input.
VSWING
where tINT is the integration time.
Using the values derived above (assuming 60 Hz
operation), the equation becomes:
Battery
16.7msec x 13.3 µA
CINT
=
= 0.1 µF.
2V
The typical circuit uses a 9V battery as a power source.
Any value between 6V and 12V can be used. For operation
from batteries with voltages lower than 6V and for operation
from power supplies, see "Powering the TC7129."
The capacitor should have low dielectric absorption to
ensure good integration linearity. Polypropylene and Teflon
capacitors are usually suitable. A good measurement of the
dielectric absorption is to connect the reference capacitor
across the inputs by connecting:
SPECIAL APPLICATIONS
The TC7129 as a Replacement Part
Pin to Pin
20 → 33 (CREF+ to IN HI)
30 → 32 (CREF– to IN LO)
The TC7129 is a direct pin-for-pin replacement part for
the ICL7129. Note, however, that part requires a capacitor
and resistor between pins 26 and 28 for phase compensa-
tion. Since the TC7129 uses internal phase compensation,
these parts are not required and, in fact, must be removed
from the circuit for stable operation.
A reading between 10,000 and 9998 is acceptable;
anything lower indicates unacceptably high dielectric ab-
sorption.
Reference Capacitor (CREF
)
Powering the TC7129
The reference capacitor stores the reference voltage
during several phases of the measurement cycle. Low
leakageistheprimaryselectioncriterionforthiscomponent.
The value must be high enough to offset the effect of stray
capacitance at the capacitor terminals. A value of at least
1 µF is recommended.
While the most common power source for the TC7129
is a 9V battery, there are other possibilities. Some of the
more common ones are explained below.
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4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
±5V Power Supply
Measurements are made with respect to power supply
ground. DGND (pin 36) is set internally to about 5V less than
V+ (pin 24); it is not intended as a power supply input and
must not be tied directly to power supply ground. (It can be
used as a reference for external logic, as explained in
"Connecting to External Logic." (See Figure 2.)
24
+
V
34
REF HI
TC04
36
DGND
+
3.8V
TO
6V
35
28
REF LO
COM
+5V
TC7129
+
33
32
IN HI
V
IN
8
24
IN LO
+
–
V
2
–
V
34
REF HI
0.1 µF
+
23
TC04
10 µF
4
5
35
TC7660
3
REF LO
36
DGND
28
COM
0.1 µF
10 µF
33
+
+
IN HI
V
TC7129
IN LO
IN
–
32
Figure 3. Powering the TC7129 From a Low-Voltage Battery
0.1 µF
–
V
23
+
5V
–5V
Figure 2. Powering the TC7129 From a ±5V Power Supply
24
+
Low-Voltage Battery Source
V
34
0.1 µF
TC04
Abatterywithvoltagebetween3.8Vand6Vcanbeused
to power the TC7129 when used with a voltage-doubler
circuit as shown in Figure 3. The voltage doubler uses the
TC7660 DC-to-DC voltage converter and two external ca-
pacitors.
35
28
36
DGND
0.1 µF
+
33
32
+5V Power Supply
TC7129
V
IN
8
+
Measurements are made with respect to power supply
ground. COMMON(pin28)isconnectedtoREFLO(pin35).
A voltage doubler is needed, since the supply voltage is less
than the 6V minimum needed by the TC7129. DGND (pin
36) must be isolated from power supply ground.
(See Figure 4.)
–
V
–
2
V
23
+
10 µF
4
5
TC7660
GND
3
10 µF
Connecting to External Logic
+
External logic can be directly referenced to DGND (pin
36), provided that the supply current of the external logic
doesnotexceedthesinkcurrentofDGND(Figure5). Asafe
value for DGND sink current is 1.2 mA. If the sink current is
expected to exceed this value, a buffer is recommended.
(See Figure 6.)
Figure 4. Powering the TC7129 From a +5V Power Supply
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3
TC7129
+
+
V
V
24
24
EXTERNAL
LOGIC
EXTERNAL
LOGIC
TC7129
36
TC7129
DGND
–
+
36
I
LOGIC
DGND
I
LOGIC
23
23
–
–
V
V
Figure 5. External Logic Referenced Directly to DGND
Figure 6. External Logic Referenced to DGND With Buffer
Temperature Compensation
adjusted to give temperature compensation of about 10
mV/°C between V+ (pin 24) and VDISP. The diode between
DGND and VDISP should have a low turn-ON voltage be-
cause VDISP cannot exceed 0.3V below DGND.
For most applications, VDISP (pin 19) can be connected
directly to DGND (pin 36). For applications with a wide
temperature range, some LCDs require that the drive levels
vary with temperature to maintain good viewing angle and
display contrast. Figure 7 shows two circuits that can be
+
+
V
V
1N4148
39 kΩ
39 kΩ
24
24
200 kΩ
20 kΩ
2N2222
TC7129
–
TC7129
19
19
36
V
DISP
V
+
DISP
5 kΩ
36
DGND
DGND
75 kΩ
18 kΩ
23
23
–
–
V
V
Figure 7. Temperature Compensating Circuits
TELCOM SEMICONDUCTOR, INC.
3-239
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
measurement of the time to ramp the integrated voltage to
zero, and is therefore proportional to the input voltage being
measured. This count can then be scaled and displayed as
a measurement of the input voltage. Figure 9 shows the
phases of the dual-slope conversion.
The dual-slope method has a fundamental limitation.
The count can only stop on a clock cycle, so that measure-
ment accuracy is limited to the clock frequency. In addition,
a delay in the zero-crossing comparator can add to the
inaccuracy. Figure 10 shows these errors in an actual
measurement.
RC Oscillator
For applications in which 3-1/2 digit (100 µV) resolution
is sufficient, an RC oscillator is adequate. A recommended
value for the capacitor is 51 pF. Other values can be used as
long as they are sufficiently larger than the circuit parasitic
capacitance. The resistor value is calculated from:
0.45
R =
freq
C
*
For 120 kHz frequency and C = 51 pF, the calculated
value of R is 75 kΩ. The RC oscillator and the crystal
oscillator circuits are shown in Figure 8.
DEINTEGRATE
INTEGRATE
Measuring Techniques
Two important techniques are used in the TC7129:
successive integration and digital auto-zeroing. Successive
integration is a refinement to the traditional dual-slope
conversion technique.
ZERO
CROSSING
Dual-Slope Conversion
TIME
A dual-slope conversion has two basic phases: inte-
grate and deintegrate. During the integrate phase, the input
signal is integrated for a fixed period of time; the integrated
voltage level is thus proportional to the input voltage. During
the deintegrate phase, the integrated voltage is ramped
down at a fixed slope, and a counter counts the clock cycles
until the integrator voltage crosses zero. The count is a
Figure 9. Dual-Slope Conversion
Successive Integration
The successive integration technique picks up where
dual-slope conversion ends. The overshoot voltage shown
in Figure 10, called the "integrator residue voltage," is
measuredtoobtainacorrectiontotheinitialcount. Figure11
shows the cycles in a successive integration measurement.
The waveform shown is for a negative input signal. The
sequence of events during the measurement cycle is:
Phase
Description
TC7129
1
40
2
INT1
Input signal is integrated for fixed time. (1000 clock
cycles on 2V scale, 10,000 on 200 mV)
270 kΩ
DE1
Integrator voltage is ramped to zero. Counter counts
up until zero crossing to produce reading accurate
to 3-1/2 digits. Residue represents an overshoot of
the actual input voltage.
5 pF
10 pF
120 kHz
+
+
V
V
REST
X10
Rest; circuit settles.
Residue voltage is amplified 10 times and inverted.
DE2
Integrator voltage is ramped to zero. Counter counts
down until zero crossing to correct reading to 4-1/2
digits. Residue represents an undershoot of the
actual input voltage.
TC7129
1
40
2
REST
X10
Rest; circuit settles.
75 kΩ
Residue voltage is amplified 10 times and inverted.
51 pF
DE3
Integrator voltage is ramped to zero. Counter counts
up until zero crossing to correct reading to 5-1/2
digits. Residue is discarded.
Figure 8. Oscillator Circuits
3-240
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3
TC7129
DEINTEGRATE
INTEGRATE
OVERSHOOT DUE TO ZERO CROSSING
BETWEEN CLOCK PULSES
TIME
INTEGRATOR RESIDUE VOLTAGE
OVERSHOOT CAUSED BY
COMPARATOR DELAY OF
1 CLOCK PULSE
CLOCK PULSES
Figure 10. Accuracy Errors in Dual-Slope Conversion
ZERO
INTEGRATE
AND LATCH
INT
1
INTEGRATE
DE
1
DEINTEGRATE
REST X10
DE
REST X10
DE
ZERO INTEGRATE
2
3
TC7129
NOTE: Shaded area greatly expanded
in time and amplitude.
INTEGRATOR
Figure 11. Integrator Waveform
RESIDUAL VOLTAGE
Digital Auto-Zeroing
Inside the TC7129
To eliminate the effect of amplifier offset errors, the
TC7129 uses a digital auto-zeroing technique. After the
input voltage is measured as described above, the mea-
surement is repeated with the inputs shorted internally. The
reading with inputs shorted is a measurement of the internal
errors and is subtracted from the previous reading to obtain
a corrected measurement. Digital auto-zeroing eliminates
theneedforanexternalauto-zeroingcapacitorusedinother
ADCs.
Figure 12 shows a simplified block diagram of the
TC7129.
Integrator Section
Theintegratorsectionincludestheintegrator, compara-
tor, input buffer amplifier, and analog switches used to
change the circuit configuration during the separate mea-
surement phases described earlier.
TELCOM SEMICONDUCTOR, INC.
3-241
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
LOW BATTERY
CONTINUITY
BACKPLANE
DRIVES
SEGMENT DRIVES
ANNUNCIATOR
DRIVE
OSC
1
2
3
V
LATCH, DECODE DISPLAY MULTIPLEXER
DISP
OSC
OSC
UP/DOWN RESULTS COUNTER
SEQUENCE COUNTER/DECODER
CONTROL LOGIC
RANGE
DP
1
2
DP
L/H
CONT
UR/DP
3
OR/DP
4
+
V
ANALOG SECTION
–
V
REF HI
DGND
REF LO
INT OUT
INT IN
TC7129
BUFF
COMMON
IN IN
HI LO
Figure 12. Functional Block Diagram
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TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3
TC7129
C
C
R
REF
INT
INT
REF HI
REF LO
DE
DE
INTE-
GRATOR
X10
–
+
10
pF
COMPARATOR 1
INT
1
–
IN HI
+
–
TO DIGITAL
SECTION
BUFFER
DE–
DE+
DE+
DE–
+
100 pF
COMPARATOR 2
ZI, X10
COMMON
IN LO
INT
REST
INT INT
1,
2
–
+
500 kΩ
+
–
TC7129
V
CONTINUITY
COMPARATOR
200 mV
CONTINUITY
TO DISPLAY DRIVER
Figure 13. Integrator Block Diagram
Table I. Switch Legends
Label
Meaning
DE
Open during all deintegrate phases.
DE–
Closed during all deintegrate phases when input
voltage is negative.
–
+
DE+
INT1
INT2
Closed during all deintegrate phases when input
voltage is positive.
IN HI
COM
BUFFER
Closed during the first integrate phase
(measurement of the input voltage).
Closed during the second integrate phase
(measurement of the amplifier offset).
INT
REST
ZI
Open during both integrate phases.
Closed during the rest phase.
TC7129
Closed during the zero-integrate phase.
Closed during the X10 phase.
Open during the X10 phase.
X10
X10
IN LO
CONT
–
+
500 kΩ
200 mV
V
TO DISPLAY
DRIVER
(NOT LATCHED)
The buffer amplifier has a common-mode input voltage
range from 1.5V above V– to 1V below V+. The integrator
amplifier can swing to within 0.3V of the rails, although for
best linearity the swing is usually limited to within 1V. Both
amplifiers can supply up to 80 µA of output current, but
should be limited to 20 µA for good linearity.
Figure 14. Continuity Indicator Circuit
CONTINUITY output (pin 27) will be pulled HIGH, activating
the continuity annunciator on the display. The continuity
pin can also be used as an input to drive the continuity
annunciator directly from an external source. A schematic
of the input/output nature of this pin is shown in Figure 15.
Continuity Indicator
A comparator with a 200 mV threshold is connected
between IN HI (pin 33) and IN LO (pin 32). Whenever the
voltage between inputs is less than 200 mV, the
TELCOM SEMICONDUCTOR, INC.
3-243
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
TC7129
Sequence and Results Counter
A sequence counter and associated control logic pro-
vide signals that operate the analog switches in the integra-
tor section. The comparator output from the integrator gates
the results counter. The results counter is a six-section up/
down decade counter which holds the intermediate results
from each successive integration.
TC7129
Ϸ500 kΩ
DP /OR, PIN 20
4
DP /UR, PIN 21
3
LATCH/HOLD PIN 22
CONTINUITY, PIN 27
Overrange and Underrange Outputs
When the results counter holds a value greater than
±19,999, the DP4/OR output (pin 20) is driven HIGH. When
the results counter value is less than ±1000, the DP3/UR
output (pin 21) is driven HIGH. Both signals are valid on the
falling edge of LATCH/HOLD (L/H) and do not change until
the end of the next conversion cycle. The signals are
updated at the end of each conversion unless the L/H input
(pin 22) is held HIGH. Pins 20 and 21 can also be used as
inputs for external control of decimal points 3 and 4. Figure
15 shows a schematic of the input/output nature of these
pins.
Figure 15. Input/Output Pin Schematic
Common and Digital Ground
The common and digital ground (DGND) outputs are
generated from internal zener diodes. The voltage between
V+ and DGND is the internal supply voltage for the digital
section of the TC7129. Common can source approximately
12 µA; DGND has essentially no source capability.
Latch/Hold
Low Battery
The L/H output goes LOW during the last 100 cycles of
eachconversion.Thispulselatchestheconversiondatainto
the display driver section of the TC7129. This pin can also
be used as an input. When driven HIGH, the display will not
be updated; the previous reading is displayed. When driven
LOW, the display reading is not latched; the sequence
counter reading will be displayed. Since the counter is
counting much faster than the backplanes are being up-
dated, the reading shown in this mode is somewhat erratic.
The low battery annunciator turns on when supply
voltage between V+ and V– drops below 6.8V. The internal
zener has a threshold of 6.3V. When the supply voltage
drops below 6.8V, the transistor tied to V– turns OFF, pulling
the "Low Battery" point HIGH. (See Figure 16.)
24
3.2V
28
+
V
12 µA
Display Driver
COM
The TC7129 drives a triplexed LCD with three back-
planes. The LCD can include decimal points, polarity sign,
and annunciators for continuity and low battery. Figure 17
shows the assignment of the display segments to the
backplanes and segment drive lines. The backplane drive
frequency is obtained by dividing the oscillator frequency by
1200. This results in a backplane drive frequency of 100 Hz
for 60 Hz operation (120 kHz crystal) and 83.3 Hz for 50 Hz
operation (100 kHz crystal).
Backplane waveforms are shown in Figure 18. These
appearonoutputsBP1, BP2, BP3 (pins16, 17, and18). They
remain the same regardless of the segments being driven.
Other display output lines (pins 4 through 15) have
waveforms that vary depending on the displayed values.
Figure 19 shows a set of waveforms for the A, G, D outputs
(pins 5, 8, 11, and 14) for several combinations of "ON"
segments.
–
+
N
5V
LOGIC
SECTION
36
23
DGND
P
N
TC7129
–
V
Figure 16. Digital Ground (DGND) and Common Outputs
3-244
TELCOM SEMICONDUCTOR, INC.
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
3
TC7129
LOW BATTERY
CONTINUITY
BP
BP
1
2
BACKPLANE
CONNECTIONS
BP
3
LOW BATTERY
CONTINUITY
F
E
DP
D
B
C
CONTINUITY
4, 4,
4
4
4
3
3
1, 1,
A
G
A
G
D
1
4, 4,
1, 1,
B
C
BC
F
E
DP
4, 4,
1, 1,
1
F
E
DP
D
B
C
LOW BATTERY
3, 3,
2, 2,
A
G
A
G
D
2
DP
2
3, 3,
2, 2,
B
C
MINUS
F
E
3, 3,
2, 2,
Figure 17. Display Segment Assignments
V
DD
V
b SEGMENT
LINE
H
BP
1
V
L
ALL OFF
V
DISP
V
DD
V
a SEGMENT
ON
H
BP
BP
2
3
d, g OFF
V
L
V
DISP
V
DD
V
a, g ON
d OFF
H
V
L
V
DISP
V
DD
Figure 18. Backplane Waveforms
V
H
ALL ON
The ANNUNCIATOR DRIVE output (pin 3) is a square-
waverunningatthebackplanefrequency(100Hzor83.3 Hz),
with a peak-to-peak voltage equal to DGND voltage. Con-
necting an annunciator to pin 3 turns it ON; connecting it to
its backplane turns it OFF.
V
L
V
DISP
Figure 19. Typical Display Output Waveforms
TELCOM SEMICONDUCTOR, INC.
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