TC7135C/KW [MICROCHIP]
1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQFP44, 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MQFP-44;
| 型号： | TC7135C/KW |
| 厂家： | 
MICROCHIP |
| 描述： | 1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQFP44, 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MQFP-44 转换器 |
| 文件： | 总24页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC7135
4-1/2 Digit A/D Converter
Features
General Description
• Low Rollover Error: ±1 Count Max
• Nonlinearity Error: ±1 Count Max
• Reading for 0V Input
The TC7135 4-1/2 digit A/D Converter (ADC) offers
50 ppm (1 part in 20,000) resolution with a maximum
nonlinearity error of 1 count. An auto-zero cycle
reduces zero error to below 10 µV and zero drift to
0.5 µV/°C. Source impedance errors are minimized by
a 10 pA maximum input current. Rollover error is
limited to ±1 count.
• True Polarity Indication at Zero for Null Detection
• Multiplexed BCD Data Output
• TTL-Compatible Outputs
• Differential Input
Microprocessor-based measurement systems are
supported by the BUSY, STROBE and RUN/HOLD
control signals. Remote data acquisition systems with
data transfer via UARTs are also possible. The addi-
tional control pins and multiplexed BCD outputs make
the TC7135 the ideal converter for display or
microprocessor-based measurement systems.
• Control Signals Permit Interface to UARTs and
Microprocessors
• Blinking Display Visually Indicates Overrange
Condition
• Low Input Current: 1 pA
• Low Zero Reading Drift: 2 µV/°C
• Auto-Ranging Supported with Overrange and
Underrange Signals
• Available in PDIP and Surface-Mount Packages
Applications
• Precision Analog Signal Processor
• Precision Sensor Interface
• High Accuracy DC Measurements
Functional Block Diagram
5V
TC7135
Set VREF = 1V
1
2
3
4
VREF IN
V–
28
UNDERRANGE
100 kΩ
REF IN
27
OVERRANGE
ANALOG
COMMON
26
25
24
23
22
21
20
19
18
STROBE
RUN/HOLD
DIGTAL GND
POLARITY
CLOCK IN
BUSY
Analog GND
INT OUT
1 µF
0.47 µF
5
6
AZ IN
BUFF OUT
100 kΩ
Clock Input
120 kHz
7
8
9
CREF
CREF
–
+
Signal
Input
1 µF
100 kΩ
–INPUT
(LSD) D1
D2
0.1 µF
10
11
12
13
14
+INPUT
V+
D3
+
5V
17
16
15
D5 (MSD)
D4
B1 (LSB)
B2
(MSB) B8
B4
2004 Microchip Technology Inc.
DS21460C-page 1
TC7135
Package Types
28-Pin PLCC
44-Pin MQFP
4
3
2
1 28 27 26
AZ IN
BUFF OUT
REF CAP–
REF CAP+
–INPUT
5
6
7
8
9
25
RUN/HOLD
33 32 31 30 29 28 27 26 25 24 23
24 DIGTAL GND
NC
34
22 NC
23
22
21
20
19
POLARITY
CLOCK IN
BUSY
NC 35
STROBE 36
OVERRANGE 37
UNDERRANGE 38
V– 39
NC
D3
D4
B8
B4
21
20
19
18
17
TC7135
+INPUT 10
D1 (LSD)
D2
11
V+
12 13 14 15 16 17 18
TC7135
REF IN 40
16 B2
15 B1
COMMON ANALOG 41
NC 42
14
13
D5
NC 43
NC
NC 44
12 NC
4
6
9
11
10
1
3
8
2
5
7
28-Pin PDIP
64-Pin MQFP
UNDERRANGE
28
V–
1
2
REF IN
27 OVERRANGE
ANALOG
COM
26
25
24
STROBE
3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
l
RUN/HOLD
DIGiTAL GND
INT OUT
4
1
2
48
47
46
45
NC
NC
NC
D3
NC
AZ IN
5
NC
BUFF OUT
6
23 POLARITY
3
NC
CREF
–
+
CLOCK IN
BUSY
22
21
20
19
7
TC7135
4
NC
CREF
8
5
44 D4
NC
9
D1 (LSD)
D2
–INPUT
+INPUT
V+
6
43
42
41
40
39
38
37
36
35
34
33
NC
B8
B4
B2
NC
10
11
12
13
7
OVERRANGE
18 D3
17 D4
TC7135
8
UNDERRANGE
(MSD) D5
(LSB) B1
9
NC
16
15
B8 (MSB)
B4
10
11
12
13
14
15
16
V–
B1
B2 14
D5
NC
NC
NC
NC
NC
REF IN
ANALOG COM
NC
NC
NC
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTE: NC = No internal connection.
DS21460C-page 2
2004 Microchip Technology Inc.
TC7135
† Notice: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the
device at these or any other conditions above those indicated
in the operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
1.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings†
Positive Supply Voltage.....................................................+6V
Negative Supply Voltage...................................................- 9V
Analog Input Voltage (Pin 9 or 10) ...............V+ to V- (Note 2)
Reference Input Voltage (Pin 2)................................. V+ to V-
Clock Input Voltage ................................................... 0V to V+
Operating Temperature Range ..........................0°C to +70°C
Storage Temperature Range........................–65°C to +150°C
Package Power Dissipation; (T ≤ 70°C)
A
28-Pin PDIP .......................................................... 1.14Ω
28-Pin PLCC......................................................... 1.00Ω
44-Pin MQFP..........................................................................
64-Pin MQFP ........................................................ 1.14Ω
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T = +25°C, F
= 120 kHz, V+ = +5V, V- = -5V.
A
CLOCK
(see Functional Block Diagram).
Parameters
Sym
Min.
Typ.
Max.
Units
Conditions
Analog
Display Reading with Zero Volt
Input
-0.0000 ±0.0000 +0.0000 Display Reading Note 2, Note 3
Zero Reading Temperature
Coefficient
TC
—
—
0.5
—
2
5
µV/°C
V
= 0V, (Note 4)
Z
IN
Full Scale Temperature
Coefficient
TC
ppm/°C
V
= 2V,
FS
IN
(Note 4, Note 5)
Nonlinearity Error
NL
—
—
0.5
1
Count
LSB
Note 6
Differential Linearity Error
DNL
0.01
—
Note 6
Display Reading in Ratiometric
Operation
+0.9996 +0.9999 +1.0000 Display Reading
V
= V
(Note 2)
REF,
IN
± Full Scale Symmetry Error
(Rollover Error)
±FSE
—
0.5
1
Count
-V = +V (Note 7)
IN
IN,
Input Leakage Current
Noise
I
—
—
1
10
—
pA
Note 3
IN
e
15
µV
Peak-to-Peak Value not
Exceeded 95% of Time
N
P-P
Digital
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage;
I
—
—
10
0.08
0.2
100
10
0.4
5
µA
V
V
= 0V
IL
IN
IN
I
µA
V
= +5V
IH
V
—
I
I
I
= 1.6 mA
= 1 mA
= 10 µA
OL
OL
OH
OH
V
2.4
4.9
4.4
V
OH
B , B , B , B , D D
1 – 5
4.99
5
V
1
2
4
8
Busy, Polarity, Overrange,
Underrange, Strobe
Clock Frequency
F
0
200
1200
kHz
Note 8
CLK
Note 1: Limit input current to under 100 µA if input voltages exceed supply voltage.
2: Full-scale voltage = 2V
3:
V
= 0V
IN
4: 30°C ≤ T ≤ +70°C
A
5: External reference temperature coefficient less than 0.01 ppm/°C.
6: -2V ≤ V ≤ +2V. Error of reading from best fit straight line.
IN
7: IV | = 1.9959
IN
8: Specification related to clock frequency range over which the TC7135 correctly performs its various functions.
Increased errors result at higher operating frequencies.
2004 Microchip Technology Inc.
DS21460C-page 3
TC7135
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, T = +25°C, F
= 120 kHz, V+ = +5V, V- = -5V.
A
CLOCK
(see Functional Block Diagram).
Parameters
Power Supply
Sym
Min.
Typ.
Max.
Units
Conditions
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
V+
V-
I+
4
5
-5
6
-8
3
V
V
-3
—
—
—
1
mA
mA
mW
F
F
F
= 0 Hz
CLK
CLK
CLK
I-
0.7
8.5
3
= 0 Hz
= 0 Hz
PD
30
Note 1: Limit input current to under 100 µA if input voltages exceed supply voltage.
2: Full-scale voltage = 2V
3:
V
= 0V
IN
4: 30°C ≤ T ≤ +70°C
A
5: External reference temperature coefficient less than 0.01 ppm/°C.
6: -2V ≤ V ≤ +2V. Error of reading from best fit straight line.
IN
7: IV | = 1.9959
IN
8: Specification related to clock frequency range over which the TC7135 correctly performs its various functions.
Increased errors result at higher operating frequencies.
DS21460C-page 4
2004 Microchip Technology Inc.
TC7135
2.0
PIN DESCRIPTIONS
The description of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
28-Pin PDIP,
28-Pin PLCC
Pin Number
44-Pin MQFP* 64-Pin MQFP*
Pin Number
Symbol
Description
1
2
3
4
5
6
39
40
41
2
10
11
12
18
20
22
V–
Negative power supply input.
External reference input.
REF IN
ANALOG COMMON Reference point for REF IN.
INT OUT
AZ IN
Integrator output. Integrator capacitor connection.
Auto-zero inpt. Auto-zero capacitor connection.
3
4
BUFF OUT
Analog input buffer output. Integrator resistor
connection.
7
8
5
6
23
26
C
C
–
+
Reference capacitor input. Reference capacitor
negative connection.
REF
Reference capacitor input. Reference capacitor
positive connection.
REF
9
7
8
28
30
32
38
39
–INPUT
+INPUT
V+
Analog input. Analog input negative connection.
Analog input. Analog input positive connection.
Positive power supply input.
10
11
12
13
9
14
15
D5
Digit drive output. Most Significant Digit (MSD)
B1
Binary Coded Decimal (BCD) output. Least Significant
bit (LSb).
14
15
16
17
18
19
20
21
16
17
18
19
20
25
26
27
41
42
43
44
45
52
53
54
B2
B4
BCD output.
BCD output.
B8
BCD output. Most Significant bit (MSb).
Digit drive output.
D4
D3
Digit drive output.
D2
Digit drive output.
D1
Digit drive output. Least Significant Digit (LSD).
BUSY
Busy output. At the beginning of the signal-integration
phase, BUSY goes high and remains high until the
first clock pulse after the integrator zero crossing.
22
23
28
29
55
57
CLOCK IN
POLARITY
Clock input. Conversion clock connection.
Polarity output. A positive input is indicated by a logic
high output. The polarity output is valid at the
beginning of the reference integrate phase and
remains valid until determined during the next
conversion.
24
25
30
31
58
59
DGND
Digital logic reference input.
RUN/HOLD
Run/Hold input. When at a logic high, conversions are
performed continuously. A logic low holds the current
data as long as the low condition exists.
26
27
28
36
37
38
60
7
STROBE
Strobe output. The STROBE output pulses low in the
center of the digit drive outputs.
OVERRANGE
UNDERRANGE
Overrange output. A logic high indicates that the
analog input exceeds the full-scale input range.
8
Underrange output. A logic high indicates that the
analog input is less than 9% of the full-scale input
range.
* Pins not identified or documented are NC (no connects).
2004 Microchip Technology Inc.
DS21460C-page 5
TC7135
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated, or averaged, to zero during the integration
periods.
3.0
DETAILED DESCRIPTION
All pin designations refer to the 28-pin PDIP package.
3.1
Dual-Slope Conversion Principles
The TC7135 is a dual-slope, integrating A/D converter.
An understanding of the dual-slope conversion
technique will aid in following the detailed TC7135
operational theory.
Integrated ADCs are immune to the large conversion
errors that plague successive approximation converters
in high-noise environments (see Figure 3-1).
The conventional dual-slope converter measurement
cycle has two distinct phases:
Analog Input
Integrator
Signal
Comparator
-
1. Input signal integration.
-
2. Reference voltage integration (de-integration).
+
+
The input signal being converted is integrated for a
fixed time period. Time is measured by counting clock
pulses. An opposite polarity constant reference voltage
is then integrated until the integrator output voltage
returns to zero. The reference integration time is
directly proportional to the input signal.
Switch
Drive
Clock
Phase
Control
REF
Voltage
Control
Logic
Polarity Control
In
a
simple dual-slope converter,
a
complete
Counter
Display
conversion requires the integrator output to “ramp-up”
and “ramp-down”.
VIN
VIN
≈
VREF
1/2 VREF
A simple mathematical equation relates the input
signal, reference voltage and integration time:
≈
Fixed Variable
Signal Reference
Integrate Integrate
Time Time
EQUATION 3-1:
VREFTDEINT
TINT
1
-----------------------
-------------------------------
VIN(T)DT =
FIGURE 3-1:
Basic Dual-Slope Converter.
∫
0
R
INTCINT
RINTCINT
Where:
3.2 TC7135 Operational Theory
VREF
TINT
=
=
=
Reference voltage
The TC7135 incorporates a system zero phase and
integrator output voltage zero phase to the normal two-
phase dual-slope measurement cycle. Reduced
system errors, fewer calibration steps and a shorter
overrange recovery time result.
Signal integration time (fixed)
TDEINT
Reference voltage integration time
(variable)
For a constant VIN:
The TC7135 measurement cycle contains four phases:
1. System zero.
EQUATION 3-2:
2. Analog input signal integration.
3. Reference voltage integration.
4. Integrator output zero.
VREFTDEINT
-------------------------------
TINT
VIN
=
Internal analog gate status for each phase is shown in
Figure 3-1.
TABLE 3-1:
INTERNAL ANALOG GATE STATUS
Conversion Cycle Phase
SW
SW
+
SW
-
SW
SW
SW
SW
IZ
Reference Figures
I
RI
RI
Z
R
1
System Zero
—
—
—
Closed
—
Closed
—
Closed
—
—
—
—
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Input Signal Integration
Reference Voltage Integration
Integrator Output Zero
Closed
—
—
—
—
—
Closed*
—
—
Closed
Closed
—
—
—
—
Closed
* Assumes a positive polarity input signal. SW would be closed for a negative input signal.
RI
DS21460C-page 6
2004 Microchip Technology Inc.
TC7135
3.2.1
SYSTEM ZERO
3.2.3
REFERENCE VOLTAGE
INTEGRATION
During this phase, errors due to buffer, integrator and
comparator offset voltages are compensated for by
charging CAZ (auto-zero capacitor) with a compensat-
ing error voltage. With a zero input voltage, the
integrator output will remain at zero.
The previously charged reference capacitor is con-
nected with the proper polarity to ramp the integrator
output back to zero (see Figure 3-4). The digital
reading displayed is:
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to the ANALOG
COMMON pin. The reference capacitor charges to the
reference voltage potential through SWR. A feedback
loop, closed around the integrator and comparator,
charges the CAZ capacitor with a voltage to compen-
sate for buffer amplifier, integrator and comparator
offset voltages (see Figure 3-2).
EQUATION 3-3:
[Differential Input]
----------------------------------------------
Reading = 10, 000
VREF
Analog
Input Buffer
SWI
CINT
RINT
+
–
+IN
CSZ
–
Analog
SWIZ SWZ
Input Buffer
SWI
CREF
Comparator
SWR
CINT
RINT
REF
IN
+
+IN
+
–
+
–
To
Integrator
CSZ
–
Digital
Section
SWZ
SWZ
SWIZ SWZ
CREF
Comparator
SWR
Analog
Common
REF
IN
+
SW1
+
SWI
Switch Open
Switch Closed
To
–
Integrator
IN
SWZ
SWZ
Digital
Section
Analog
Common
SWI
FIGURE 3-4:
Integration Cycle.
Reference Voltage
SW1
Switch Open
Switch Closed
IN
3.2.4 INTEGRATOR OUTPUT ZERO
FIGURE 3-2:
System Zero Phase.
This phase ensures the integrator output is at 0V when
the system zero phase is entered. It also ensures that
the true system offset voltages are compensated for.
This phase normally lasts 100 to 200 clock cycles. If an
overrange condition exists, the phase is extended to
6200 clock cycles (see Figure 3-5).
3.2.2
ANALOG INPUT SIGNAL
INTEGRATION
The TC7135 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage
must be within the device Common mode range; -1V
from either supply rail, typically. The input signal
polarity is determined at the end of this phase.
Analog
Input Buffer
+
SWI
CINT
RINT
+IN
Analog
–
Input Buffer
CSZ
–
SWI
CINT
RINT
+IN
+
–
SWIZ SWZ
CREF
SWR
Comparator
REF
IN
+
CSZ
–
+
–
To
SWIZ SWZ
Integrator
SWZ
SWZ
Digital
Section
CREF
Comparator
SWR
+
REF
IN
+
Analog
Common
–
To
Digital
Section
Integrator
SWZ
SWZ
SW1
SWI
Switch Open
Switch Closed
IN
Analog
Common
SW1
SWI
Switch Open
Switch Closed
FIGURE 3-5:
Integrator Output Zero
IN
Phase.
FIGURE 3-3:
Input Signal Integration
Phase.
2004 Microchip Technology Inc.
DS21460C-page 7
TC7135
4.3
Reference Voltage Input
4.0
ANALOG SECTION
FUNCTIONAL DESCRIPTION
The reference voltage input (REF IN) must be a posi-
tive voltage with respect to ANALOG COMMON. A
reference voltage circuit is shown in Figure 4-1.
4.1
Differential Inputs
The TC7135 operates with differential voltages
(+INPUT, pin 10 and -INPUT, pin 9) within the input
amplifier Common mode range, which extends from 1V
below the positive supply to 1V above the negative
supply. Within this Common mode voltage range, an
86 dB Common mode rejection ratio is typical.
V+
V+
10 kΩ
MCP1525
TC7135
2.5 V
REF
REF
IN
The integrator output also follows the Common mode
voltage and must not be allowed to saturate. A worst-
case condition exists, for example, when a large
positive Common mode voltage with a near full scale
negative differential input voltage is applied. The
negative input signal drives the integrator positive when
most of its swing has been used up by the positive Com-
mon mode voltage. For these critical applications, the
integrator swing can be reduced to less than the
recommended 4V full scale swing, resulting in some
loss of accuracy. The integrator output can swing within
0.3V of either supply without loss of linearity.
10 kΩ
1 µF
ANALOG
COMMON
Analog Ground
FIGURE 4-1:
Reference.
Using An External
4.2
Analog Common Input
The ANALOG COMMON pin is used as the -INPUT
return during auto-zero and de-integrate. If -INPUT is
different from ANALOG COMMON, a Common mode
voltage exists in the system. However, this signal is
rejected by the excellent CMRR of the converter. In
most applications, –INPUT will be set at a fixed, known
voltage (power supply common, for instance). In this
application, ANALOG COMMON should be tied to the
same point, thus removing the Common mode voltage
from the converter. The reference voltage is referenced
to ANALOG COMMON.
DS21460C-page 8
2004 Microchip Technology Inc.
TC7135
5.0
DIGITAL SECTION
FUNCTIONAL DESCRIPTION
The major digital subsystems within the TC7135 are
illustrated in Figure 5-1, with timing relationships
shown in Figure 5-2. The multiplexed BCD output data
can be displayed on LCD or LED displays. The digital
section is best described through a discussion of the
control signals and data outputs.
Polarity
D5
MSB
D4
Digit
D3
Drive
D2
D1
13 B1
14 B2
15 B4
16 B8
Signal
LSB
Data
Output
Multiplexer
From
Analog
Section
Latch
Latch
Latch
Latch
Latch
Polarity
FF
Zero
Cross
Detect
Counters
Control Logic
27
24
22
25
28
26
STROBE
21
Busy
DGND
Clock
In
RUN/
HOLD
Overrange Underrange
FIGURE 5-1:
Digital Section Functional Diagram.
2004 Microchip Technology Inc.
DS21460C-page 9
TC7135
5.2
STROBE Output
During the measurement cycle, the STROBE control
line is pulsed low five times. The five low pulses occur
in the center of the digit drive signals (D1, D2, D3, D5)
(see Figure 5-3).
Integrator
Output
Signal
System Integrate Reference
Zero 10,000
10,001 Counts
Counts (Fixed) Counts (Max)
Integrate
20,001
Full Measurement Cycle
40,002 Counts
D5 (MSD) goes high for 201 counts when the
measurement cycles end. In the center of the D5 pulse,
101 clock pulses after the end of the measurement
cycle, the first STROBE occurs for one half clock pulse.
After the D5 digit strobe, D4 goes high for 200 clock
pulses. The STROBE then goes low 100 clock pulses
after D4 goes high. This continues through the D1 digit
drive pulse.
Busy
Overrange when
Applicable
Underrange when
Applicable
Expanded Scale Below
Digit Scan
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will
not continue if the previous signal resulted in an
overrange condition.
D5
D4
D3
D2
D1
* First D5 of System Zero and
100
Counts
Reference Integrate One Count
Longer
The active-low STROBE pulses aid BCD data transfer
to UARTs, processors and external latches. For more
information, please refer to Application Note 784
(DS00784).
STROBE
Signal
Integrate
Reference
Integrate
Auto-Zero
*
Digit Scan
for Overrange
D5
D4
D3
D2
D1
*
TC835
Outputs
Busy
End of Conversion
*
D5
D1
(LSD)
Data
B1 B8
D4
Data
D3
D2
D5
Data
(MSD)
Data
Data
Data
STROBE
Note Absence
of STROBE
FIGURE 5-2:
Timing Diagrams For
200
Counts
Outputs.
201
Counts
200
D5
D4
D3
D2
D1
Counts
5.1
RUN/HOLD Input
200
Counts
When left open, this pin assumes a logic ‘1’ level. With
a RUN/HOLD = 1, the TC7135 performs conversions
continuously, with a new measurement cycle beginning
every 40,002 clock pulses.
200
Counts
200
When RUN/HOLD changes to a logic ‘0’, the measure-
ment cycle in progress will be completed, with the data
held and displayed as long as the logic ‘0’ condition
exists.
Counts
200
Counts
*Delay between Busy going Low and First STROBE pulse is
A positive pulse (>300 nsec) at RUN/HOLD initiates a
new measurement cycle. The measurement cycle in
progress when RUN/HOLD initially assumed the logic
‘0’ state must be completed before the positive pulse
can be recognized as a single conversion run
command.
dependent on Analog Input.
FIGURE 5-3:
Strobe Signal Low Five
Times Per Conversion.
The new measurement cycle begins with a 10,001
count auto-zero phase. At the end of this phase, the
busy signal goes high.
DS21460C-page 10
2004 Microchip Technology Inc.
TC7135
5.3
BUSY Output
5.6
POLARITY Output
At the beginning of the signal integration phase, BUSY
goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to the
logic ‘0’ state once the measurement cycle ends in an
overrange condition. The internal display latches are
loaded during the first clock pulse after BUSY and are
latched at the clock pulse end. The BUSY signal does
not go high at the beginning of the measurement cycle,
which starts with the auto-zero cycle.
A positive input is registered by a logic ‘1’ polarity
signal. The polarity bit is valid at the beginning of
reference integrate and remains valid until determined
during the next conversion.
The polarity bit is valid even for a zero reading. Signals
less than the converter's LSB will have the signal
polarity determined correctly. This is useful in null
applications.
5.7
Digit Drive Outputs
5.4
OVERRANGE Output
Digit drive signals are positive-going signals. The scan
sequence is D5 to D1. All positive pulses are 200 clock
pulses wide, with the exception D5, which is 201 clock
pulses wide.
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVER-
RANGE output is set to a logic ‘1’. The OVERRANGE
output register is set when BUSY goes low and is reset
at the beginning of the next reference integration
phase.
All five digits are scanned continuously, unless an
overrange condition occurs. In an overrange condition,
all digit drives are held low from the final STROBE
pulse until the beginning of the next reference integrate
phase. The scanning sequence is then repeated. This
provides a blinking visual display indication.
5.5
UNDERRANGE Output
If the output count is 9% of full scale or less (-1800
counts), the UNDERRANGE register bit is set at the
end of BUSY. The bit is set low at the next signal
integration phase.
5.8
BCD Data Outputs
The binary coded decimal (BCD) bits B8, B4, B2 and B1
are positive-true logic signals. The data bits become
active at the same time as the digit drive signals. In an
overrange condition, all data bits are at a logic ‘0’ state.
2004 Microchip Technology Inc.
DS21460C-page 11
TC7135
6.1.3
AUTO-ZERO AND REFERENCE
CAPACITORS
6.0
TYPICAL APPLICATIONS
6.1
Component Value Selection
The size of the auto-zero capacitor has some influence
on the noise of the system, with a larger capacitor
reducing the noise. The reference capacitor should be
large enough such that stray capacitance to ground
from its nodes is negligible.
6.1.1
INTEGRATING RESISTOR
The integrating resistor RINT is determined by the full-
scale input voltage and the output current of the buffer
used to charge the integrator capacitor (CINT). Both the
buffer amplifier and the integrator have a class A output
stage, with 100 µA of quiescent current. A 20 µA drive
current gives negligible linearity errors. Values of 5 µA
to 40 µA give good results. The exact value of an
integrating resistor for a 20 µA current is easily
calculated.
The dielectric absorption of the reference and auto-
zero capacitors are only important at power-on or when
the circuit is recovering from an overload. Smaller or
cheaper capacitors can be used if accurate readings
are not required for the first few seconds of recovery.
6.1.4
The analog input required to generate a full-scale
output is VIN = 2 VREF
REFERENCE VOLTAGE
EQUATION 6-1:
.
Full Scale Voltage
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. For this
reason, it is recommended that a high-quality reference
be used where high-accuracy absolute measurements
are being made.
--------------------------------------------
=
RINT
20µA
6.1.2
INTEGRATING CAPACITOR (CINT
)
The product of integrating resistor and capacitor should
be selected to give the maximum voltage swing that
ensures the tolerance build-up will not saturate the
integrator swing (approximately 0.3V from either
supply). For ±5V supplies and ANALOG COMMON tied
to supply ground, a ±3.5V to ±4V full scale integrator
6.2
Conversion Timing
6.2.1
LINE FREQUENCY REJECTION
A signal integration period at a multiple of the 60 Hz
line frequency will maximize 60 Hz “line noise”
rejection. A 100 kHz clock frequency will reject 50 Hz,
60 Hz and 400 Hz noise. This corresponds to five
readings per second (see Table 6-1 and Table 6-2).
swing is adequate.
A
0.10 µF to 0.47 µF is
recommended. In general, the value of CINT is given
by:
EQUATION 6-2:
TABLE 6-1:
CONVERSION RATE VS.
CLOCK FREQUENCY
[10, 000 × clock period] × IINT
---------------------------------------------------------------------------
CINT
=
=
integrator output voltage swing
Oscillator Frequency
(kHz)
Conversion Rate
(Conv./Sec.)
(10, 000)(clock period) × 20µA
-----------------------------------------------------------------------------
integrator output voltage swing
100
120
200
300
400
800
1200
2.5
3
A very important characteristic of the integrating
capacitor CINT is that it has low dielectric absorption to
prevent rollover or ratiometric errors. A good test for
dielectric absorption is to use the capacitor with the
input tied to the reference. This ratiometric condition
should read half scale 0.9999, with any deviation
probably due to dielectric absorption. Polypropylene
capacitors give undetectable errors at reasonable cost.
Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
5
7.5
10
20
30
DS21460C-page 12
2004 Microchip Technology Inc.
TC7135
the ratio between this resistor and the integrating
resistor (a few tens of ohms in the recommended
circuit), the comparator delay can be compensated and
the maximum clock frequency extended by
approximately a factor of 3. At higher frequencies,
ringing and second-order breaks will cause significant
nonlinearities in the first few counts of the instrument.
TABLE 6-2:
LINE FREQUENCY
REJECTION VS. CLOCK
FREQUENCY
Line Frequency
Oscillator Frequency
(kHz)
Rejection
(Hz)
300
200
60
The minimum clock frequency is established by
leakage on the auto-zero and reference capacitors.
With most devices, measurement cycles as long as 10
seconds give no measurable leakage error.
150
120
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators
are shown in Section 6.0 “Typical Applications”. The
multiplexed output means that if the display takes
significant current from the logic supply, the clock
should have good PSRR.
100
40
33-1/3
250
50
166-2/3
125
6.4
Zero Crossing Flip Flop
100
The flip flop interrogates the data once every clock
pulse after the transients of the previous clock pulse and
half clock pulse have died down. False zero crossings
caused by clock pulses are not recognized. Of course,
the flip flop delays the true zero crossing by up to one
count in every instance. If a correction were not made,
the display would always be one count too high.
Therefore, the counter is disabled for one clock pulse at
the beginning of the reference integrate (de-integrate)
phase. This one-count delay compensates for the delay
of the zero crossing flip flop and allows the correct
number to be latched into the display. Similarly, a one-
count delay at the beginning of auto-zero gives an
overload display of 0000 instead of 0001. No delay
occurs during signal integrate so that true ratiometric
readings result.
100
50, 60,400
The conversion rate is easily calculated:
EQUATION 6-3:
Clock Frequency (Hz)
----------------------------------------------------
Reading 1/sec =
4000
6.3
High Speed Operation
The maximum conversion rate of most dual-slope A/D
converters is limited by the frequency response of the
comparator. The comparator in this circuit follows the
integrator ramp with a 3 µsec delay, at a clock
frequency of 160 kHz (6 µsec period). Half of the first
reference integrate clock period is lost in delay. This
means that the meter reading will change from 0 to 1
with a 50 µV input, 1 to 2 with 150 µV, 2 to 3 at 250 µV,
etc. This transition at midpoint is considered desirable
by most users. However, if the clock frequency is
increased appreciably above 200 kHz, the instrument
will flash "1" on noise peaks, even when the input is
shorted.
6.5
Generating a Negative Supply
A negative voltage can be generated from the positive
supply by using a TC7135 (see Figure 6-1).
+5V
11
V+
8
For many dedicated applications where the input signal
is always of one polarity, the delay of the comparator
need not be a limitation. Since the nonlinearity and
noise do not increase substantially with frequency, clock
rates of up to ~1 MHz may be used. For a fixed clock
frequency, the extra count (or counts) caused by
comparator delay will be a constant and can be
subtracted out digitally.
TC7135
1
(-5V)
5
V–
TC7660
10 µF
+
4
2
3
+
24
10 µF
The clock frequency may be extended above 160 kHz
without this error, however, by using a low value
resistor in series with the integrating capacitor. The
effect of the resistor is to introduce a small pedestal
voltage on to the integrator output at the beginning of
the reference integrate phase. By careful selection of
FIGURE 6-1:
Generator.
Negative Supply Voltage
2004 Microchip Technology Inc.
DS21460C-page 13
TC7135
+5V
20 19 18 17 12
D1 D2 D3 D4 D5
INT OUT
4
5
1 µF
0.33 µF
200 kHz
AZ IN
4.7 kΩ
23
7
POL
6
BUFF
OUT
b
c
7
7
7
7
CREF
–
100 kΩ
22
10
TC7135
FIN
1 µF
X7
8
CREF
+
Blank MSD On Zero
6
100 kΩ
+
+INPUT
9 15
5
Analog
Input
16
15
14
13
1 µF
B8
D
9
3
RBI
DM7447A
2
1
7
–INPUT
–
C
B
A
B4
B2
B1
16
+5V
ANALOG
COMMON
REF
V–
IN
V+
1
2
11
V+
5V
100 kΩ
MCP1525
1 µF
FIGURE 6-2:
R2
4-1/2 Digit ADC With Multiplexed Common Anode Led Display.
+5V
R1
C
16 kΩ
1 kΩ
FO
56 kΩ
2
8
V
+
OUT
Gates are 74C04
0.22 µF
7
LM311
R1R2
1
3
--------------------------------------------------
, RP =
------------------
R1 + R2
FO
=
1.
–
1
2C(0.41RP + 0.7R1)
30 kΩ
4
16 kΩ
a. If R1 = R2 = R1, F 0.55/RC
b. If R2 >> R1, F 0.45/R1C
c. If R2 << R1, F 0.72/R1C
390 pF
R
R
4
2
+5V
6
2 kΩ
2. Examples:
a. F = 120 kHz, C = 420 pF
R1 = R2 ≈ 10.9 kΩ
100 kΩ
C
2
2
3
b. F = 120 kHz, C = 420pF, R2 = 50 kΩ
10 pF
+
R
7
R1 = 8.93 kΩ
c. F = 120 kHz, C = 220 pF, R2 = 5 kΩ
R1 = 27.3 kΩ
2
V
LM311
OUT
100 kΩ
4
–
R
3
1
50 kΩ
C
1
0.1 µF
FIGURE 6-3:
RC Oscillator Circuit.
FIGURE 6-4:
Comparator Clock Circuits.
DS21460C-page 14
2004 Microchip Technology Inc.
TC7135
+5V
+5V
SET V
= 1V
REF
5V
28
27
26
1
2
3
V–
UR
OR
TC7135
MCP1525
100
REF IN
kΩ
1 µF
150Ω
ANALOG
GND
STROBE
47
10
11
9
8
7
Analog
GND
kΩ
150Ω
25
24
23
22
21
20
4
5
INT
OUT
RUN/HOLD
DGND
1 µF
0.33 µF
12
13
14
15
AZ IN
BUFF
OUT
6
6
5
4
3
2
1
MC14513
POLARITY
100 kΩ
7
C
+
CLK IN
BUSY
(LSD) D1
D2
REF
1 µF
100
k
8
C
–
REF
Ω
+5V
9
16
17
+
SIG
IN
–INPUT
+INPUT
0.1
µF
10
11
19
18
17
18
+5V
D3
V+
12
D4
D5 (MSD)
13
14
16
15
(MSB) B8
B4
B1 (LSB)
B2
F
= 200 kHz
OSC
FIGURE 6-5:
4-1/2 Digit ADC With Multiplexed Common Cathode LED Display.
2004 Microchip Technology Inc.
DS21460C-page 15
TC7135
7.0
7.1
PACKAGING INFORMATION
Package Marking Information
28-Pin PLCC
Example:
1
1
M
XXXXXXXXXX
XXXXXXXXXX
M
TC7135CLI
0444256
YYWWNNN
28-Pin PDIP (Wide)
Example:
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
YYWWNNN
TC7135CPI
0444256
*h
*h
44-Pin MQFP
Example:
M
M
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
TC7135CKW
0444256
64-Pin MQFP
Example:
M
M
TC7135CBU
0444256
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
DS21460C-page 16
2004 Microchip Technology Inc.
TC7135
28-Lead Plastic Leaded Chip Carrier (LI) – Square (PLCC)
E
E1
#leads=n1
D1
D
n
1 2
CH1 x 45°
CH2 x 45 °
α
A3
A2
A
32°
B1
B
c
A1
β
p
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.050
7
1.27
7
Pins per Side
Overall Height
n1
A
.165
.173
.153
.028
.026
.045
.005
.490
.490
.453
.453
.420
.420
.011
.029
.020
5
.180
.160
.035
.031
.055
.010
.495
.495
.456
.456
.430
.430
.013
.032
.021
10
4.19
3.68
4.39
3.87
0.71
0.66
1.14
0.13
12.45
12.45
11.51
11.51
10.67
10.67
0.27
0.74
0.51
5
4.57
4.06
0.89
0.79
1.40
0.25
12.57
12.57
11.58
11.58
10.92
10.92
0.33
0.81
0.53
10
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.145
.020
.021
.035
.000
.485
.485
.450
.450
.410
.410
.008
.026
.013
0
§
0.51
0.53
0.89
0.00
12.32
12.32
11.43
11.43
10.41
10.41
0.20
0.66
0.33
0
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-026
2004 Microchip Technology Inc.
DS21460C-page 17
TC7135
28-Lead Plastic Dual In-line (PI) – 600 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
B1
β
A1
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.505
1.395
.120
.008
.030
.014
.620
5
.160
0.38
15.11
12.83
35.43
3.05
0.20
0.76
0.36
15.75
5
.600
.545
1.430
.130
.012
.050
.018
.650
10
.625
.560
1.465
.135
.015
.070
.022
.680
15
15.24
13.84
36.32
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
37.21
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-079
DS21460C-page 18
2004 Microchip Technology Inc.
TC7135
44-Lead Plastic Metric Quad Flatpack (KW) 10x10x2 mm Body, Lead Form (MQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
c
n
°
CH x 45
α
A1
A
φ
β
(F)
L
A2
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.079
.077
.002
.029
.086
.080
.006
.035
.063
3.5
.093
2.00
1.95
2.18
2.03
0.15
0.88
1.60
3.5
2.35
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.083
.010
.041
2.10
0.25
1.03
§
0.05
0.73
Foot Length
Footprint (Reference)
Foot Angle
0
.510
.510
.390
.390
.005
.012
.025
5
7
.530
.530
.398
.398
.009
.018
.045
15
0
12.95
12.95
9.90
9.90
0.13
0.30
0.64
5
7
13.45
13.45
10.10
10.10
0.23
0.45
1.14
15
Overall Width
E
D
.520
.520
.394
.394
.007
.015
.035
10
13.20
13.20
10.00
10.00
0.18
0.38
0.89
10
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-022
Drawing No. C04-071
2004 Microchip Technology Inc.
DS21460C-page 19
TC7135
64 Lead Metric Plastic Quad Flat (BU) (MQFP)
E
E1
e
D1
D
B
2
1
n
a
A
c
A2
b
f
A1
(F)
L
Units
Dimension Limits
INCHES
MILLIMETERS*
MIN
NOM
MAX
MIN
NOM
MAX
n
e
Number of Pins
Pitch
64
64
.031 BSC
0.80 BSC
Overall Height
A
A2
A1
E
.098
.098
.000
--
.124
.114
.010
2.50
--
3.15
Molded Package Thickness
Standoff §
.106
2.50
0.00
2.70
2.90
0.25
--
.677 BSC
.551 BSC
.677 BSC
.551 BSC
.035
--
Overall Width
17.20 BSC
Molded Package Width
Overall Length
E1
D
14.00 BSC
17.20 BSC
Molded Package Length
Foot Length
D1
L
14.00 BSC
.029
.041
0.73
0.88
1.03
(F)
f
c
Footprint (Reference)
Foot Angle
.063 REF
--
1.60 REF
0°
.004
.011
5°
6°
.009
.018
16°
0°
0.11
0.29
5°
--
--
--
--
--
7°
0.23
0.45
16°
Lead Thickness
--
Lead Width
B
a
--
Mold Draft Angle Top
Mold Draft Angle Bottom
--
b
5°
--
16°
5°
16°
*Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash
or protrusions shall not exceed .010" (0.254mm) per side.
JEDEC equivalent: MS-022 BE.
Formerly TelCom PQFP package.
Drawing No. C04-022
DS21460C-page 20
2004 Microchip Technology Inc.
TC7135
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Examples:
Temperature
Range
Package
a)
b)
c)
TC7135CLI:
4-1/2 Digit A/D, BCD Output,
PLCC package.
4-1/2 Digit A/D, BCD Output,
PDIP package.
TC7135CPI:
TC7135CLI713: 4-1/2 Digit A/D, BCD Output,
PLCC package,
Device
TC7135: 4-1/2 Digit A/D, BCD Output
Tape and Reel.
d)
TC7135CBU:
4-1/2 Digit A/D, BCD Output,
MQFP package.
Temperature Range
Package
C
=
=
0°C to +70°C
LI
Plastic Leaded Chip Carrier (PLCC), 28-lead
LI713 = Plastic Leaded Chip Carrier (PLCC), 28-lead,
Tape and Reel
PI
KW
BU
=
=
=
Plastic DIP, (600 mil Body), 28-lead
Plastic Metric Quad Flatpack, (MQFP), 44-lead
Plastic Metric Quad Flatpack, (MQFP), 64-lead
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21460C-page 21
TC7135
NOTES:
DS21460C-page 22
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21460C-page 23
WORLDWIDE SALES AND SERVICE
China - Beijing
Korea
AMERICAS
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Tel: 91-80-22290061 Fax: 91-80-22290062
Japan
Fax: 650-961-0286
Toronto
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
Waegenburghtplein 4
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ASIA/PACIFIC
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Tel: 44-118-921-5869
Fax: 44-118-921-5820
05/28/04
DS21460C-page 24
2004 Microchip Technology Inc.
相关型号：
TC7135C/PI
1-CH 4-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
MICROCHIP
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